781 lines
19 KiB
C
781 lines
19 KiB
C
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/*
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* Blackfin On-Chip Two Wire Interface Driver
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*
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* Copyright 2005-2007 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/timer.h>
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#include <linux/spinlock.h>
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#include <linux/completion.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <asm/blackfin.h>
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#include <asm/portmux.h>
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#include <asm/irq.h>
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#define POLL_TIMEOUT (2 * HZ)
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/* SMBus mode*/
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#define TWI_I2C_MODE_STANDARD 1
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#define TWI_I2C_MODE_STANDARDSUB 2
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#define TWI_I2C_MODE_COMBINED 3
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#define TWI_I2C_MODE_REPEAT 4
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struct bfin_twi_iface {
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int irq;
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spinlock_t lock;
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char read_write;
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u8 command;
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u8 *transPtr;
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int readNum;
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int writeNum;
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int cur_mode;
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int manual_stop;
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int result;
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int timeout_count;
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struct timer_list timeout_timer;
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struct i2c_adapter adap;
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struct completion complete;
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struct i2c_msg *pmsg;
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int msg_num;
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int cur_msg;
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u16 saved_clkdiv;
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u16 saved_control;
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void __iomem *regs_base;
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};
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#define DEFINE_TWI_REG(reg, off) \
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static inline u16 read_##reg(struct bfin_twi_iface *iface) \
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{ return bfin_read16(iface->regs_base + (off)); } \
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static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
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{ bfin_write16(iface->regs_base + (off), v); }
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DEFINE_TWI_REG(CLKDIV, 0x00)
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DEFINE_TWI_REG(CONTROL, 0x04)
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DEFINE_TWI_REG(SLAVE_CTL, 0x08)
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DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
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DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
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DEFINE_TWI_REG(MASTER_CTL, 0x14)
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DEFINE_TWI_REG(MASTER_STAT, 0x18)
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DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
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DEFINE_TWI_REG(INT_STAT, 0x20)
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DEFINE_TWI_REG(INT_MASK, 0x24)
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DEFINE_TWI_REG(FIFO_CTL, 0x28)
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DEFINE_TWI_REG(FIFO_STAT, 0x2C)
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DEFINE_TWI_REG(XMT_DATA8, 0x80)
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DEFINE_TWI_REG(XMT_DATA16, 0x84)
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DEFINE_TWI_REG(RCV_DATA8, 0x88)
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DEFINE_TWI_REG(RCV_DATA16, 0x8C)
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static const u16 pin_req[2][3] = {
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{P_TWI0_SCL, P_TWI0_SDA, 0},
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{P_TWI1_SCL, P_TWI1_SDA, 0},
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};
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static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
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{
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unsigned short twi_int_status = read_INT_STAT(iface);
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unsigned short mast_stat = read_MASTER_STAT(iface);
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if (twi_int_status & XMTSERV) {
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/* Transmit next data */
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if (iface->writeNum > 0) {
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write_XMT_DATA8(iface, *(iface->transPtr++));
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iface->writeNum--;
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}
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/* start receive immediately after complete sending in
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* combine mode.
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*/
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else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) | MDIR | RSTART);
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else if (iface->manual_stop)
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) | STOP);
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else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
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iface->cur_msg + 1 < iface->msg_num) {
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if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) | RSTART | MDIR);
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else
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write_MASTER_CTL(iface,
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(read_MASTER_CTL(iface) | RSTART) & ~MDIR);
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}
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SSYNC();
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/* Clear status */
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write_INT_STAT(iface, XMTSERV);
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SSYNC();
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}
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if (twi_int_status & RCVSERV) {
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if (iface->readNum > 0) {
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/* Receive next data */
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*(iface->transPtr) = read_RCV_DATA8(iface);
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if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
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/* Change combine mode into sub mode after
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* read first data.
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*/
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iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
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/* Get read number from first byte in block
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* combine mode.
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*/
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if (iface->readNum == 1 && iface->manual_stop)
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iface->readNum = *iface->transPtr + 1;
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}
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iface->transPtr++;
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iface->readNum--;
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} else if (iface->manual_stop) {
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) | STOP);
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SSYNC();
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} else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
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iface->cur_msg + 1 < iface->msg_num) {
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if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) | RSTART | MDIR);
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else
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write_MASTER_CTL(iface,
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(read_MASTER_CTL(iface) | RSTART) & ~MDIR);
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SSYNC();
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}
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/* Clear interrupt source */
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write_INT_STAT(iface, RCVSERV);
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SSYNC();
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}
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if (twi_int_status & MERR) {
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write_INT_STAT(iface, MERR);
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write_INT_MASK(iface, 0);
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write_MASTER_STAT(iface, 0x3e);
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write_MASTER_CTL(iface, 0);
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SSYNC();
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iface->result = -EIO;
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/* if both err and complete int stats are set, return proper
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* results.
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*/
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if (twi_int_status & MCOMP) {
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write_INT_STAT(iface, MCOMP);
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write_INT_MASK(iface, 0);
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write_MASTER_CTL(iface, 0);
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SSYNC();
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/* If it is a quick transfer, only address bug no data,
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* not an err, return 1.
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*/
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if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
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iface->result = 1;
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/* If address not acknowledged return -1,
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* else return 0.
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*/
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else if (!(mast_stat & ANAK))
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iface->result = 0;
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}
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complete(&iface->complete);
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return;
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}
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if (twi_int_status & MCOMP) {
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write_INT_STAT(iface, MCOMP);
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SSYNC();
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if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
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if (iface->readNum == 0) {
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/* set the read number to 1 and ask for manual
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* stop in block combine mode
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*/
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iface->readNum = 1;
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iface->manual_stop = 1;
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) | (0xff << 6));
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} else {
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/* set the readd number in other
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* combine mode.
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*/
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write_MASTER_CTL(iface,
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(read_MASTER_CTL(iface) &
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(~(0xff << 6))) |
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(iface->readNum << 6));
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}
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/* remove restart bit and enable master receive */
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) & ~RSTART);
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SSYNC();
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} else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
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iface->cur_msg+1 < iface->msg_num) {
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iface->cur_msg++;
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iface->transPtr = iface->pmsg[iface->cur_msg].buf;
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iface->writeNum = iface->readNum =
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iface->pmsg[iface->cur_msg].len;
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/* Set Transmit device address */
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write_MASTER_ADDR(iface,
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iface->pmsg[iface->cur_msg].addr);
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if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
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iface->read_write = I2C_SMBUS_READ;
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else {
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iface->read_write = I2C_SMBUS_WRITE;
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/* Transmit first data */
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if (iface->writeNum > 0) {
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write_XMT_DATA8(iface,
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*(iface->transPtr++));
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iface->writeNum--;
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SSYNC();
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}
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}
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if (iface->pmsg[iface->cur_msg].len <= 255)
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write_MASTER_CTL(iface,
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(read_MASTER_CTL(iface) &
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(~(0xff << 6))) |
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(iface->pmsg[iface->cur_msg].len << 6));
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else {
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write_MASTER_CTL(iface,
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(read_MASTER_CTL(iface) |
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(0xff << 6)));
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iface->manual_stop = 1;
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}
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/* remove restart bit and enable master receive */
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) & ~RSTART);
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SSYNC();
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} else {
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iface->result = 1;
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write_INT_MASK(iface, 0);
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write_MASTER_CTL(iface, 0);
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SSYNC();
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complete(&iface->complete);
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}
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}
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}
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/* Interrupt handler */
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static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
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{
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struct bfin_twi_iface *iface = dev_id;
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unsigned long flags;
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spin_lock_irqsave(&iface->lock, flags);
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del_timer(&iface->timeout_timer);
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bfin_twi_handle_interrupt(iface);
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spin_unlock_irqrestore(&iface->lock, flags);
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return IRQ_HANDLED;
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}
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static void bfin_twi_timeout(unsigned long data)
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{
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struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
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unsigned long flags;
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spin_lock_irqsave(&iface->lock, flags);
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bfin_twi_handle_interrupt(iface);
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if (iface->result == 0) {
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iface->timeout_count--;
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if (iface->timeout_count > 0) {
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iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
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add_timer(&iface->timeout_timer);
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} else {
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iface->result = -1;
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complete(&iface->complete);
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}
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}
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spin_unlock_irqrestore(&iface->lock, flags);
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}
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/*
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* Generic i2c master transfer entrypoint
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*/
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static int bfin_twi_master_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msgs, int num)
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{
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struct bfin_twi_iface *iface = adap->algo_data;
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struct i2c_msg *pmsg;
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int rc = 0;
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if (!(read_CONTROL(iface) & TWI_ENA))
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return -ENXIO;
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while (read_MASTER_STAT(iface) & BUSBUSY)
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yield();
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iface->pmsg = msgs;
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iface->msg_num = num;
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iface->cur_msg = 0;
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pmsg = &msgs[0];
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if (pmsg->flags & I2C_M_TEN) {
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dev_err(&adap->dev, "10 bits addr not supported!\n");
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return -EINVAL;
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}
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iface->cur_mode = TWI_I2C_MODE_REPEAT;
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iface->manual_stop = 0;
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iface->transPtr = pmsg->buf;
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iface->writeNum = iface->readNum = pmsg->len;
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iface->result = 0;
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iface->timeout_count = 10;
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init_completion(&(iface->complete));
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/* Set Transmit device address */
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write_MASTER_ADDR(iface, pmsg->addr);
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/* FIFO Initiation. Data in FIFO should be
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* discarded before start a new operation.
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*/
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write_FIFO_CTL(iface, 0x3);
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SSYNC();
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write_FIFO_CTL(iface, 0);
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SSYNC();
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if (pmsg->flags & I2C_M_RD)
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iface->read_write = I2C_SMBUS_READ;
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else {
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iface->read_write = I2C_SMBUS_WRITE;
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/* Transmit first data */
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if (iface->writeNum > 0) {
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write_XMT_DATA8(iface, *(iface->transPtr++));
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iface->writeNum--;
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SSYNC();
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}
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}
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/* clear int stat */
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write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
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/* Interrupt mask . Enable XMT, RCV interrupt */
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write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
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SSYNC();
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if (pmsg->len <= 255)
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write_MASTER_CTL(iface, pmsg->len << 6);
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else {
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||
|
|
write_MASTER_CTL(iface, 0xff << 6);
|
||
|
|
iface->manual_stop = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
|
||
|
|
add_timer(&iface->timeout_timer);
|
||
|
|
|
||
|
|
/* Master enable */
|
||
|
|
write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
|
||
|
|
((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
|
||
|
|
((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
|
||
|
|
SSYNC();
|
||
|
|
|
||
|
|
wait_for_completion(&iface->complete);
|
||
|
|
|
||
|
|
rc = iface->result;
|
||
|
|
|
||
|
|
if (rc == 1)
|
||
|
|
return num;
|
||
|
|
else
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* SMBus type transfer entrypoint
|
||
|
|
*/
|
||
|
|
|
||
|
|
int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
|
||
|
|
unsigned short flags, char read_write,
|
||
|
|
u8 command, int size, union i2c_smbus_data *data)
|
||
|
|
{
|
||
|
|
struct bfin_twi_iface *iface = adap->algo_data;
|
||
|
|
int rc = 0;
|
||
|
|
|
||
|
|
if (!(read_CONTROL(iface) & TWI_ENA))
|
||
|
|
return -ENXIO;
|
||
|
|
|
||
|
|
while (read_MASTER_STAT(iface) & BUSBUSY)
|
||
|
|
yield();
|
||
|
|
|
||
|
|
iface->writeNum = 0;
|
||
|
|
iface->readNum = 0;
|
||
|
|
|
||
|
|
/* Prepare datas & select mode */
|
||
|
|
switch (size) {
|
||
|
|
case I2C_SMBUS_QUICK:
|
||
|
|
iface->transPtr = NULL;
|
||
|
|
iface->cur_mode = TWI_I2C_MODE_STANDARD;
|
||
|
|
break;
|
||
|
|
case I2C_SMBUS_BYTE:
|
||
|
|
if (data == NULL)
|
||
|
|
iface->transPtr = NULL;
|
||
|
|
else {
|
||
|
|
if (read_write == I2C_SMBUS_READ)
|
||
|
|
iface->readNum = 1;
|
||
|
|
else
|
||
|
|
iface->writeNum = 1;
|
||
|
|
iface->transPtr = &data->byte;
|
||
|
|
}
|
||
|
|
iface->cur_mode = TWI_I2C_MODE_STANDARD;
|
||
|
|
break;
|
||
|
|
case I2C_SMBUS_BYTE_DATA:
|
||
|
|
if (read_write == I2C_SMBUS_READ) {
|
||
|
|
iface->readNum = 1;
|
||
|
|
iface->cur_mode = TWI_I2C_MODE_COMBINED;
|
||
|
|
} else {
|
||
|
|
iface->writeNum = 1;
|
||
|
|
iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
|
||
|
|
}
|
||
|
|
iface->transPtr = &data->byte;
|
||
|
|
break;
|
||
|
|
case I2C_SMBUS_WORD_DATA:
|
||
|
|
if (read_write == I2C_SMBUS_READ) {
|
||
|
|
iface->readNum = 2;
|
||
|
|
iface->cur_mode = TWI_I2C_MODE_COMBINED;
|
||
|
|
} else {
|
||
|
|
iface->writeNum = 2;
|
||
|
|
iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
|
||
|
|
}
|
||
|
|
iface->transPtr = (u8 *)&data->word;
|
||
|
|
break;
|
||
|
|
case I2C_SMBUS_PROC_CALL:
|
||
|
|
iface->writeNum = 2;
|
||
|
|
iface->readNum = 2;
|
||
|
|
iface->cur_mode = TWI_I2C_MODE_COMBINED;
|
||
|
|
iface->transPtr = (u8 *)&data->word;
|
||
|
|
break;
|
||
|
|
case I2C_SMBUS_BLOCK_DATA:
|
||
|
|
if (read_write == I2C_SMBUS_READ) {
|
||
|
|
iface->readNum = 0;
|
||
|
|
iface->cur_mode = TWI_I2C_MODE_COMBINED;
|
||
|
|
} else {
|
||
|
|
iface->writeNum = data->block[0] + 1;
|
||
|
|
iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
|
||
|
|
}
|
||
|
|
iface->transPtr = data->block;
|
||
|
|
break;
|
||
|
|
case I2C_SMBUS_I2C_BLOCK_DATA:
|
||
|
|
if (read_write == I2C_SMBUS_READ) {
|
||
|
|
iface->readNum = data->block[0];
|
||
|
|
iface->cur_mode = TWI_I2C_MODE_COMBINED;
|
||
|
|
} else {
|
||
|
|
iface->writeNum = data->block[0];
|
||
|
|
iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
|
||
|
|
}
|
||
|
|
iface->transPtr = (u8 *)&data->block[1];
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
iface->result = 0;
|
||
|
|
iface->manual_stop = 0;
|
||
|
|
iface->read_write = read_write;
|
||
|
|
iface->command = command;
|
||
|
|
iface->timeout_count = 10;
|
||
|
|
init_completion(&(iface->complete));
|
||
|
|
|
||
|
|
/* FIFO Initiation. Data in FIFO should be discarded before
|
||
|
|
* start a new operation.
|
||
|
|
*/
|
||
|
|
write_FIFO_CTL(iface, 0x3);
|
||
|
|
SSYNC();
|
||
|
|
write_FIFO_CTL(iface, 0);
|
||
|
|
|
||
|
|
/* clear int stat */
|
||
|
|
write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
|
||
|
|
|
||
|
|
/* Set Transmit device address */
|
||
|
|
write_MASTER_ADDR(iface, addr);
|
||
|
|
SSYNC();
|
||
|
|
|
||
|
|
iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
|
||
|
|
add_timer(&iface->timeout_timer);
|
||
|
|
|
||
|
|
switch (iface->cur_mode) {
|
||
|
|
case TWI_I2C_MODE_STANDARDSUB:
|
||
|
|
write_XMT_DATA8(iface, iface->command);
|
||
|
|
write_INT_MASK(iface, MCOMP | MERR |
|
||
|
|
((iface->read_write == I2C_SMBUS_READ) ?
|
||
|
|
RCVSERV : XMTSERV));
|
||
|
|
SSYNC();
|
||
|
|
|
||
|
|
if (iface->writeNum + 1 <= 255)
|
||
|
|
write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
|
||
|
|
else {
|
||
|
|
write_MASTER_CTL(iface, 0xff << 6);
|
||
|
|
iface->manual_stop = 1;
|
||
|
|
}
|
||
|
|
/* Master enable */
|
||
|
|
write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
|
||
|
|
((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
|
||
|
|
break;
|
||
|
|
case TWI_I2C_MODE_COMBINED:
|
||
|
|
write_XMT_DATA8(iface, iface->command);
|
||
|
|
write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
|
||
|
|
SSYNC();
|
||
|
|
|
||
|
|
if (iface->writeNum > 0)
|
||
|
|
write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
|
||
|
|
else
|
||
|
|
write_MASTER_CTL(iface, 0x1 << 6);
|
||
|
|
/* Master enable */
|
||
|
|
write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
|
||
|
|
((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
write_MASTER_CTL(iface, 0);
|
||
|
|
if (size != I2C_SMBUS_QUICK) {
|
||
|
|
/* Don't access xmit data register when this is a
|
||
|
|
* read operation.
|
||
|
|
*/
|
||
|
|
if (iface->read_write != I2C_SMBUS_READ) {
|
||
|
|
if (iface->writeNum > 0) {
|
||
|
|
write_XMT_DATA8(iface,
|
||
|
|
*(iface->transPtr++));
|
||
|
|
if (iface->writeNum <= 255)
|
||
|
|
write_MASTER_CTL(iface,
|
||
|
|
iface->writeNum << 6);
|
||
|
|
else {
|
||
|
|
write_MASTER_CTL(iface,
|
||
|
|
0xff << 6);
|
||
|
|
iface->manual_stop = 1;
|
||
|
|
}
|
||
|
|
iface->writeNum--;
|
||
|
|
} else {
|
||
|
|
write_XMT_DATA8(iface, iface->command);
|
||
|
|
write_MASTER_CTL(iface, 1 << 6);
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
if (iface->readNum > 0 && iface->readNum <= 255)
|
||
|
|
write_MASTER_CTL(iface,
|
||
|
|
iface->readNum << 6);
|
||
|
|
else if (iface->readNum > 255) {
|
||
|
|
write_MASTER_CTL(iface, 0xff << 6);
|
||
|
|
iface->manual_stop = 1;
|
||
|
|
} else {
|
||
|
|
del_timer(&iface->timeout_timer);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
write_INT_MASK(iface, MCOMP | MERR |
|
||
|
|
((iface->read_write == I2C_SMBUS_READ) ?
|
||
|
|
RCVSERV : XMTSERV));
|
||
|
|
SSYNC();
|
||
|
|
|
||
|
|
/* Master enable */
|
||
|
|
write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
|
||
|
|
((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
|
||
|
|
((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
SSYNC();
|
||
|
|
|
||
|
|
wait_for_completion(&iface->complete);
|
||
|
|
|
||
|
|
rc = (iface->result >= 0) ? 0 : -1;
|
||
|
|
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Return what the adapter supports
|
||
|
|
*/
|
||
|
|
static u32 bfin_twi_functionality(struct i2c_adapter *adap)
|
||
|
|
{
|
||
|
|
return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
|
||
|
|
I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
|
||
|
|
I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
|
||
|
|
I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct i2c_algorithm bfin_twi_algorithm = {
|
||
|
|
.master_xfer = bfin_twi_master_xfer,
|
||
|
|
.smbus_xfer = bfin_twi_smbus_xfer,
|
||
|
|
.functionality = bfin_twi_functionality,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
|
||
|
|
{
|
||
|
|
struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
|
||
|
|
|
||
|
|
iface->saved_clkdiv = read_CLKDIV(iface);
|
||
|
|
iface->saved_control = read_CONTROL(iface);
|
||
|
|
|
||
|
|
free_irq(iface->irq, iface);
|
||
|
|
|
||
|
|
/* Disable TWI */
|
||
|
|
write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int i2c_bfin_twi_resume(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
|
||
|
|
|
||
|
|
int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
|
||
|
|
IRQF_DISABLED, pdev->name, iface);
|
||
|
|
if (rc) {
|
||
|
|
dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Resume TWI interface clock as specified */
|
||
|
|
write_CLKDIV(iface, iface->saved_clkdiv);
|
||
|
|
|
||
|
|
/* Resume TWI */
|
||
|
|
write_CONTROL(iface, iface->saved_control);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int i2c_bfin_twi_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct bfin_twi_iface *iface;
|
||
|
|
struct i2c_adapter *p_adap;
|
||
|
|
struct resource *res;
|
||
|
|
int rc;
|
||
|
|
unsigned int clkhilow;
|
||
|
|
|
||
|
|
iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
|
||
|
|
if (!iface) {
|
||
|
|
dev_err(&pdev->dev, "Cannot allocate memory\n");
|
||
|
|
rc = -ENOMEM;
|
||
|
|
goto out_error_nomem;
|
||
|
|
}
|
||
|
|
|
||
|
|
spin_lock_init(&(iface->lock));
|
||
|
|
|
||
|
|
/* Find and map our resources */
|
||
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||
|
|
if (res == NULL) {
|
||
|
|
dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
|
||
|
|
rc = -ENOENT;
|
||
|
|
goto out_error_get_res;
|
||
|
|
}
|
||
|
|
|
||
|
|
iface->regs_base = ioremap(res->start, resource_size(res));
|
||
|
|
if (iface->regs_base == NULL) {
|
||
|
|
dev_err(&pdev->dev, "Cannot map IO\n");
|
||
|
|
rc = -ENXIO;
|
||
|
|
goto out_error_ioremap;
|
||
|
|
}
|
||
|
|
|
||
|
|
iface->irq = platform_get_irq(pdev, 0);
|
||
|
|
if (iface->irq < 0) {
|
||
|
|
dev_err(&pdev->dev, "No IRQ specified\n");
|
||
|
|
rc = -ENOENT;
|
||
|
|
goto out_error_no_irq;
|
||
|
|
}
|
||
|
|
|
||
|
|
init_timer(&(iface->timeout_timer));
|
||
|
|
iface->timeout_timer.function = bfin_twi_timeout;
|
||
|
|
iface->timeout_timer.data = (unsigned long)iface;
|
||
|
|
|
||
|
|
p_adap = &iface->adap;
|
||
|
|
p_adap->nr = pdev->id;
|
||
|
|
strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
|
||
|
|
p_adap->algo = &bfin_twi_algorithm;
|
||
|
|
p_adap->algo_data = iface;
|
||
|
|
p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
|
||
|
|
p_adap->dev.parent = &pdev->dev;
|
||
|
|
|
||
|
|
rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
|
||
|
|
if (rc) {
|
||
|
|
dev_err(&pdev->dev, "Can't setup pin mux!\n");
|
||
|
|
goto out_error_pin_mux;
|
||
|
|
}
|
||
|
|
|
||
|
|
rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
|
||
|
|
IRQF_DISABLED, pdev->name, iface);
|
||
|
|
if (rc) {
|
||
|
|
dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
|
||
|
|
rc = -ENODEV;
|
||
|
|
goto out_error_req_irq;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set TWI internal clock as 10MHz */
|
||
|
|
write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* We will not end up with a CLKDIV=0 because no one will specify
|
||
|
|
* 20kHz SCL or less in Kconfig now. (5 * 1024 / 20 = 0x100)
|
||
|
|
*/
|
||
|
|
clkhilow = 5 * 1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ;
|
||
|
|
|
||
|
|
/* Set Twi interface clock as specified */
|
||
|
|
write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
|
||
|
|
|
||
|
|
/* Enable TWI */
|
||
|
|
write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
|
||
|
|
SSYNC();
|
||
|
|
|
||
|
|
rc = i2c_add_numbered_adapter(p_adap);
|
||
|
|
if (rc < 0) {
|
||
|
|
dev_err(&pdev->dev, "Can't add i2c adapter!\n");
|
||
|
|
goto out_error_add_adapter;
|
||
|
|
}
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, iface);
|
||
|
|
|
||
|
|
dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
|
||
|
|
"regs_base@%p\n", iface->regs_base);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
out_error_add_adapter:
|
||
|
|
free_irq(iface->irq, iface);
|
||
|
|
out_error_req_irq:
|
||
|
|
out_error_no_irq:
|
||
|
|
peripheral_free_list(pin_req[pdev->id]);
|
||
|
|
out_error_pin_mux:
|
||
|
|
iounmap(iface->regs_base);
|
||
|
|
out_error_ioremap:
|
||
|
|
out_error_get_res:
|
||
|
|
kfree(iface);
|
||
|
|
out_error_nomem:
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int i2c_bfin_twi_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, NULL);
|
||
|
|
|
||
|
|
i2c_del_adapter(&(iface->adap));
|
||
|
|
free_irq(iface->irq, iface);
|
||
|
|
peripheral_free_list(pin_req[pdev->id]);
|
||
|
|
iounmap(iface->regs_base);
|
||
|
|
kfree(iface);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver i2c_bfin_twi_driver = {
|
||
|
|
.probe = i2c_bfin_twi_probe,
|
||
|
|
.remove = i2c_bfin_twi_remove,
|
||
|
|
.suspend = i2c_bfin_twi_suspend,
|
||
|
|
.resume = i2c_bfin_twi_resume,
|
||
|
|
.driver = {
|
||
|
|
.name = "i2c-bfin-twi",
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init i2c_bfin_twi_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&i2c_bfin_twi_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __exit i2c_bfin_twi_exit(void)
|
||
|
|
{
|
||
|
|
platform_driver_unregister(&i2c_bfin_twi_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
module_init(i2c_bfin_twi_init);
|
||
|
|
module_exit(i2c_bfin_twi_exit);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
|
||
|
|
MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
|
||
|
|
MODULE_LICENSE("GPL");
|
||
|
|
MODULE_ALIAS("platform:i2c-bfin-twi");
|