417 lines
12 KiB
C
417 lines
12 KiB
C
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/***************************************************************************\
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|* *|
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|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
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|* *|
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|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
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|* international laws. Users and possessors of this source code are *|
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|* hereby granted a nonexclusive, royalty-free copyright license to *|
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|* use this code in individual and commercial software. *|
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|* *|
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|* Any use of this source code must include, in the user documenta- *|
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|* tion and internal comments to the code, notices to the end user *|
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|* as follows: *|
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|* *|
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|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
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|* *|
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|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
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|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
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|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
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|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
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|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
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|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
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|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
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|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
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|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
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|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
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|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
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|* *|
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|* U.S. Government End Users. This source code is a "commercial *|
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|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
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|* consisting of "commercial computer software" and "commercial *|
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|* computer software documentation," as such terms are used in *|
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|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
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|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
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|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
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|* all U.S. Government End Users acquire the source code with only *|
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|* those rights set forth herein. *|
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|* *|
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\***************************************************************************/
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/*
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* GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
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* XFree86 'nv' driver, this source code is provided under MIT-style licensing
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* where the source code is provided "as is" without warranty of any kind.
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* The only usage restriction is for the copyright notices to be retained
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* whenever code is used.
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*
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* Antonino Daplas <adaplas@pol.net> 2005-03-11
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*/
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#include <linux/fb.h>
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#include "nv_type.h"
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#include "nv_proto.h"
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#include "nv_dma.h"
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#include "nv_local.h"
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/* There is a HW race condition with videoram command buffers.
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You can't jump to the location of your put offset. We write put
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at the jump offset + SKIPS dwords with noop padding in between
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to solve this problem */
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#define SKIPS 8
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static const int NVCopyROP[16] = {
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0xCC, /* copy */
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0x55 /* invert */
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};
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static const int NVCopyROP_PM[16] = {
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0xCA, /* copy */
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0x5A, /* invert */
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};
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static inline void nvidiafb_safe_mode(struct fb_info *info)
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{
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struct nvidia_par *par = info->par;
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touch_softlockup_watchdog();
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info->pixmap.scan_align = 1;
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par->lockup = 1;
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}
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static inline void NVFlush(struct fb_info *info)
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{
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struct nvidia_par *par = info->par;
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int count = 1000000000;
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while (--count && READ_GET(par) != par->dmaPut) ;
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if (!count) {
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printk("nvidiafb: DMA Flush lockup\n");
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nvidiafb_safe_mode(info);
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}
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}
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static inline void NVSync(struct fb_info *info)
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{
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struct nvidia_par *par = info->par;
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int count = 1000000000;
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while (--count && NV_RD32(par->PGRAPH, 0x0700)) ;
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if (!count) {
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printk("nvidiafb: DMA Sync lockup\n");
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nvidiafb_safe_mode(info);
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}
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}
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static void NVDmaKickoff(struct nvidia_par *par)
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{
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if (par->dmaCurrent != par->dmaPut) {
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par->dmaPut = par->dmaCurrent;
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WRITE_PUT(par, par->dmaPut);
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}
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}
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static void NVDmaWait(struct fb_info *info, int size)
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{
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struct nvidia_par *par = info->par;
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int dmaGet;
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int count = 1000000000, cnt;
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size++;
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while (par->dmaFree < size && --count && !par->lockup) {
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dmaGet = READ_GET(par);
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if (par->dmaPut >= dmaGet) {
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par->dmaFree = par->dmaMax - par->dmaCurrent;
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if (par->dmaFree < size) {
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NVDmaNext(par, 0x20000000);
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if (dmaGet <= SKIPS) {
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if (par->dmaPut <= SKIPS)
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WRITE_PUT(par, SKIPS + 1);
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cnt = 1000000000;
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do {
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dmaGet = READ_GET(par);
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} while (--cnt && dmaGet <= SKIPS);
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if (!cnt) {
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printk("DMA Get lockup\n");
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par->lockup = 1;
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}
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}
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WRITE_PUT(par, SKIPS);
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par->dmaCurrent = par->dmaPut = SKIPS;
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par->dmaFree = dmaGet - (SKIPS + 1);
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}
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} else
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par->dmaFree = dmaGet - par->dmaCurrent - 1;
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}
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if (!count) {
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printk("nvidiafb: DMA Wait Lockup\n");
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nvidiafb_safe_mode(info);
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}
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}
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static void NVSetPattern(struct fb_info *info, u32 clr0, u32 clr1,
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u32 pat0, u32 pat1)
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{
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struct nvidia_par *par = info->par;
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NVDmaStart(info, par, PATTERN_COLOR_0, 4);
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NVDmaNext(par, clr0);
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NVDmaNext(par, clr1);
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NVDmaNext(par, pat0);
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NVDmaNext(par, pat1);
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}
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static void NVSetRopSolid(struct fb_info *info, u32 rop, u32 planemask)
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{
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struct nvidia_par *par = info->par;
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if (planemask != ~0) {
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NVSetPattern(info, 0, planemask, ~0, ~0);
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if (par->currentRop != (rop + 32)) {
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NVDmaStart(info, par, ROP_SET, 1);
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NVDmaNext(par, NVCopyROP_PM[rop]);
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par->currentRop = rop + 32;
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}
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} else if (par->currentRop != rop) {
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if (par->currentRop >= 16)
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NVSetPattern(info, ~0, ~0, ~0, ~0);
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NVDmaStart(info, par, ROP_SET, 1);
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NVDmaNext(par, NVCopyROP[rop]);
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par->currentRop = rop;
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}
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}
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static void NVSetClippingRectangle(struct fb_info *info, int x1, int y1,
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int x2, int y2)
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{
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struct nvidia_par *par = info->par;
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int h = y2 - y1 + 1;
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int w = x2 - x1 + 1;
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NVDmaStart(info, par, CLIP_POINT, 2);
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NVDmaNext(par, (y1 << 16) | x1);
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NVDmaNext(par, (h << 16) | w);
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}
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void NVResetGraphics(struct fb_info *info)
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{
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struct nvidia_par *par = info->par;
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u32 surfaceFormat, patternFormat, rectFormat, lineFormat;
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int pitch, i;
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pitch = info->fix.line_length;
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par->dmaBase = (u32 __iomem *) (&par->FbStart[par->FbUsableSize]);
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for (i = 0; i < SKIPS; i++)
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NV_WR32(&par->dmaBase[i], 0, 0x00000000);
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NV_WR32(&par->dmaBase[0x0 + SKIPS], 0, 0x00040000);
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NV_WR32(&par->dmaBase[0x1 + SKIPS], 0, 0x80000010);
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NV_WR32(&par->dmaBase[0x2 + SKIPS], 0, 0x00042000);
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NV_WR32(&par->dmaBase[0x3 + SKIPS], 0, 0x80000011);
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NV_WR32(&par->dmaBase[0x4 + SKIPS], 0, 0x00044000);
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NV_WR32(&par->dmaBase[0x5 + SKIPS], 0, 0x80000012);
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NV_WR32(&par->dmaBase[0x6 + SKIPS], 0, 0x00046000);
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NV_WR32(&par->dmaBase[0x7 + SKIPS], 0, 0x80000013);
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NV_WR32(&par->dmaBase[0x8 + SKIPS], 0, 0x00048000);
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NV_WR32(&par->dmaBase[0x9 + SKIPS], 0, 0x80000014);
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NV_WR32(&par->dmaBase[0xA + SKIPS], 0, 0x0004A000);
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NV_WR32(&par->dmaBase[0xB + SKIPS], 0, 0x80000015);
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NV_WR32(&par->dmaBase[0xC + SKIPS], 0, 0x0004C000);
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NV_WR32(&par->dmaBase[0xD + SKIPS], 0, 0x80000016);
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NV_WR32(&par->dmaBase[0xE + SKIPS], 0, 0x0004E000);
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NV_WR32(&par->dmaBase[0xF + SKIPS], 0, 0x80000017);
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par->dmaPut = 0;
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par->dmaCurrent = 16 + SKIPS;
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par->dmaMax = 8191;
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par->dmaFree = par->dmaMax - par->dmaCurrent;
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switch (info->var.bits_per_pixel) {
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case 32:
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case 24:
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surfaceFormat = SURFACE_FORMAT_DEPTH24;
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patternFormat = PATTERN_FORMAT_DEPTH24;
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rectFormat = RECT_FORMAT_DEPTH24;
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lineFormat = LINE_FORMAT_DEPTH24;
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break;
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case 16:
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surfaceFormat = SURFACE_FORMAT_DEPTH16;
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patternFormat = PATTERN_FORMAT_DEPTH16;
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rectFormat = RECT_FORMAT_DEPTH16;
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lineFormat = LINE_FORMAT_DEPTH16;
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break;
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default:
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surfaceFormat = SURFACE_FORMAT_DEPTH8;
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patternFormat = PATTERN_FORMAT_DEPTH8;
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rectFormat = RECT_FORMAT_DEPTH8;
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lineFormat = LINE_FORMAT_DEPTH8;
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break;
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}
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NVDmaStart(info, par, SURFACE_FORMAT, 4);
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NVDmaNext(par, surfaceFormat);
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NVDmaNext(par, pitch | (pitch << 16));
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NVDmaNext(par, 0);
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NVDmaNext(par, 0);
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NVDmaStart(info, par, PATTERN_FORMAT, 1);
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NVDmaNext(par, patternFormat);
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NVDmaStart(info, par, RECT_FORMAT, 1);
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NVDmaNext(par, rectFormat);
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NVDmaStart(info, par, LINE_FORMAT, 1);
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NVDmaNext(par, lineFormat);
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par->currentRop = ~0; /* set to something invalid */
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NVSetRopSolid(info, ROP_COPY, ~0);
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NVSetClippingRectangle(info, 0, 0, info->var.xres_virtual,
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info->var.yres_virtual);
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NVDmaKickoff(par);
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}
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int nvidiafb_sync(struct fb_info *info)
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{
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struct nvidia_par *par = info->par;
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if (info->state != FBINFO_STATE_RUNNING)
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return 0;
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if (!par->lockup)
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NVFlush(info);
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if (!par->lockup)
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NVSync(info);
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return 0;
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}
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void nvidiafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
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{
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struct nvidia_par *par = info->par;
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if (info->state != FBINFO_STATE_RUNNING)
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return;
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if (par->lockup) {
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cfb_copyarea(info, region);
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return;
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}
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NVDmaStart(info, par, BLIT_POINT_SRC, 3);
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NVDmaNext(par, (region->sy << 16) | region->sx);
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NVDmaNext(par, (region->dy << 16) | region->dx);
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NVDmaNext(par, (region->height << 16) | region->width);
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NVDmaKickoff(par);
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}
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void nvidiafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
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{
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struct nvidia_par *par = info->par;
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u32 color;
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if (info->state != FBINFO_STATE_RUNNING)
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return;
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if (par->lockup) {
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cfb_fillrect(info, rect);
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return;
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}
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if (info->var.bits_per_pixel == 8)
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color = rect->color;
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else
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color = ((u32 *) info->pseudo_palette)[rect->color];
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if (rect->rop != ROP_COPY)
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NVSetRopSolid(info, rect->rop, ~0);
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NVDmaStart(info, par, RECT_SOLID_COLOR, 1);
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NVDmaNext(par, color);
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NVDmaStart(info, par, RECT_SOLID_RECTS(0), 2);
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NVDmaNext(par, (rect->dx << 16) | rect->dy);
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NVDmaNext(par, (rect->width << 16) | rect->height);
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NVDmaKickoff(par);
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if (rect->rop != ROP_COPY)
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NVSetRopSolid(info, ROP_COPY, ~0);
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}
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static void nvidiafb_mono_color_expand(struct fb_info *info,
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const struct fb_image *image)
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{
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struct nvidia_par *par = info->par;
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u32 fg, bg, mask = ~(~0 >> (32 - info->var.bits_per_pixel));
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||
|
|
u32 dsize, width, *data = (u32 *) image->data, tmp;
|
||
|
|
int j, k = 0;
|
||
|
|
|
||
|
|
width = (image->width + 31) & ~31;
|
||
|
|
dsize = (width * image->height) >> 5;
|
||
|
|
|
||
|
|
if (info->var.bits_per_pixel == 8) {
|
||
|
|
fg = image->fg_color | mask;
|
||
|
|
bg = image->bg_color | mask;
|
||
|
|
} else {
|
||
|
|
fg = ((u32 *) info->pseudo_palette)[image->fg_color] | mask;
|
||
|
|
bg = ((u32 *) info->pseudo_palette)[image->bg_color] | mask;
|
||
|
|
}
|
||
|
|
|
||
|
|
NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_CLIP, 7);
|
||
|
|
NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
|
||
|
|
NVDmaNext(par, ((image->dy + image->height) << 16) |
|
||
|
|
((image->dx + image->width) & 0xffff));
|
||
|
|
NVDmaNext(par, bg);
|
||
|
|
NVDmaNext(par, fg);
|
||
|
|
NVDmaNext(par, (image->height << 16) | width);
|
||
|
|
NVDmaNext(par, (image->height << 16) | width);
|
||
|
|
NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
|
||
|
|
|
||
|
|
while (dsize >= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS) {
|
||
|
|
NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0),
|
||
|
|
RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS);
|
||
|
|
|
||
|
|
for (j = RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS; j--;) {
|
||
|
|
tmp = data[k++];
|
||
|
|
reverse_order(&tmp);
|
||
|
|
NVDmaNext(par, tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
dsize -= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (dsize) {
|
||
|
|
NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0), dsize);
|
||
|
|
|
||
|
|
for (j = dsize; j--;) {
|
||
|
|
tmp = data[k++];
|
||
|
|
reverse_order(&tmp);
|
||
|
|
NVDmaNext(par, tmp);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
NVDmaKickoff(par);
|
||
|
|
}
|
||
|
|
|
||
|
|
void nvidiafb_imageblit(struct fb_info *info, const struct fb_image *image)
|
||
|
|
{
|
||
|
|
struct nvidia_par *par = info->par;
|
||
|
|
|
||
|
|
if (info->state != FBINFO_STATE_RUNNING)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (image->depth == 1 && !par->lockup)
|
||
|
|
nvidiafb_mono_color_expand(info, image);
|
||
|
|
else
|
||
|
|
cfb_imageblit(info, image);
|
||
|
|
}
|