47 lines
1.0 KiB
C
47 lines
1.0 KiB
C
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#ifndef __ASM_CPU_SH3_DMA_H
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#define __ASM_CPU_SH3_DMA_H
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#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721) || \
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defined(CONFIG_CPU_SUBTYPE_SH7710) || \
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defined(CONFIG_CPU_SUBTYPE_SH7712)
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#define SH_DMAC_BASE0 0xa4010020
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#else /* SH7705/06/07/09 */
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#define SH_DMAC_BASE0 0xa4000020
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#endif
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#define DMTE0_IRQ 48
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#define DMTE4_IRQ 76
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/* Definitions for the SuperH DMAC */
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#define TM_BURST 0x00000020
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#define TS_8 0x00000000
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#define TS_16 0x00000008
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#define TS_32 0x00000010
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#define TS_128 0x00000018
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#define CHCR_TS_MASK 0x18
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#define CHCR_TS_SHIFT 3
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#define DMAOR_INIT DMAOR_DME
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/*
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* The SuperH DMAC supports a number of transmit sizes, we list them here,
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* with their respective values as they appear in the CHCR registers.
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*/
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enum {
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XMIT_SZ_8BIT,
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XMIT_SZ_16BIT,
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XMIT_SZ_32BIT,
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XMIT_SZ_128BIT,
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};
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static unsigned int ts_shift[] __maybe_unused = {
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[XMIT_SZ_8BIT] = 0,
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[XMIT_SZ_16BIT] = 1,
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[XMIT_SZ_32BIT] = 2,
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[XMIT_SZ_128BIT] = 4,
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};
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#endif /* __ASM_CPU_SH3_DMA_H */
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