440 lines
11 KiB
C
440 lines
11 KiB
C
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/*
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* arch/arm/mach-ixp23xx/core.c
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*
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* Core routines for IXP23xx chips
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*
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* Author: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright 2005 (c) MontaVista Software, Inc.
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*
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* Based on 2.4 code Copyright 2004 (c) Intel Corporation
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/serial.h>
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#include <linux/tty.h>
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#include <linux/bitops.h>
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#include <linux/serial_8250.h>
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#include <linux/serial_core.h>
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#include <linux/device.h>
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#include <linux/mm.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <asm/types.h>
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#include <asm/setup.h>
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#include <asm/memory.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/tlbflush.h>
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#include <asm/pgtable.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/arch.h>
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/*************************************************************************
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* Chip specific mappings shared by all IXP23xx systems
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*************************************************************************/
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static struct map_desc ixp23xx_io_desc[] __initdata = {
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{ /* XSI-CPP CSRs */
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.virtual = IXP23XX_XSI2CPP_CSR_VIRT,
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.pfn = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS),
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.length = IXP23XX_XSI2CPP_CSR_SIZE,
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.type = MT_DEVICE,
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}, { /* Expansion Bus Config */
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.virtual = IXP23XX_EXP_CFG_VIRT,
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.pfn = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS),
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.length = IXP23XX_EXP_CFG_SIZE,
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.type = MT_DEVICE,
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}, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */
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.virtual = IXP23XX_PERIPHERAL_VIRT,
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.pfn = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS),
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.length = IXP23XX_PERIPHERAL_SIZE,
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.type = MT_DEVICE,
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}, { /* CAP CSRs */
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.virtual = IXP23XX_CAP_CSR_VIRT,
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.pfn = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS),
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.length = IXP23XX_CAP_CSR_SIZE,
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.type = MT_DEVICE,
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}, { /* MSF CSRs */
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.virtual = IXP23XX_MSF_CSR_VIRT,
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.pfn = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
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.length = IXP23XX_MSF_CSR_SIZE,
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.type = MT_DEVICE,
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}, { /* PCI I/O Space */
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.virtual = IXP23XX_PCI_IO_VIRT,
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.pfn = __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
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.length = IXP23XX_PCI_IO_SIZE,
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.type = MT_DEVICE,
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}, { /* PCI Config Space */
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.virtual = IXP23XX_PCI_CFG_VIRT,
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.pfn = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
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.length = IXP23XX_PCI_CFG_SIZE,
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.type = MT_DEVICE,
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}, { /* PCI local CFG CSRs */
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.virtual = IXP23XX_PCI_CREG_VIRT,
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.pfn = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS),
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.length = IXP23XX_PCI_CREG_SIZE,
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.type = MT_DEVICE,
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}, { /* PCI MEM Space */
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.virtual = IXP23XX_PCI_MEM_VIRT,
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.pfn = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS),
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.length = IXP23XX_PCI_MEM_SIZE,
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.type = MT_DEVICE,
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}
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};
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void __init ixp23xx_map_io(void)
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{
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iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
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}
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/***************************************************************************
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* IXP23xx Interrupt Handling
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***************************************************************************/
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enum ixp23xx_irq_type {
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IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE
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};
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static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
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static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
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{
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int line = irq - IRQ_IXP23XX_GPIO6 + 6;
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u32 int_style;
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enum ixp23xx_irq_type irq_type;
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volatile u32 *int_reg;
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/*
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* Only GPIOs 6-15 are wired to interrupts on IXP23xx
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*/
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if (line < 6 || line > 15)
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return -EINVAL;
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
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irq_type = IXP23XX_IRQ_EDGE;
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break;
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case IRQ_TYPE_EDGE_RISING:
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int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
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irq_type = IXP23XX_IRQ_EDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
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irq_type = IXP23XX_IRQ_EDGE;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
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irq_type = IXP23XX_IRQ_LEVEL;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
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irq_type = IXP23XX_IRQ_LEVEL;
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break;
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default:
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return -EINVAL;
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}
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ixp23xx_config_irq(irq, irq_type);
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if (line >= 8) { /* pins 8-15 */
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line -= 8;
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int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R;
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} else { /* pins 0-7 */
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int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R;
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}
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/*
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* Clear pending interrupts
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*/
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*IXP23XX_GPIO_GPISR = (1 << line);
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/* Clear the style for the appropriate pin */
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*int_reg &= ~(IXP23XX_GPIO_STYLE_MASK <<
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(line * IXP23XX_GPIO_STYLE_SIZE));
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/* Set the new style */
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*int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE));
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return 0;
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}
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static void ixp23xx_irq_mask(unsigned int irq)
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{
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volatile unsigned long *intr_reg;
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if (irq >= 56)
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irq += 8;
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intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
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*intr_reg &= ~(1 << (irq % 32));
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}
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static void ixp23xx_irq_ack(unsigned int irq)
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{
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int line = irq - IRQ_IXP23XX_GPIO6 + 6;
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if ((line < 6) || (line > 15))
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return;
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*IXP23XX_GPIO_GPISR = (1 << line);
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}
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/*
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* Level triggered interrupts on GPIO lines can only be cleared when the
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* interrupt condition disappears.
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*/
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static void ixp23xx_irq_level_unmask(unsigned int irq)
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{
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volatile unsigned long *intr_reg;
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ixp23xx_irq_ack(irq);
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if (irq >= 56)
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irq += 8;
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intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
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*intr_reg |= (1 << (irq % 32));
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}
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static void ixp23xx_irq_edge_unmask(unsigned int irq)
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{
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volatile unsigned long *intr_reg;
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if (irq >= 56)
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irq += 8;
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intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
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*intr_reg |= (1 << (irq % 32));
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}
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static struct irq_chip ixp23xx_irq_level_chip = {
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.ack = ixp23xx_irq_mask,
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.mask = ixp23xx_irq_mask,
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.unmask = ixp23xx_irq_level_unmask,
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.set_type = ixp23xx_irq_set_type
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};
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static struct irq_chip ixp23xx_irq_edge_chip = {
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.ack = ixp23xx_irq_ack,
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.mask = ixp23xx_irq_mask,
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.unmask = ixp23xx_irq_edge_unmask,
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.set_type = ixp23xx_irq_set_type
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};
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static void ixp23xx_pci_irq_mask(unsigned int irq)
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{
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*IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
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}
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static void ixp23xx_pci_irq_unmask(unsigned int irq)
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{
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*IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
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}
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/*
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* TODO: Should this just be done at ASM level?
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*/
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static void pci_handler(unsigned int irq, struct irq_desc *desc)
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{
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u32 pci_interrupt;
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unsigned int irqno;
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pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
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desc->chip->ack(irq);
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/* See which PCI_INTA, or PCI_INTB interrupted */
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if (pci_interrupt & (1 << 26)) {
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irqno = IRQ_IXP23XX_INTB;
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} else if (pci_interrupt & (1 << 27)) {
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irqno = IRQ_IXP23XX_INTA;
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} else {
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BUG();
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}
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generic_handle_irq(irqno);
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desc->chip->unmask(irq);
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}
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static struct irq_chip ixp23xx_pci_irq_chip = {
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.ack = ixp23xx_pci_irq_mask,
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.mask = ixp23xx_pci_irq_mask,
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.unmask = ixp23xx_pci_irq_unmask
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};
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static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
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{
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switch (type) {
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case IXP23XX_IRQ_LEVEL:
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set_irq_chip(irq, &ixp23xx_irq_level_chip);
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set_irq_handler(irq, handle_level_irq);
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break;
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case IXP23XX_IRQ_EDGE:
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set_irq_chip(irq, &ixp23xx_irq_edge_chip);
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set_irq_handler(irq, handle_edge_irq);
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break;
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}
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set_irq_flags(irq, IRQF_VALID);
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}
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void __init ixp23xx_init_irq(void)
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{
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int irq;
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/* Route everything to IRQ */
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*IXP23XX_INTR_SEL1 = 0x0;
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*IXP23XX_INTR_SEL2 = 0x0;
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*IXP23XX_INTR_SEL3 = 0x0;
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*IXP23XX_INTR_SEL4 = 0x0;
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/* Mask all sources */
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*IXP23XX_INTR_EN1 = 0x0;
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*IXP23XX_INTR_EN2 = 0x0;
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*IXP23XX_INTR_EN3 = 0x0;
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*IXP23XX_INTR_EN4 = 0x0;
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/*
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* Configure all IRQs for level-sensitive operation
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*/
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for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
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ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
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}
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for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
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set_irq_chip(irq, &ixp23xx_pci_irq_chip);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
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}
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/*************************************************************************
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* Timer-tick functions for IXP23xx
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*************************************************************************/
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#define CLOCK_TICKS_PER_USEC (CLOCK_TICK_RATE / USEC_PER_SEC)
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static unsigned long next_jiffy_time;
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static unsigned long
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ixp23xx_gettimeoffset(void)
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{
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unsigned long elapsed;
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elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH);
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return elapsed / CLOCK_TICKS_PER_USEC;
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}
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static irqreturn_t
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ixp23xx_timer_interrupt(int irq, void *dev_id)
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{
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/* Clear Pending Interrupt by writing '1' to it */
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*IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
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while ((signed long)(*IXP23XX_TIMER_CONT - next_jiffy_time) >= LATCH) {
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timer_tick();
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next_jiffy_time += LATCH;
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}
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return IRQ_HANDLED;
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}
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static struct irqaction ixp23xx_timer_irq = {
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.name = "IXP23xx Timer Tick",
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||
|
|
.handler = ixp23xx_timer_interrupt,
|
||
|
|
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
|
||
|
|
};
|
||
|
|
|
||
|
|
void __init ixp23xx_init_timer(void)
|
||
|
|
{
|
||
|
|
/* Clear Pending Interrupt by writing '1' to it */
|
||
|
|
*IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
|
||
|
|
|
||
|
|
/* Setup the Timer counter value */
|
||
|
|
*IXP23XX_TIMER1_RELOAD =
|
||
|
|
(LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE;
|
||
|
|
|
||
|
|
*IXP23XX_TIMER_CONT = 0;
|
||
|
|
next_jiffy_time = LATCH;
|
||
|
|
|
||
|
|
/* Connect the interrupt handler and enable the interrupt */
|
||
|
|
setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq);
|
||
|
|
}
|
||
|
|
|
||
|
|
struct sys_timer ixp23xx_timer = {
|
||
|
|
.init = ixp23xx_init_timer,
|
||
|
|
.offset = ixp23xx_gettimeoffset,
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
/*************************************************************************
|
||
|
|
* IXP23xx Platform Initialization
|
||
|
|
*************************************************************************/
|
||
|
|
static struct resource ixp23xx_uart_resources[] = {
|
||
|
|
{
|
||
|
|
.start = IXP23XX_UART1_PHYS,
|
||
|
|
.end = IXP23XX_UART1_PHYS + 0x0fff,
|
||
|
|
.flags = IORESOURCE_MEM
|
||
|
|
}, {
|
||
|
|
.start = IXP23XX_UART2_PHYS,
|
||
|
|
.end = IXP23XX_UART2_PHYS + 0x0fff,
|
||
|
|
.flags = IORESOURCE_MEM
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct plat_serial8250_port ixp23xx_uart_data[] = {
|
||
|
|
{
|
||
|
|
.mapbase = IXP23XX_UART1_PHYS,
|
||
|
|
.membase = (char *)(IXP23XX_UART1_VIRT + 3),
|
||
|
|
.irq = IRQ_IXP23XX_UART1,
|
||
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
|
||
|
|
.iotype = UPIO_MEM,
|
||
|
|
.regshift = 2,
|
||
|
|
.uartclk = IXP23XX_UART_XTAL,
|
||
|
|
}, {
|
||
|
|
.mapbase = IXP23XX_UART2_PHYS,
|
||
|
|
.membase = (char *)(IXP23XX_UART2_VIRT + 3),
|
||
|
|
.irq = IRQ_IXP23XX_UART2,
|
||
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
|
||
|
|
.iotype = UPIO_MEM,
|
||
|
|
.regshift = 2,
|
||
|
|
.uartclk = IXP23XX_UART_XTAL,
|
||
|
|
},
|
||
|
|
{ },
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device ixp23xx_uart = {
|
||
|
|
.name = "serial8250",
|
||
|
|
.id = 0,
|
||
|
|
.dev.platform_data = ixp23xx_uart_data,
|
||
|
|
.num_resources = 2,
|
||
|
|
.resource = ixp23xx_uart_resources,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device *ixp23xx_devices[] __initdata = {
|
||
|
|
&ixp23xx_uart,
|
||
|
|
};
|
||
|
|
|
||
|
|
void __init ixp23xx_sys_init(void)
|
||
|
|
{
|
||
|
|
*IXP23XX_EXP_UNIT_FUSE |= 0xf;
|
||
|
|
platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
|
||
|
|
}
|