139 lines
5.6 KiB
C
139 lines
5.6 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 - 2002 by Ralf Baechle
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* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
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* Copyright (C) 2002 Maciej W. Rozycki
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*/
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#ifndef _ASM_PGTABLE_BITS_H
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#define _ASM_PGTABLE_BITS_H
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/*
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* Note that we shift the lower 32bits of each EntryLo[01] entry
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* 6 bits to the left. That way we can convert the PFN into the
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* physical address by a single 'and' operation and gain 6 additional
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* bits for storing information which isn't present in a normal
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* MIPS page table.
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*
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* Similar to the Alpha port, we need to keep track of the ref
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* and mod bits in software. We have a software "yeah you can read
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* from this page" bit, and a hardware one which actually lets the
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* process read from the page. On the same token we have a software
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* writable bit and the real hardware one which actually lets the
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* process write to the page, this keeps a mod bit via the hardware
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* dirty bit.
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*
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* Certain revisions of the R4000 and R5000 have a bug where if a
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* certain sequence occurs in the last 3 instructions of an executable
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* page, and the following page is not mapped, the cpu can do
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* unpredictable things. The code (when it is written) to deal with
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* this problem will be in the update_mmu_cache() code for the r4k.
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*/
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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#define _PAGE_PRESENT (1<<6) /* implemented in software */
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#define _PAGE_READ (1<<7) /* implemented in software */
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#define _PAGE_WRITE (1<<8) /* implemented in software */
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#define _PAGE_ACCESSED (1<<9) /* implemented in software */
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#define _PAGE_MODIFIED (1<<10) /* implemented in software */
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#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */
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#define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */
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#define _PAGE_GLOBAL (1<<0)
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#define _PAGE_VALID (1<<1)
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#define _PAGE_SILENT_READ (1<<1) /* synonym */
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#define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */
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#define _PAGE_SILENT_WRITE (1<<2)
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#define _CACHE_SHIFT 3
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#define _CACHE_MASK (7<<3)
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#else
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#define _PAGE_PRESENT (1<<0) /* implemented in software */
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#define _PAGE_READ (1<<1) /* implemented in software */
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#define _PAGE_WRITE (1<<2) /* implemented in software */
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#define _PAGE_ACCESSED (1<<3) /* implemented in software */
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#define _PAGE_MODIFIED (1<<4) /* implemented in software */
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#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define _PAGE_GLOBAL (1<<8)
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#define _PAGE_VALID (1<<9)
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#define _PAGE_SILENT_READ (1<<9) /* synonym */
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#define _PAGE_DIRTY (1<<10) /* The MIPS dirty bit */
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#define _PAGE_SILENT_WRITE (1<<10)
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#define _CACHE_UNCACHED (1<<11)
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#define _CACHE_MASK (1<<11)
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#else
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#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */
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#define _PAGE_HUGE (1<<5) /* huge tlb page */
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#define _PAGE_GLOBAL (1<<6)
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#define _PAGE_VALID (1<<7)
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#define _PAGE_SILENT_READ (1<<7) /* synonym */
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#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */
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#define _PAGE_SILENT_WRITE (1<<8)
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#define _CACHE_SHIFT 9
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#define _CACHE_MASK (7<<9)
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#endif
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#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
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/*
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* Cache attributes
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*/
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define _CACHE_CACHABLE_NONCOHERENT 0
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#elif defined(CONFIG_CPU_SB1)
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/* No penalty for being coherent on the SB1, so just
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use it for "noncoherent" spaces, too. Shouldn't hurt. */
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#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
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#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
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#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
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#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
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#elif defined(CONFIG_CPU_RM9000)
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#define _CACHE_WT (0<<_CACHE_SHIFT)
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#define _CACHE_WTWA (1<<_CACHE_SHIFT)
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#define _CACHE_UC_B (2<<_CACHE_SHIFT)
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#define _CACHE_WB (3<<_CACHE_SHIFT)
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#define _CACHE_CWBEA (4<<_CACHE_SHIFT)
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#define _CACHE_CWB (5<<_CACHE_SHIFT)
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#define _CACHE_UCNB (6<<_CACHE_SHIFT)
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#define _CACHE_FPC (7<<_CACHE_SHIFT)
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#define _CACHE_UNCACHED _CACHE_UC_B
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#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
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#else
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#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */
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#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */
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#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */
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#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */
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#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */
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#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */
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#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */
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#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */
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#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */
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#endif
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#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
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#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
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#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
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#endif /* _ASM_PGTABLE_BITS_H */
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