559 lines
13 KiB
C
559 lines
13 KiB
C
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/*
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* Mips Jazz DMA controller support
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* Copyright (C) 1995, 1996 by Andreas Busse
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*
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* NOTE: Some of the argument checking could be removed when
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* things have settled down. Also, instead of returning 0xffffffff
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* on failure of vdma_alloc() one could leave page #0 unused
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* and return the more usual NULL pointer as logical address.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/mm.h>
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#include <linux/bootmem.h>
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#include <linux/spinlock.h>
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#include <asm/mipsregs.h>
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#include <asm/jazz.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/dma.h>
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#include <asm/jazzdma.h>
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#include <asm/pgtable.h>
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/*
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* Set this to one to enable additional vdma debug code.
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*/
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#define CONF_DEBUG_VDMA 0
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static VDMA_PGTBL_ENTRY *pgtbl;
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static DEFINE_SPINLOCK(vdma_lock);
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/*
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* Debug stuff
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*/
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#define vdma_debug ((CONF_DEBUG_VDMA) ? debuglvl : 0)
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static int debuglvl = 3;
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/*
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* Initialize the pagetable with a one-to-one mapping of
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* the first 16 Mbytes of main memory and declare all
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* entries to be unused. Using this method will at least
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* allow some early device driver operations to work.
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*/
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static inline void vdma_pgtbl_init(void)
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{
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unsigned long paddr = 0;
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int i;
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for (i = 0; i < VDMA_PGTBL_ENTRIES; i++) {
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pgtbl[i].frame = paddr;
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pgtbl[i].owner = VDMA_PAGE_EMPTY;
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paddr += VDMA_PAGESIZE;
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}
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}
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/*
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* Initialize the Jazz R4030 dma controller
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*/
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static int __init vdma_init(void)
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{
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/*
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* Allocate 32k of memory for DMA page tables. This needs to be page
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* aligned and should be uncached to avoid cache flushing after every
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* update.
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*/
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pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA,
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get_order(VDMA_PGTBL_SIZE));
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BUG_ON(!pgtbl);
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dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE);
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pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl);
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/*
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* Clear the R4030 translation table
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*/
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vdma_pgtbl_init();
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r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, CPHYSADDR(pgtbl));
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r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE);
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r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
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printk(KERN_INFO "VDMA: R4030 DMA pagetables initialized.\n");
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return 0;
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}
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/*
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* Allocate DMA pagetables using a simple first-fit algorithm
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*/
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unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
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{
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int first, last, pages, frame, i;
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unsigned long laddr, flags;
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/* check arguments */
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if (paddr > 0x1fffffff) {
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if (vdma_debug)
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printk("vdma_alloc: Invalid physical address: %08lx\n",
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paddr);
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return VDMA_ERROR; /* invalid physical address */
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}
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if (size > 0x400000 || size == 0) {
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if (vdma_debug)
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printk("vdma_alloc: Invalid size: %08lx\n", size);
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return VDMA_ERROR; /* invalid physical address */
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}
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spin_lock_irqsave(&vdma_lock, flags);
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/*
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* Find free chunk
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*/
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pages = VDMA_PAGE(paddr + size) - VDMA_PAGE(paddr) + 1;
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first = 0;
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while (1) {
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while (pgtbl[first].owner != VDMA_PAGE_EMPTY &&
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first < VDMA_PGTBL_ENTRIES) first++;
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if (first + pages > VDMA_PGTBL_ENTRIES) { /* nothing free */
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spin_unlock_irqrestore(&vdma_lock, flags);
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return VDMA_ERROR;
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}
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last = first + 1;
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while (pgtbl[last].owner == VDMA_PAGE_EMPTY
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&& last - first < pages)
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last++;
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if (last - first == pages)
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break; /* found */
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first = last + 1;
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}
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/*
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* Mark pages as allocated
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*/
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laddr = (first << 12) + (paddr & (VDMA_PAGESIZE - 1));
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frame = paddr & ~(VDMA_PAGESIZE - 1);
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for (i = first; i < last; i++) {
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pgtbl[i].frame = frame;
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pgtbl[i].owner = laddr;
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frame += VDMA_PAGESIZE;
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}
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/*
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* Update translation table and return logical start address
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*/
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r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
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if (vdma_debug > 1)
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printk("vdma_alloc: Allocated %d pages starting from %08lx\n",
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pages, laddr);
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if (vdma_debug > 2) {
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printk("LADDR: ");
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for (i = first; i < last; i++)
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printk("%08x ", i << 12);
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printk("\nPADDR: ");
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for (i = first; i < last; i++)
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printk("%08x ", pgtbl[i].frame);
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printk("\nOWNER: ");
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for (i = first; i < last; i++)
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printk("%08x ", pgtbl[i].owner);
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printk("\n");
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}
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spin_unlock_irqrestore(&vdma_lock, flags);
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return laddr;
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}
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EXPORT_SYMBOL(vdma_alloc);
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/*
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* Free previously allocated dma translation pages
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* Note that this does NOT change the translation table,
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* it just marks the free'd pages as unused!
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*/
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int vdma_free(unsigned long laddr)
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{
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int i;
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i = laddr >> 12;
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if (pgtbl[i].owner != laddr) {
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printk
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("vdma_free: trying to free other's dma pages, laddr=%8lx\n",
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laddr);
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return -1;
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}
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while (i < VDMA_PGTBL_ENTRIES && pgtbl[i].owner == laddr) {
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pgtbl[i].owner = VDMA_PAGE_EMPTY;
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i++;
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}
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if (vdma_debug > 1)
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printk("vdma_free: freed %ld pages starting from %08lx\n",
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i - (laddr >> 12), laddr);
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return 0;
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}
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EXPORT_SYMBOL(vdma_free);
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/*
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* Map certain page(s) to another physical address.
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* Caller must have allocated the page(s) before.
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*/
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int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size)
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{
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int first, pages, npages;
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if (laddr > 0xffffff) {
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if (vdma_debug)
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printk
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("vdma_map: Invalid logical address: %08lx\n",
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laddr);
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return -EINVAL; /* invalid logical address */
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}
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if (paddr > 0x1fffffff) {
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if (vdma_debug)
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printk
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("vdma_map: Invalid physical address: %08lx\n",
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paddr);
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return -EINVAL; /* invalid physical address */
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}
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npages = pages =
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(((paddr & (VDMA_PAGESIZE - 1)) + size) >> 12) + 1;
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first = laddr >> 12;
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if (vdma_debug)
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printk("vdma_remap: first=%x, pages=%x\n", first, pages);
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if (first + pages > VDMA_PGTBL_ENTRIES) {
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if (vdma_debug)
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printk("vdma_alloc: Invalid size: %08lx\n", size);
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return -EINVAL;
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}
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paddr &= ~(VDMA_PAGESIZE - 1);
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while (pages > 0 && first < VDMA_PGTBL_ENTRIES) {
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if (pgtbl[first].owner != laddr) {
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if (vdma_debug)
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printk("Trying to remap other's pages.\n");
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return -EPERM; /* not owner */
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}
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pgtbl[first].frame = paddr;
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paddr += VDMA_PAGESIZE;
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first++;
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pages--;
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}
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/*
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* Update translation table
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*/
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r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
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if (vdma_debug > 2) {
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int i;
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pages = (((paddr & (VDMA_PAGESIZE - 1)) + size) >> 12) + 1;
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first = laddr >> 12;
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printk("LADDR: ");
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for (i = first; i < first + pages; i++)
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printk("%08x ", i << 12);
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printk("\nPADDR: ");
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for (i = first; i < first + pages; i++)
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printk("%08x ", pgtbl[i].frame);
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printk("\nOWNER: ");
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for (i = first; i < first + pages; i++)
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printk("%08x ", pgtbl[i].owner);
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printk("\n");
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}
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return 0;
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}
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/*
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* Translate a physical address to a logical address.
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* This will return the logical address of the first
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* match.
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*/
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unsigned long vdma_phys2log(unsigned long paddr)
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{
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int i;
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int frame;
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frame = paddr & ~(VDMA_PAGESIZE - 1);
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for (i = 0; i < VDMA_PGTBL_ENTRIES; i++) {
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if (pgtbl[i].frame == frame)
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break;
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}
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if (i == VDMA_PGTBL_ENTRIES)
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return ~0UL;
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return (i << 12) + (paddr & (VDMA_PAGESIZE - 1));
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}
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EXPORT_SYMBOL(vdma_phys2log);
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/*
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* Translate a logical DMA address to a physical address
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*/
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unsigned long vdma_log2phys(unsigned long laddr)
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{
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return pgtbl[laddr >> 12].frame + (laddr & (VDMA_PAGESIZE - 1));
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}
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EXPORT_SYMBOL(vdma_log2phys);
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/*
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* Print DMA statistics
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*/
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void vdma_stats(void)
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{
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int i;
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printk("vdma_stats: CONFIG: %08x\n",
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r4030_read_reg32(JAZZ_R4030_CONFIG));
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printk("R4030 translation table base: %08x\n",
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r4030_read_reg32(JAZZ_R4030_TRSTBL_BASE));
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printk("R4030 translation table limit: %08x\n",
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r4030_read_reg32(JAZZ_R4030_TRSTBL_LIM));
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printk("vdma_stats: INV_ADDR: %08x\n",
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r4030_read_reg32(JAZZ_R4030_INV_ADDR));
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printk("vdma_stats: R_FAIL_ADDR: %08x\n",
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r4030_read_reg32(JAZZ_R4030_R_FAIL_ADDR));
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printk("vdma_stats: M_FAIL_ADDR: %08x\n",
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r4030_read_reg32(JAZZ_R4030_M_FAIL_ADDR));
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printk("vdma_stats: IRQ_SOURCE: %08x\n",
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r4030_read_reg32(JAZZ_R4030_IRQ_SOURCE));
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printk("vdma_stats: I386_ERROR: %08x\n",
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r4030_read_reg32(JAZZ_R4030_I386_ERROR));
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printk("vdma_chnl_modes: ");
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for (i = 0; i < 8; i++)
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printk("%04x ",
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(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_MODE +
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(i << 5)));
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printk("\n");
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printk("vdma_chnl_enables: ");
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for (i = 0; i < 8; i++)
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printk("%04x ",
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(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
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(i << 5)));
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printk("\n");
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}
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/*
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* DMA transfer functions
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*/
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/*
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* Enable a DMA channel. Also clear any error conditions.
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*/
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void vdma_enable(int channel)
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{
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int status;
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if (vdma_debug)
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printk("vdma_enable: channel %d\n", channel);
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/*
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* Check error conditions first
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*/
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status = r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5));
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if (status & 0x400)
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printk("VDMA: Channel %d: Address error!\n", channel);
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if (status & 0x200)
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printk("VDMA: Channel %d: Memory error!\n", channel);
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/*
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* Clear all interrupt flags
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*/
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r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
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r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
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(channel << 5)) | R4030_TC_INTR
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| R4030_MEM_INTR | R4030_ADDR_INTR);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Enable the desired channel
|
||
|
|
*/
|
||
|
|
r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
|
||
|
|
r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
|
||
|
|
(channel << 5)) |
|
||
|
|
R4030_CHNL_ENABLE);
|
||
|
|
}
|
||
|
|
|
||
|
|
EXPORT_SYMBOL(vdma_enable);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Disable a DMA channel
|
||
|
|
*/
|
||
|
|
void vdma_disable(int channel)
|
||
|
|
{
|
||
|
|
if (vdma_debug) {
|
||
|
|
int status =
|
||
|
|
r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
|
||
|
|
(channel << 5));
|
||
|
|
|
||
|
|
printk("vdma_disable: channel %d\n", channel);
|
||
|
|
printk("VDMA: channel %d status: %04x (%s) mode: "
|
||
|
|
"%02x addr: %06x count: %06x\n",
|
||
|
|
channel, status,
|
||
|
|
((status & 0x600) ? "ERROR" : "OK"),
|
||
|
|
(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_MODE +
|
||
|
|
(channel << 5)),
|
||
|
|
(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_ADDR +
|
||
|
|
(channel << 5)),
|
||
|
|
(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_COUNT +
|
||
|
|
(channel << 5)));
|
||
|
|
}
|
||
|
|
|
||
|
|
r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
|
||
|
|
r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
|
||
|
|
(channel << 5)) &
|
||
|
|
~R4030_CHNL_ENABLE);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* After disabling a DMA channel a remote bus register should be
|
||
|
|
* read to ensure that the current DMA acknowledge cycle is completed.
|
||
|
|
*/
|
||
|
|
*((volatile unsigned int *) JAZZ_DUMMY_DEVICE);
|
||
|
|
}
|
||
|
|
|
||
|
|
EXPORT_SYMBOL(vdma_disable);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set DMA mode. This function accepts the mode values used
|
||
|
|
* to set a PC-style DMA controller. For the SCSI and FDC
|
||
|
|
* channels, we also set the default modes each time we're
|
||
|
|
* called.
|
||
|
|
* NOTE: The FAST and BURST dma modes are supported by the
|
||
|
|
* R4030 Rev. 2 and PICA chipsets only. I leave them disabled
|
||
|
|
* for now.
|
||
|
|
*/
|
||
|
|
void vdma_set_mode(int channel, int mode)
|
||
|
|
{
|
||
|
|
if (vdma_debug)
|
||
|
|
printk("vdma_set_mode: channel %d, mode 0x%x\n", channel,
|
||
|
|
mode);
|
||
|
|
|
||
|
|
switch (channel) {
|
||
|
|
case JAZZ_SCSI_DMA: /* scsi */
|
||
|
|
r4030_write_reg32(JAZZ_R4030_CHNL_MODE + (channel << 5),
|
||
|
|
/* R4030_MODE_FAST | */
|
||
|
|
/* R4030_MODE_BURST | */
|
||
|
|
R4030_MODE_INTR_EN |
|
||
|
|
R4030_MODE_WIDTH_16 |
|
||
|
|
R4030_MODE_ATIME_80);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case JAZZ_FLOPPY_DMA: /* floppy */
|
||
|
|
r4030_write_reg32(JAZZ_R4030_CHNL_MODE + (channel << 5),
|
||
|
|
/* R4030_MODE_FAST | */
|
||
|
|
/* R4030_MODE_BURST | */
|
||
|
|
R4030_MODE_INTR_EN |
|
||
|
|
R4030_MODE_WIDTH_8 |
|
||
|
|
R4030_MODE_ATIME_120);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case JAZZ_AUDIOL_DMA:
|
||
|
|
case JAZZ_AUDIOR_DMA:
|
||
|
|
printk("VDMA: Audio DMA not supported yet.\n");
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
printk
|
||
|
|
("VDMA: vdma_set_mode() called with unsupported channel %d!\n",
|
||
|
|
channel);
|
||
|
|
}
|
||
|
|
|
||
|
|
switch (mode) {
|
||
|
|
case DMA_MODE_READ:
|
||
|
|
r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
|
||
|
|
r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
|
||
|
|
(channel << 5)) &
|
||
|
|
~R4030_CHNL_WRITE);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case DMA_MODE_WRITE:
|
||
|
|
r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
|
||
|
|
r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
|
||
|
|
(channel << 5)) |
|
||
|
|
R4030_CHNL_WRITE);
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
printk
|
||
|
|
("VDMA: vdma_set_mode() called with unknown dma mode 0x%x\n",
|
||
|
|
mode);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
EXPORT_SYMBOL(vdma_set_mode);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set Transfer Address
|
||
|
|
*/
|
||
|
|
void vdma_set_addr(int channel, long addr)
|
||
|
|
{
|
||
|
|
if (vdma_debug)
|
||
|
|
printk("vdma_set_addr: channel %d, addr %lx\n", channel,
|
||
|
|
addr);
|
||
|
|
|
||
|
|
r4030_write_reg32(JAZZ_R4030_CHNL_ADDR + (channel << 5), addr);
|
||
|
|
}
|
||
|
|
|
||
|
|
EXPORT_SYMBOL(vdma_set_addr);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set Transfer Count
|
||
|
|
*/
|
||
|
|
void vdma_set_count(int channel, int count)
|
||
|
|
{
|
||
|
|
if (vdma_debug)
|
||
|
|
printk("vdma_set_count: channel %d, count %08x\n", channel,
|
||
|
|
(unsigned) count);
|
||
|
|
|
||
|
|
r4030_write_reg32(JAZZ_R4030_CHNL_COUNT + (channel << 5), count);
|
||
|
|
}
|
||
|
|
|
||
|
|
EXPORT_SYMBOL(vdma_set_count);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Get Residual
|
||
|
|
*/
|
||
|
|
int vdma_get_residue(int channel)
|
||
|
|
{
|
||
|
|
int residual;
|
||
|
|
|
||
|
|
residual = r4030_read_reg32(JAZZ_R4030_CHNL_COUNT + (channel << 5));
|
||
|
|
|
||
|
|
if (vdma_debug)
|
||
|
|
printk("vdma_get_residual: channel %d: residual=%d\n",
|
||
|
|
channel, residual);
|
||
|
|
|
||
|
|
return residual;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Get DMA channel enable register
|
||
|
|
*/
|
||
|
|
int vdma_get_enable(int channel)
|
||
|
|
{
|
||
|
|
int enable;
|
||
|
|
|
||
|
|
enable = r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5));
|
||
|
|
|
||
|
|
if (vdma_debug)
|
||
|
|
printk("vdma_get_enable: channel %d: enable=%d\n", channel,
|
||
|
|
enable);
|
||
|
|
|
||
|
|
return enable;
|
||
|
|
}
|
||
|
|
|
||
|
|
arch_initcall(vdma_init);
|