433 lines
10 KiB
Plaintext
433 lines
10 KiB
Plaintext
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/*
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* MPC8323E EMDS Device Tree Source
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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* To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
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* this:
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*
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* 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
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* 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
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* next to the serial ports.
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* 3) Solder a wire from U61-22 to P19K-22.
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*
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* Note that there's a typo in the schematic. The board labels the last column
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* of pins "P19K", but in the schematic, that column is called "P19J". So if
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* you're going by the schematic, the pin is called "P19J-K22".
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*/
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/dts-v1/;
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/ {
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model = "MPC8323EMDS";
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compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8323@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <16384>; // L1, 16K
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i-cache-size = <16384>; // L1, 16K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x08000000>;
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};
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bcsr@f8000000 {
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compatible = "fsl,mpc8323mds-bcsr";
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reg = <0xf8000000 0x8000>;
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};
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soc8323@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <132000000>;
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wdt@200 {
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device_type = "watchdog";
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compatible = "mpc83xx_wdt";
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reg = <0x200 0x100>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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rtc@68 {
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compatible = "dallas,ds1374";
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reg = <0x68>;
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};
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <10 0x8>;
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interrupt-parent = <&ipic>;
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};
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dma@82a8 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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ranges = <0 0x8100 0x1a8>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
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reg = <0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
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reg = <0x180 0x28>;
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cell-index = <3>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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};
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crypto@30000 {
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compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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fsl,num-channels = <1>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x4c>;
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fsl,descriptor-types-mask = <0x0122003f>;
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};
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ipic: pic@700 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x700 0x100>;
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device_type = "ipic";
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};
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par_io@1400 {
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reg = <0x1400 0x100>;
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device_type = "par_io";
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num-ports = <7>;
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pio3: ucc_pin@03 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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3 4 3 0 2 0 /* MDIO */
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3 5 1 0 2 0 /* MDC */
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0 13 2 0 1 0 /* RX_CLK (CLK9) */
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3 24 2 0 1 0 /* TX_CLK (CLK10) */
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1 0 1 0 1 0 /* TxD0 */
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1 1 1 0 1 0 /* TxD1 */
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1 2 1 0 1 0 /* TxD2 */
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1 3 1 0 1 0 /* TxD3 */
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1 4 2 0 1 0 /* RxD0 */
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1 5 2 0 1 0 /* RxD1 */
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1 6 2 0 1 0 /* RxD2 */
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1 7 2 0 1 0 /* RxD3 */
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1 8 2 0 1 0 /* RX_ER */
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1 9 1 0 1 0 /* TX_ER */
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1 10 2 0 1 0 /* RX_DV */
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1 11 2 0 1 0 /* COL */
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1 12 1 0 1 0 /* TX_EN */
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1 13 2 0 1 0>; /* CRS */
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};
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pio4: ucc_pin@04 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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3 31 2 0 1 0 /* RX_CLK (CLK7) */
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3 6 2 0 1 0 /* TX_CLK (CLK8) */
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1 18 1 0 1 0 /* TxD0 */
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1 19 1 0 1 0 /* TxD1 */
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1 20 1 0 1 0 /* TxD2 */
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1 21 1 0 1 0 /* TxD3 */
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1 22 2 0 1 0 /* RxD0 */
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1 23 2 0 1 0 /* RxD1 */
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1 24 2 0 1 0 /* RxD2 */
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1 25 2 0 1 0 /* RxD3 */
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1 26 2 0 1 0 /* RX_ER */
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1 27 1 0 1 0 /* TX_ER */
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1 28 2 0 1 0 /* RX_DV */
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1 29 2 0 1 0 /* COL */
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1 30 1 0 1 0 /* TX_EN */
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1 31 2 0 1 0>; /* CRS */
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};
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pio5: ucc_pin@05 {
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pio-map = <
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/*
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* open has
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* port pin dir drain sel irq
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*/
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2 0 1 0 2 0 /* TxD5 */
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2 8 2 0 2 0 /* RxD5 */
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2 29 2 0 0 0 /* CTS5 */
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2 31 1 0 2 0 /* RTS5 */
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2 24 2 0 0 0 /* CD */
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>;
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};
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};
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};
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qe@e0100000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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ranges = <0x0 0xe0100000 0x00100000>;
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reg = <0xe0100000 0x480>;
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brg-frequency = <0>;
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bus-frequency = <198000000>;
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fsl,qe-num-riscs = <1>;
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fsl,qe-num-snums = <28>;
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muram@10000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0x0 0x00010000 0x00004000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0x0 0x4000>;
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};
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};
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spi@4c0 {
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cell-index = <0>;
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compatible = "fsl,spi";
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reg = <0x4c0 0x40>;
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interrupts = <2>;
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interrupt-parent = <&qeic>;
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mode = "cpu";
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};
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spi@500 {
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cell-index = <1>;
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compatible = "fsl,spi";
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reg = <0x500 0x40>;
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interrupts = <1>;
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interrupt-parent = <&qeic>;
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mode = "cpu";
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};
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usb@6c0 {
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compatible = "qe_udc";
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reg = <0x6c0 0x40 0x8b00 0x100>;
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interrupts = <11>;
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interrupt-parent = <&qeic>;
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mode = "slave";
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};
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enet0: ucc@2200 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <3>;
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reg = <0x2200 0x200>;
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interrupts = <34>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "clk9";
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tx-clock-name = "clk10";
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phy-handle = <&phy3>;
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pio-handle = <&pio3>;
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};
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enet1: ucc@3200 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <4>;
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reg = <0x3200 0x200>;
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interrupts = <35>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "clk7";
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tx-clock-name = "clk8";
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phy-handle = <&phy4>;
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pio-handle = <&pio4>;
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};
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ucc@2400 {
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device_type = "serial";
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compatible = "ucc_uart";
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cell-index = <5>; /* The UCC number, 1-7*/
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port-number = <0>; /* Which ttyQEx device */
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soft-uart; /* We need Soft-UART */
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reg = <0x2400 0x200>;
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interrupts = <40>; /* From Table 18-12 */
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interrupt-parent = < &qeic >;
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/*
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* For Soft-UART, we need to set TX to 1X, which
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* means specifying separate clock sources.
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*/
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rx-clock-name = "brg5";
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tx-clock-name = "brg6";
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pio-handle = < &pio5 >;
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};
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mdio@2320 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2320 0x18>;
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compatible = "fsl,ucc-mdio";
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phy3: ethernet-phy@03 {
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interrupt-parent = <&ipic>;
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interrupts = <17 0x8>;
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reg = <0x3>;
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device_type = "ethernet-phy";
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};
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phy4: ethernet-phy@04 {
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interrupt-parent = <&ipic>;
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interrupts = <18 0x8>;
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reg = <0x4>;
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device_type = "ethernet-phy";
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};
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};
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qeic: interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x80 0x80>;
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big-endian;
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interrupts = <32 0x8 33 0x8>; //high:32 low:33
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interrupt-parent = <&ipic>;
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};
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};
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pci0: pci@e0008500 {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x11 AD17 */
|
||
|
|
0x8800 0x0 0x0 0x1 &ipic 20 0x8
|
||
|
|
0x8800 0x0 0x0 0x2 &ipic 21 0x8
|
||
|
|
0x8800 0x0 0x0 0x3 &ipic 22 0x8
|
||
|
|
0x8800 0x0 0x0 0x4 &ipic 23 0x8
|
||
|
|
|
||
|
|
/* IDSEL 0x12 AD18 */
|
||
|
|
0x9000 0x0 0x0 0x1 &ipic 22 0x8
|
||
|
|
0x9000 0x0 0x0 0x2 &ipic 23 0x8
|
||
|
|
0x9000 0x0 0x0 0x3 &ipic 20 0x8
|
||
|
|
0x9000 0x0 0x0 0x4 &ipic 21 0x8
|
||
|
|
|
||
|
|
/* IDSEL 0x13 AD19 */
|
||
|
|
0x9800 0x0 0x0 0x1 &ipic 23 0x8
|
||
|
|
0x9800 0x0 0x0 0x2 &ipic 20 0x8
|
||
|
|
0x9800 0x0 0x0 0x3 &ipic 21 0x8
|
||
|
|
0x9800 0x0 0x0 0x4 &ipic 22 0x8
|
||
|
|
|
||
|
|
/* IDSEL 0x15 AD21*/
|
||
|
|
0xa800 0x0 0x0 0x1 &ipic 20 0x8
|
||
|
|
0xa800 0x0 0x0 0x2 &ipic 21 0x8
|
||
|
|
0xa800 0x0 0x0 0x3 &ipic 22 0x8
|
||
|
|
0xa800 0x0 0x0 0x4 &ipic 23 0x8
|
||
|
|
|
||
|
|
/* IDSEL 0x16 AD22*/
|
||
|
|
0xb000 0x0 0x0 0x1 &ipic 23 0x8
|
||
|
|
0xb000 0x0 0x0 0x2 &ipic 20 0x8
|
||
|
|
0xb000 0x0 0x0 0x3 &ipic 21 0x8
|
||
|
|
0xb000 0x0 0x0 0x4 &ipic 22 0x8
|
||
|
|
|
||
|
|
/* IDSEL 0x17 AD23*/
|
||
|
|
0xb800 0x0 0x0 0x1 &ipic 22 0x8
|
||
|
|
0xb800 0x0 0x0 0x2 &ipic 23 0x8
|
||
|
|
0xb800 0x0 0x0 0x3 &ipic 20 0x8
|
||
|
|
0xb800 0x0 0x0 0x4 &ipic 21 0x8
|
||
|
|
|
||
|
|
/* IDSEL 0x18 AD24*/
|
||
|
|
0xc000 0x0 0x0 0x1 &ipic 21 0x8
|
||
|
|
0xc000 0x0 0x0 0x2 &ipic 22 0x8
|
||
|
|
0xc000 0x0 0x0 0x3 &ipic 23 0x8
|
||
|
|
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
|
||
|
|
interrupt-parent = <&ipic>;
|
||
|
|
interrupts = <66 0x8>;
|
||
|
|
bus-range = <0x0 0x0>;
|
||
|
|
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||
|
|
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||
|
|
0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
|
||
|
|
clock-frequency = <0>;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
#address-cells = <3>;
|
||
|
|
reg = <0xe0008500 0x100 /* internal registers */
|
||
|
|
0xe0008300 0x8>; /* config space access registers */
|
||
|
|
compatible = "fsl,mpc8349-pci";
|
||
|
|
device_type = "pci";
|
||
|
|
};
|
||
|
|
};
|