233 lines
7.7 KiB
C
233 lines
7.7 KiB
C
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/*
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* SCC (Super Companion Chip) definitions
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*
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* (C) Copyright 2004-2006 TOSHIBA CORPORATION
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef _CELLEB_SCC_H
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#define _CELLEB_SCC_H
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#define PCI_VENDOR_ID_TOSHIBA_2 0x102f
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#define PCI_DEVICE_ID_TOSHIBA_SCC_PCIEXC_BRIDGE 0x01b0
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#define PCI_DEVICE_ID_TOSHIBA_SCC_EPCI_BRIDGE 0x01b1
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#define PCI_DEVICE_ID_TOSHIBA_SCC_BRIDGE 0x01b2
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#define PCI_DEVICE_ID_TOSHIBA_SCC_GBE 0x01b3
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#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
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#define PCI_DEVICE_ID_TOSHIBA_SCC_USB2 0x01b5
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#define PCI_DEVICE_ID_TOSHIBA_SCC_USB 0x01b6
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#define PCI_DEVICE_ID_TOSHIBA_SCC_ENCDEC 0x01b7
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#define SCC_EPCI_REG 0x0000d000
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/* EPCI registers */
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#define SCC_EPCI_CNF10_REG 0x010
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#define SCC_EPCI_CNF14_REG 0x014
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#define SCC_EPCI_CNF18_REG 0x018
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#define SCC_EPCI_PVBAT 0x100
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#define SCC_EPCI_VPMBAT 0x104
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#define SCC_EPCI_VPIBAT 0x108
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#define SCC_EPCI_VCSR 0x110
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#define SCC_EPCI_VIENAB 0x114
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#define SCC_EPCI_VISTAT 0x118
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#define SCC_EPCI_VRDCOUNT 0x124
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#define SCC_EPCI_BAM0 0x12c
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#define SCC_EPCI_BAM1 0x134
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#define SCC_EPCI_BAM2 0x13c
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#define SCC_EPCI_IADR 0x164
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#define SCC_EPCI_CLKRST 0x800
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#define SCC_EPCI_INTSET 0x804
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#define SCC_EPCI_STATUS 0x808
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#define SCC_EPCI_ABTSET 0x80c
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#define SCC_EPCI_WATRP 0x810
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#define SCC_EPCI_DUMYRADR 0x814
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#define SCC_EPCI_SWRESP 0x818
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#define SCC_EPCI_CNTOPT 0x81c
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#define SCC_EPCI_ECMODE 0xf00
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#define SCC_EPCI_IOM_AC_NUM 5
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#define SCC_EPCI_IOM_ACTE(n) (0xf10 + (n) * 4)
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#define SCC_EPCI_IOT_AC_NUM 4
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#define SCC_EPCI_IOT_ACTE(n) (0xf30 + (n) * 4)
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#define SCC_EPCI_MAEA 0xf50
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#define SCC_EPCI_MAEC 0xf54
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#define SCC_EPCI_CKCTRL 0xff0
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/* bits for SCC_EPCI_VCSR */
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#define SCC_EPCI_VCSR_FRE 0x00020000
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#define SCC_EPCI_VCSR_FWE 0x00010000
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#define SCC_EPCI_VCSR_DR 0x00000400
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#define SCC_EPCI_VCSR_SR 0x00000008
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#define SCC_EPCI_VCSR_AT 0x00000004
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/* bits for SCC_EPCI_VIENAB/SCC_EPCI_VISTAT */
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#define SCC_EPCI_VISTAT_PMPE 0x00000008
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#define SCC_EPCI_VISTAT_PMFE 0x00000004
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#define SCC_EPCI_VISTAT_PRA 0x00000002
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#define SCC_EPCI_VISTAT_PRD 0x00000001
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#define SCC_EPCI_VISTAT_ALL 0x0000000f
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#define SCC_EPCI_VIENAB_PMPEE 0x00000008
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#define SCC_EPCI_VIENAB_PMFEE 0x00000004
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#define SCC_EPCI_VIENAB_PRA 0x00000002
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#define SCC_EPCI_VIENAB_PRD 0x00000001
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#define SCC_EPCI_VIENAB_ALL 0x0000000f
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/* bits for SCC_EPCI_CLKRST */
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#define SCC_EPCI_CLKRST_CKS_MASK 0x00030000
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#define SCC_EPCI_CLKRST_CKS_2 0x00000000
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#define SCC_EPCI_CLKRST_CKS_4 0x00010000
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#define SCC_EPCI_CLKRST_CKS_8 0x00020000
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#define SCC_EPCI_CLKRST_PCICRST 0x00000400
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#define SCC_EPCI_CLKRST_BC 0x00000200
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#define SCC_EPCI_CLKRST_PCIRST 0x00000100
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#define SCC_EPCI_CLKRST_PCKEN 0x00000001
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/* bits for SCC_EPCI_INTSET/SCC_EPCI_STATUS */
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#define SCC_EPCI_INT_2M 0x01000000
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#define SCC_EPCI_INT_RERR 0x00200000
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#define SCC_EPCI_INT_SERR 0x00100000
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#define SCC_EPCI_INT_PRTER 0x00080000
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#define SCC_EPCI_INT_SER 0x00040000
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#define SCC_EPCI_INT_PER 0x00020000
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#define SCC_EPCI_INT_PAI 0x00010000
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#define SCC_EPCI_INT_1M 0x00000100
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#define SCC_EPCI_INT_PME 0x00000010
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#define SCC_EPCI_INT_INTD 0x00000008
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#define SCC_EPCI_INT_INTC 0x00000004
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#define SCC_EPCI_INT_INTB 0x00000002
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#define SCC_EPCI_INT_INTA 0x00000001
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#define SCC_EPCI_INT_DEVINT 0x0000000f
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#define SCC_EPCI_INT_ALL 0x003f001f
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#define SCC_EPCI_INT_ALLERR 0x003f0000
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/* bits for SCC_EPCI_CKCTRL */
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#define SCC_EPCI_CKCTRL_CRST0 0x00010000
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#define SCC_EPCI_CKCTRL_CRST1 0x00020000
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#define SCC_EPCI_CKCTRL_OCLKEN 0x00000100
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#define SCC_EPCI_CKCTRL_LCLKEN 0x00000001
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#define SCC_EPCI_IDSEL_AD_TO_SLOT(ad) ((ad) - 10)
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#define SCC_EPCI_MAX_DEVNU SCC_EPCI_IDSEL_AD_TO_SLOT(32)
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/* bits for SCC_EPCI_CNTOPT */
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#define SCC_EPCI_CNTOPT_O2PMB 0x00000002
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/* SCC PCIEXC SMMIO registers */
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#define PEXCADRS 0x000
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#define PEXCWDATA 0x004
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#define PEXCRDATA 0x008
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#define PEXDADRS 0x010
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#define PEXDCMND 0x014
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#define PEXDWDATA 0x018
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#define PEXDRDATA 0x01c
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#define PEXREQID 0x020
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#define PEXTIDMAP 0x024
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#define PEXINTMASK 0x028
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#define PEXINTSTS 0x02c
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#define PEXAERRMASK 0x030
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#define PEXAERRSTS 0x034
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#define PEXPRERRMASK 0x040
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#define PEXPRERRSTS 0x044
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#define PEXPRERRID01 0x048
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#define PEXPRERRID23 0x04c
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#define PEXVDMASK 0x050
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#define PEXVDSTS 0x054
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#define PEXRCVCPLIDA 0x060
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#define PEXLENERRIDA 0x068
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#define PEXPHYPLLST 0x070
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#define PEXDMRDEN0 0x100
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#define PEXDMRDADR0 0x104
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#define PEXDMRDENX 0x110
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#define PEXDMRDADRX 0x114
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#define PEXECMODE 0xf00
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#define PEXMAEA(n) (0xf50 + (8 * n))
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#define PEXMAEC(n) (0xf54 + (8 * n))
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#define PEXCCRCTRL 0xff0
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/* SCC PCIEXC bits and shifts for PEXCADRS */
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#define PEXCADRS_BYTE_EN_SHIFT 20
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#define PEXCADRS_CMD_SHIFT 16
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#define PEXCADRS_CMD_READ (0xa << PEXCADRS_CMD_SHIFT)
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#define PEXCADRS_CMD_WRITE (0xb << PEXCADRS_CMD_SHIFT)
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/* SCC PCIEXC shifts for PEXDADRS */
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#define PEXDADRS_BUSNO_SHIFT 20
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#define PEXDADRS_DEVNO_SHIFT 15
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#define PEXDADRS_FUNCNO_SHIFT 12
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/* SCC PCIEXC bits and shifts for PEXDCMND */
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#define PEXDCMND_BYTE_EN_SHIFT 4
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#define PEXDCMND_IO_READ 0x2
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#define PEXDCMND_IO_WRITE 0x3
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#define PEXDCMND_CONFIG_READ 0xa
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#define PEXDCMND_CONFIG_WRITE 0xb
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/* SCC PCIEXC bits for PEXPHYPLLST */
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#define PEXPHYPLLST_PEXPHYAPLLST 0x00000001
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/* SCC PCIEXC bits for PEXECMODE */
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#define PEXECMODE_ALL_THROUGH 0x00000000
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#define PEXECMODE_ALL_8BIT 0x00550155
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#define PEXECMODE_ALL_16BIT 0x00aa02aa
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/* SCC PCIEXC bits for PEXCCRCTRL */
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#define PEXCCRCTRL_PEXIPCOREEN 0x00040000
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#define PEXCCRCTRL_PEXIPCONTEN 0x00020000
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#define PEXCCRCTRL_PEXPHYPLLEN 0x00010000
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#define PEXCCRCTRL_PCIEXCAOCKEN 0x00000100
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/* SCC PCIEXC port configuration registers */
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#define PEXTCERRCHK 0x21c
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#define PEXTAMAPB0 0x220
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#define PEXTAMAPL0 0x224
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#define PEXTAMAPB(n) (PEXTAMAPB0 + 8 * (n))
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#define PEXTAMAPL(n) (PEXTAMAPL0 + 8 * (n))
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#define PEXCHVC0P 0x500
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#define PEXCHVC0NP 0x504
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#define PEXCHVC0C 0x508
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#define PEXCDVC0P 0x50c
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#define PEXCDVC0NP 0x510
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#define PEXCDVC0C 0x514
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#define PEXCHVCXP 0x518
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#define PEXCHVCXNP 0x51c
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#define PEXCHVCXC 0x520
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#define PEXCDVCXP 0x524
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#define PEXCDVCXNP 0x528
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#define PEXCDVCXC 0x52c
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#define PEXCTTRG 0x530
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#define PEXTSCTRL 0x700
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#define PEXTSSTS 0x704
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#define PEXSKPCTRL 0x708
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/* UHC registers */
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#define SCC_UHC_CKRCTRL 0xff0
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#define SCC_UHC_ECMODE 0xf00
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/* bits for SCC_UHC_CKRCTRL */
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#define SCC_UHC_F48MCKLEN 0x00000001
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#define SCC_UHC_P_SUSPEND 0x00000002
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#define SCC_UHC_PHY_SUSPEND_SEL 0x00000004
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#define SCC_UHC_HCLKEN 0x00000100
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#define SCC_UHC_USBEN 0x00010000
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#define SCC_UHC_USBCEN 0x00020000
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#define SCC_UHC_PHYEN 0x00040000
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/* bits for SCC_UHC_ECMODE */
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#define SCC_UHC_ECMODE_BY_BYTE 0x00000555
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#define SCC_UHC_ECMODE_BY_WORD 0x00000aaa
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#endif /* _CELLEB_SCC_H */
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