123 lines
3.9 KiB
C
123 lines
3.9 KiB
C
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/*
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*************************************************************************
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* Ralink Tech Inc.
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* 5F., No.36, Taiyuan St., Jhubei City,
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* Hsinchu County 302,
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* Taiwan, R.O.C.
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*
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* (c) Copyright 2002-2007, Ralink Technology, Inc.
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*
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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* *
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*************************************************************************
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Module Name:
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rt3390.c
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Abstract:
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Specific funcitons and variables for RT30xx.
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Revision History:
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Who When What
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-------- ---------- ----------------------------------------------
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*/
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#ifdef RT3390
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#include "../rt_config.h"
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#ifndef RTMP_RF_RW_SUPPORT
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#error "You Should Enable compile flag RTMP_RF_RW_SUPPORT for this chip"
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#endif // RTMP_RF_RW_SUPPORT //
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VOID NICInitRT3390RFRegisters(IN PRTMP_ADAPTER pAd)
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{
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INT i;
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// Driver must read EEPROM to get RfIcType before initial RF registers
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// Initialize RF register to default value
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if (IS_RT3090(pAd)||IS_RT3390(pAd)||IS_RT3572(pAd))
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{
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// Init RF calibration
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// Driver should toggle RF R30 bit7 before init RF registers
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UINT32 RfReg = 0, data;
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RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
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RfReg |= 0x80;
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RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
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RTMPusecDelay(1000);
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RfReg &= 0x7F;
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RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
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// init R24, R31
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RT30xxWriteRFRegister(pAd, RF_R24, 0x0F);
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RT30xxWriteRFRegister(pAd, RF_R31, 0x0F);
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if (IS_RT3390(pAd))
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{
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// patch LNA_PE_G1 failed issue
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RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
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data &= ~(0x20);
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RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
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// RF registers initialization
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for (i = 0; i < NUM_RF_REG_PARMS_OVER_RT3390; i++)
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{
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RT30xxWriteRFRegister(pAd, RFRegTableOverRT3390[i].Register, RFRegTableOverRT3390[i].Value);
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}
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}
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// patch LNA_PE_G1 failed issue
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RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
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data &= ~(0x20);
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RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
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// Initialize RF register to default value
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for (i = 0; i < NUM_RF_REG_PARMS_OVER_RT3390; i++)
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{
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RT30xxWriteRFRegister(pAd, RFRegTableOverRT3390[i].Register, RFRegTableOverRT3390[i].Value);
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}
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// Driver should set RF R6 bit6 on before calibration
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RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
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RfReg |= 0x40;
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RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
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//For RF filter Calibration
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RTMPFilterCalibration(pAd);
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// Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration()
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if ((pAd->MACVersion & 0xffff) < 0x0211)
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RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
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// set led open drain enable
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RTMP_IO_READ32(pAd, OPT_14, &data);
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data |= 0x01;
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RTMP_IO_WRITE32(pAd, OPT_14, data);
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// set default antenna as main
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if (pAd->RfIcType == RFIC_3020)
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AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
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// add by johnli, RF power sequence setup, load RF normal operation-mode setup
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RT33xxLoadRFNormalModeSetup(pAd);
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}
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}
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#endif // RT3390 //
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