47 lines
1.4 KiB
Plaintext
47 lines
1.4 KiB
Plaintext
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S3C2410 DMA
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===========
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Introduction
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------------
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The kernel provides an interface to manage DMA transfers
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using the DMA channels in the CPU, so that the central
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duty of managing channel mappings, and programming the
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channel generators is in one place.
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DMA Channel Ordering
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--------------------
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Many of the range do not have connections for the DMA
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channels to all sources, which means that some devices
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have a restricted number of channels that can be used.
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To allow flexibility for each CPU type and board, the
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DMA code can be given a DMA ordering structure which
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allows the order of channel search to be specified, as
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well as allowing the prohibition of certain claims.
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struct s3c24xx_dma_order has a list of channels, and
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each channel within has a slot for a list of DMA
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channel numbers. The slots are searched in order for
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the presence of a DMA channel number with DMA_CH_VALID
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or-ed in.
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If the order has the flag DMA_CH_NEVER set, then after
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checking the channel list, the system will return no
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found channel, thus denying the request.
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A board support file can call s3c24xx_dma_order_set()
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to register a complete ordering set. The routine will
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copy the data, so the original can be discarded with
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__initdata.
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Authour
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-------
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Ben Dooks,
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Copyright (c) 2007 Ben Dooks, Simtec Electronics
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Licensed under the GPL v2
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