399 lines
10 KiB
C
399 lines
10 KiB
C
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/*
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* Copyright (c) 2008-2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "ath9k.h"
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void
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ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex,
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int regWrites)
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{
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REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
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}
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bool
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ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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u32 channelSel = 0;
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u32 bModeSynth = 0;
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u32 aModeRefSel = 0;
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u32 reg32 = 0;
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u16 freq;
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struct chan_centers centers;
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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freq = centers.synth_center;
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if (freq < 4800) {
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u32 txctl;
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if (((freq - 2192) % 5) == 0) {
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channelSel = ((freq - 672) * 2 - 3040) / 10;
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bModeSynth = 0;
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} else if (((freq - 2224) % 5) == 0) {
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channelSel = ((freq - 704) * 2 - 3040) / 10;
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bModeSynth = 1;
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} else {
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DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
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"Invalid channel %u MHz\n", freq);
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return false;
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}
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channelSel = (channelSel << 2) & 0xff;
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channelSel = ath9k_hw_reverse_bits(channelSel, 8);
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txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
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if (freq == 2484) {
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REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
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txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
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} else {
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REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
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txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
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}
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} else if ((freq % 20) == 0 && freq >= 5120) {
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channelSel =
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ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
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aModeRefSel = ath9k_hw_reverse_bits(1, 2);
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} else if ((freq % 10) == 0) {
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channelSel =
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ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
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if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
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aModeRefSel = ath9k_hw_reverse_bits(2, 2);
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else
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aModeRefSel = ath9k_hw_reverse_bits(1, 2);
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} else if ((freq % 5) == 0) {
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channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
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aModeRefSel = ath9k_hw_reverse_bits(1, 2);
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} else {
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DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
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"Invalid channel %u MHz\n", freq);
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return false;
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}
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reg32 =
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(channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
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(1 << 5) | 0x1;
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REG_WRITE(ah, AR_PHY(0x37), reg32);
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ah->curchan = chan;
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ah->curchan_rad_index = -1;
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return true;
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}
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void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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u16 bMode, fracMode, aModeRefSel = 0;
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u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
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struct chan_centers centers;
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u32 refDivA = 24;
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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freq = centers.synth_center;
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reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
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reg32 &= 0xc0000000;
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if (freq < 4800) {
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u32 txctl;
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bMode = 1;
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fracMode = 1;
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aModeRefSel = 0;
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channelSel = (freq * 0x10000) / 15;
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txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
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if (freq == 2484) {
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REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
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txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
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} else {
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REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
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txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
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}
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} else {
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bMode = 0;
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fracMode = 0;
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switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
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case 0:
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if ((freq % 20) == 0) {
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aModeRefSel = 3;
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} else if ((freq % 10) == 0) {
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aModeRefSel = 2;
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}
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if (aModeRefSel)
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break;
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case 1:
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default:
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aModeRefSel = 0;
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fracMode = 1;
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refDivA = 1;
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channelSel = (freq * 0x8000) / 15;
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REG_RMW_FIELD(ah, AR_AN_SYNTH9,
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AR_AN_SYNTH9_REFDIVA, refDivA);
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}
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if (!fracMode) {
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ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
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channelSel = ndiv & 0x1ff;
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channelFrac = (ndiv & 0xfffffe00) * 2;
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channelSel = (channelSel << 17) | channelFrac;
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}
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}
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reg32 = reg32 |
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(bMode << 29) |
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(fracMode << 28) | (aModeRefSel << 26) | (channelSel);
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REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
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ah->curchan = chan;
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ah->curchan_rad_index = -1;
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}
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static void
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ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
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u32 numBits, u32 firstBit,
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u32 column)
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{
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u32 tmp32, mask, arrayEntry, lastBit;
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int32_t bitPosition, bitsLeft;
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tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
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arrayEntry = (firstBit - 1) / 8;
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bitPosition = (firstBit - 1) % 8;
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bitsLeft = numBits;
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while (bitsLeft > 0) {
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lastBit = (bitPosition + bitsLeft > 8) ?
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8 : bitPosition + bitsLeft;
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mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
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(column * 8);
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rfBuf[arrayEntry] &= ~mask;
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rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
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(column * 8)) & mask;
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bitsLeft -= 8 - bitPosition;
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tmp32 = tmp32 >> (8 - bitPosition);
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bitPosition = 0;
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arrayEntry++;
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}
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}
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bool
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ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
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u16 modesIndex)
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{
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u32 eepMinorRev;
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u32 ob5GHz = 0, db5GHz = 0;
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u32 ob2GHz = 0, db2GHz = 0;
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int regWrites = 0;
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if (AR_SREV_9280_10_OR_LATER(ah))
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return true;
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eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
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RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
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RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
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RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
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RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
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modesIndex);
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{
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int i;
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for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
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ah->analogBank6Data[i] =
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INI_RA(&ah->iniBank6TPC, i, modesIndex);
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}
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}
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if (eepMinorRev >= 2) {
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if (IS_CHAN_2GHZ(chan)) {
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ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
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db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
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ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
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ob2GHz, 3, 197, 0);
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ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
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db2GHz, 3, 194, 0);
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} else {
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ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
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db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
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ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
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ob5GHz, 3, 203, 0);
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ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
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db5GHz, 3, 200, 0);
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}
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}
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RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
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REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
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regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
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regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
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regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
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regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
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regWrites);
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REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
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regWrites);
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return true;
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}
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void
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ath9k_hw_rf_free(struct ath_hw *ah)
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{
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#define ATH_FREE_BANK(bank) do { \
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kfree(bank); \
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bank = NULL; \
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} while (0);
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ATH_FREE_BANK(ah->analogBank0Data);
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ATH_FREE_BANK(ah->analogBank1Data);
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ATH_FREE_BANK(ah->analogBank2Data);
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ATH_FREE_BANK(ah->analogBank3Data);
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ATH_FREE_BANK(ah->analogBank6Data);
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ATH_FREE_BANK(ah->analogBank6TPCData);
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ATH_FREE_BANK(ah->analogBank7Data);
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ATH_FREE_BANK(ah->addac5416_21);
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ATH_FREE_BANK(ah->bank6Temp);
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#undef ATH_FREE_BANK
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}
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bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
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{
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if (!AR_SREV_9280_10_OR_LATER(ah)) {
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ah->analogBank0Data =
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kzalloc((sizeof(u32) *
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ah->iniBank0.ia_rows), GFP_KERNEL);
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ah->analogBank1Data =
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kzalloc((sizeof(u32) *
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ah->iniBank1.ia_rows), GFP_KERNEL);
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ah->analogBank2Data =
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kzalloc((sizeof(u32) *
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ah->iniBank2.ia_rows), GFP_KERNEL);
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ah->analogBank3Data =
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kzalloc((sizeof(u32) *
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ah->iniBank3.ia_rows), GFP_KERNEL);
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ah->analogBank6Data =
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kzalloc((sizeof(u32) *
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ah->iniBank6.ia_rows), GFP_KERNEL);
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ah->analogBank6TPCData =
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kzalloc((sizeof(u32) *
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ah->iniBank6TPC.ia_rows), GFP_KERNEL);
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ah->analogBank7Data =
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kzalloc((sizeof(u32) *
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ah->iniBank7.ia_rows), GFP_KERNEL);
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if (ah->analogBank0Data == NULL
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|| ah->analogBank1Data == NULL
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|| ah->analogBank2Data == NULL
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|| ah->analogBank3Data == NULL
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|| ah->analogBank6Data == NULL
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|| ah->analogBank6TPCData == NULL
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|| ah->analogBank7Data == NULL) {
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DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
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"Cannot allocate RF banks\n");
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*status = -ENOMEM;
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return false;
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}
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ah->addac5416_21 =
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kzalloc((sizeof(u32) *
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ah->iniAddac.ia_rows *
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ah->iniAddac.ia_columns), GFP_KERNEL);
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if (ah->addac5416_21 == NULL) {
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DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
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"Cannot allocate addac5416_21\n");
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*status = -ENOMEM;
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return false;
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}
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ah->bank6Temp =
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kzalloc((sizeof(u32) *
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ah->iniBank6.ia_rows), GFP_KERNEL);
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if (ah->bank6Temp == NULL) {
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DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
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"Cannot allocate bank6Temp\n");
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*status = -ENOMEM;
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return false;
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}
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}
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return true;
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}
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void
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ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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int i, regWrites = 0;
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u32 bank6SelMask;
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u32 *bank6Temp = ah->bank6Temp;
|
||
|
|
|
||
|
|
switch (ah->config.diversity_control) {
|
||
|
|
case ATH9K_ANT_FIXED_A:
|
||
|
|
bank6SelMask =
|
||
|
|
(ah->config.antenna_switch_swap & ANTSWAP_AB) ?
|
||
|
|
REDUCE_CHAIN_0 : REDUCE_CHAIN_1;
|
||
|
|
break;
|
||
|
|
case ATH9K_ANT_FIXED_B:
|
||
|
|
bank6SelMask =
|
||
|
|
(ah->config.antenna_switch_swap & ANTSWAP_AB) ?
|
||
|
|
REDUCE_CHAIN_1 : REDUCE_CHAIN_0;
|
||
|
|
break;
|
||
|
|
case ATH9K_ANT_VARIABLE:
|
||
|
|
return;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0; i < ah->iniBank6.ia_rows; i++)
|
||
|
|
bank6Temp[i] = ah->analogBank6Data[i];
|
||
|
|
|
||
|
|
REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
|
||
|
|
|
||
|
|
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
|
||
|
|
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
|
||
|
|
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
|
||
|
|
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
|
||
|
|
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
|
||
|
|
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
|
||
|
|
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
|
||
|
|
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
|
||
|
|
ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
|
||
|
|
|
||
|
|
REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
|
||
|
|
|
||
|
|
REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
|
||
|
|
#ifdef ALTER_SWITCH
|
||
|
|
REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
|
||
|
|
(REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
|
||
|
|
| ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
|
||
|
|
#endif
|
||
|
|
}
|