564 lines
15 KiB
C
564 lines
15 KiB
C
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/***************************************************************************\
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|* *|
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|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
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|* *|
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|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
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|* international laws. Users and possessors of this source code are *|
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|* hereby granted a nonexclusive, royalty-free copyright license to *|
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|* use this code in individual and commercial software. *|
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|* *|
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|* Any use of this source code must include, in the user documenta- *|
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|* tion and internal comments to the code, notices to the end user *|
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|* as follows: *|
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|* *|
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|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
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|* *|
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|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
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|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
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|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
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|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
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|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
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|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
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|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
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|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
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|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
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|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
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|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
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|* *|
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|* U.S. Government End Users. This source code is a "commercial *|
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|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
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|* consisting of "commercial computer software" and "commercial *|
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|* computer software documentation," as such terms are used in *|
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|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
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|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
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|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
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|* all U.S. Government End Users acquire the source code with only *|
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|* those rights set forth herein. *|
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|* *|
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\***************************************************************************/
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/*
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* GPL licensing note -- nVidia is allowing a liberal interpretation of
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* the documentation restriction above, to merely say that this nVidia's
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* copyright and disclaimer should be included with all code derived
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* from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
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*/
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/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.21 2002/10/14 18:22:46 mvojkovi Exp $ */
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#ifndef __RIVA_HW_H__
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#define __RIVA_HW_H__
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#define RIVA_SW_VERSION 0x00010003
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#ifndef Bool
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typedef int Bool;
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#endif
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#ifndef TRUE
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#define TRUE 1
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#endif
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#ifndef FALSE
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#define FALSE 0
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#endif
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#ifndef NULL
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#define NULL 0
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#endif
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/*
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* Typedefs to force certain sized values.
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*/
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typedef unsigned char U008;
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typedef unsigned short U016;
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typedef unsigned int U032;
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/*
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* HW access macros.
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*/
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#include <asm/io.h>
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#define NV_WR08(p,i,d) (__raw_writeb((d), (void __iomem *)(p) + (i)))
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#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i)))
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#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i)))
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#define NV_RD16(p,i) (__raw_readw((void __iomem *)(p) + (i)))
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#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i)))
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#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i)))
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#define VGA_WR08(p,i,d) (writeb((d), (void __iomem *)(p) + (i)))
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#define VGA_RD08(p,i) (readb((void __iomem *)(p) + (i)))
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/*
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* Define different architectures.
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*/
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#define NV_ARCH_03 0x03
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#define NV_ARCH_04 0x04
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#define NV_ARCH_10 0x10
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#define NV_ARCH_20 0x20
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#define NV_ARCH_30 0x30
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#define NV_ARCH_40 0x40
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/***************************************************************************\
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* *
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* FIFO registers. *
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* *
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\***************************************************************************/
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/*
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* Raster OPeration. Windows style ROP3.
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*/
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typedef volatile struct
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{
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U032 reserved00[4];
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#ifdef __BIG_ENDIAN
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U032 FifoFree;
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#else
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U016 FifoFree;
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U016 Nop;
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#endif
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U032 reserved01[0x0BB];
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U032 Rop3;
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} RivaRop;
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/*
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* 8X8 Monochrome pattern.
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*/
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typedef volatile struct
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{
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U032 reserved00[4];
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#ifdef __BIG_ENDIAN
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U032 FifoFree;
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#else
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U016 FifoFree;
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U016 Nop;
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#endif
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U032 reserved01[0x0BD];
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U032 Shape;
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U032 reserved03[0x001];
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U032 Color0;
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U032 Color1;
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U032 Monochrome[2];
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} RivaPattern;
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/*
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* Scissor clip rectangle.
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*/
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typedef volatile struct
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{
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U032 reserved00[4];
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#ifdef __BIG_ENDIAN
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U032 FifoFree;
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#else
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U016 FifoFree;
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U016 Nop;
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#endif
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U032 reserved01[0x0BB];
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U032 TopLeft;
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U032 WidthHeight;
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} RivaClip;
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/*
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* 2D filled rectangle.
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*/
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typedef volatile struct
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{
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U032 reserved00[4];
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#ifdef __BIG_ENDIAN
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U032 FifoFree;
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#else
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U016 FifoFree;
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U016 Nop[1];
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#endif
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U032 reserved01[0x0BC];
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U032 Color;
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U032 reserved03[0x03E];
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U032 TopLeft;
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U032 WidthHeight;
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} RivaRectangle;
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/*
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* 2D screen-screen BLT.
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*/
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typedef volatile struct
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{
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U032 reserved00[4];
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#ifdef __BIG_ENDIAN
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U032 FifoFree;
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#else
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U016 FifoFree;
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U016 Nop;
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#endif
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U032 reserved01[0x0BB];
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U032 TopLeftSrc;
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U032 TopLeftDst;
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U032 WidthHeight;
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} RivaScreenBlt;
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/*
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* 2D pixel BLT.
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*/
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typedef volatile struct
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{
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U032 reserved00[4];
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#ifdef __BIG_ENDIAN
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U032 FifoFree;
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#else
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U016 FifoFree;
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U016 Nop[1];
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#endif
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U032 reserved01[0x0BC];
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U032 TopLeft;
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U032 WidthHeight;
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U032 WidthHeightIn;
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U032 reserved02[0x03C];
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U032 Pixels;
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} RivaPixmap;
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/*
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* Filled rectangle combined with monochrome expand. Useful for glyphs.
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*/
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typedef volatile struct
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{
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U032 reserved00[4];
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#ifdef __BIG_ENDIAN
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U032 FifoFree;
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#else
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U016 FifoFree;
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U016 Nop;
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#endif
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U032 reserved01[0x0BB];
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U032 reserved03[(0x040)-1];
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U032 Color1A;
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struct
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{
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U032 TopLeft;
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U032 WidthHeight;
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} UnclippedRectangle[64];
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U032 reserved04[(0x080)-3];
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struct
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{
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U032 TopLeft;
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U032 BottomRight;
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} ClipB;
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U032 Color1B;
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struct
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{
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U032 TopLeft;
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U032 BottomRight;
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} ClippedRectangle[64];
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U032 reserved05[(0x080)-5];
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struct
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{
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U032 TopLeft;
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U032 BottomRight;
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} ClipC;
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U032 Color1C;
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U032 WidthHeightC;
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U032 PointC;
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U032 MonochromeData1C;
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U032 reserved06[(0x080)+121];
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struct
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{
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U032 TopLeft;
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U032 BottomRight;
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} ClipD;
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U032 Color1D;
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U032 WidthHeightInD;
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U032 WidthHeightOutD;
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U032 PointD;
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U032 MonochromeData1D;
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U032 reserved07[(0x080)+120];
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struct
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{
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U032 TopLeft;
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U032 BottomRight;
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} ClipE;
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U032 Color0E;
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U032 Color1E;
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U032 WidthHeightInE;
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U032 WidthHeightOutE;
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U032 PointE;
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U032 MonochromeData01E;
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} RivaBitmap;
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/*
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* 3D textured, Z buffered triangle.
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*/
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typedef volatile struct
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{
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U032 reserved00[4];
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#ifdef __BIG_ENDIAN
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U032 FifoFree;
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#else
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U016 FifoFree;
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U016 Nop;
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#endif
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U032 reserved01[0x0BC];
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U032 TextureOffset;
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U032 TextureFormat;
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U032 TextureFilter;
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U032 FogColor;
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/* This is a problem on LynxOS */
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#ifdef Control
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#undef Control
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#endif
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U032 Control;
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U032 AlphaTest;
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U032 reserved02[0x339];
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U032 FogAndIndex;
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U032 Color;
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float ScreenX;
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float ScreenY;
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float ScreenZ;
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float EyeM;
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float TextureS;
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float TextureT;
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} RivaTexturedTriangle03;
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typedef volatile struct
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{
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U032 reserved00[4];
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#ifdef __BIG_ENDIAN
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U032 FifoFree;
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#else
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U016 FifoFree;
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U016 Nop;
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#endif
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U032 reserved01[0x0BB];
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U032 ColorKey;
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U032 TextureOffset;
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U032 TextureFormat;
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U032 TextureFilter;
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U032 Blend;
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/* This is a problem on LynxOS */
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#ifdef Control
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#undef Control
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#endif
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U032 Control;
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U032 FogColor;
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U032 reserved02[0x39];
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struct
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{
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float ScreenX;
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float ScreenY;
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float ScreenZ;
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float EyeM;
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U032 Color;
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U032 Specular;
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float TextureS;
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float TextureT;
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} Vertex[16];
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U032 DrawTriangle3D;
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} RivaTexturedTriangle05;
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/*
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* 2D line.
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*/
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typedef volatile struct
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{
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U032 reserved00[4];
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#ifdef __BIG_ENDIAN
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U032 FifoFree;
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#else
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U016 FifoFree;
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U016 Nop[1];
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#endif
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U032 reserved01[0x0BC];
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U032 Color; /* source color 0304-0307*/
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U032 Reserved02[0x03e];
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struct { /* start aliased methods in array 0400- */
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U032 point0; /* y_x S16_S16 in pixels 0- 3*/
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U032 point1; /* y_x S16_S16 in pixels 4- 7*/
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} Lin[16]; /* end of aliased methods in array -047f*/
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struct { /* start aliased methods in array 0480- */
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U032 point0X; /* in pixels, 0 at left 0- 3*/
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U032 point0Y; /* in pixels, 0 at top 4- 7*/
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U032 point1X; /* in pixels, 0 at left 8- b*/
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U032 point1Y; /* in pixels, 0 at top c- f*/
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} Lin32[8]; /* end of aliased methods in array -04ff*/
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U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/
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struct { /* start aliased methods in array 0580- */
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U032 x; /* in pixels, 0 at left 0- 3*/
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U032 y; /* in pixels, 0 at top 4- 7*/
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} PolyLin32[16]; /* end of aliased methods in array -05ff*/
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struct { /* start aliased methods in array 0600- */
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U032 color; /* source color 0- 3*/
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U032 point; /* y_x S16_S16 in pixels 4- 7*/
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} ColorPolyLin[16]; /* end of aliased methods in array -067f*/
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} RivaLine;
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/*
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* 2D/3D surfaces
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*/
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typedef volatile struct
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{
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U032 reserved00[4];
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#ifdef __BIG_ENDIAN
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U032 FifoFree;
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||
|
|
#else
|
||
|
|
U016 FifoFree;
|
||
|
|
U016 Nop;
|
||
|
|
#endif
|
||
|
|
U032 reserved01[0x0BE];
|
||
|
|
U032 Offset;
|
||
|
|
} RivaSurface;
|
||
|
|
typedef volatile struct
|
||
|
|
{
|
||
|
|
U032 reserved00[4];
|
||
|
|
#ifdef __BIG_ENDIAN
|
||
|
|
U032 FifoFree;
|
||
|
|
#else
|
||
|
|
U016 FifoFree;
|
||
|
|
U016 Nop;
|
||
|
|
#endif
|
||
|
|
U032 reserved01[0x0BD];
|
||
|
|
U032 Pitch;
|
||
|
|
U032 RenderBufferOffset;
|
||
|
|
U032 ZBufferOffset;
|
||
|
|
} RivaSurface3D;
|
||
|
|
|
||
|
|
/***************************************************************************\
|
||
|
|
* *
|
||
|
|
* Virtualized RIVA H/W interface. *
|
||
|
|
* *
|
||
|
|
\***************************************************************************/
|
||
|
|
|
||
|
|
#define FP_ENABLE 1
|
||
|
|
#define FP_DITHER 2
|
||
|
|
|
||
|
|
struct _riva_hw_inst;
|
||
|
|
struct _riva_hw_state;
|
||
|
|
/*
|
||
|
|
* Virtialized chip interface. Makes RIVA 128 and TNT look alike.
|
||
|
|
*/
|
||
|
|
typedef struct _riva_hw_inst
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* Chip specific settings.
|
||
|
|
*/
|
||
|
|
U032 Architecture;
|
||
|
|
U032 Version;
|
||
|
|
U032 Chipset;
|
||
|
|
U032 CrystalFreqKHz;
|
||
|
|
U032 RamAmountKBytes;
|
||
|
|
U032 MaxVClockFreqKHz;
|
||
|
|
U032 RamBandwidthKBytesPerSec;
|
||
|
|
U032 EnableIRQ;
|
||
|
|
U032 IO;
|
||
|
|
U032 VBlankBit;
|
||
|
|
U032 FifoFreeCount;
|
||
|
|
U032 FifoEmptyCount;
|
||
|
|
U032 CursorStart;
|
||
|
|
U032 flatPanel;
|
||
|
|
Bool twoHeads;
|
||
|
|
/*
|
||
|
|
* Non-FIFO registers.
|
||
|
|
*/
|
||
|
|
volatile U032 __iomem *PCRTC0;
|
||
|
|
volatile U032 __iomem *PCRTC;
|
||
|
|
volatile U032 __iomem *PRAMDAC0;
|
||
|
|
volatile U032 __iomem *PFB;
|
||
|
|
volatile U032 __iomem *PFIFO;
|
||
|
|
volatile U032 __iomem *PGRAPH;
|
||
|
|
volatile U032 __iomem *PEXTDEV;
|
||
|
|
volatile U032 __iomem *PTIMER;
|
||
|
|
volatile U032 __iomem *PMC;
|
||
|
|
volatile U032 __iomem *PRAMIN;
|
||
|
|
volatile U032 __iomem *FIFO;
|
||
|
|
volatile U032 __iomem *CURSOR;
|
||
|
|
volatile U008 __iomem *PCIO0;
|
||
|
|
volatile U008 __iomem *PCIO;
|
||
|
|
volatile U008 __iomem *PVIO;
|
||
|
|
volatile U008 __iomem *PDIO0;
|
||
|
|
volatile U008 __iomem *PDIO;
|
||
|
|
volatile U032 __iomem *PRAMDAC;
|
||
|
|
/*
|
||
|
|
* Common chip functions.
|
||
|
|
*/
|
||
|
|
int (*Busy)(struct _riva_hw_inst *);
|
||
|
|
void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
|
||
|
|
void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
|
||
|
|
void (*SetStartAddress)(struct _riva_hw_inst *,U032);
|
||
|
|
void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032);
|
||
|
|
void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032);
|
||
|
|
int (*ShowHideCursor)(struct _riva_hw_inst *,int);
|
||
|
|
void (*LockUnlock)(struct _riva_hw_inst *, int);
|
||
|
|
/*
|
||
|
|
* Current extended mode settings.
|
||
|
|
*/
|
||
|
|
struct _riva_hw_state *CurrentState;
|
||
|
|
/*
|
||
|
|
* FIFO registers.
|
||
|
|
*/
|
||
|
|
RivaRop __iomem *Rop;
|
||
|
|
RivaPattern __iomem *Patt;
|
||
|
|
RivaClip __iomem *Clip;
|
||
|
|
RivaPixmap __iomem *Pixmap;
|
||
|
|
RivaScreenBlt __iomem *Blt;
|
||
|
|
RivaBitmap __iomem *Bitmap;
|
||
|
|
RivaLine __iomem *Line;
|
||
|
|
RivaTexturedTriangle03 __iomem *Tri03;
|
||
|
|
RivaTexturedTriangle05 __iomem *Tri05;
|
||
|
|
} RIVA_HW_INST;
|
||
|
|
/*
|
||
|
|
* Extended mode state information.
|
||
|
|
*/
|
||
|
|
typedef struct _riva_hw_state
|
||
|
|
{
|
||
|
|
U032 bpp;
|
||
|
|
U032 width;
|
||
|
|
U032 height;
|
||
|
|
U032 interlace;
|
||
|
|
U032 repaint0;
|
||
|
|
U032 repaint1;
|
||
|
|
U032 screen;
|
||
|
|
U032 scale;
|
||
|
|
U032 dither;
|
||
|
|
U032 extra;
|
||
|
|
U032 pixel;
|
||
|
|
U032 horiz;
|
||
|
|
U032 arbitration0;
|
||
|
|
U032 arbitration1;
|
||
|
|
U032 vpll;
|
||
|
|
U032 vpll2;
|
||
|
|
U032 pllsel;
|
||
|
|
U032 general;
|
||
|
|
U032 crtcOwner;
|
||
|
|
U032 head;
|
||
|
|
U032 head2;
|
||
|
|
U032 config;
|
||
|
|
U032 cursorConfig;
|
||
|
|
U032 cursor0;
|
||
|
|
U032 cursor1;
|
||
|
|
U032 cursor2;
|
||
|
|
U032 offset0;
|
||
|
|
U032 offset1;
|
||
|
|
U032 offset2;
|
||
|
|
U032 offset3;
|
||
|
|
U032 pitch0;
|
||
|
|
U032 pitch1;
|
||
|
|
U032 pitch2;
|
||
|
|
U032 pitch3;
|
||
|
|
} RIVA_HW_STATE;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* function prototypes
|
||
|
|
*/
|
||
|
|
|
||
|
|
extern int CalcStateExt
|
||
|
|
(
|
||
|
|
RIVA_HW_INST *chip,
|
||
|
|
RIVA_HW_STATE *state,
|
||
|
|
int bpp,
|
||
|
|
int width,
|
||
|
|
int hDisplaySize,
|
||
|
|
int height,
|
||
|
|
int dotClock
|
||
|
|
);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* External routines.
|
||
|
|
*/
|
||
|
|
int RivaGetConfig(RIVA_HW_INST *, unsigned int);
|
||
|
|
/*
|
||
|
|
* FIFO Free Count. Should attempt to yield processor if RIVA is busy.
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \
|
||
|
|
{ \
|
||
|
|
while ((hwinst).FifoFreeCount < (cnt)) { \
|
||
|
|
mb();mb(); \
|
||
|
|
(hwinst).FifoFreeCount = NV_RD32(&(hwinst).hwptr->FifoFree, 0) >> 2; \
|
||
|
|
} \
|
||
|
|
(hwinst).FifoFreeCount -= (cnt); \
|
||
|
|
}
|
||
|
|
#endif /* __RIVA_HW_H__ */
|
||
|
|
|