frodovdr/satip-axe
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

add idl4k kernel firmware version 1.13.0.105

Browse Source
This commit is contained in:
Jaroslav Kysela
2015-03-26 17:22:37 +01:00
parent 5194d2792e
commit e9070cdc77
31064 changed files with 12769984 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
kernel/arch/arm/mach-ep93xx/include/mach/clkdev.h Normal file
View File

@@ -0,0 +1,7 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

22
kernel/arch/arm/mach-ep93xx/include/mach/debug-macro.S Normal file
View File

@@ -0,0 +1,22 @@
/*
* arch/arm/mach-ep93xx/include/mach/debug-macro.S
* Debugging macro include header
*
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*/
#include <mach/ep93xx-regs.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
ldreq \rx, =EP93XX_APB_PHYS_BASE @ Physical base
ldrne \rx, =EP93XX_APB_VIRT_BASE @ virtual base
orr \rx, \rx, #0x000c0000
.endm
#include <asm/hardware/debug-pl01x.S>

52
kernel/arch/arm/mach-ep93xx/include/mach/dma.h Normal file
View File

@@ -0,0 +1,52 @@
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#include <linux/list.h>
#include <linux/types.h>
struct ep93xx_dma_buffer {
struct list_head list;
u32 bus_addr;
u16 size;
};
struct ep93xx_dma_m2p_client {
char *name;
u8 flags;
void *cookie;
void (*buffer_started)(void *cookie,
struct ep93xx_dma_buffer *buf);
void (*buffer_finished)(void *cookie,
struct ep93xx_dma_buffer *buf,
int bytes, int error);
/* Internal to the DMA code. */
void *channel;
};
#define EP93XX_DMA_M2P_PORT_I2S1 0x00
#define EP93XX_DMA_M2P_PORT_I2S2 0x01
#define EP93XX_DMA_M2P_PORT_AAC1 0x02
#define EP93XX_DMA_M2P_PORT_AAC2 0x03
#define EP93XX_DMA_M2P_PORT_AAC3 0x04
#define EP93XX_DMA_M2P_PORT_I2S3 0x05
#define EP93XX_DMA_M2P_PORT_UART1 0x06
#define EP93XX_DMA_M2P_PORT_UART2 0x07
#define EP93XX_DMA_M2P_PORT_UART3 0x08
#define EP93XX_DMA_M2P_PORT_IRDA 0x09
#define EP93XX_DMA_M2P_PORT_MASK 0x0f
#define EP93XX_DMA_M2P_TX 0x00
#define EP93XX_DMA_M2P_RX 0x10
#define EP93XX_DMA_M2P_ABORT_ON_ERROR 0x20
#define EP93XX_DMA_M2P_IGNORE_ERROR 0x40
#define EP93XX_DMA_M2P_ERROR_MASK 0x60
int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *m2p);
void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *m2p);
void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *m2p,
struct ep93xx_dma_buffer *buf);
void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *m2p,
struct ep93xx_dma_buffer *buf);
void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *m2p);
#endif /* __ASM_ARCH_DMA_H */

59
kernel/arch/arm/mach-ep93xx/include/mach/entry-macro.S Normal file
View File

@@ -0,0 +1,59 @@
/*
* arch/arm/mach-ep93xx/include/mach/entry-macro.S
* IRQ demultiplexing for EP93xx
*
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*/
#include <mach/ep93xx-regs.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =(EP93XX_AHB_VIRT_BASE)
orr \base, \base, #0x000b0000
mov \irqnr, #0
ldr \irqstat, [\base] @ lower 32 interrupts
cmp \irqstat, #0
bne 1001f
eor \base, \base, #0x00070000
ldr \irqstat, [\base] @ upper 32 interrupts
cmp \irqstat, #0
beq 1002f
mov \irqnr, #0x20
1001:
movs \tmp, \irqstat, lsl #16
movne \irqstat, \tmp
addeq \irqnr, \irqnr, #16
movs \tmp, \irqstat, lsl #8
movne \irqstat, \tmp
addeq \irqnr, \irqnr, #8
movs \tmp, \irqstat, lsl #4
movne \irqstat, \tmp
addeq \irqnr, \irqnr, #4
movs \tmp, \irqstat, lsl #2
movne \irqstat, \tmp
addeq \irqnr, \irqnr, #2
movs \tmp, \irqstat, lsl #1
addeq \irqnr, \irqnr, #1
orrs \base, \base, #1
1002:
.endm

228
kernel/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h Normal file
View File

@@ -0,0 +1,228 @@
/*
* arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
*/
#ifndef __ASM_ARCH_EP93XX_REGS_H
#define __ASM_ARCH_EP93XX_REGS_H
/*
* EP93xx Physical Memory Map:
*
* The ASDO pin is sampled at system reset to select a synchronous or
* asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up)
* the synchronous boot mode is selected. When ASDO is "0" (i.e
* pulled-down) the asynchronous boot mode is selected.
*
* In synchronous boot mode nSDCE3 is decoded starting at physical address
* 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
* boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
* decoded at 0xf0000000.
*
* There is known errata for the EP93xx dealing with External Memory
* Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design
* Guidelines" for more information. This document can be found at:
*
* http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
*/
#define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
#define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
#define EP93XX_CS1_PHYS_BASE 0x10000000
#define EP93XX_CS2_PHYS_BASE 0x20000000
#define EP93XX_CS3_PHYS_BASE 0x30000000
#define EP93XX_PCMCIA_PHYS_BASE 0x40000000
#define EP93XX_CS6_PHYS_BASE 0x60000000
#define EP93XX_CS7_PHYS_BASE 0x70000000
#define EP93XX_SDCE0_PHYS_BASE 0xc0000000
#define EP93XX_SDCE1_PHYS_BASE 0xd0000000
#define EP93XX_SDCE2_PHYS_BASE 0xe0000000
#define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */
#define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */
/*
* EP93xx linux memory map:
*
* virt phys size
* fe800000 5M per-platform mappings
* fed00000 80800000 2M APB
* fef00000 80000000 1M AHB
*/
#define EP93XX_AHB_PHYS_BASE 0x80000000
#define EP93XX_AHB_VIRT_BASE 0xfef00000
#define EP93XX_AHB_SIZE 0x00100000
#define EP93XX_AHB_PHYS(x) (EP93XX_AHB_PHYS_BASE + (x))
#define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x))
#define EP93XX_APB_PHYS_BASE 0x80800000
#define EP93XX_APB_VIRT_BASE 0xfed00000
#define EP93XX_APB_SIZE 0x00200000
#define EP93XX_APB_PHYS(x) (EP93XX_APB_PHYS_BASE + (x))
#define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x))
/* AHB peripherals */
#define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000)
#define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000)
#define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000)
#define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000)
#define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000)
#define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000)
#define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000)
#define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000)
#define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000)
#define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000)
#define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
#define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
#define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
#define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000)
/* APB peripherals */
#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000)
#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c)
#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0)
#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc)
#define EP93XX_GPIO_EEDRIVE EP93XX_GPIO_REG(0xc8)
#define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
#define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000)
#define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000)
#define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000)
#define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000)
#define EP93XX_UART2_PHYS_BASE EP93XX_APB_PHYS(0x000d0000)
#define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000)
#define EP93XX_UART3_PHYS_BASE EP93XX_APB_PHYS(0x000e0000)
#define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000)
#define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
#define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
#define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
#define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000)
#define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000)
#define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000)
#define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000)
#define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000)
#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
#define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20)
#define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24)
#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15)
#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
#define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
#endif

42
kernel/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h Normal file
View File

@@ -0,0 +1,42 @@
/*
* arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h
*/
#ifndef __ASM_ARCH_EP93XX_KEYPAD_H
#define __ASM_ARCH_EP93XX_KEYPAD_H
#define MAX_MATRIX_KEY_ROWS (8)
#define MAX_MATRIX_KEY_COLS (8)
/* flags for the ep93xx_keypad driver */
#define EP93XX_KEYPAD_DISABLE_3_KEY (1<<0) /* disable 3-key reset */
#define EP93XX_KEYPAD_DIAG_MODE (1<<1) /* diagnostic mode */
#define EP93XX_KEYPAD_BACK_DRIVE (1<<2) /* back driving mode */
#define EP93XX_KEYPAD_TEST_MODE (1<<3) /* scan only column 0 */
#define EP93XX_KEYPAD_KDIV (1<<4) /* 1/4 clock or 1/16 clock */
#define EP93XX_KEYPAD_AUTOREPEAT (1<<5) /* enable key autorepeat */
/**
* struct ep93xx_keypad_platform_data - platform specific device structure
* @matrix_key_rows: number of rows in the keypad matrix
* @matrix_key_cols: number of columns in the keypad matrix
* @matrix_key_map: array of keycodes defining the keypad matrix
* @matrix_key_map_size: ARRAY_SIZE(matrix_key_map)
* @debounce: debounce start count; terminal count is 0xff
* @prescale: row/column counter pre-scaler load value
* @flags: see above
*/
struct ep93xx_keypad_platform_data {
unsigned int matrix_key_rows;
unsigned int matrix_key_cols;
unsigned int *matrix_key_map;
int matrix_key_map_size;
unsigned int debounce;
unsigned int prescale;
unsigned int flags;
};
/* macro for creating the matrix_key_map table */
#define KEY(row, col, val) (((row) << 28) | ((col) << 24) | (val))
#endif /* __ASM_ARCH_EP93XX_KEYPAD_H */

56
kernel/arch/arm/mach-ep93xx/include/mach/fb.h Normal file
View File

@@ -0,0 +1,56 @@
/*
* arch/arm/mach-ep93xx/include/mach/fb.h
*/
#ifndef __ASM_ARCH_EP93XXFB_H
#define __ASM_ARCH_EP93XXFB_H
struct platform_device;
struct fb_videomode;
struct fb_info;
#define EP93XXFB_USE_MODEDB 0
/* VideoAttributes flags */
#define EP93XXFB_STATE_MACHINE_ENABLE (1 << 0)
#define EP93XXFB_PIXEL_CLOCK_ENABLE (1 << 1)
#define EP93XXFB_VSYNC_ENABLE (1 << 2)
#define EP93XXFB_PIXEL_DATA_ENABLE (1 << 3)
#define EP93XXFB_COMPOSITE_SYNC (1 << 4)
#define EP93XXFB_SYNC_VERT_HIGH (1 << 5)
#define EP93XXFB_SYNC_HORIZ_HIGH (1 << 6)
#define EP93XXFB_SYNC_BLANK_HIGH (1 << 7)
#define EP93XXFB_PCLK_FALLING (1 << 8)
#define EP93XXFB_ENABLE_AC (1 << 9)
#define EP93XXFB_ENABLE_LCD (1 << 10)
#define EP93XXFB_ENABLE_CCIR (1 << 12)
#define EP93XXFB_USE_PARALLEL_INTERFACE (1 << 13)
#define EP93XXFB_ENABLE_INTERRUPT (1 << 14)
#define EP93XXFB_USB_INTERLACE (1 << 16)
#define EP93XXFB_USE_EQUALIZATION (1 << 17)
#define EP93XXFB_USE_DOUBLE_HORZ (1 << 18)
#define EP93XXFB_USE_DOUBLE_VERT (1 << 19)
#define EP93XXFB_USE_BLANK_PIXEL (1 << 20)
#define EP93XXFB_USE_SDCSN0 (0 << 21)
#define EP93XXFB_USE_SDCSN1 (1 << 21)
#define EP93XXFB_USE_SDCSN2 (2 << 21)
#define EP93XXFB_USE_SDCSN3 (3 << 21)
#define EP93XXFB_ENABLE (EP93XXFB_STATE_MACHINE_ENABLE | \
EP93XXFB_PIXEL_CLOCK_ENABLE | \
EP93XXFB_VSYNC_ENABLE | \
EP93XXFB_PIXEL_DATA_ENABLE)
struct ep93xxfb_mach_info {
unsigned int num_modes;
const struct fb_videomode *modes;
const struct fb_videomode *default_mode;
int bpp;
unsigned int flags;
int (*setup)(struct platform_device *pdev);
void (*teardown)(struct platform_device *pdev);
void (*blank)(int blank_mode, struct fb_info *info);
};
#endif /* __ASM_ARCH_EP93XXFB_H */

122
kernel/arch/arm/mach-ep93xx/include/mach/gpio.h Normal file
View File

@@ -0,0 +1,122 @@
/*
* arch/arm/mach-ep93xx/include/mach/gpio.h
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
/* GPIO port A. */
#define EP93XX_GPIO_LINE_A(x) ((x) + 0)
#define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0)
#define EP93XX_GPIO_LINE_EGPIO1 EP93XX_GPIO_LINE_A(1)
#define EP93XX_GPIO_LINE_EGPIO2 EP93XX_GPIO_LINE_A(2)
#define EP93XX_GPIO_LINE_EGPIO3 EP93XX_GPIO_LINE_A(3)
#define EP93XX_GPIO_LINE_EGPIO4 EP93XX_GPIO_LINE_A(4)
#define EP93XX_GPIO_LINE_EGPIO5 EP93XX_GPIO_LINE_A(5)
#define EP93XX_GPIO_LINE_EGPIO6 EP93XX_GPIO_LINE_A(6)
#define EP93XX_GPIO_LINE_EGPIO7 EP93XX_GPIO_LINE_A(7)
/* GPIO port B. */
#define EP93XX_GPIO_LINE_B(x) ((x) + 8)
#define EP93XX_GPIO_LINE_EGPIO8 EP93XX_GPIO_LINE_B(0)
#define EP93XX_GPIO_LINE_EGPIO9 EP93XX_GPIO_LINE_B(1)
#define EP93XX_GPIO_LINE_EGPIO10 EP93XX_GPIO_LINE_B(2)
#define EP93XX_GPIO_LINE_EGPIO11 EP93XX_GPIO_LINE_B(3)
#define EP93XX_GPIO_LINE_EGPIO12 EP93XX_GPIO_LINE_B(4)
#define EP93XX_GPIO_LINE_EGPIO13 EP93XX_GPIO_LINE_B(5)
#define EP93XX_GPIO_LINE_EGPIO14 EP93XX_GPIO_LINE_B(6)
#define EP93XX_GPIO_LINE_EGPIO15 EP93XX_GPIO_LINE_B(7)
/* GPIO port C. */
#define EP93XX_GPIO_LINE_C(x) ((x) + 40)
#define EP93XX_GPIO_LINE_ROW0 EP93XX_GPIO_LINE_C(0)
#define EP93XX_GPIO_LINE_ROW1 EP93XX_GPIO_LINE_C(1)
#define EP93XX_GPIO_LINE_ROW2 EP93XX_GPIO_LINE_C(2)
#define EP93XX_GPIO_LINE_ROW3 EP93XX_GPIO_LINE_C(3)
#define EP93XX_GPIO_LINE_ROW4 EP93XX_GPIO_LINE_C(4)
#define EP93XX_GPIO_LINE_ROW5 EP93XX_GPIO_LINE_C(5)
#define EP93XX_GPIO_LINE_ROW6 EP93XX_GPIO_LINE_C(6)
#define EP93XX_GPIO_LINE_ROW7 EP93XX_GPIO_LINE_C(7)
/* GPIO port D. */
#define EP93XX_GPIO_LINE_D(x) ((x) + 24)
#define EP93XX_GPIO_LINE_COL0 EP93XX_GPIO_LINE_D(0)
#define EP93XX_GPIO_LINE_COL1 EP93XX_GPIO_LINE_D(1)
#define EP93XX_GPIO_LINE_COL2 EP93XX_GPIO_LINE_D(2)
#define EP93XX_GPIO_LINE_COL3 EP93XX_GPIO_LINE_D(3)
#define EP93XX_GPIO_LINE_COL4 EP93XX_GPIO_LINE_D(4)
#define EP93XX_GPIO_LINE_COL5 EP93XX_GPIO_LINE_D(5)
#define EP93XX_GPIO_LINE_COL6 EP93XX_GPIO_LINE_D(6)
#define EP93XX_GPIO_LINE_COL7 EP93XX_GPIO_LINE_D(7)
/* GPIO port E. */
#define EP93XX_GPIO_LINE_E(x) ((x) + 32)
#define EP93XX_GPIO_LINE_GRLED EP93XX_GPIO_LINE_E(0)
#define EP93XX_GPIO_LINE_RDLED EP93XX_GPIO_LINE_E(1)
#define EP93XX_GPIO_LINE_DIORn EP93XX_GPIO_LINE_E(2)
#define EP93XX_GPIO_LINE_IDECS1n EP93XX_GPIO_LINE_E(3)
#define EP93XX_GPIO_LINE_IDECS2n EP93XX_GPIO_LINE_E(4)
#define EP93XX_GPIO_LINE_IDEDA0 EP93XX_GPIO_LINE_E(5)
#define EP93XX_GPIO_LINE_IDEDA1 EP93XX_GPIO_LINE_E(6)
#define EP93XX_GPIO_LINE_IDEDA2 EP93XX_GPIO_LINE_E(7)
/* GPIO port F. */
#define EP93XX_GPIO_LINE_F(x) ((x) + 16)
#define EP93XX_GPIO_LINE_WP EP93XX_GPIO_LINE_F(0)
#define EP93XX_GPIO_LINE_MCCD1 EP93XX_GPIO_LINE_F(1)
#define EP93XX_GPIO_LINE_MCCD2 EP93XX_GPIO_LINE_F(2)
#define EP93XX_GPIO_LINE_MCBVD1 EP93XX_GPIO_LINE_F(3)
#define EP93XX_GPIO_LINE_MCBVD2 EP93XX_GPIO_LINE_F(4)
#define EP93XX_GPIO_LINE_VS1 EP93XX_GPIO_LINE_F(5)
#define EP93XX_GPIO_LINE_READY EP93XX_GPIO_LINE_F(6)
#define EP93XX_GPIO_LINE_VS2 EP93XX_GPIO_LINE_F(7)
/* GPIO port G. */
#define EP93XX_GPIO_LINE_G(x) ((x) + 48)
#define EP93XX_GPIO_LINE_EECLK EP93XX_GPIO_LINE_G(0)
#define EP93XX_GPIO_LINE_EEDAT EP93XX_GPIO_LINE_G(1)
#define EP93XX_GPIO_LINE_SLA0 EP93XX_GPIO_LINE_G(2)
#define EP93XX_GPIO_LINE_SLA1 EP93XX_GPIO_LINE_G(3)
#define EP93XX_GPIO_LINE_DD12 EP93XX_GPIO_LINE_G(4)
#define EP93XX_GPIO_LINE_DD13 EP93XX_GPIO_LINE_G(5)
#define EP93XX_GPIO_LINE_DD14 EP93XX_GPIO_LINE_G(6)
#define EP93XX_GPIO_LINE_DD15 EP93XX_GPIO_LINE_G(7)
/* GPIO port H. */
#define EP93XX_GPIO_LINE_H(x) ((x) + 56)
#define EP93XX_GPIO_LINE_DD0 EP93XX_GPIO_LINE_H(0)
#define EP93XX_GPIO_LINE_DD1 EP93XX_GPIO_LINE_H(1)
#define EP93XX_GPIO_LINE_DD2 EP93XX_GPIO_LINE_H(2)
#define EP93XX_GPIO_LINE_DD3 EP93XX_GPIO_LINE_H(3)
#define EP93XX_GPIO_LINE_DD4 EP93XX_GPIO_LINE_H(4)
#define EP93XX_GPIO_LINE_DD5 EP93XX_GPIO_LINE_H(5)
#define EP93XX_GPIO_LINE_DD6 EP93XX_GPIO_LINE_H(6)
#define EP93XX_GPIO_LINE_DD7 EP93XX_GPIO_LINE_H(7)
/* maximum value for gpio line identifiers */
#define EP93XX_GPIO_LINE_MAX EP93XX_GPIO_LINE_H(7)
/* maximum value for irq capable line identifiers */
#define EP93XX_GPIO_LINE_MAX_IRQ EP93XX_GPIO_LINE_F(7)
extern void ep93xx_gpio_int_debounce(unsigned int irq, int enable);
/* new generic GPIO API - see Documentation/gpio.txt */
#include <asm-generic/gpio.h>
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
/*
* Map GPIO A0..A7 (0..7) to irq 64..71,
* B0..B7 (7..15) to irq 72..79, and
* F0..F7 (16..24) to irq 80..87.
*/
#define gpio_to_irq(gpio) \
(((gpio) <= EP93XX_GPIO_LINE_MAX_IRQ) ? (64 + (gpio)) : -EINVAL)
#define irq_to_gpio(irq) ((irq) - gpio_to_irq(0))
#endif

26
kernel/arch/arm/mach-ep93xx/include/mach/hardware.h Normal file
View File

@@ -0,0 +1,26 @@
/*
* arch/arm/mach-ep93xx/include/mach/hardware.h
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <mach/ep93xx-regs.h>
#include <mach/platform.h>
#define pcibios_assign_all_busses() 0
/*
* The EP93xx has two external crystal oscillators. To generate the
* required high-frequency clocks, the processor uses two phase-locked-
* loops (PLLs) to multiply the incoming external clock signal to much
* higher frequencies that are then divided down by programmable dividers
* to produce the needed clocks. The PLLs operate independently of one
* another.
*/
#define EP93XX_EXT_CLK_RATE 14745600
#define EP93XX_EXT_RTC_RATE 32768
#define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4)
#define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16)
#endif

21
kernel/arch/arm/mach-ep93xx/include/mach/io.h Normal file
View File

@@ -0,0 +1,21 @@
/*
* arch/arm/mach-ep93xx/include/mach/io.h
*/
#ifndef __ASM_MACH_IO_H
#define __ASM_MACH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(p) __typesafe_io(p)
#define __mem_pci(p) (p)
/*
* A typesafe __io() variation for variable initialisers
*/
#ifdef __ASSEMBLER__
#define IOMEM(p) p
#else
#define IOMEM(p) ((void __iomem __force *)(p))
#endif
#endif /* __ASM_MACH_IO_H */

78
kernel/arch/arm/mach-ep93xx/include/mach/irqs.h Normal file
View File

@@ -0,0 +1,78 @@
/*
* arch/arm/mach-ep93xx/include/mach/irqs.h
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#define IRQ_EP93XX_COMMRX 2
#define IRQ_EP93XX_COMMTX 3
#define IRQ_EP93XX_TIMER1 4
#define IRQ_EP93XX_TIMER2 5
#define IRQ_EP93XX_AACINTR 6
#define IRQ_EP93XX_DMAM2P0 7
#define IRQ_EP93XX_DMAM2P1 8
#define IRQ_EP93XX_DMAM2P2 9
#define IRQ_EP93XX_DMAM2P3 10
#define IRQ_EP93XX_DMAM2P4 11
#define IRQ_EP93XX_DMAM2P5 12
#define IRQ_EP93XX_DMAM2P6 13
#define IRQ_EP93XX_DMAM2P7 14
#define IRQ_EP93XX_DMAM2P8 15
#define IRQ_EP93XX_DMAM2P9 16
#define IRQ_EP93XX_DMAM2M0 17
#define IRQ_EP93XX_DMAM2M1 18
#define IRQ_EP93XX_GPIO0MUX 19
#define IRQ_EP93XX_GPIO1MUX 20
#define IRQ_EP93XX_GPIO2MUX 21
#define IRQ_EP93XX_GPIO3MUX 22
#define IRQ_EP93XX_UART1RX 23
#define IRQ_EP93XX_UART1TX 24
#define IRQ_EP93XX_UART2RX 25
#define IRQ_EP93XX_UART2TX 26
#define IRQ_EP93XX_UART3RX 27
#define IRQ_EP93XX_UART3TX 28
#define IRQ_EP93XX_KEY 29
#define IRQ_EP93XX_TOUCH 30
#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc
#define IRQ_EP93XX_EXT0 32
#define IRQ_EP93XX_EXT1 33
#define IRQ_EP93XX_EXT2 34
#define IRQ_EP93XX_64HZ 35
#define IRQ_EP93XX_WATCHDOG 36
#define IRQ_EP93XX_RTC 37
#define IRQ_EP93XX_IRDA 38
#define IRQ_EP93XX_ETHERNET 39
#define IRQ_EP93XX_EXT3 40
#define IRQ_EP93XX_PROG 41
#define IRQ_EP93XX_1HZ 42
#define IRQ_EP93XX_VSYNC 43
#define IRQ_EP93XX_VIDEO_FIFO 44
#define IRQ_EP93XX_SSP1RX 45
#define IRQ_EP93XX_SSP1TX 46
#define IRQ_EP93XX_GPIO4MUX 47
#define IRQ_EP93XX_GPIO5MUX 48
#define IRQ_EP93XX_GPIO6MUX 49
#define IRQ_EP93XX_GPIO7MUX 50
#define IRQ_EP93XX_TIMER3 51
#define IRQ_EP93XX_UART1 52
#define IRQ_EP93XX_SSP 53
#define IRQ_EP93XX_UART2 54
#define IRQ_EP93XX_UART3 55
#define IRQ_EP93XX_USB 56
#define IRQ_EP93XX_ETHERNET_PME 57
#define IRQ_EP93XX_DSP 58
#define IRQ_EP93XX_GPIO_AB 59
#define IRQ_EP93XX_SAI 60
#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff
#define NR_EP93XX_IRQS (64 + 24)
#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x))
#define EP93XX_BOARD_IRQS 32
#define NR_IRQS (NR_EP93XX_IRQS + EP93XX_BOARD_IRQS)
#endif

22
kernel/arch/arm/mach-ep93xx/include/mach/memory.h Normal file
View File

@@ -0,0 +1,22 @@
/*
* arch/arm/mach-ep93xx/include/mach/memory.h
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#if defined(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET)
#define PHYS_OFFSET UL(0x00000000)
#elif defined(CONFIG_EP93XX_SDCE0_PHYS_OFFSET)
#define PHYS_OFFSET UL(0xc0000000)
#elif defined(CONFIG_EP93XX_SDCE1_PHYS_OFFSET)
#define PHYS_OFFSET UL(0xd0000000)
#elif defined(CONFIG_EP93XX_SDCE2_PHYS_OFFSET)
#define PHYS_OFFSET UL(0xe0000000)
#elif defined(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET)
#define PHYS_OFFSET UL(0xf0000000)
#else
#error "Kconfig bug: No EP93xx PHYS_OFFSET set"
#endif
#endif

46
kernel/arch/arm/mach-ep93xx/include/mach/platform.h Normal file
View File

@@ -0,0 +1,46 @@
/*
* arch/arm/mach-ep93xx/include/mach/platform.h
*/
#ifndef __ASSEMBLY__
struct i2c_gpio_platform_data;
struct i2c_board_info;
struct platform_device;
struct ep93xxfb_mach_info;
struct ep93xx_eth_data
{
unsigned char dev_addr[6];
unsigned char phy_id;
};
void ep93xx_map_io(void);
void ep93xx_init_irq(void);
/* EP93xx System Controller software locked register write */
void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
static inline void ep93xx_devcfg_set_bits(unsigned int bits)
{
ep93xx_devcfg_set_clear(bits, 0x00);
}
static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
{
ep93xx_devcfg_set_clear(0x00, bits);
}
void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
void ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
struct i2c_board_info *devices, int num);
void ep93xx_register_fb(struct ep93xxfb_mach_info *data);
void ep93xx_register_pwm(int pwm0, int pwm1);
int ep93xx_pwm_acquire_gpio(struct platform_device *pdev);
void ep93xx_pwm_release_gpio(struct platform_device *pdev);
void ep93xx_init_devices(void);
extern struct sys_timer ep93xx_timer;
#endif

24
kernel/arch/arm/mach-ep93xx/include/mach/system.h Normal file
View File

@@ -0,0 +1,24 @@
/*
* arch/arm/mach-ep93xx/include/mach/system.h
*/
#include <mach/hardware.h>
static inline void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode, const char *cmd)
{
local_irq_disable();
/*
* Set then clear the SWRST bit to initiate a software reset
*/
ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
while (1)
;
}

5
kernel/arch/arm/mach-ep93xx/include/mach/timex.h Normal file
View File

@@ -0,0 +1,5 @@
/*
* arch/arm/mach-ep93xx/include/mach/timex.h
*/
#define CLOCK_TICK_RATE 983040

97
kernel/arch/arm/mach-ep93xx/include/mach/ts72xx.h Normal file
View File

@@ -0,0 +1,97 @@
/*
* arch/arm/mach-ep93xx/include/mach/ts72xx.h
*/
/*
* TS72xx memory map:
*
* virt phys size
* febff000 22000000 4K model number register
* febfe000 22400000 4K options register
* febfd000 22800000 4K options register #2
* febfc000 [67]0000000 4K NAND data register
* febfb000 [67]0400000 4K NAND control register
* febfa000 [67]0800000 4K NAND busy register
* febf9000 10800000 4K TS-5620 RTC index register
* febf8000 11700000 4K TS-5620 RTC data register
*/
#define TS72XX_MODEL_PHYS_BASE 0x22000000
#define TS72XX_MODEL_VIRT_BASE 0xfebff000
#define TS72XX_MODEL_SIZE 0x00001000
#define TS72XX_MODEL_TS7200 0x00
#define TS72XX_MODEL_TS7250 0x01
#define TS72XX_MODEL_TS7260 0x02
#define TS72XX_OPTIONS_PHYS_BASE 0x22400000
#define TS72XX_OPTIONS_VIRT_BASE 0xfebfe000
#define TS72XX_OPTIONS_SIZE 0x00001000
#define TS72XX_OPTIONS_COM2_RS485 0x02
#define TS72XX_OPTIONS_MAX197 0x01
#define TS72XX_OPTIONS2_PHYS_BASE 0x22800000
#define TS72XX_OPTIONS2_VIRT_BASE 0xfebfd000
#define TS72XX_OPTIONS2_SIZE 0x00001000
#define TS72XX_OPTIONS2_TS9420 0x04
#define TS72XX_OPTIONS2_TS9420_BOOT 0x02
#define TS72XX_NAND1_DATA_PHYS_BASE 0x60000000
#define TS72XX_NAND2_DATA_PHYS_BASE 0x70000000
#define TS72XX_NAND_DATA_VIRT_BASE 0xfebfc000
#define TS72XX_NAND_DATA_SIZE 0x00001000
#define TS72XX_NAND1_CONTROL_PHYS_BASE 0x60400000
#define TS72XX_NAND2_CONTROL_PHYS_BASE 0x70400000
#define TS72XX_NAND_CONTROL_VIRT_BASE 0xfebfb000
#define TS72XX_NAND_CONTROL_SIZE 0x00001000
#define TS72XX_NAND1_BUSY_PHYS_BASE 0x60800000
#define TS72XX_NAND2_BUSY_PHYS_BASE 0x70800000
#define TS72XX_NAND_BUSY_VIRT_BASE 0xfebfa000
#define TS72XX_NAND_BUSY_SIZE 0x00001000
#define TS72XX_RTC_INDEX_VIRT_BASE 0xfebf9000
#define TS72XX_RTC_INDEX_PHYS_BASE 0x10800000
#define TS72XX_RTC_INDEX_SIZE 0x00001000
#define TS72XX_RTC_DATA_VIRT_BASE 0xfebf8000
#define TS72XX_RTC_DATA_PHYS_BASE 0x11700000
#define TS72XX_RTC_DATA_SIZE 0x00001000
#ifndef __ASSEMBLY__
static inline int board_is_ts7200(void)
{
return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7200;
}
static inline int board_is_ts7250(void)
{
return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7250;
}
static inline int board_is_ts7260(void)
{
return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7260;
}
static inline int is_max197_installed(void)
{
return !!(__raw_readb(TS72XX_OPTIONS_VIRT_BASE) &
TS72XX_OPTIONS_MAX197);
}
static inline int is_ts9420_installed(void)
{
return !!(__raw_readb(TS72XX_OPTIONS2_VIRT_BASE) &
TS72XX_OPTIONS2_TS9420);
}
#endif

94
kernel/arch/arm/mach-ep93xx/include/mach/uncompress.h Normal file
View File

@@ -0,0 +1,94 @@
/*
* arch/arm/mach-ep93xx/include/mach/uncompress.h
*
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*/
#include <mach/ep93xx-regs.h>
static unsigned char __raw_readb(unsigned int ptr)
{
return *((volatile unsigned char *)ptr);
}
static unsigned int __raw_readl(unsigned int ptr)
{
return *((volatile unsigned int *)ptr);
}
static void __raw_writeb(unsigned char value, unsigned int ptr)
{
*((volatile unsigned char *)ptr) = value;
}
static void __raw_writel(unsigned int value, unsigned int ptr)
{
*((volatile unsigned int *)ptr) = value;
}
#if defined(CONFIG_EP93XX_EARLY_UART1)
#define UART_BASE EP93XX_UART1_PHYS_BASE
#elif defined(CONFIG_EP93XX_EARLY_UART2)
#define UART_BASE EP93XX_UART2_PHYS_BASE
#elif defined(CONFIG_EP93XX_EARLY_UART3)
#define UART_BASE EP93XX_UART3_PHYS_BASE
#else
#define UART_BASE EP93XX_UART1_PHYS_BASE
#endif
#define PHYS_UART_DATA (UART_BASE + 0x00)
#define PHYS_UART_FLAG (UART_BASE + 0x18)
#define UART_FLAG_TXFF 0x20
static inline void putc(int c)
{
int i;
for (i = 0; i < 1000; i++) {
/* Transmit fifo not full? */
if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF))
break;
}
__raw_writeb(c, PHYS_UART_DATA);
}
static inline void flush(void)
{
}
/*
* Some bootloaders don't turn off DMA from the ethernet MAC before
* jumping to linux, which means that we might end up with bits of RX
* status and packet data scribbled over the uncompressed kernel image.
* Work around this by resetting the ethernet MAC before we uncompress.
*/
#define PHYS_ETH_SELF_CTL 0x80010020
#define ETH_SELF_CTL_RESET 0x00000001
static void ethernet_reset(void)
{
unsigned int v;
/* Reset the ethernet MAC. */
v = __raw_readl(PHYS_ETH_SELF_CTL);
__raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL);
/* Wait for reset to finish. */
while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET)
;
}
static void arch_decomp_setup(void)
{
ethernet_reset();
}
#define arch_decomp_wdog()

5
kernel/arch/arm/mach-ep93xx/include/mach/vmalloc.h Normal file
View File

@@ -0,0 +1,5 @@
/*
* arch/arm/mach-ep93xx/include/mach/vmalloc.h
*/
#define VMALLOC_END 0xfe800000