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add idl4k kernel firmware version 1.13.0.105

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This commit is contained in:
Jaroslav Kysela
2015-03-26 17:22:37 +01:00
parent 5194d2792e
commit e9070cdc77
31064 changed files with 12769984 additions and 0 deletions
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62
kernel/arch/arm/mach-pnx4008/include/mach/clock.h Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/clock.h
*
* Clock control driver for PNX4008 - header file
*
* Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __PNX4008_CLOCK_H__
#define __PNX4008_CLOCK_H__
struct module;
struct clk;
#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
#define HCLKDIVCTRL_REG (PWRMAN_VA_BASE + 0x40)
#define PWRCTRL_REG (PWRMAN_VA_BASE + 0x44)
#define PLLCTRL_REG (PWRMAN_VA_BASE + 0x48)
#define OSC13CTRL_REG (PWRMAN_VA_BASE + 0x4c)
#define SYSCLKCTRL_REG (PWRMAN_VA_BASE + 0x50)
#define HCLKPLLCTRL_REG (PWRMAN_VA_BASE + 0x58)
#define USBCTRL_REG (PWRMAN_VA_BASE + 0x64)
#define SDRAMCLKCTRL_REG (PWRMAN_VA_BASE + 0x68)
#define MSCTRL_REG (PWRMAN_VA_BASE + 0x80)
#define BTCLKCTRL (PWRMAN_VA_BASE + 0x84)
#define DUMCLKCTRL_REG (PWRMAN_VA_BASE + 0x90)
#define I2CCLKCTRL_REG (PWRMAN_VA_BASE + 0xac)
#define KEYCLKCTRL_REG (PWRMAN_VA_BASE + 0xb0)
#define TSCLKCTRL_REG (PWRMAN_VA_BASE + 0xb4)
#define PWMCLKCTRL_REG (PWRMAN_VA_BASE + 0xb8)
#define TIMCLKCTRL_REG (PWRMAN_VA_BASE + 0xbc)
#define SPICTRL_REG (PWRMAN_VA_BASE + 0xc4)
#define FLASHCLKCTRL_REG (PWRMAN_VA_BASE + 0xc8)
#define UART3CLK_REG (PWRMAN_VA_BASE + 0xd0)
#define UARTCLKCTRL_REG (PWRMAN_VA_BASE + 0xe4)
#define DMACLKCTRL_REG (PWRMAN_VA_BASE + 0xe8)
#define AUTOCLK_CTRL (PWRMAN_VA_BASE + 0xec)
#define JPEGCLKCTRL_REG (PWRMAN_VA_BASE + 0xfc)
#define AUDIOCONFIG_VA_BASE IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
#define DSPPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x60)
#define DSPCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x64)
#define AUDIOCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x68)
#define AUDIOPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x6C)
#define USB_OTG_CLKCTRL_REG IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
#define VFP9CLKCTRL_REG IO_ADDRESS(PNX4008_DEBUG_BASE)
#define CLK_RATE_13MHZ 13000
#define CLK_RATE_1MHZ 1000
#define CLK_RATE_208MHZ 208000
#define CLK_RATE_48MHZ 48000
#define CLK_RATE_32KHZ 32
#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
#endif

23
kernel/arch/arm/mach-pnx4008/include/mach/debug-macro.S Normal file
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/* arch/arm/mach-pnx4008/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
mov \rx, #0x00090000
addeq \rx, \rx, #0x40000000
addne \rx, \rx, #0xf4000000
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>

160
kernel/arch/arm/mach-pnx4008/include/mach/dma.h Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/dma.h
*
* PNX4008 DMA header file
*
* Author: Vitaly Wool
* Copyright: MontaVista Software Inc. (c) 2005
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#include "platform.h"
#define MAX_DMA_CHANNELS 8
#define DMAC_BASE IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
#define DMAC_INT_STAT (DMAC_BASE + 0x0000)
#define DMAC_INT_TC_STAT (DMAC_BASE + 0x0004)
#define DMAC_INT_TC_CLEAR (DMAC_BASE + 0x0008)
#define DMAC_INT_ERR_STAT (DMAC_BASE + 0x000c)
#define DMAC_INT_ERR_CLEAR (DMAC_BASE + 0x0010)
#define DMAC_SOFT_SREQ (DMAC_BASE + 0x0024)
#define DMAC_CONFIG (DMAC_BASE + 0x0030)
#define DMAC_Cx_SRC_ADDR(c) (DMAC_BASE + 0x0100 + (c) * 0x20)
#define DMAC_Cx_DEST_ADDR(c) (DMAC_BASE + 0x0104 + (c) * 0x20)
#define DMAC_Cx_LLI(c) (DMAC_BASE + 0x0108 + (c) * 0x20)
#define DMAC_Cx_CONTROL(c) (DMAC_BASE + 0x010c + (c) * 0x20)
#define DMAC_Cx_CONFIG(c) (DMAC_BASE + 0x0110 + (c) * 0x20)
enum {
WIDTH_BYTE = 0,
WIDTH_HWORD,
WIDTH_WORD
};
enum {
FC_MEM2MEM_DMA,
FC_MEM2PER_DMA,
FC_PER2MEM_DMA,
FC_PER2PER_DMA,
FC_PER2PER_DPER,
FC_MEM2PER_PER,
FC_PER2MEM_PER,
FC_PER2PER_SPER
};
enum {
DMA_INT_UNKNOWN = 0,
DMA_ERR_INT = 1,
DMA_TC_INT = 2,
};
enum {
DMA_BUFFER_ALLOCATED = 1,
DMA_HAS_LL = 2,
};
enum {
PER_CAM_DMA_1 = 0,
PER_NDF_FLASH = 1,
PER_MBX_SLAVE_FIFO = 2,
PER_SPI2_REC_XMIT = 3,
PER_MS_SD_RX_XMIT = 4,
PER_HS_UART_1_XMIT = 5,
PER_HS_UART_1_RX = 6,
PER_HS_UART_2_XMIT = 7,
PER_HS_UART_2_RX = 8,
PER_HS_UART_7_XMIT = 9,
PER_HS_UART_7_RX = 10,
PER_SPI1_REC_XMIT = 11,
PER_MLC_NDF_SREC = 12,
PER_CAM_DMA_2 = 13,
PER_PRNG_INFIFO = 14,
PER_PRNG_OUTFIFO = 15,
};
struct pnx4008_dma_ch_ctrl {
int tc_mask;
int cacheable;
int bufferable;
int priv_mode;
int di;
int si;
int dest_ahb1;
int src_ahb1;
int dwidth;
int swidth;
int dbsize;
int sbsize;
int tr_size;
};
struct pnx4008_dma_ch_config {
int halt;
int active;
int lock;
int itc;
int ie;
int flow_cntrl;
int dest_per;
int src_per;
};
struct pnx4008_dma_ll {
unsigned long src_addr;
unsigned long dest_addr;
u32 next_dma;
unsigned long ch_ctrl;
struct pnx4008_dma_ll *next;
int flags;
void *alloc_data;
int (*free) (void *);
};
struct pnx4008_dma_config {
int is_ll;
unsigned long src_addr;
unsigned long dest_addr;
unsigned long ch_ctrl;
unsigned long ch_cfg;
struct pnx4008_dma_ll *ll;
u32 ll_dma;
int flags;
void *alloc_data;
int (*free) (void *);
};
extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
extern int pnx4008_request_channel(char *, int,
void (*)(int, int, void *),
void *);
extern void pnx4008_free_channel(int);
extern int pnx4008_config_dma(int, int, int);
extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
unsigned long *);
extern int pnx4008_dma_parse_control(unsigned long,
struct pnx4008_dma_ch_ctrl *);
extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
unsigned long *);
extern int pnx4008_dma_parse_config(unsigned long,
struct pnx4008_dma_ch_config *);
extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
extern int pnx4008_dma_ch_enable(int);
extern int pnx4008_dma_ch_disable(int);
extern int pnx4008_dma_ch_enabled(int);
extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
struct pnx4008_dma_ch_ctrl *);
extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
struct pnx4008_dma_ch_ctrl *);
#endif /* _ASM_ARCH_DMA_H */

127
kernel/arch/arm/mach-pnx4008/include/mach/entry-macro.S Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for PNX4008-based platforms
*
* 2005-2006 (c) MontaVista Software, Inc.
* Author: Vitaly Wool <vwool@ru.mvista.com>
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "platform.h"
#define IO_BASE 0xF0000000
#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
#define INTRC_MASK 0x00
#define INTRC_RAW_STAT 0x04
#define INTRC_STAT 0x08
#define INTRC_POLAR 0x0C
#define INTRC_ACT_TYPE 0x10
#define INTRC_TYPE 0x14
#define SIC1_BASE_INT 32
#define SIC2_BASE_INT 64
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
/* decode the MIC interrupt numbers */
ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
ldr \irqstat, [\base, #INTRC_STAT]
cmp \irqstat,#1<<16
movhs \irqnr,#16
movlo \irqnr,#0
movhs \irqstat,\irqstat,lsr#16
cmp \irqstat,#1<<8
addhs \irqnr,\irqnr,#8
movhs \irqstat,\irqstat,lsr#8
cmp \irqstat,#1<<4
addhs \irqnr,\irqnr,#4
movhs \irqstat,\irqstat,lsr#4
cmp \irqstat,#1<<2
addhs \irqnr,\irqnr,#2
movhs \irqstat,\irqstat,lsr#2
cmp \irqstat,#1<<1
addhs \irqnr,\irqnr,#1
/* was there an interrupt ? if not then drop out with EQ status */
teq \irqstat,#0
beq 1003f
/* and now check for extended IRQ reasons */
cmp \irqnr,#1
bls 1003f
cmp \irqnr,#30
blo 1002f
/* IRQ 31,30 : High priority cascade IRQ handle */
/* read the correct SIC */
/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
/* set the base IRQ number */
ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
moveq \irqnr,#SIC1_BASE_INT
ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
movne \irqnr,#SIC2_BASE_INT
ldr \irqstat, [\base, #INTRC_STAT]
ldr \tmp, [\base, #INTRC_TYPE]
/* and with inverted mask : low priority interrupts */
and \irqstat,\irqstat,\tmp
b 1004f
1003:
/* IRQ 1,0 : Low priority cascade IRQ handle */
/* read the correct SIC */
/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
/* read the correct SIC */
/* set the base IRQ number */
ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
movne \irqnr,#SIC1_BASE_INT
ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
moveq \irqnr,#SIC2_BASE_INT
ldr \irqstat, [\base, #INTRC_STAT]
ldr \tmp, [\base, #INTRC_TYPE]
/* and with inverted mask : low priority interrupts */
bic \irqstat,\irqstat,\tmp
1004:
cmp \irqstat,#1<<16
addhs \irqnr,\irqnr,#16
movhs \irqstat,\irqstat,lsr#16
cmp \irqstat,#1<<8
addhs \irqnr,\irqnr,#8
movhs \irqstat,\irqstat,lsr#8
cmp \irqstat,#1<<4
addhs \irqnr,\irqnr,#4
movhs \irqstat,\irqstat,lsr#4
cmp \irqstat,#1<<2
addhs \irqnr,\irqnr,#2
movhs \irqstat,\irqstat,lsr#2
cmp \irqstat,#1<<1
addhs \irqnr,\irqnr,#1
/* is irqstat not zero */
1002:
/* we assert that irqstat is not equal to zero and return ne status if true*/
teq \irqstat,#0
1003:
.endm
.macro irq_prio_table
.endm

241
kernel/arch/arm/mach-pnx4008/include/mach/gpio.h Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/gpio.h
*
* PNX4008 GPIO driver - header file
*
* Author: Dmitry Chigirev <source@mvista.com>
*
* Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
* Copyright (c) 2005 Koninklijke Philips Electronics N.V.
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef _PNX4008_GPIO_H_
#define _PNX4008_GPIO_H_
/* Block numbers */
#define GPIO_IN (0)
#define GPIO_OUT (0x100)
#define GPIO_BID (0x200)
#define GPIO_RAM (0x300)
#define GPIO_MUX (0x400)
#define GPIO_TYPE_MASK(K) ((K) & 0x700)
/* INPUT GPIOs */
/* GPI */
#define GPI_00 (GPIO_IN | 0)
#define GPI_01 (GPIO_IN | 1)
#define GPI_02 (GPIO_IN | 2)
#define GPI_03 (GPIO_IN | 3)
#define GPI_04 (GPIO_IN | 4)
#define GPI_05 (GPIO_IN | 5)
#define GPI_06 (GPIO_IN | 6)
#define GPI_07 (GPIO_IN | 7)
#define GPI_08 (GPIO_IN | 8)
#define GPI_09 (GPIO_IN | 9)
#define U1_RX (GPIO_IN | 15)
#define U2_HTCS (GPIO_IN | 16)
#define U2_RX (GPIO_IN | 17)
#define U3_RX (GPIO_IN | 18)
#define U4_RX (GPIO_IN | 19)
#define U5_RX (GPIO_IN | 20)
#define U6_IRRX (GPIO_IN | 21)
#define U7_HCTS (GPIO_IN | 22)
#define U7_RX (GPIO_IN | 23)
/* MISC IN */
#define SPI1_DATIN (GPIO_IN | 25)
#define DISP_SYNC (GPIO_IN | 26)
#define SPI2_DATIN (GPIO_IN | 27)
#define GPI_11 (GPIO_IN | 28)
#define GPIO_IN_MASK 0x1eff83ff
/* OUTPUT GPIOs */
/* GPO */
#define GPO_00 (GPIO_OUT | 0)
#define GPO_01 (GPIO_OUT | 1)
#define GPO_02 (GPIO_OUT | 2)
#define GPO_03 (GPIO_OUT | 3)
#define GPO_04 (GPIO_OUT | 4)
#define GPO_05 (GPIO_OUT | 5)
#define GPO_06 (GPIO_OUT | 6)
#define GPO_07 (GPIO_OUT | 7)
#define GPO_08 (GPIO_OUT | 8)
#define GPO_09 (GPIO_OUT | 9)
#define GPO_10 (GPIO_OUT | 10)
#define GPO_11 (GPIO_OUT | 11)
#define GPO_12 (GPIO_OUT | 12)
#define GPO_13 (GPIO_OUT | 13)
#define GPO_14 (GPIO_OUT | 14)
#define GPO_15 (GPIO_OUT | 15)
#define GPO_16 (GPIO_OUT | 16)
#define GPO_17 (GPIO_OUT | 17)
#define GPO_18 (GPIO_OUT | 18)
#define GPO_19 (GPIO_OUT | 19)
#define GPO_20 (GPIO_OUT | 20)
#define GPO_21 (GPIO_OUT | 21)
#define GPO_22 (GPIO_OUT | 22)
#define GPO_23 (GPIO_OUT | 23)
#define GPIO_OUT_MASK 0xffffff
/* BIDIRECTIONAL GPIOs */
/* RAM pins */
#define RAM_D19 (GPIO_RAM | 0)
#define RAM_D20 (GPIO_RAM | 1)
#define RAM_D21 (GPIO_RAM | 2)
#define RAM_D22 (GPIO_RAM | 3)
#define RAM_D23 (GPIO_RAM | 4)
#define RAM_D24 (GPIO_RAM | 5)
#define RAM_D25 (GPIO_RAM | 6)
#define RAM_D26 (GPIO_RAM | 7)
#define RAM_D27 (GPIO_RAM | 8)
#define RAM_D28 (GPIO_RAM | 9)
#define RAM_D29 (GPIO_RAM | 10)
#define RAM_D30 (GPIO_RAM | 11)
#define RAM_D31 (GPIO_RAM | 12)
#define GPIO_RAM_MASK 0x1fff
/* I/O pins */
#define GPIO_00 (GPIO_BID | 25)
#define GPIO_01 (GPIO_BID | 26)
#define GPIO_02 (GPIO_BID | 27)
#define GPIO_03 (GPIO_BID | 28)
#define GPIO_04 (GPIO_BID | 29)
#define GPIO_05 (GPIO_BID | 30)
#define GPIO_BID_MASK 0x7e000000
/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
#define GPIO_SDRAM_SEL (GPIO_MUX | 3)
#define GPIO_MUX_MASK 0x8
/* Extraction/assembly macros */
#define GPIO_BIT_MASK(K) ((K) & 0x1F)
#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
#define GPIO_ISIN(K) ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
/* Start Enable Pin Interrupts - table 58 page 66 */
#define SE_PIN_BASE_INT 32
#define SE_U7_RX_INT 63
#define SE_U7_HCTS_INT 62
#define SE_BT_CLKREQ_INT 61
#define SE_U6_IRRX_INT 60
/*59 unused*/
#define SE_U5_RX_INT 58
#define SE_GPI_11_INT 57
#define SE_U3_RX_INT 56
#define SE_U2_HCTS_INT 55
#define SE_U2_RX_INT 54
#define SE_U1_RX_INT 53
#define SE_DISP_SYNC_INT 52
/*51 unused*/
#define SE_SDIO_INT_N 50
#define SE_MSDIO_START_INT 49
#define SE_GPI_06_INT 48
#define SE_GPI_05_INT 47
#define SE_GPI_04_INT 46
#define SE_GPI_03_INT 45
#define SE_GPI_02_INT 44
#define SE_GPI_01_INT 43
#define SE_GPI_00_INT 42
#define SE_SYSCLKEN_PIN_INT 41
#define SE_SPI1_DATAIN_INT 40
#define SE_GPI_07_INT 39
#define SE_SPI2_DATAIN_INT 38
#define SE_GPI_10_INT 37
#define SE_GPI_09_INT 36
#define SE_GPI_08_INT 35
/*34-32 unused*/
/* Start Enable Internal Interrupts - table 57 page 65 */
#define SE_INT_BASE_INT 0
#define SE_TS_IRQ 31
#define SE_TS_P_INT 30
#define SE_TS_AUX_INT 29
/*27-28 unused*/
#define SE_USB_AHB_NEED_CLK_INT 26
#define SE_MSTIMER_INT 25
#define SE_RTC_INT 24
#define SE_USB_NEED_CLK_INT 23
#define SE_USB_INT 22
#define SE_USB_I2C_INT 21
#define SE_USB_OTG_TIMER_INT 20
#define SE_USB_OTG_ATX_INT_N 19
/*18 unused*/
#define SE_DSP_GPIO4_INT 17
#define SE_KEY_IRQ 16
#define SE_DSP_SLAVEPORT_INT 15
#define SE_DSP_GPIO1_INT 14
#define SE_DSP_GPIO0_INT 13
#define SE_DSP_AHB_INT 12
/*11-6 unused*/
#define SE_GPIO_05_INT 5
#define SE_GPIO_04_INT 4
#define SE_GPIO_03_INT 3
#define SE_GPIO_02_INT 2
#define SE_GPIO_01_INT 1
#define SE_GPIO_00_INT 0
#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
extern int pnx4008_gpio_register_pin(unsigned short pin);
extern int pnx4008_gpio_unregister_pin(unsigned short pin);
extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
static inline void start_int_umask(u8 irq)
{
__raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
}
static inline void start_int_mask(u8 irq)
{
__raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
}
static inline void start_int_ack(u8 irq)
{
__raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
}
static inline void start_int_set_falling_edge(u8 irq)
{
__raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
}
static inline void start_int_set_rising_edge(u8 irq)
{
__raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
}
#endif /* _PNX4008_GPIO_H_ */

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kernel/arch/arm/mach-pnx4008/include/mach/hardware.h Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/hardware.h
*
* Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
#include <mach/platform.h>
/* Start of virtual addresses for IO devices */
#define IO_BASE 0xF0000000
/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
#endif

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/*
* PNX4008-specific tweaks for I2C IP3204 block
*
* Author: Vitaly Wool <vwool@ru.mvista.com>
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_ARCH_I2C_H__
#define __ASM_ARCH_I2C_H__
enum {
mstatus_tdi = 0x00000001,
mstatus_afi = 0x00000002,
mstatus_nai = 0x00000004,
mstatus_drmi = 0x00000008,
mstatus_active = 0x00000020,
mstatus_scl = 0x00000040,
mstatus_sda = 0x00000080,
mstatus_rff = 0x00000100,
mstatus_rfe = 0x00000200,
mstatus_tff = 0x00000400,
mstatus_tfe = 0x00000800,
};
enum {
mcntrl_tdie = 0x00000001,
mcntrl_afie = 0x00000002,
mcntrl_naie = 0x00000004,
mcntrl_drmie = 0x00000008,
mcntrl_daie = 0x00000020,
mcntrl_rffie = 0x00000040,
mcntrl_tffie = 0x00000080,
mcntrl_reset = 0x00000100,
mcntrl_cdbmode = 0x00000400,
};
enum {
rw_bit = 1 << 0,
start_bit = 1 << 8,
stop_bit = 1 << 9,
};
#define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
#define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
#define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
#define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
#define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
#define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
#define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
#define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
#define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */
#define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */
#define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */
#define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */
#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */
#define HCLK_MHZ 13
#define I2C_CHIP_NAME "PNX4008-I2C"
#endif /* __ASM_ARCH_I2C_H___ */

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/*
* arch/arm/mach-pnx4008/include/mach/io.h
*
* Author: Dmitry Chigirev <chigirev@ru.mvista.com>
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

42
kernel/arch/arm/mach-pnx4008/include/mach/irq.h Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/irq.h
*
* PNX4008 IRQ controller driver - header file
* this one is used in entry-arnv.S as well so it cannot contain C code
*
* Copyright (c) 2005 Philips Semiconductors
* Copyright (c) 2005 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __PNX4008_IRQ_H__
#define __PNX4008_IRQ_H__
#define MIC_VA_BASE IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
#define SIC1_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
#define SIC2_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
/* Manual: Chapter 20, page 195 */
#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
#define INTC_ER(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
#define INTC_RSR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
#define INTC_SR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
#define INTC_APR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
#define INTC_ATR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
#define INTC_ITR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
extern void __init pnx4008_init_irq(void);
#endif /* __PNX4008_IRQ_H__ */

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/*
* arch/arm/mach-pnx4008/include/mach/irqs.h
*
* PNX4008 IRQ controller driver - header file
*
* Author: Dmitry Chigirev <source@mvista.com>
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __PNX4008_IRQS_h__
#define __PNX4008_IRQS_h__
#define NR_IRQS 96
/*Manual: table 259, page 199*/
/*SUB2 Interrupt Routing (SIC2)*/
#define SIC2_BASE_INT 64
#define CLK_SWITCH_ARM_INT 95 /*manual: Clkswitch ARM */
#define CLK_SWITCH_DSP_INT 94 /*manual: ClkSwitch DSP */
#define CLK_SWITCH_AUD_INT 93 /*manual: Clkswitch AUD */
#define GPI_06_INT 92
#define GPI_05_INT 91
#define GPI_04_INT 90
#define GPI_03_INT 89
#define GPI_02_INT 88
#define GPI_01_INT 87
#define GPI_00_INT 86
#define BT_CLKREQ_INT 85
#define SPI1_DATIN_INT 84
#define U5_RX_INT 83
#define SDIO_INT_N 82
#define CAM_HS_INT 81
#define CAM_VS_INT 80
#define GPI_07_INT 79
#define DISP_SYNC_INT 78
#define DSP_INT8 77
#define U7_HCTS_INT 76
#define GPI_10_INT 75
#define GPI_09_INT 74
#define GPI_08_INT 73
#define DSP_INT7 72
#define U2_HCTS_INT 71
#define SPI2_DATIN_INT 70
#define GPIO_05_INT 69
#define GPIO_04_INT 68
#define GPIO_03_INT 67
#define GPIO_02_INT 66
#define GPIO_01_INT 65
#define GPIO_00_INT 64
/*Manual: table 258, page 198*/
/*SUB1 Interrupt Routing (SIC1)*/
#define SIC1_BASE_INT 32
#define USB_I2C_INT 63
#define USB_DEV_HP_INT 62
#define USB_DEV_LP_INT 61
#define USB_DEV_DMA_INT 60
#define USB_HOST_INT 59
#define USB_OTG_ATX_INT_N 58
#define USB_OTG_TIMER_INT 57
#define SW_INT 56
#define SPI1_INT 55
#define KEY_IRQ 54
#define DSP_M_INT 53
#define RTC_INT 52
#define I2C_1_INT 51
#define I2C_2_INT 50
#define PLL1_LOCK_INT 49
#define PLL2_LOCK_INT 48
#define PLL3_LOCK_INT 47
#define PLL4_LOCK_INT 46
#define PLL5_LOCK_INT 45
#define SPI2_INT 44
#define DSP_INT1 43
#define DSP_INT2 42
#define DSP_TDM_INT2 41
#define TS_AUX_INT 40
#define TS_IRQ 39
#define TS_P_INT 38
#define UOUT1_TO_PAD_INT 37
#define GPI_11_INT 36
#define DSP_INT4 35
#define JTAG_COMM_RX_INT 34
#define JTAG_COMM_TX_INT 33
#define DSP_INT3 32
/*Manual: table 257, page 197*/
/*MAIN Interrupt Routing*/
#define MAIN_BASE_INT 0
#define SUB2_FIQ_N 31 /*active low */
#define SUB1_FIQ_N 30 /*active low */
#define JPEG_INT 29
#define DMA_INT 28
#define MSTIMER_INT 27
#define IIR1_INT 26
#define IIR2_INT 25
#define IIR7_INT 24
#define DSP_TDM_INT0 23
#define DSP_TDM_INT1 22
#define DSP_P_INT 21
#define DSP_INT0 20
#define DUM_INT 19
#define UOUT0_TO_PAD_INT 18
#define MP4_ENC_INT 17
#define MP4_DEC_INT 16
#define SD0_INT 15
#define MBX_INT 14
#define SD1_INT 13
#define MS_INT_N 12
#define FLASH_INT 11 /*NAND*/
#define IIR6_INT 10
#define IIR5_INT 9
#define IIR4_INT 8
#define IIR3_INT 7
#define WATCH_INT 6
#define HSTIMER_INT 5
#define ARCH_TIMER_IRQ HSTIMER_INT
#define CAM_INT 4
#define PRNG_INT 3
#define CRYPTO_INT 2
#define SUB2_IRQ_N 1 /*active low */
#define SUB1_IRQ_N 0 /*active low */
#define PNX4008_IRQ_TYPES \
{ /*IRQ #'s: */ \
IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 0, 1, 2, 3 */ \
IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 4, 5, 6, 7 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 8, 9,10,11 */ \
IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 28,29,30,31 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 48,49,50,51 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */ \
IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */ \
}
/* Start Enable Pin Interrupts - table 58 page 66 */
#define SE_PIN_BASE_INT 32
#define SE_U7_RX_INT 63
#define SE_U7_HCTS_INT 62
#define SE_BT_CLKREQ_INT 61
#define SE_U6_IRRX_INT 60
/*59 unused*/
#define SE_U5_RX_INT 58
#define SE_GPI_11_INT 57
#define SE_U3_RX_INT 56
#define SE_U2_HCTS_INT 55
#define SE_U2_RX_INT 54
#define SE_U1_RX_INT 53
#define SE_DISP_SYNC_INT 52
/*51 unused*/
#define SE_SDIO_INT_N 50
#define SE_MSDIO_START_INT 49
#define SE_GPI_06_INT 48
#define SE_GPI_05_INT 47
#define SE_GPI_04_INT 46
#define SE_GPI_03_INT 45
#define SE_GPI_02_INT 44
#define SE_GPI_01_INT 43
#define SE_GPI_00_INT 42
#define SE_SYSCLKEN_PIN_INT 41
#define SE_SPI1_DATAIN_INT 40
#define SE_GPI_07_INT 39
#define SE_SPI2_DATAIN_INT 38
#define SE_GPI_10_INT 37
#define SE_GPI_09_INT 36
#define SE_GPI_08_INT 35
/*34-32 unused*/
/* Start Enable Internal Interrupts - table 57 page 65 */
#define SE_INT_BASE_INT 0
#define SE_TS_IRQ 31
#define SE_TS_P_INT 30
#define SE_TS_AUX_INT 29
/*27-28 unused*/
#define SE_USB_AHB_NEED_CLK_INT 26
#define SE_MSTIMER_INT 25
#define SE_RTC_INT 24
#define SE_USB_NEED_CLK_INT 23
#define SE_USB_INT 22
#define SE_USB_I2C_INT 21
#define SE_USB_OTG_TIMER_INT 20
#endif /* __PNX4008_IRQS_h__ */

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kernel/arch/arm/mach-pnx4008/include/mach/memory.h Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/memory.h
*
* Copyright (c) 2005 Philips Semiconductors
* Copyright (c) 2005 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET UL(0x80000000)
#endif

21
kernel/arch/arm/mach-pnx4008/include/mach/param.h Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/param.h
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define HZ 100

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kernel/arch/arm/mach-pnx4008/include/mach/platform.h Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/platform.h
*
* PNX4008 Base addresses - header file
*
* Author: Dmitry Chigirev <source@mvista.com>
*
* Based on reference code received from Philips:
* Copyright (C) 2003 Philips Semiconductors
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_ARCH_PLATFORM_H__
#define __ASM_ARCH_PLATFORM_H__
#define PNX4008_IRAM_BASE 0x08000000
#define PNX4008_IRAM_SIZE 0x00010000
#define PNX4008_YUV_SLAVE_BASE 0x10000000
#define PNX4008_DUM_SLAVE_BASE 0x18000000
#define PNX4008_NDF_FLASH_BASE 0x20020000
#define PNX4008_SPI1_BASE 0x20088000
#define PNX4008_SPI2_BASE 0x20090000
#define PNX4008_SD_CONFIG_BASE 0x20098000
#define PNX4008_FLASH_DATA 0x200B0000
#define PNX4008_MLC_FLASH_BASE 0x200B8000
#define PNX4008_JPEG_CONFIG_BASE 0x300A0000
#define PNX4008_DMA_CONFIG_BASE 0x31000000
#define PNX4008_USB_CONFIG_BASE 0x31020000
#define PNX4008_SDRAM_CFG_BASE 0x31080000
#define PNX4008_AHB2FAB_BASE 0x40000000
#define PNX4008_PWRMAN_BASE 0x40004000
#define PNX4008_INTCTRLMIC_BASE 0x40008000
#define PNX4008_INTCTRLSIC1_BASE 0x4000C000
#define PNX4008_INTCTRLSIC2_BASE 0x40010000
#define PNX4008_HSUART1_BASE 0x40014000
#define PNX4008_HSUART2_BASE 0x40018000
#define PNX4008_HSUART7_BASE 0x4001C000
#define PNX4008_RTC_BASE 0x40024000
#define PNX4008_PIO_BASE 0x40028000
#define PNX4008_MSTIMER_BASE 0x40034000
#define PNX4008_HSTIMER_BASE 0x40038000
#define PNX4008_WDOG_BASE 0x4003C000
#define PNX4008_DEBUG_BASE 0x40040000
#define PNX4008_TOUCH1_BASE 0x40048000
#define PNX4008_KEYSCAN_BASE 0x40050000
#define PNX4008_UARTCTRL_BASE 0x40054000
#define PNX4008_PWM_BASE 0x4005C000
#define PNX4008_UART3_BASE 0x40080000
#define PNX4008_UART4_BASE 0x40088000
#define PNX4008_UART5_BASE 0x40090000
#define PNX4008_UART6_BASE 0x40098000
#define PNX4008_I2C1_BASE 0x400A0000
#define PNX4008_I2C2_BASE 0x400A8000
#define PNX4008_MAGICGATE_BASE 0x400B0000
#define PNX4008_DUMCONF_BASE 0x400B8000
#define PNX4008_DUM_MAINCFG_BASE 0x400BC000
#define PNX4008_DSP_BASE 0x400C0000
#define PNX4008_PROFCOUNTER_BASE 0x400C8000
#define PNX4008_CRYPTO_BASE 0x400D0000
#define PNX4008_CAMIFCONF_BASE 0x400D8000
#define PNX4008_YUV2RGB_BASE 0x400E0000
#define PNX4008_AUDIOCONFIG_BASE 0x400E8000
#endif

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kernel/arch/arm/mach-pnx4008/include/mach/pm.h Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/pm.h
*
* PNX4008 Power Management Routiness - header file
*
* Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_ARCH_PNX4008_PM_H
#define __ASM_ARCH_PNX4008_PM_H
#ifndef __ASSEMBLER__
#include "irq.h"
#include "irqs.h"
#include "clock.h"
extern void pnx4008_pm_idle(void);
extern void pnx4008_pm_suspend(void);
extern unsigned int pnx4008_cpu_suspend_sz;
extern void pnx4008_cpu_suspend(void);
extern unsigned int pnx4008_cpu_standby_sz;
extern void pnx4008_cpu_standby(void);
extern int pnx4008_startup_pll(struct clk *);
extern int pnx4008_shutdown_pll(struct clk *);
#endif /* ASSEMBLER */
#endif /* __ASM_ARCH_PNX4008_PM_H */

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kernel/arch/arm/mach-pnx4008/include/mach/system.h Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/system.h
*
* Copyright (C) 2003 Philips Semiconductors
* Copyright (C) 2005 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/platform.h>
static void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode, const char *cmd)
{
cpu_reset(0);
}
#endif

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kernel/arch/arm/mach-pnx4008/include/mach/timex.h Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/timex.h
*
* PNX4008 timers header file
*
* Author: Dmitry Chigirev <source@mvista.com>
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __PNX4008_TIMEX_H
#define __PNX4008_TIMEX_H
#include <linux/io.h>
#include <mach/hardware.h>
#define CLOCK_TICK_RATE 1000000
#define TICKS2USECS(x) (x)
/* MilliSecond Timer - Chapter 21 Page 202 */
#define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
#define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
#define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
#define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
#define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
/* High Speed Timer - Chpater 22, Page 205 */
#define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
#define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
#define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
#define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
#define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
#define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
#define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
#define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
#define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
#define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
#define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
/* IMPORTANT: both timers are UPCOUNTING */
/* xSTIM_MCTRL bit definitions */
#define MR0_INT 1
#define RESET_COUNT0 (1<<1)
#define STOP_COUNT0 (1<<2)
#define MR1_INT (1<<3)
#define RESET_COUNT1 (1<<4)
#define STOP_COUNT1 (1<<5)
#define MR2_INT (1<<6)
#define RESET_COUNT2 (1<<7)
#define STOP_COUNT2 (1<<8)
/* xSTIM_CTRL bit definitions */
#define COUNT_ENAB 1
#define RESET_COUNT (1<<1)
#define DEBUG_EN (1<<2)
/* xSTIM_INT bit definitions */
#define MATCH0_INT 1
#define MATCH1_INT (1<<1)
#define MATCH2_INT (1<<2)
#define RTC_TICK0 (1<<4)
#define RTC_TICK1 (1<<5)
#endif

46
kernel/arch/arm/mach-pnx4008/include/mach/uncompress.h Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/uncompress.h
*
* Copyright (C) 1999 ARM Limited
* Copyright (C) 2006 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define UART5_BASE 0x40090000
#define UART5_DR (*(volatile unsigned char *) (UART5_BASE))
#define UART5_FR (*(volatile unsigned char *) (UART5_BASE + 18))
static __inline__ void putc(char c)
{
while (UART5_FR & (1 << 5))
barrier();
UART5_DR = c;
}
/*
* This does not append a newline
*/
static inline void flush(void)
{
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()

20
kernel/arch/arm/mach-pnx4008/include/mach/vmalloc.h Normal file
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/*
* arch/arm/mach-pnx4008/include/mach/vmalloc.h
*
* Author: Vitaly Wool <source@mvista.com>
*
* 2006 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)