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add idl4k kernel firmware version 1.13.0.105

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This commit is contained in:
Jaroslav Kysela
2015-03-26 17:22:37 +01:00
parent 5194d2792e
commit e9070cdc77
31064 changed files with 12769984 additions and 0 deletions
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1
kernel/arch/m32r/platforms/m32700ut/Makefile Normal file
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obj-y := setup.o io.o

249
kernel/arch/m32r/platforms/m32700ut/dot.gdbinit_200MHz_16MB Normal file
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# .gdbinit file
# $Id: dot.gdbinit_200MHz_16MB,v 1.2 2004/10/20 03:02:27 fujiwara Exp $
#-----
# NOTE: this file is generated by a script, "gen_gdbinit.pl".
# (Please type "gen_gdbinit.pl --help" and check the help message).
# $ Id: gen_gdbinit.pl,v 1.12 2004/07/26 09:56:10 takata Exp $
#-----
# target platform: m32700ut
# setting
set width 0d70
set radix 0d16
debug_chaos
# clk xin:cpu:bif:bus=25:200:50:50
define clock_init
set *(unsigned long *)0x00ef4008 = 0x00000000
set *(unsigned long *)0x00ef4004 = 0
shell sleep 0.1
# NOTE: Please change the master clock source from PLL-clock to Xin-clock
# and switch off PLL, before resetting the clock gear ratio.
set *(unsigned long *)0x00ef4024 = 2
set *(unsigned long *)0x00ef4020 = 2
set *(unsigned long *)0x00ef4010 = 0
set *(unsigned long *)0x00ef4014 = 0
set *(unsigned long *)0x00ef4004 = 3
shell sleep 0.1
set *(unsigned long *)0x00ef4008 = 0x00000200
end
# Initialize SDRAM controller
define sdram_init
# SDIR0
set *(unsigned long *)0x00ef6008 = 0x00000182
# SDIR1
set *(unsigned long *)0x00ef600c = 0x00000001
# Initialize wait
shell sleep 0.1
# Ch0-MOD
set *(unsigned long *)0x00ef602c = 0x00000020
# Ch0-TR
set *(unsigned long *)0x00ef6028 = 0x00041302
# Ch0-ADR (size:16MB)
set *(unsigned long *)0x00ef6020 = 0x08000002
# AutoRef On
set *(unsigned long *)0x00ef6004 = 0x00010517
# Access enable
set *(unsigned long *)0x00ef6024 = 0x00000001
end
document sdram_init
SDRAM controller initialization
0x08000000 - 0x08ffffff (16MB)
end
# Initialize BSEL3 for UT-CFC
define cfc_init
set $sfrbase = 0xa0ef0000
# too fast
# set *(unsigned long *)($sfrbase + 0x5300) = 0x0b0b8000
# set *(unsigned long *)($sfrbase + 0x5304) = 0x00102204
# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f8000
# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f1fdf
# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013220f
# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013330f
end
document cfc_init
CF controller initialization
end
# MMU enable
define mmu_enable
set $evb=0x88000000
set *(unsigned long *)0xffff0024=1
end
# MMU disable
define mmu_disable
set $evb=0
set *(unsigned long *)0xffff0024=0
end
# Show TLB entries
define show_tlb_entries
set $i = 0
set $addr = $arg0
set $nr_entries = $arg1
use_mon_code
while ($i < $nr_entries)
set $tlb_tag = *(unsigned long*)$addr
set $tlb_data = *(unsigned long*)($addr + 4)
printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
set $i = $i + 1
set $addr = $addr + 8
end
use_debug_dma
end
define itlb
set $itlb=0xfe000000
show_tlb_entries $itlb 0d32
end
define dtlb
set $dtlb=0xfe000800
show_tlb_entries $dtlb 0d32
end
# Initialize TLB entries
define init_tlb_entries
set $i = 0
set $addr = $arg0
set $nr_entries = $arg1
use_mon_code
while ($i < $nr_entries)
set *(unsigned long *)($addr + 0x4) = 0
set $i = $i + 1
set $addr = $addr + 8
end
use_debug_dma
end
define tlb_init
set $itlb=0xfe000000
init_tlb_entries $itlb 0d32
set $dtlb=0xfe000800
init_tlb_entries $dtlb 0d32
end
# Show current task structure
define show_current
set $current = $spi & 0xffffe000
printf "$current=0x%08lX\n",$current
print *(struct task_struct *)$current
end
# Show user assigned task structure
define show_task
set = $arg0 & 0xffffe000
printf "$task=0x%08lX\n",$task
print *(struct task_struct *)$task
end
document show_task
Show user assigned task structure
arg0 : task structure address
end
# Show M32R registers
define show_regs
printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
printf "EVB[0x%08lX]\n",$evb
end
# Setup all
define setup
use_mon_code
set *(unsigned int)0xfffffffc=0x60
shell sleep 0.1
clock_init
shell sleep 0.1
# SDRAM: 16MB
set *(unsigned long *)0x00ef6020 = 0x08000002
cfc_init
# USB
set *(unsigned short *)0xb0301000 = 0x100
set $evb=0x08000000
end
# Load modules
define load_modules
use_debug_dma
load
end
# Set kernel parameters
define set_kernel_parameters
set $param = (void*)0x08001000
# INITRD_START
# set *(unsigned long *)($param + 0x0010) = 0x08300000
# INITRD_SIZE
# set *(unsigned long *)($param + 0x0014) = 0x00000000
# M32R_CPUCLK
set *(unsigned long *)($param + 0x0018) = 0d200000000
# M32R_BUSCLK
set *(unsigned long *)($param + 0x001c) = 0d50000000
# M32R_TIMER_DIVIDE
set *(unsigned long *)($param + 0x0020) = 0d128
set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x console=tty1 root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/rootfs,rsize=1024,wsize=1024 nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 mem=16M \0"
end
# Boot
define boot
set_kernel_parameters
set $fp = 0
set $pc = 0x08002000
# set *(unsigned char *)0xffffffff = 0x03
si
c
end
# Set breakpoints
define set_breakpoints
b *0x08000030
end
# Restart
define restart
sdireset
sdireset
set $pc = 0
b *0x04001000
b *0x08001000
b *0x08002000
si
c
tlb_init
del
setup
load_modules
boot
end
define si
stepi
x/i $pc
show_reg
end
sdireset
sdireset
file vmlinux
target m32rsdi
set $pc = 0
b *0x04001000
b *0x08001000
b *0x08002000
c
tlb_init
del
setup
load_modules
boot

249
kernel/arch/m32r/platforms/m32700ut/dot.gdbinit_300MHz_32MB Normal file
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# .gdbinit file
# $Id: dot.gdbinit_300MHz_32MB,v 1.2 2004/10/20 03:02:27 fujiwara Exp $
#-----
# NOTE: this file is generated by a script, "gen_gdbinit.pl".
# (Please type "gen_gdbinit.pl --help" and check the help message).
# $ Id: gen_gdbinit.pl,v 1.12 2004/07/26 09:56:10 takata Exp $
#-----
# target platform: m32700ut
# setting
set width 0d70
set radix 0d16
debug_chaos
# clk xin:cpu:bif:bus=25:300:75:75
define clock_init
set *(unsigned long *)0x00ef4008 = 0x00000000
set *(unsigned long *)0x00ef4004 = 0
shell sleep 0.1
# NOTE: Please change the master clock source from PLL-clock to Xin-clock
# and switch off PLL, before resetting the clock gear ratio.
set *(unsigned long *)0x00ef4024 = 2
set *(unsigned long *)0x00ef4020 = 2
set *(unsigned long *)0x00ef4010 = 0
set *(unsigned long *)0x00ef4014 = 0
set *(unsigned long *)0x00ef4004 = 5
shell sleep 0.1
set *(unsigned long *)0x00ef4008 = 0x00000200
end
# Initialize SDRAM controller
define sdram_init
# SDIR0
set *(unsigned long *)0x00ef6008 = 0x00000182
# SDIR1
set *(unsigned long *)0x00ef600c = 0x00000001
# Initialize wait
shell sleep 0.1
# Ch0-MOD
set *(unsigned long *)0x00ef602c = 0x00000020
# Ch0-TR
set *(unsigned long *)0x00ef6028 = 0x00051502
# Ch0-ADR (size:32MB)
set *(unsigned long *)0x00ef6020 = 0x08000003
# AutoRef On
set *(unsigned long *)0x00ef6004 = 0x00010e24
# Access enable
set *(unsigned long *)0x00ef6024 = 0x00000001
end
document sdram_init
SDRAM controller initialization
0x08000000 - 0x09ffffff (32MB)
end
# Initialize BSEL3 for UT-CFC
define cfc_init
set $sfrbase = 0xa0ef0000
# too fast
# set *(unsigned long *)($sfrbase + 0x5300) = 0x0b0b8000
# set *(unsigned long *)($sfrbase + 0x5304) = 0x00102204
# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f8000
# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f1fdf
# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013220f
# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013330f
end
document cfc_init
CF controller initialization
end
# MMU enable
define mmu_enable
set $evb=0x88000000
set *(unsigned long *)0xffff0024=1
end
# MMU disable
define mmu_disable
set $evb=0
set *(unsigned long *)0xffff0024=0
end
# Show TLB entries
define show_tlb_entries
set $i = 0
set $addr = $arg0
set $nr_entries = $arg1
use_mon_code
while ($i < $nr_entries)
set $tlb_tag = *(unsigned long*)$addr
set $tlb_data = *(unsigned long*)($addr + 4)
printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
set $i = $i + 1
set $addr = $addr + 8
end
use_debug_dma
end
define itlb
set $itlb=0xfe000000
show_tlb_entries $itlb 0d32
end
define dtlb
set $dtlb=0xfe000800
show_tlb_entries $dtlb 0d32
end
# Initialize TLB entries
define init_tlb_entries
set $i = 0
set $addr = $arg0
set $nr_entries = $arg1
use_mon_code
while ($i < $nr_entries)
set *(unsigned long *)($addr + 0x4) = 0
set $i = $i + 1
set $addr = $addr + 8
end
use_debug_dma
end
define tlb_init
set $itlb=0xfe000000
init_tlb_entries $itlb 0d32
set $dtlb=0xfe000800
init_tlb_entries $dtlb 0d32
end
# Show current task structure
define show_current
set $current = $spi & 0xffffe000
printf "$current=0x%08lX\n",$current
print *(struct task_struct *)$current
end
# Show user assigned task structure
define show_task
set = $arg0 & 0xffffe000
printf "$task=0x%08lX\n",$task
print *(struct task_struct *)$task
end
document show_task
Show user assigned task structure
arg0 : task structure address
end
# Show M32R registers
define show_regs
printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
printf "EVB[0x%08lX]\n",$evb
end
# Setup all
define setup
use_mon_code
set *(unsigned int)0xfffffffc=0x60
shell sleep 0.1
clock_init
shell sleep 0.1
# SDRAM: 32MB
set *(unsigned long *)0x00ef6020 = 0x08000003
cfc_init
# USB
set *(unsigned short *)0xb0301000 = 0x100
set $evb=0x08000000
end
# Load modules
define load_modules
use_debug_dma
load
end
# Set kernel parameters
define set_kernel_parameters
set $param = (void*)0x08001000
# INITRD_START
# set *(unsigned long *)($param + 0x0010) = 0x08300000
# INITRD_SIZE
# set *(unsigned long *)($param + 0x0014) = 0x00000000
# M32R_CPUCLK
set *(unsigned long *)($param + 0x0018) = 0d300000000
# M32R_BUSCLK
set *(unsigned long *)($param + 0x001c) = 0d75000000
# M32R_TIMER_DIVIDE
set *(unsigned long *)($param + 0x0020) = 0d128
set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x console=tty1 root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/rootfs,rsize=1024,wsize=1024 nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 mem=32M \0"
end
# Boot
define boot
set_kernel_parameters
set $fp = 0
set $pc = 0x08002000
# set *(unsigned char *)0xffffffff = 0x03
si
c
end
# Set breakpoints
define set_breakpoints
b *0x08000030
end
# Restart
define restart
sdireset
sdireset
set $pc = 0
b *0x04001000
b *0x08001000
b *0x08002000
si
c
tlb_init
del
setup
load_modules
boot
end
define si
stepi
x/i $pc
show_reg
end
sdireset
sdireset
file vmlinux
target m32rsdi
set $pc = 0
b *0x04001000
b *0x08001000
b *0x08002000
c
tlb_init
del
setup
load_modules
boot

249
kernel/arch/m32r/platforms/m32700ut/dot.gdbinit_400MHz_32MB Normal file
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# .gdbinit file
# $Id: dot.gdbinit_400MHz_32MB,v 1.1 2004/10/21 01:41:27 fujiwara Exp $
#-----
# NOTE: this file is generated by a script, "gen_gdbinit.pl".
# (Please type "gen_gdbinit.pl --help" and check the help message).
# $ Id: gen_gdbinit.pl,v 1.12 2004/07/26 09:56:10 takata Exp $
#-----
# target platform: m32700ut
# setting
set width 0d70
set radix 0d16
debug_chaos
# clk xin:cpu:bif:bus=25:400:100:50
define clock_init
set *(unsigned long *)0x00ef4008 = 0x00000000
set *(unsigned long *)0x00ef4004 = 0
shell sleep 0.1
# NOTE: Please change the master clock source from PLL-clock to Xin-clock
# and switch off PLL, before resetting the clock gear ratio.
set *(unsigned long *)0x00ef4024 = 3
set *(unsigned long *)0x00ef4020 = 2
set *(unsigned long *)0x00ef4010 = 0
set *(unsigned long *)0x00ef4014 = 0
set *(unsigned long *)0x00ef4004 = 7
shell sleep 0.1
set *(unsigned long *)0x00ef4008 = 0x00000200
end
# Initialize SDRAM controller
define sdram_init
# SDIR0
set *(unsigned long *)0x00ef6008 = 0x00000182
# SDIR1
set *(unsigned long *)0x00ef600c = 0x00000001
# Initialize wait
shell sleep 0.1
# Ch0-MOD
set *(unsigned long *)0x00ef602c = 0x00000020
# Ch0-TR
set *(unsigned long *)0x00ef6028 = 0x00041302
# Ch0-ADR (size:32MB)
set *(unsigned long *)0x00ef6020 = 0x08000003
# AutoRef On
set *(unsigned long *)0x00ef6004 = 0x00010517
# Access enable
set *(unsigned long *)0x00ef6024 = 0x00000001
end
document sdram_init
SDRAM controller initialization
0x08000000 - 0x09ffffff (32MB)
end
# Initialize BSEL3 for UT-CFC
define cfc_init
set $sfrbase = 0xa0ef0000
# too fast
# set *(unsigned long *)($sfrbase + 0x5300) = 0x0b0b8000
# set *(unsigned long *)($sfrbase + 0x5304) = 0x00102204
# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f8000
# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f1fdf
# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013220f
# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013330f
end
document cfc_init
CF controller initialization
end
# MMU enable
define mmu_enable
set $evb=0x88000000
set *(unsigned long *)0xffff0024=1
end
# MMU disable
define mmu_disable
set $evb=0
set *(unsigned long *)0xffff0024=0
end
# Show TLB entries
define show_tlb_entries
set $i = 0
set $addr = $arg0
set $nr_entries = $arg1
use_mon_code
while ($i < $nr_entries)
set $tlb_tag = *(unsigned long*)$addr
set $tlb_data = *(unsigned long*)($addr + 4)
printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
set $i = $i + 1
set $addr = $addr + 8
end
use_debug_dma
end
define itlb
set $itlb=0xfe000000
show_tlb_entries $itlb 0d32
end
define dtlb
set $dtlb=0xfe000800
show_tlb_entries $dtlb 0d32
end
# Initialize TLB entries
define init_tlb_entries
set $i = 0
set $addr = $arg0
set $nr_entries = $arg1
use_mon_code
while ($i < $nr_entries)
set *(unsigned long *)($addr + 0x4) = 0
set $i = $i + 1
set $addr = $addr + 8
end
use_debug_dma
end
define tlb_init
set $itlb=0xfe000000
init_tlb_entries $itlb 0d32
set $dtlb=0xfe000800
init_tlb_entries $dtlb 0d32
end
# Show current task structure
define show_current
set $current = $spi & 0xffffe000
printf "$current=0x%08lX\n",$current
print *(struct task_struct *)$current
end
# Show user assigned task structure
define show_task
set = $arg0 & 0xffffe000
printf "$task=0x%08lX\n",$task
print *(struct task_struct *)$task
end
document show_task
Show user assigned task structure
arg0 : task structure address
end
# Show M32R registers
define show_regs
printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
printf "EVB[0x%08lX]\n",$evb
end
# Setup all
define setup
use_mon_code
set *(unsigned int)0xfffffffc=0x60
shell sleep 0.1
clock_init
shell sleep 0.1
# SDRAM: 32MB
set *(unsigned long *)0x00ef6020 = 0x08000003
cfc_init
# USB
set *(unsigned short *)0xb0301000 = 0x100
set $evb=0x08000000
end
# Load modules
define load_modules
use_debug_dma
load
end
# Set kernel parameters
define set_kernel_parameters
set $param = (void*)0x08001000
# INITRD_START
# set *(unsigned long *)($param + 0x0010) = 0x08300000
# INITRD_SIZE
# set *(unsigned long *)($param + 0x0014) = 0x00000000
# M32R_CPUCLK
set *(unsigned long *)($param + 0x0018) = 0d400000000
# M32R_BUSCLK
set *(unsigned long *)($param + 0x001c) = 0d50000000
# M32R_TIMER_DIVIDE
set *(unsigned long *)($param + 0x0020) = 0d128
set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x console=tty1 root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/rootfs,rsize=1024,wsize=1024 nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 mem=32M \0"
end
# Boot
define boot
set_kernel_parameters
set $fp = 0
set $pc = 0x08002000
# set *(unsigned char *)0xffffffff = 0x03
si
c
end
# Set breakpoints
define set_breakpoints
b *0x08000030
end
# Restart
define restart
sdireset
sdireset
set $pc = 0
b *0x04001000
b *0x08001000
b *0x08002000
si
c
tlb_init
del
setup
load_modules
boot
end
define si
stepi
x/i $pc
show_reg
end
sdireset
sdireset
file vmlinux
target m32rsdi
set $pc = 0
b *0x04001000
b *0x08001000
b *0x08002000
c
tlb_init
del
setup
load_modules
boot

395
kernel/arch/m32r/platforms/m32700ut/io.c Normal file
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@@ -0,0 +1,395 @@
/*
* linux/arch/m32r/platforms/m32700ut/io.c
*
* Typical I/O routines for M32700UT board.
*
* Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
* Hitoshi Yamamoto, Takeo Takahashi
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of this
* archive for more details.
*/
#include <asm/m32r.h>
#include <asm/page.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
#include <linux/types.h>
#define M32R_PCC_IOMAP_SIZE 0x1000
#define M32R_PCC_IOSTART0 0x1000
#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
#define PORT2ADDR(port) _port2addr(port)
#define PORT2ADDR_USB(port) _port2addr_usb(port)
static inline void *_port2addr(unsigned long port)
{
return (void *)(port | NONCACHE_OFFSET);
}
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
static inline void *__port2addr_ata(unsigned long port)
{
static int dummy_reg;
switch (port) {
case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
default: return (void *)&dummy_reg;
}
}
#endif
/*
* M32700UT-LAN is located in the extended bus space
* from 0x10000000 to 0x13ffffff on physical address.
* The base address of LAN controller(LAN91C111) is 0x300.
*/
#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
static inline void *_port2addr_ne(unsigned long port)
{
return (void *)(port + 0x10000000);
}
static inline void *_port2addr_usb(unsigned long port)
{
return (void *)((port & 0x0f) + NONCACHE_OFFSET + 0x10303000);
}
static inline void delay(void)
{
__asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
}
/*
* NIC I/O function
*/
#define PORT2ADDR_NE(port) _port2addr_ne(port)
static inline unsigned char _ne_inb(void *portp)
{
return *(volatile unsigned char *)portp;
}
static inline unsigned short _ne_inw(void *portp)
{
return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
}
static inline void _ne_insb(void *portp, void *addr, unsigned long count)
{
unsigned char *buf = (unsigned char *)addr;
while (count--)
*buf++ = _ne_inb(portp);
}
static inline void _ne_outb(unsigned char b, void *portp)
{
*(volatile unsigned char *)portp = b;
}
static inline void _ne_outw(unsigned short w, void *portp)
{
*(volatile unsigned short *)portp = cpu_to_le16(w);
}
unsigned char _inb(unsigned long port)
{
if (port >= LAN_IOSTART && port < LAN_IOEND)
return _ne_inb(PORT2ADDR_NE(port));
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
return *(volatile unsigned char *)__port2addr_ata(port);
}
#endif
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
unsigned char b;
pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
return b;
} else
#endif
return *(volatile unsigned char *)PORT2ADDR(port);
}
unsigned short _inw(unsigned long port)
{
if (port >= LAN_IOSTART && port < LAN_IOEND)
return _ne_inw(PORT2ADDR_NE(port));
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
return *(volatile unsigned short *)__port2addr_ata(port);
}
#endif
#if defined(CONFIG_USB)
else if(port >= 0x340 && port < 0x3a0)
return *(volatile unsigned short *)PORT2ADDR_USB(port);
#endif
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
unsigned short w;
pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
return w;
} else
#endif
return *(volatile unsigned short *)PORT2ADDR(port);
}
unsigned long _inl(unsigned long port)
{
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
unsigned long l;
pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
return l;
} else
#endif
return *(volatile unsigned long *)PORT2ADDR(port);
}
unsigned char _inb_p(unsigned long port)
{
unsigned char v = _inb(port);
delay();
return (v);
}
unsigned short _inw_p(unsigned long port)
{
unsigned short v = _inw(port);
delay();
return (v);
}
unsigned long _inl_p(unsigned long port)
{
unsigned long v = _inl(port);
delay();
return (v);
}
void _outb(unsigned char b, unsigned long port)
{
if (port >= LAN_IOSTART && port < LAN_IOEND)
_ne_outb(b, PORT2ADDR_NE(port));
else
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
*(volatile unsigned char *)__port2addr_ata(port) = b;
} else
#endif
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
} else
#endif
*(volatile unsigned char *)PORT2ADDR(port) = b;
}
void _outw(unsigned short w, unsigned long port)
{
if (port >= LAN_IOSTART && port < LAN_IOEND)
_ne_outw(w, PORT2ADDR_NE(port));
else
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
*(volatile unsigned short *)__port2addr_ata(port) = w;
} else
#endif
#if defined(CONFIG_USB)
if(port >= 0x340 && port < 0x3a0)
*(volatile unsigned short *)PORT2ADDR_USB(port) = w;
else
#endif
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
} else
#endif
*(volatile unsigned short *)PORT2ADDR(port) = w;
}
void _outl(unsigned long l, unsigned long port)
{
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
} else
#endif
*(volatile unsigned long *)PORT2ADDR(port) = l;
}
void _outb_p(unsigned char b, unsigned long port)
{
_outb(b, port);
delay();
}
void _outw_p(unsigned short w, unsigned long port)
{
_outw(w, port);
delay();
}
void _outl_p(unsigned long l, unsigned long port)
{
_outl(l, port);
delay();
}
void _insb(unsigned int port, void *addr, unsigned long count)
{
if (port >= LAN_IOSTART && port < LAN_IOEND)
_ne_insb(PORT2ADDR_NE(port), addr, count);
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
unsigned char *buf = addr;
unsigned char *portp = __port2addr_ata(port);
while (count--)
*buf++ = *(volatile unsigned char *)portp;
}
#endif
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char),
count, 1);
}
#endif
else {
unsigned char *buf = addr;
unsigned char *portp = PORT2ADDR(port);
while (count--)
*buf++ = *(volatile unsigned char *)portp;
}
}
void _insw(unsigned int port, void *addr, unsigned long count)
{
unsigned short *buf = addr;
unsigned short *portp;
if (port >= LAN_IOSTART && port < LAN_IOEND) {
/*
* This portion is only used by smc91111.c to read data
* from the DATA_REG. Do not swap the data.
*/
portp = PORT2ADDR_NE(port);
while (count--)
*buf++ = *(volatile unsigned short *)portp;
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
count, 1);
#endif
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
portp = __port2addr_ata(port);
while (count--)
*buf++ = *(volatile unsigned short *)portp;
#endif
} else {
portp = PORT2ADDR(port);
while (count--)
*buf++ = *(volatile unsigned short *)portp;
}
}
void _insl(unsigned int port, void *addr, unsigned long count)
{
unsigned long *buf = addr;
unsigned long *portp;
portp = PORT2ADDR(port);
while (count--)
*buf++ = *(volatile unsigned long *)portp;
}
void _outsb(unsigned int port, const void *addr, unsigned long count)
{
const unsigned char *buf = addr;
unsigned char *portp;
if (port >= LAN_IOSTART && port < LAN_IOEND) {
portp = PORT2ADDR_NE(port);
while (count--)
_ne_outb(*buf++, portp);
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
portp = __port2addr_ata(port);
while (count--)
*(volatile unsigned char *)portp = *buf++;
#endif
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
count, 1);
#endif
} else {
portp = PORT2ADDR(port);
while (count--)
*(volatile unsigned char *)portp = *buf++;
}
}
void _outsw(unsigned int port, const void *addr, unsigned long count)
{
const unsigned short *buf = addr;
unsigned short *portp;
if (port >= LAN_IOSTART && port < LAN_IOEND) {
/*
* This portion is only used by smc91111.c to write data
* into the DATA_REG. Do not swap the data.
*/
portp = PORT2ADDR_NE(port);
while (count--)
*(volatile unsigned short *)portp = *buf++;
#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
} else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
portp = __port2addr_ata(port);
while (count--)
*(volatile unsigned short *)portp = *buf++;
#endif
#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
} else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
count, 1);
#endif
} else {
portp = PORT2ADDR(port);
while (count--)
*(volatile unsigned short *)portp = *buf++;
}
}
void _outsl(unsigned int port, const void *addr, unsigned long count)
{
const unsigned long *buf = addr;
unsigned char *portp;
portp = PORT2ADDR(port);
while (count--)
*(volatile unsigned long *)portp = *buf++;
}

518
kernel/arch/m32r/platforms/m32700ut/setup.c Normal file
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@@ -0,0 +1,518 @@
/*
* linux/arch/m32r/platforms/m32700ut/setup.c
*
* Setup routines for Renesas M32700UT Board
*
* Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
* Hitoshi Yamamoto, Takeo Takahashi
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file "COPYING" in the main directory of this
* archive for more details.
*/
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/system.h>
#include <asm/m32r.h>
#include <asm/io.h>
/*
* M32700 Interrupt Control Unit (Level 1)
*/
#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
static void disable_m32700ut_irq(unsigned int irq)
{
unsigned long port, data;
port = irq2port(irq);
data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
outl(data, port);
}
static void enable_m32700ut_irq(unsigned int irq)
{
unsigned long port, data;
port = irq2port(irq);
data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
outl(data, port);
}
static void mask_and_ack_m32700ut(unsigned int irq)
{
disable_m32700ut_irq(irq);
}
static void end_m32700ut_irq(unsigned int irq)
{
enable_m32700ut_irq(irq);
}
static unsigned int startup_m32700ut_irq(unsigned int irq)
{
enable_m32700ut_irq(irq);
return (0);
}
static void shutdown_m32700ut_irq(unsigned int irq)
{
unsigned long port;
port = irq2port(irq);
outl(M32R_ICUCR_ILEVEL7, port);
}
static struct irq_chip m32700ut_irq_type =
{
.typename = "M32700UT-IRQ",
.startup = startup_m32700ut_irq,
.shutdown = shutdown_m32700ut_irq,
.enable = enable_m32700ut_irq,
.disable = disable_m32700ut_irq,
.ack = mask_and_ack_m32700ut,
.end = end_m32700ut_irq
};
/*
* Interrupt Control Unit of PLD on M32700UT (Level 2)
*/
#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
(((x) - 1) * sizeof(unsigned short)))
typedef struct {
unsigned short icucr; /* ICU Control Register */
} pld_icu_data_t;
static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
static void disable_m32700ut_pld_irq(unsigned int irq)
{
unsigned long port, data;
unsigned int pldirq;
pldirq = irq2pldirq(irq);
// disable_m32700ut_irq(M32R_IRQ_INT1);
port = pldirq2port(pldirq);
data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
outw(data, port);
}
static void enable_m32700ut_pld_irq(unsigned int irq)
{
unsigned long port, data;
unsigned int pldirq;
pldirq = irq2pldirq(irq);
// enable_m32700ut_irq(M32R_IRQ_INT1);
port = pldirq2port(pldirq);
data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
outw(data, port);
}
static void mask_and_ack_m32700ut_pld(unsigned int irq)
{
disable_m32700ut_pld_irq(irq);
// mask_and_ack_m32700ut(M32R_IRQ_INT1);
}
static void end_m32700ut_pld_irq(unsigned int irq)
{
enable_m32700ut_pld_irq(irq);
end_m32700ut_irq(M32R_IRQ_INT1);
}
static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
{
enable_m32700ut_pld_irq(irq);
return (0);
}
static void shutdown_m32700ut_pld_irq(unsigned int irq)
{
unsigned long port;
unsigned int pldirq;
pldirq = irq2pldirq(irq);
// shutdown_m32700ut_irq(M32R_IRQ_INT1);
port = pldirq2port(pldirq);
outw(PLD_ICUCR_ILEVEL7, port);
}
static struct irq_chip m32700ut_pld_irq_type =
{
.typename = "M32700UT-PLD-IRQ",
.startup = startup_m32700ut_pld_irq,
.shutdown = shutdown_m32700ut_pld_irq,
.enable = enable_m32700ut_pld_irq,
.disable = disable_m32700ut_pld_irq,
.ack = mask_and_ack_m32700ut_pld,
.end = end_m32700ut_pld_irq
};
/*
* Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
*/
#define irq2lanpldirq(x) ((x) - M32700UT_LAN_PLD_IRQ_BASE)
#define lanpldirq2port(x) (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
(((x) - 1) * sizeof(unsigned short)))
static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
static void disable_m32700ut_lanpld_irq(unsigned int irq)
{
unsigned long port, data;
unsigned int pldirq;
pldirq = irq2lanpldirq(irq);
port = lanpldirq2port(pldirq);
data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
outw(data, port);
}
static void enable_m32700ut_lanpld_irq(unsigned int irq)
{
unsigned long port, data;
unsigned int pldirq;
pldirq = irq2lanpldirq(irq);
port = lanpldirq2port(pldirq);
data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
outw(data, port);
}
static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
{
disable_m32700ut_lanpld_irq(irq);
}
static void end_m32700ut_lanpld_irq(unsigned int irq)
{
enable_m32700ut_lanpld_irq(irq);
end_m32700ut_irq(M32R_IRQ_INT0);
}
static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
{
enable_m32700ut_lanpld_irq(irq);
return (0);
}
static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
{
unsigned long port;
unsigned int pldirq;
pldirq = irq2lanpldirq(irq);
port = lanpldirq2port(pldirq);
outw(PLD_ICUCR_ILEVEL7, port);
}
static struct irq_chip m32700ut_lanpld_irq_type =
{
.typename = "M32700UT-PLD-LAN-IRQ",
.startup = startup_m32700ut_lanpld_irq,
.shutdown = shutdown_m32700ut_lanpld_irq,
.enable = enable_m32700ut_lanpld_irq,
.disable = disable_m32700ut_lanpld_irq,
.ack = mask_and_ack_m32700ut_lanpld,
.end = end_m32700ut_lanpld_irq
};
/*
* Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
*/
#define irq2lcdpldirq(x) ((x) - M32700UT_LCD_PLD_IRQ_BASE)
#define lcdpldirq2port(x) (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
(((x) - 1) * sizeof(unsigned short)))
static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
static void disable_m32700ut_lcdpld_irq(unsigned int irq)
{
unsigned long port, data;
unsigned int pldirq;
pldirq = irq2lcdpldirq(irq);
port = lcdpldirq2port(pldirq);
data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
outw(data, port);
}
static void enable_m32700ut_lcdpld_irq(unsigned int irq)
{
unsigned long port, data;
unsigned int pldirq;
pldirq = irq2lcdpldirq(irq);
port = lcdpldirq2port(pldirq);
data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
outw(data, port);
}
static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
{
disable_m32700ut_lcdpld_irq(irq);
}
static void end_m32700ut_lcdpld_irq(unsigned int irq)
{
enable_m32700ut_lcdpld_irq(irq);
end_m32700ut_irq(M32R_IRQ_INT2);
}
static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
{
enable_m32700ut_lcdpld_irq(irq);
return (0);
}
static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
{
unsigned long port;
unsigned int pldirq;
pldirq = irq2lcdpldirq(irq);
port = lcdpldirq2port(pldirq);
outw(PLD_ICUCR_ILEVEL7, port);
}
static struct irq_chip m32700ut_lcdpld_irq_type =
{
.typename = "M32700UT-PLD-LCD-IRQ",
.startup = startup_m32700ut_lcdpld_irq,
.shutdown = shutdown_m32700ut_lcdpld_irq,
.enable = enable_m32700ut_lcdpld_irq,
.disable = disable_m32700ut_lcdpld_irq,
.ack = mask_and_ack_m32700ut_lcdpld,
.end = end_m32700ut_lcdpld_irq
};
void __init init_IRQ(void)
{
#if defined(CONFIG_SMC91X)
/* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type;
irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
#endif /* CONFIG_SMC91X */
/* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
disable_m32700ut_irq(M32R_IRQ_MFT2);
/* SIO0 : receive */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
disable_m32700ut_irq(M32R_IRQ_SIO0_R);
/* SIO0 : send */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
disable_m32700ut_irq(M32R_IRQ_SIO0_S);
/* SIO1 : receive */
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_SIO1_R].action = 0;
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
disable_m32700ut_irq(M32R_IRQ_SIO1_R);
/* SIO1 : send */
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_SIO1_S].action = 0;
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
disable_m32700ut_irq(M32R_IRQ_SIO1_S);
/* DMA1 : */
irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_DMA1].action = 0;
irq_desc[M32R_IRQ_DMA1].depth = 1;
icu_data[M32R_IRQ_DMA1].icucr = 0;
disable_m32700ut_irq(M32R_IRQ_DMA1);
#ifdef CONFIG_SERIAL_M32R_PLDSIO
/* INT#1: SIO0 Receive on PLD */
irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
/* INT#1: SIO0 Send on PLD */
irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_SIO0_SND].action = 0;
irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
#endif /* CONFIG_SERIAL_M32R_PLDSIO */
/* INT#1: CFC IREQ on PLD */
irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_CFIREQ].action = 0;
irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
/* INT#1: CFC Insert on PLD */
irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
/* INT#1: CFC Eject on PLD */
irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type;
irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
/*
* INT0# is used for LAN, DIO
* We enable it here.
*/
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
enable_m32700ut_irq(M32R_IRQ_INT0);
/*
* INT1# is used for UART, MMC, CF Controller in FPGA.
* We enable it here.
*/
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
enable_m32700ut_irq(M32R_IRQ_INT1);
#if defined(CONFIG_USB)
outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type;
irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
#endif
/*
* INT2# is used for BAT, USB, AUDIO
* We enable it here.
*/
icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
enable_m32700ut_irq(M32R_IRQ_INT2);
#if defined(CONFIG_VIDEO_M32R_AR)
/*
* INT3# is used for AR
*/
irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type;
irq_desc[M32R_IRQ_INT3].action = 0;
irq_desc[M32R_IRQ_INT3].depth = 1;
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
disable_m32700ut_irq(M32R_IRQ_INT3);
#endif /* CONFIG_VIDEO_M32R_AR */
}
#if defined(CONFIG_SMC91X)
#define LAN_IOSTART 0x300
#define LAN_IOEND 0x320
static struct resource smc91x_resources[] = {
[0] = {
.start = (LAN_IOSTART),
.end = (LAN_IOEND),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = M32700UT_LAN_IRQ_LAN,
.end = M32700UT_LAN_IRQ_LAN,
.flags = IORESOURCE_IRQ,
}
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
#endif
#if defined(CONFIG_FB_S1D13XXX)
#include <video/s1d13xxxfb.h>
#include <asm/s1d13806.h>
static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
.initregs = s1d13xxxfb_initregs,
.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
.platform_init_video = NULL,
#ifdef CONFIG_PM
.platform_suspend_video = NULL,
.platform_resume_video = NULL,
#endif
};
static struct resource s1d13xxxfb_resources[] = {
[0] = {
.start = 0x10600000UL,
.end = 0x1073FFFFUL,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0x10400000UL,
.end = 0x104001FFUL,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device s1d13xxxfb_device = {
.name = S1D_DEVICENAME,
.id = 0,
.dev = {
.platform_data = &s1d13xxxfb_data,
},
.num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
.resource = s1d13xxxfb_resources,
};
#endif
static int __init platform_init(void)
{
#if defined(CONFIG_SMC91X)
platform_device_register(&smc91x_device);
#endif
#if defined(CONFIG_FB_S1D13XXX)
platform_device_register(&s1d13xxxfb_device);
#endif
return 0;
}
arch_initcall(platform_init);