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add idl4k kernel firmware version 1.13.0.105

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This commit is contained in:
Jaroslav Kysela
2015-03-26 17:22:37 +01:00
parent 5194d2792e
commit e9070cdc77
31064 changed files with 12769984 additions and 0 deletions
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1791
kernel/arch/mips/include/asm/mach-au1x00/au1000.h Normal file
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kernel/arch/mips/include/asm/mach-au1x00/au1000_dma.h Normal file
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/*
* BRIEF MODULE DESCRIPTION
* Defines for using and allocating DMA channels on the Alchemy
* Au1x00 MIPS processors.
*
* Copyright 2000, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __ASM_AU1000_DMA_H
#define __ASM_AU1000_DMA_H
#include <linux/io.h> /* need byte IO */
#include <linux/spinlock.h> /* And spinlocks */
#include <linux/delay.h>
#include <asm/system.h>
#define NUM_AU1000_DMA_CHANNELS 8
/* DMA Channel Base Addresses */
#define DMA_CHANNEL_BASE 0xB4002000
#define DMA_CHANNEL_LEN 0x00000100
/* DMA Channel Register Offsets */
#define DMA_MODE_SET 0x00000000
#define DMA_MODE_READ DMA_MODE_SET
#define DMA_MODE_CLEAR 0x00000004
/* DMA Mode register bits follow */
#define DMA_DAH_MASK (0x0f << 20)
#define DMA_DID_BIT 16
#define DMA_DID_MASK (0x0f << DMA_DID_BIT)
#define DMA_DS (1 << 15)
#define DMA_BE (1 << 13)
#define DMA_DR (1 << 12)
#define DMA_TS8 (1 << 11)
#define DMA_DW_BIT 9
#define DMA_DW_MASK (0x03 << DMA_DW_BIT)
#define DMA_DW8 (0 << DMA_DW_BIT)
#define DMA_DW16 (1 << DMA_DW_BIT)
#define DMA_DW32 (2 << DMA_DW_BIT)
#define DMA_NC (1 << 8)
#define DMA_IE (1 << 7)
#define DMA_HALT (1 << 6)
#define DMA_GO (1 << 5)
#define DMA_AB (1 << 4)
#define DMA_D1 (1 << 3)
#define DMA_BE1 (1 << 2)
#define DMA_D0 (1 << 1)
#define DMA_BE0 (1 << 0)
#define DMA_PERIPHERAL_ADDR 0x00000008
#define DMA_BUFFER0_START 0x0000000C
#define DMA_BUFFER1_START 0x00000014
#define DMA_BUFFER0_COUNT 0x00000010
#define DMA_BUFFER1_COUNT 0x00000018
#define DMA_BAH_BIT 16
#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
#define DMA_COUNT_BIT 0
#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
/* DMA Device IDs follow */
enum {
DMA_ID_UART0_TX = 0,
DMA_ID_UART0_RX,
DMA_ID_GP04,
DMA_ID_GP05,
DMA_ID_AC97C_TX,
DMA_ID_AC97C_RX,
DMA_ID_UART3_TX,
DMA_ID_UART3_RX,
DMA_ID_USBDEV_EP0_RX,
DMA_ID_USBDEV_EP0_TX,
DMA_ID_USBDEV_EP2_TX,
DMA_ID_USBDEV_EP3_TX,
DMA_ID_USBDEV_EP4_RX,
DMA_ID_USBDEV_EP5_RX,
DMA_ID_I2S_TX,
DMA_ID_I2S_RX,
DMA_NUM_DEV
};
/* DMA Device ID's for 2nd bank (AU1100) follow */
enum {
DMA_ID_SD0_TX = 0,
DMA_ID_SD0_RX,
DMA_ID_SD1_TX,
DMA_ID_SD1_RX,
DMA_NUM_DEV_BANK2
};
struct dma_chan {
int dev_id; /* this channel is allocated if >= 0, */
/* free otherwise */
unsigned int io;
const char *dev_str;
int irq;
void *irq_dev;
unsigned int fifo_addr;
unsigned int mode;
};
/* These are in arch/mips/au1000/common/dma.c */
extern struct dma_chan au1000_dma_table[];
extern int request_au1000_dma(int dev_id,
const char *dev_str,
irq_handler_t irqhandler,
unsigned long irqflags,
void *irq_dev_id);
extern void free_au1000_dma(unsigned int dmanr);
extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
int length, int *eof, void *data);
extern void dump_au1000_dma_channel(unsigned int dmanr);
extern spinlock_t au1000_dma_spin_lock;
static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
{
if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
au1000_dma_table[dmanr].dev_id < 0)
return NULL;
return &au1000_dma_table[dmanr];
}
static inline unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&au1000_dma_spin_lock, flags);
return flags;
}
static inline void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
}
/*
* Set the DMA buffer enable bits in the mode register.
*/
static inline void enable_dma_buffer0(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
}
static inline void enable_dma_buffer1(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
}
static inline void enable_dma_buffers(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
}
static inline void start_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_GO, chan->io + DMA_MODE_SET);
}
#define DMA_HALT_POLL 0x5000
static inline void halt_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
int i;
if (!chan)
return;
au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
/* Poll the halt bit */
for (i = 0; i < DMA_HALT_POLL; i++)
if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
break;
if (i == DMA_HALT_POLL)
printk(KERN_INFO "halt_dma: HALT poll expired!\n");
}
static inline void disable_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
halt_dma(dmanr);
/* Now we can disable the buffers */
au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
}
static inline int dma_halted(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 1;
return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
}
/* Initialize a DMA channel. */
static inline void init_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
u32 mode;
if (!chan)
return;
disable_dma(dmanr);
/* Set device FIFO address */
au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
if (chan->irq)
mode |= DMA_IE;
au_writel(~mode, chan->io + DMA_MODE_CLEAR);
au_writel(mode, chan->io + DMA_MODE_SET);
}
/*
* Set mode for a specific DMA channel
*/
static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
/*
* set_dma_mode is only allowed to change endianess, direction,
* transfer size, device FIFO width, and coherency settings.
* Make sure anything else is masked off.
*/
mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
chan->mode |= mode;
}
static inline unsigned int get_dma_mode(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 0;
return chan->mode;
}
static inline int get_dma_active_buffer(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return -1;
return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
}
/*
* Set the device FIFO address for a specific DMA channel - only
* applicable to GPO4 and GPO5. All the other devices have fixed
* FIFO addresses.
*/
static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
if (chan->mode & DMA_DS) /* second bank of device IDs */
return;
if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
return;
au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
}
/*
* Clear the DMA buffer done bits in the mode register.
*/
static inline void clear_dma_done0(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
}
static inline void clear_dma_done1(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
}
/*
* This does nothing - not applicable to Au1000 DMA.
*/
static inline void set_dma_page(unsigned int dmanr, char pagenr)
{
}
/*
* Set Buffer 0 transfer address for specific DMA channel.
*/
static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(a, chan->io + DMA_BUFFER0_START);
}
/*
* Set Buffer 1 transfer address for specific DMA channel.
*/
static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
au_writel(a, chan->io + DMA_BUFFER1_START);
}
/*
* Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
*/
static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
count &= DMA_COUNT_MASK;
au_writel(count, chan->io + DMA_BUFFER0_COUNT);
}
/*
* Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
*/
static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
count &= DMA_COUNT_MASK;
au_writel(count, chan->io + DMA_BUFFER1_COUNT);
}
/*
* Set both buffer transfer sizes (max 64k) for a specific DMA channel.
*/
static inline void set_dma_count(unsigned int dmanr, unsigned int count)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
count &= DMA_COUNT_MASK;
au_writel(count, chan->io + DMA_BUFFER0_COUNT);
au_writel(count, chan->io + DMA_BUFFER1_COUNT);
}
/*
* Returns which buffer has its done bit set in the mode register.
* Returns -1 if neither or both done bits set.
*/
static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 0;
return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
}
/*
* Returns the DMA channel's Buffer Done IRQ number.
*/
static inline int get_dma_done_irq(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return -1;
return chan->irq;
}
/*
* Get DMA residue count. Returns the number of _bytes_ left to transfer.
*/
static inline int get_dma_residue(unsigned int dmanr)
{
int curBufCntReg, count;
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return 0;
curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
count <<= 1;
else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
count <<= 2;
return count;
}
#endif /* __ASM_AU1000_DMA_H */

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kernel/arch/mips/include/asm/mach-au1x00/au1100_mmc.h Normal file
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/*
* BRIEF MODULE DESCRIPTION
* Defines for using the MMC/SD controllers on the
* Alchemy Au1100 mips processor.
*
* Copyright (c) 2003 Embedded Edge, LLC.
* Author: Embedded Edge, LLC.
* dan@embeddededge.com or tim@embeddededge.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
/*
* AU1100 MMC/SD definitions.
*
* From "AMD Alchemy Solutions Au1100 Processor Data Book - Preliminary"
* June, 2003
*/
#ifndef __ASM_AU1100_MMC_H
#define __ASM_AU1100_MMC_H
#include <linux/leds.h>
struct au1xmmc_platform_data {
int(*cd_setup)(void *mmc_host, int on);
int(*card_inserted)(void *mmc_host);
int(*card_readonly)(void *mmc_host);
void(*set_power)(void *mmc_host, int state);
struct led_classdev *led;
};
#define SD0_BASE 0xB0600000
#define SD1_BASE 0xB0680000
/*
* Register offsets.
*/
#define SD_TXPORT (0x0000)
#define SD_RXPORT (0x0004)
#define SD_CONFIG (0x0008)
#define SD_ENABLE (0x000C)
#define SD_CONFIG2 (0x0010)
#define SD_BLKSIZE (0x0014)
#define SD_STATUS (0x0018)
#define SD_DEBUG (0x001C)
#define SD_CMD (0x0020)
#define SD_CMDARG (0x0024)
#define SD_RESP3 (0x0028)
#define SD_RESP2 (0x002C)
#define SD_RESP1 (0x0030)
#define SD_RESP0 (0x0034)
#define SD_TIMEOUT (0x0038)
/*
* SD_TXPORT bit definitions.
*/
#define SD_TXPORT_TXD (0x000000ff)
/*
* SD_RXPORT bit definitions.
*/
#define SD_RXPORT_RXD (0x000000ff)
/*
* SD_CONFIG bit definitions.
*/
#define SD_CONFIG_DIV (0x000001ff)
#define SD_CONFIG_DE (0x00000200)
#define SD_CONFIG_NE (0x00000400)
#define SD_CONFIG_TU (0x00000800)
#define SD_CONFIG_TO (0x00001000)
#define SD_CONFIG_RU (0x00002000)
#define SD_CONFIG_RO (0x00004000)
#define SD_CONFIG_I (0x00008000)
#define SD_CONFIG_CR (0x00010000)
#define SD_CONFIG_RAT (0x00020000)
#define SD_CONFIG_DD (0x00040000)
#define SD_CONFIG_DT (0x00080000)
#define SD_CONFIG_SC (0x00100000)
#define SD_CONFIG_RC (0x00200000)
#define SD_CONFIG_WC (0x00400000)
#define SD_CONFIG_xxx (0x00800000)
#define SD_CONFIG_TH (0x01000000)
#define SD_CONFIG_TE (0x02000000)
#define SD_CONFIG_TA (0x04000000)
#define SD_CONFIG_RH (0x08000000)
#define SD_CONFIG_RA (0x10000000)
#define SD_CONFIG_RF (0x20000000)
#define SD_CONFIG_CD (0x40000000)
#define SD_CONFIG_SI (0x80000000)
/*
* SD_ENABLE bit definitions.
*/
#define SD_ENABLE_CE (0x00000001)
#define SD_ENABLE_R (0x00000002)
/*
* SD_CONFIG2 bit definitions.
*/
#define SD_CONFIG2_EN (0x00000001)
#define SD_CONFIG2_FF (0x00000002)
#define SD_CONFIG2_xx1 (0x00000004)
#define SD_CONFIG2_DF (0x00000008)
#define SD_CONFIG2_DC (0x00000010)
#define SD_CONFIG2_xx2 (0x000000e0)
#define SD_CONFIG2_WB (0x00000100)
#define SD_CONFIG2_RW (0x00000200)
/*
* SD_BLKSIZE bit definitions.
*/
#define SD_BLKSIZE_BS (0x000007ff)
#define SD_BLKSIZE_BS_SHIFT (0)
#define SD_BLKSIZE_BC (0x01ff0000)
#define SD_BLKSIZE_BC_SHIFT (16)
/*
* SD_STATUS bit definitions.
*/
#define SD_STATUS_DCRCW (0x00000007)
#define SD_STATUS_xx1 (0x00000008)
#define SD_STATUS_CB (0x00000010)
#define SD_STATUS_DB (0x00000020)
#define SD_STATUS_CF (0x00000040)
#define SD_STATUS_D3 (0x00000080)
#define SD_STATUS_xx2 (0x00000300)
#define SD_STATUS_NE (0x00000400)
#define SD_STATUS_TU (0x00000800)
#define SD_STATUS_TO (0x00001000)
#define SD_STATUS_RU (0x00002000)
#define SD_STATUS_RO (0x00004000)
#define SD_STATUS_I (0x00008000)
#define SD_STATUS_CR (0x00010000)
#define SD_STATUS_RAT (0x00020000)
#define SD_STATUS_DD (0x00040000)
#define SD_STATUS_DT (0x00080000)
#define SD_STATUS_SC (0x00100000)
#define SD_STATUS_RC (0x00200000)
#define SD_STATUS_WC (0x00400000)
#define SD_STATUS_xx3 (0x00800000)
#define SD_STATUS_TH (0x01000000)
#define SD_STATUS_TE (0x02000000)
#define SD_STATUS_TA (0x04000000)
#define SD_STATUS_RH (0x08000000)
#define SD_STATUS_RA (0x10000000)
#define SD_STATUS_RF (0x20000000)
#define SD_STATUS_CD (0x40000000)
#define SD_STATUS_SI (0x80000000)
/*
* SD_CMD bit definitions.
*/
#define SD_CMD_GO (0x00000001)
#define SD_CMD_RY (0x00000002)
#define SD_CMD_xx1 (0x0000000c)
#define SD_CMD_CT_MASK (0x000000f0)
#define SD_CMD_CT_0 (0x00000000)
#define SD_CMD_CT_1 (0x00000010)
#define SD_CMD_CT_2 (0x00000020)
#define SD_CMD_CT_3 (0x00000030)
#define SD_CMD_CT_4 (0x00000040)
#define SD_CMD_CT_5 (0x00000050)
#define SD_CMD_CT_6 (0x00000060)
#define SD_CMD_CT_7 (0x00000070)
#define SD_CMD_CI (0x0000ff00)
#define SD_CMD_CI_SHIFT (8)
#define SD_CMD_RT_MASK (0x00ff0000)
#define SD_CMD_RT_0 (0x00000000)
#define SD_CMD_RT_1 (0x00010000)
#define SD_CMD_RT_2 (0x00020000)
#define SD_CMD_RT_3 (0x00030000)
#define SD_CMD_RT_4 (0x00040000)
#define SD_CMD_RT_5 (0x00050000)
#define SD_CMD_RT_6 (0x00060000)
#define SD_CMD_RT_1B (0x00810000)
#endif /* __ASM_AU1100_MMC_H */

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kernel/arch/mips/include/asm/mach-au1x00/au1550_spi.h Normal file
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/*
* au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure
*/
#ifndef _AU1550_SPI_H_
#define _AU1550_SPI_H_
struct au1550_spi_info {
u32 mainclk_hz; /* main input clock frequency of PSC */
u16 num_chipselect; /* number of chipselects supported */
void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
void (*deactivate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
};
#endif

43
kernel/arch/mips/include/asm/mach-au1x00/au1xxx.h Normal file
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/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _AU1XXX_H_
#define _AU1XXX_H_
#include <asm/mach-au1x00/au1000.h>
#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
#include <asm/mach-db1x00/db1x00.h>
#elif defined(CONFIG_MIPS_PB1550)
#include <asm/mach-pb1x00/pb1550.h>
#elif defined(CONFIG_MIPS_PB1200)
#include <asm/mach-pb1x00/pb1200.h>
#elif defined(CONFIG_MIPS_DB1200)
#include <asm/mach-db1x00/db1200.h>
#endif
#endif /* _AU1XXX_H_ */

391
kernel/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h Normal file
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/*
*
* BRIEF MODULE DESCRIPTION
* Include file for Alchemy Semiconductor's Au1550 Descriptor
* Based DMA Controller.
*
* Copyright 2004 Embedded Edge, LLC
* dan@embeddededge.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* Specifics for the Au1xxx Descriptor-Based DMA Controller,
* first seen in the AU1550 part.
*/
#ifndef _AU1000_DBDMA_H_
#define _AU1000_DBDMA_H_
#ifndef _LANGUAGE_ASSEMBLY
/*
* The DMA base addresses.
* The channels are every 256 bytes (0x0100) from the channel 0 base.
* Interrupt status/enable is bits 15:0 for channels 15 to zero.
*/
#define DDMA_GLOBAL_BASE 0xb4003000
#define DDMA_CHANNEL_BASE 0xb4002000
typedef volatile struct dbdma_global {
u32 ddma_config;
u32 ddma_intstat;
u32 ddma_throttle;
u32 ddma_inten;
} dbdma_global_t;
/* General Configuration. */
#define DDMA_CONFIG_AF (1 << 2)
#define DDMA_CONFIG_AH (1 << 1)
#define DDMA_CONFIG_AL (1 << 0)
#define DDMA_THROTTLE_EN (1 << 31)
/* The structure of a DMA Channel. */
typedef volatile struct au1xxx_dma_channel {
u32 ddma_cfg; /* See below */
u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
u32 ddma_statptr; /* word aligned pointer to status word */
u32 ddma_dbell; /* A write activates channel operation */
u32 ddma_irq; /* If bit 0 set, interrupt pending */
u32 ddma_stat; /* See below */
u32 ddma_bytecnt; /* Byte count, valid only when chan idle */
/* Remainder, up to the 256 byte boundary, is reserved. */
} au1x_dma_chan_t;
#define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */
#define DDMA_CFG_SP (1 << 8) /* source DMA polarity */
#define DDMA_CFG_DED (1 << 7) /* destination DMA level/edge detect */
#define DDMA_CFG_DP (1 << 6) /* destination DMA polarity */
#define DDMA_CFG_SYNC (1 << 5) /* Sync static bus controller */
#define DDMA_CFG_PPR (1 << 4) /* PCI posted read/write control */
#define DDMA_CFG_DFN (1 << 3) /* Descriptor fetch non-coherent */
#define DDMA_CFG_SBE (1 << 2) /* Source big endian */
#define DDMA_CFG_DBE (1 << 1) /* Destination big endian */
#define DDMA_CFG_EN (1 << 0) /* Channel enable */
/*
* Always set when descriptor processing done, regardless of
* interrupt enable state. Reflected in global intstat, don't
* clear this until global intstat is read/used.
*/
#define DDMA_IRQ_IN (1 << 0)
#define DDMA_STAT_DB (1 << 2) /* Doorbell pushed */
#define DDMA_STAT_V (1 << 1) /* Descriptor valid */
#define DDMA_STAT_H (1 << 0) /* Channel Halted */
/*
* "Standard" DDMA Descriptor.
* Must be 32-byte aligned.
*/
typedef volatile struct au1xxx_ddma_desc {
u32 dscr_cmd0; /* See below */
u32 dscr_cmd1; /* See below */
u32 dscr_source0; /* source phys address */
u32 dscr_source1; /* See below */
u32 dscr_dest0; /* Destination address */
u32 dscr_dest1; /* See below */
u32 dscr_stat; /* completion status */
u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
/*
* First 32 bytes are HW specific!!!
* Lets have some SW data following -- make sure it's 32 bytes.
*/
u32 sw_status;
u32 sw_context;
u32 sw_reserved[6];
} au1x_ddma_desc_t;
#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */
#define DSCR_CMD0_MEM (1 << 30) /* mem-mem transfer */
#define DSCR_CMD0_SID_MASK (0x1f << 25) /* Source ID */
#define DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */
#define DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */
#define DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */
#define DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */
#define DSCR_CMD0_DT_MASK (0x3 << 13) /* Descriptor Type */
#define DSCR_CMD0_SN (0x1 << 12) /* Source non-coherent */
#define DSCR_CMD0_DN (0x1 << 11) /* Destination non-coherent */
#define DSCR_CMD0_SM (0x1 << 10) /* Stride mode */
#define DSCR_CMD0_IE (0x1 << 8) /* Interrupt Enable */
#define DSCR_CMD0_SP (0x1 << 4) /* Status pointer select */
#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
#define SW_STATUS_INUSE (1 << 0)
/* Command 0 device IDs. */
#ifdef CONFIG_SOC_AU1550
#define DSCR_CMD0_UART0_TX 0
#define DSCR_CMD0_UART0_RX 1
#define DSCR_CMD0_UART3_TX 2
#define DSCR_CMD0_UART3_RX 3
#define DSCR_CMD0_DMA_REQ0 4
#define DSCR_CMD0_DMA_REQ1 5
#define DSCR_CMD0_DMA_REQ2 6
#define DSCR_CMD0_DMA_REQ3 7
#define DSCR_CMD0_USBDEV_RX0 8
#define DSCR_CMD0_USBDEV_TX0 9
#define DSCR_CMD0_USBDEV_TX1 10
#define DSCR_CMD0_USBDEV_TX2 11
#define DSCR_CMD0_USBDEV_RX3 12
#define DSCR_CMD0_USBDEV_RX4 13
#define DSCR_CMD0_PSC0_TX 14
#define DSCR_CMD0_PSC0_RX 15
#define DSCR_CMD0_PSC1_TX 16
#define DSCR_CMD0_PSC1_RX 17
#define DSCR_CMD0_PSC2_TX 18
#define DSCR_CMD0_PSC2_RX 19
#define DSCR_CMD0_PSC3_TX 20
#define DSCR_CMD0_PSC3_RX 21
#define DSCR_CMD0_PCI_WRITE 22
#define DSCR_CMD0_NAND_FLASH 23
#define DSCR_CMD0_MAC0_RX 24
#define DSCR_CMD0_MAC0_TX 25
#define DSCR_CMD0_MAC1_RX 26
#define DSCR_CMD0_MAC1_TX 27
#endif /* CONFIG_SOC_AU1550 */
#ifdef CONFIG_SOC_AU1200
#define DSCR_CMD0_UART0_TX 0
#define DSCR_CMD0_UART0_RX 1
#define DSCR_CMD0_UART1_TX 2
#define DSCR_CMD0_UART1_RX 3
#define DSCR_CMD0_DMA_REQ0 4
#define DSCR_CMD0_DMA_REQ1 5
#define DSCR_CMD0_MAE_BE 6
#define DSCR_CMD0_MAE_FE 7
#define DSCR_CMD0_SDMS_TX0 8
#define DSCR_CMD0_SDMS_RX0 9
#define DSCR_CMD0_SDMS_TX1 10
#define DSCR_CMD0_SDMS_RX1 11
#define DSCR_CMD0_AES_TX 13
#define DSCR_CMD0_AES_RX 12
#define DSCR_CMD0_PSC0_TX 14
#define DSCR_CMD0_PSC0_RX 15
#define DSCR_CMD0_PSC1_TX 16
#define DSCR_CMD0_PSC1_RX 17
#define DSCR_CMD0_CIM_RXA 18
#define DSCR_CMD0_CIM_RXB 19
#define DSCR_CMD0_CIM_RXC 20
#define DSCR_CMD0_MAE_BOTH 21
#define DSCR_CMD0_LCD 22
#define DSCR_CMD0_NAND_FLASH 23
#define DSCR_CMD0_PSC0_SYNC 24
#define DSCR_CMD0_PSC1_SYNC 25
#define DSCR_CMD0_CIM_SYNC 26
#endif /* CONFIG_SOC_AU1200 */
#define DSCR_CMD0_THROTTLE 30
#define DSCR_CMD0_ALWAYS 31
#define DSCR_NDEV_IDS 32
/* This macro is used to find/create custom device types */
#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
((d) & 0xFF))
#define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF)
#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
/* Source/Destination transfer width. */
#define DSCR_CMD0_BYTE 0
#define DSCR_CMD0_HALFWORD 1
#define DSCR_CMD0_WORD 2
#define DSCR_CMD0_SW(x) (((x) & 0x3) << 18)
#define DSCR_CMD0_DW(x) (((x) & 0x3) << 16)
/* DDMA Descriptor Type. */
#define DSCR_CMD0_STANDARD 0
#define DSCR_CMD0_LITERAL 1
#define DSCR_CMD0_CMP_BRANCH 2
#define DSCR_CMD0_DT(x) (((x) & 0x3) << 13)
/* Status Instruction. */
#define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */
#define DSCR_CMD0_ST_CURRENT 1 /* Write current status */
#define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */
#define DSCR_CMD0_ST_BYTECNT 3 /* Write remaining byte count */
#define DSCR_CMD0_ST(x) (((x) & 0x3) << 0)
/* Descriptor Command 1. */
#define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */
#define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */
#define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */
#define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */
/* Flag description. */
#define DSCR_CMD1_FL_MEM_STRIDE0 0
#define DSCR_CMD1_FL_MEM_STRIDE1 1
#define DSCR_CMD1_FL_MEM_STRIDE2 2
#define DSCR_CMD1_FL(x) (((x) & 0x3) << 22)
/* Source1, 1-dimensional stride. */
#define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */
#define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */
#define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */
#define DSCR_SRC1_SB(x) (((x) & 0x3fff) << 14)
#define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */
#define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)
/* Dest1, 1-dimensional stride. */
#define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */
#define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */
#define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */
#define DSCR_DEST1_DB(x) (((x) & 0x3fff) << 14)
#define DSCR_DEST1_DS_MASK (0x3fff << 0) /* Stride */
#define DSCR_DEST1_DS(x) (((x) & 0x3fff) << 0)
#define DSCR_xTS_SIZE1 0
#define DSCR_xTS_SIZE2 1
#define DSCR_xTS_SIZE4 2
#define DSCR_xTS_SIZE8 3
#define DSCR_SRC1_STS(x) (((x) & 3) << 30)
#define DSCR_DEST1_DTS(x) (((x) & 3) << 30)
#define DSCR_xAM_INCREMENT 0
#define DSCR_xAM_DECREMENT 1
#define DSCR_xAM_STATIC 2
#define DSCR_xAM_BURST 3
#define DSCR_SRC1_SAM(x) (((x) & 3) << 28)
#define DSCR_DEST1_DAM(x) (((x) & 3) << 28)
/* The next descriptor pointer. */
#define DSCR_NXTPTR_MASK (0x07ffffff)
#define DSCR_NXTPTR(x) ((x) >> 5)
#define DSCR_GET_NXTPTR(x) ((x) << 5)
#define DSCR_NXTPTR_MS (1 << 27)
/* The number of DBDMA channels. */
#define NUM_DBDMA_CHANS 16
/*
* DDMA API definitions
* FIXME: may not fit to this header file
*/
typedef struct dbdma_device_table {
u32 dev_id;
u32 dev_flags;
u32 dev_tsize;
u32 dev_devwidth;
u32 dev_physaddr; /* If FIFO */
u32 dev_intlevel;
u32 dev_intpolarity;
} dbdev_tab_t;
typedef struct dbdma_chan_config {
spinlock_t lock;
u32 chan_flags;
u32 chan_index;
dbdev_tab_t *chan_src;
dbdev_tab_t *chan_dest;
au1x_dma_chan_t *chan_ptr;
au1x_ddma_desc_t *chan_desc_base;
au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
void *chan_callparam;
void (*chan_callback)(int, void *);
} chan_tab_t;
#define DEV_FLAGS_INUSE (1 << 0)
#define DEV_FLAGS_ANYUSE (1 << 1)
#define DEV_FLAGS_OUT (1 << 2)
#define DEV_FLAGS_IN (1 << 3)
#define DEV_FLAGS_BURSTABLE (1 << 4)
#define DEV_FLAGS_SYNC (1 << 5)
/* end DDMA API definitions */
/*
* External functions for drivers to use.
* Use this to allocate a DBDMA channel. The device IDs are one of
* the DSCR_CMD0 devices IDs, which is usually redefined to a more
* meaningful name. The 'callback' is called during DMA completion
* interrupt.
*/
extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
void (*callback)(int, void *),
void *callparam);
#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
/* Set the device width of an in/out FIFO. */
u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
/* Allocate a ring of descriptors for DBDMA. */
u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
/* Put buffers on source/destination descriptors. */
u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
/* Get a buffer from the destination descriptor. */
u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
void au1xxx_dbdma_stop(u32 chanid);
void au1xxx_dbdma_start(u32 chanid);
void au1xxx_dbdma_reset(u32 chanid);
u32 au1xxx_get_dma_residue(u32 chanid);
void au1xxx_dbdma_chan_free(u32 chanid);
void au1xxx_dbdma_dump(u32 chanid);
u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
extern void au1xxx_ddma_del_device(u32 devid);
void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
#ifdef CONFIG_PM
void au1xxx_dbdma_suspend(void);
void au1xxx_dbdma_resume(void);
#endif
/*
* Some compatibilty macros -- needed to make changes to API
* without breaking existing drivers.
*/
#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \
_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \
_au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
#define put_source_flags(chanid, buf, nbytes, flags) \
au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \
_au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \
_au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
#define put_dest_flags(chanid, buf, nbytes, flags) \
au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
/*
* Flags for the put_source/put_dest functions.
*/
#define DDMA_FLAGS_IE (1 << 0)
#define DDMA_FLAGS_NOIE (1 << 1)
#endif /* _LANGUAGE_ASSEMBLY */
#endif /* _AU1000_DBDMA_H_ */

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/*
* include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005
*
* BRIEF MODULE DESCRIPTION
* AMD Alchemy Au1xxx IDE interface routines over the Static Bus
*
* Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option) any later
* version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
* Interface and Linux Device Driver" Application Note.
*/
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
#define DMA_WAIT_TIMEOUT 100
#define NUM_DESCRIPTORS PRD_ENTRIES
#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
#define NUM_DESCRIPTORS 2
#endif
#ifndef AU1XXX_ATA_RQSIZE
#define AU1XXX_ATA_RQSIZE 128
#endif
/* Disable Burstable-Support for DBDMA */
#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
#endif
typedef struct {
u32 tx_dev_id, rx_dev_id, target_dev_id;
u32 tx_chan, rx_chan;
void *tx_desc_head, *rx_desc_head;
ide_hwif_t *hwif;
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
ide_drive_t *drive;
struct dbdma_cmd *dma_table_cpu;
dma_addr_t dma_table_dma;
#endif
int irq;
u32 regbase;
} _auide_hwif;
/******************************************************************************/
/* PIO Mode timing calculation : */
/* */
/* Static Bus Spec ATA Spec */
/* Tcsoe = t1 */
/* Toecs = t9 */
/* Twcs = t9 */
/* Tcsh = t2i | t2 */
/* Tcsoff = t2i | t2 */
/* Twp = t2 */
/* Tcsw = t1 */
/* Tpm = 0 */
/* Ta = t1+t2 */
/******************************************************************************/
#define TCSOE_MASK (0x07 << 29)
#define TOECS_MASK (0x07 << 26)
#define TWCS_MASK (0x07 << 28)
#define TCSH_MASK (0x0F << 24)
#define TCSOFF_MASK (0x07 << 20)
#define TWP_MASK (0x3F << 14)
#define TCSW_MASK (0x0F << 10)
#define TPM_MASK (0x0F << 6)
#define TA_MASK (0x3F << 0)
#define TS_MASK (1 << 8)
/* Timing parameters PIO mode 0 */
#define SBC_IDE_PIO0_TCSOE (0x04 << 29)
#define SBC_IDE_PIO0_TOECS (0x01 << 26)
#define SBC_IDE_PIO0_TWCS (0x02 << 28)
#define SBC_IDE_PIO0_TCSH (0x08 << 24)
#define SBC_IDE_PIO0_TCSOFF (0x07 << 20)
#define SBC_IDE_PIO0_TWP (0x10 << 14)
#define SBC_IDE_PIO0_TCSW (0x04 << 10)
#define SBC_IDE_PIO0_TPM (0x00 << 6)
#define SBC_IDE_PIO0_TA (0x15 << 0)
/* Timing parameters PIO mode 1 */
#define SBC_IDE_PIO1_TCSOE (0x03 << 29)
#define SBC_IDE_PIO1_TOECS (0x01 << 26)
#define SBC_IDE_PIO1_TWCS (0x01 << 28)
#define SBC_IDE_PIO1_TCSH (0x06 << 24)
#define SBC_IDE_PIO1_TCSOFF (0x06 << 20)
#define SBC_IDE_PIO1_TWP (0x08 << 14)
#define SBC_IDE_PIO1_TCSW (0x03 << 10)
#define SBC_IDE_PIO1_TPM (0x00 << 6)
#define SBC_IDE_PIO1_TA (0x0B << 0)
/* Timing parameters PIO mode 2 */
#define SBC_IDE_PIO2_TCSOE (0x05 << 29)
#define SBC_IDE_PIO2_TOECS (0x01 << 26)
#define SBC_IDE_PIO2_TWCS (0x01 << 28)
#define SBC_IDE_PIO2_TCSH (0x07 << 24)
#define SBC_IDE_PIO2_TCSOFF (0x07 << 20)
#define SBC_IDE_PIO2_TWP (0x1F << 14)
#define SBC_IDE_PIO2_TCSW (0x05 << 10)
#define SBC_IDE_PIO2_TPM (0x00 << 6)
#define SBC_IDE_PIO2_TA (0x22 << 0)
/* Timing parameters PIO mode 3 */
#define SBC_IDE_PIO3_TCSOE (0x05 << 29)
#define SBC_IDE_PIO3_TOECS (0x01 << 26)
#define SBC_IDE_PIO3_TWCS (0x01 << 28)
#define SBC_IDE_PIO3_TCSH (0x0D << 24)
#define SBC_IDE_PIO3_TCSOFF (0x0D << 20)
#define SBC_IDE_PIO3_TWP (0x15 << 14)
#define SBC_IDE_PIO3_TCSW (0x05 << 10)
#define SBC_IDE_PIO3_TPM (0x00 << 6)
#define SBC_IDE_PIO3_TA (0x1A << 0)
/* Timing parameters PIO mode 4 */
#define SBC_IDE_PIO4_TCSOE (0x04 << 29)
#define SBC_IDE_PIO4_TOECS (0x01 << 26)
#define SBC_IDE_PIO4_TWCS (0x01 << 28)
#define SBC_IDE_PIO4_TCSH (0x04 << 24)
#define SBC_IDE_PIO4_TCSOFF (0x04 << 20)
#define SBC_IDE_PIO4_TWP (0x0D << 14)
#define SBC_IDE_PIO4_TCSW (0x03 << 10)
#define SBC_IDE_PIO4_TPM (0x00 << 6)
#define SBC_IDE_PIO4_TA (0x12 << 0)
/* Timing parameters MDMA mode 0 */
#define SBC_IDE_MDMA0_TCSOE (0x03 << 29)
#define SBC_IDE_MDMA0_TOECS (0x01 << 26)
#define SBC_IDE_MDMA0_TWCS (0x01 << 28)
#define SBC_IDE_MDMA0_TCSH (0x07 << 24)
#define SBC_IDE_MDMA0_TCSOFF (0x07 << 20)
#define SBC_IDE_MDMA0_TWP (0x0C << 14)
#define SBC_IDE_MDMA0_TCSW (0x03 << 10)
#define SBC_IDE_MDMA0_TPM (0x00 << 6)
#define SBC_IDE_MDMA0_TA (0x0F << 0)
/* Timing parameters MDMA mode 1 */
#define SBC_IDE_MDMA1_TCSOE (0x05 << 29)
#define SBC_IDE_MDMA1_TOECS (0x01 << 26)
#define SBC_IDE_MDMA1_TWCS (0x01 << 28)
#define SBC_IDE_MDMA1_TCSH (0x05 << 24)
#define SBC_IDE_MDMA1_TCSOFF (0x05 << 20)
#define SBC_IDE_MDMA1_TWP (0x0F << 14)
#define SBC_IDE_MDMA1_TCSW (0x05 << 10)
#define SBC_IDE_MDMA1_TPM (0x00 << 6)
#define SBC_IDE_MDMA1_TA (0x15 << 0)
/* Timing parameters MDMA mode 2 */
#define SBC_IDE_MDMA2_TCSOE (0x04 << 29)
#define SBC_IDE_MDMA2_TOECS (0x01 << 26)
#define SBC_IDE_MDMA2_TWCS (0x01 << 28)
#define SBC_IDE_MDMA2_TCSH (0x04 << 24)
#define SBC_IDE_MDMA2_TCSOFF (0x04 << 20)
#define SBC_IDE_MDMA2_TWP (0x0D << 14)
#define SBC_IDE_MDMA2_TCSW (0x04 << 10)
#define SBC_IDE_MDMA2_TPM (0x00 << 6)
#define SBC_IDE_MDMA2_TA (0x12 << 0)
#define SBC_IDE_TIMING(mode) \
(SBC_IDE_##mode##_TWCS | \
SBC_IDE_##mode##_TCSH | \
SBC_IDE_##mode##_TCSOFF | \
SBC_IDE_##mode##_TWP | \
SBC_IDE_##mode##_TCSW | \
SBC_IDE_##mode##_TPM | \
SBC_IDE_##mode##_TA)

505
kernel/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h Normal file
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/*
*
* BRIEF MODULE DESCRIPTION
* Include file for Alchemy Semiconductor's Au1k CPU.
*
* Copyright 2004 Embedded Edge, LLC
* dan@embeddededge.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* Specifics for the Au1xxx Programmable Serial Controllers, first
* seen in the AU1550 part.
*/
#ifndef _AU1000_PSC_H_
#define _AU1000_PSC_H_
/* The PSC base addresses. */
#ifdef CONFIG_SOC_AU1550
#define PSC0_BASE_ADDR 0xb1a00000
#define PSC1_BASE_ADDR 0xb1b00000
#define PSC2_BASE_ADDR 0xb0a00000
#define PSC3_BASE_ADDR 0xb0b00000
#endif
#ifdef CONFIG_SOC_AU1200
#define PSC0_BASE_ADDR 0xb1a00000
#define PSC1_BASE_ADDR 0xb1b00000
#endif
/*
* The PSC select and control registers are common to all protocols.
*/
#define PSC_SEL_OFFSET 0x00000000
#define PSC_CTRL_OFFSET 0x00000004
#define PSC_SEL_CLK_MASK (3 << 4)
#define PSC_SEL_CLK_INTCLK (0 << 4)
#define PSC_SEL_CLK_EXTCLK (1 << 4)
#define PSC_SEL_CLK_SERCLK (2 << 4)
#define PSC_SEL_PS_MASK 0x00000007
#define PSC_SEL_PS_DISABLED 0
#define PSC_SEL_PS_SPIMODE 2
#define PSC_SEL_PS_I2SMODE 3
#define PSC_SEL_PS_AC97MODE 4
#define PSC_SEL_PS_SMBUSMODE 5
#define PSC_CTRL_DISABLE 0
#define PSC_CTRL_SUSPEND 2
#define PSC_CTRL_ENABLE 3
/* AC97 Registers. */
#define PSC_AC97CFG_OFFSET 0x00000008
#define PSC_AC97MSK_OFFSET 0x0000000c
#define PSC_AC97PCR_OFFSET 0x00000010
#define PSC_AC97STAT_OFFSET 0x00000014
#define PSC_AC97EVNT_OFFSET 0x00000018
#define PSC_AC97TXRX_OFFSET 0x0000001c
#define PSC_AC97CDC_OFFSET 0x00000020
#define PSC_AC97RST_OFFSET 0x00000024
#define PSC_AC97GPO_OFFSET 0x00000028
#define PSC_AC97GPI_OFFSET 0x0000002c
#define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET)
#define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET)
#define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
#define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
#define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
#define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
#define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
#define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
#define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
#define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
/* AC97 Config Register. */
#define PSC_AC97CFG_RT_MASK (3 << 30)
#define PSC_AC97CFG_RT_FIFO1 (0 << 30)
#define PSC_AC97CFG_RT_FIFO2 (1 << 30)
#define PSC_AC97CFG_RT_FIFO4 (2 << 30)
#define PSC_AC97CFG_RT_FIFO8 (3 << 30)
#define PSC_AC97CFG_TT_MASK (3 << 28)
#define PSC_AC97CFG_TT_FIFO1 (0 << 28)
#define PSC_AC97CFG_TT_FIFO2 (1 << 28)
#define PSC_AC97CFG_TT_FIFO4 (2 << 28)
#define PSC_AC97CFG_TT_FIFO8 (3 << 28)
#define PSC_AC97CFG_DD_DISABLE (1 << 27)
#define PSC_AC97CFG_DE_ENABLE (1 << 26)
#define PSC_AC97CFG_SE_ENABLE (1 << 25)
#define PSC_AC97CFG_LEN_MASK (0xf << 21)
#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11)
#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
#define PSC_AC97CFG_GE_ENABLE (1)
/* Enable slots 3-12. */
#define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11))
#define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1))
/*
* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
* The only sensible numbers are 7, 9, or possibly 11. Nah, just do the
* arithmetic in the macro.
*/
#define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21)
#define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2)
/* AC97 Mask Register. */
#define PSC_AC97MSK_GR (1 << 25)
#define PSC_AC97MSK_CD (1 << 24)
#define PSC_AC97MSK_RR (1 << 13)
#define PSC_AC97MSK_RO (1 << 12)
#define PSC_AC97MSK_RU (1 << 11)
#define PSC_AC97MSK_TR (1 << 10)
#define PSC_AC97MSK_TO (1 << 9)
#define PSC_AC97MSK_TU (1 << 8)
#define PSC_AC97MSK_RD (1 << 5)
#define PSC_AC97MSK_TD (1 << 4)
#define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \
PSC_AC97MSK_RR | PSC_AC97MSK_RO | \
PSC_AC97MSK_RU | PSC_AC97MSK_TR | \
PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
PSC_AC97MSK_RD | PSC_AC97MSK_TD)
/* AC97 Protocol Control Register. */
#define PSC_AC97PCR_RC (1 << 6)
#define PSC_AC97PCR_RP (1 << 5)
#define PSC_AC97PCR_RS (1 << 4)
#define PSC_AC97PCR_TC (1 << 2)
#define PSC_AC97PCR_TP (1 << 1)
#define PSC_AC97PCR_TS (1 << 0)
/* AC97 Status register (read only). */
#define PSC_AC97STAT_CB (1 << 26)
#define PSC_AC97STAT_CP (1 << 25)
#define PSC_AC97STAT_CR (1 << 24)
#define PSC_AC97STAT_RF (1 << 13)
#define PSC_AC97STAT_RE (1 << 12)
#define PSC_AC97STAT_RR (1 << 11)
#define PSC_AC97STAT_TF (1 << 10)
#define PSC_AC97STAT_TE (1 << 9)
#define PSC_AC97STAT_TR (1 << 8)
#define PSC_AC97STAT_RB (1 << 5)
#define PSC_AC97STAT_TB (1 << 4)
#define PSC_AC97STAT_DI (1 << 2)
#define PSC_AC97STAT_DR (1 << 1)
#define PSC_AC97STAT_SR (1 << 0)
/* AC97 Event Register. */
#define PSC_AC97EVNT_GR (1 << 25)
#define PSC_AC97EVNT_CD (1 << 24)
#define PSC_AC97EVNT_RR (1 << 13)
#define PSC_AC97EVNT_RO (1 << 12)
#define PSC_AC97EVNT_RU (1 << 11)
#define PSC_AC97EVNT_TR (1 << 10)
#define PSC_AC97EVNT_TO (1 << 9)
#define PSC_AC97EVNT_TU (1 << 8)
#define PSC_AC97EVNT_RD (1 << 5)
#define PSC_AC97EVNT_TD (1 << 4)
/* CODEC Command Register. */
#define PSC_AC97CDC_RD (1 << 25)
#define PSC_AC97CDC_ID_MASK (3 << 23)
#define PSC_AC97CDC_INDX_MASK (0x7f << 16)
#define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23)
#define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16)
/* AC97 Reset Control Register. */
#define PSC_AC97RST_RST (1 << 1)
#define PSC_AC97RST_SNC (1 << 0)
/* PSC in I2S Mode. */
typedef struct psc_i2s {
u32 psc_sel;
u32 psc_ctrl;
u32 psc_i2scfg;
u32 psc_i2smsk;
u32 psc_i2spcr;
u32 psc_i2sstat;
u32 psc_i2sevent;
u32 psc_i2stxrx;
u32 psc_i2sudf;
} psc_i2s_t;
#define PSC_I2SCFG_OFFSET 0x08
#define PSC_I2SMASK_OFFSET 0x0C
#define PSC_I2SPCR_OFFSET 0x10
#define PSC_I2SSTAT_OFFSET 0x14
#define PSC_I2SEVENT_OFFSET 0x18
#define PSC_I2SRXTX_OFFSET 0x1C
#define PSC_I2SUDF_OFFSET 0x20
/* I2S Config Register. */
#define PSC_I2SCFG_RT_MASK (3 << 30)
#define PSC_I2SCFG_RT_FIFO1 (0 << 30)
#define PSC_I2SCFG_RT_FIFO2 (1 << 30)
#define PSC_I2SCFG_RT_FIFO4 (2 << 30)
#define PSC_I2SCFG_RT_FIFO8 (3 << 30)
#define PSC_I2SCFG_TT_MASK (3 << 28)
#define PSC_I2SCFG_TT_FIFO1 (0 << 28)
#define PSC_I2SCFG_TT_FIFO2 (1 << 28)
#define PSC_I2SCFG_TT_FIFO4 (2 << 28)
#define PSC_I2SCFG_TT_FIFO8 (3 << 28)
#define PSC_I2SCFG_DD_DISABLE (1 << 27)
#define PSC_I2SCFG_DE_ENABLE (1 << 26)
#define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16)
#define PSC_I2SCFG_WS(n) ((n & 0xFF) << 16)
#define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F))
#define PSC_I2SCFG_WI (1 << 15)
#define PSC_I2SCFG_DIV_MASK (3 << 13)
#define PSC_I2SCFG_DIV2 (0 << 13)
#define PSC_I2SCFG_DIV4 (1 << 13)
#define PSC_I2SCFG_DIV8 (2 << 13)
#define PSC_I2SCFG_DIV16 (3 << 13)
#define PSC_I2SCFG_BI (1 << 12)
#define PSC_I2SCFG_BUF (1 << 11)
#define PSC_I2SCFG_MLJ (1 << 10)
#define PSC_I2SCFG_XM (1 << 9)
/* The word length equation is simply LEN+1. */
#define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4)
#define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1)
#define PSC_I2SCFG_LB (1 << 2)
#define PSC_I2SCFG_MLF (1 << 1)
#define PSC_I2SCFG_MS (1 << 0)
/* I2S Mask Register. */
#define PSC_I2SMSK_RR (1 << 13)
#define PSC_I2SMSK_RO (1 << 12)
#define PSC_I2SMSK_RU (1 << 11)
#define PSC_I2SMSK_TR (1 << 10)
#define PSC_I2SMSK_TO (1 << 9)
#define PSC_I2SMSK_TU (1 << 8)
#define PSC_I2SMSK_RD (1 << 5)
#define PSC_I2SMSK_TD (1 << 4)
#define PSC_I2SMSK_ALLMASK (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \
PSC_I2SMSK_RU | PSC_I2SMSK_TR | \
PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
PSC_I2SMSK_RD | PSC_I2SMSK_TD)
/* I2S Protocol Control Register. */
#define PSC_I2SPCR_RC (1 << 6)
#define PSC_I2SPCR_RP (1 << 5)
#define PSC_I2SPCR_RS (1 << 4)
#define PSC_I2SPCR_TC (1 << 2)
#define PSC_I2SPCR_TP (1 << 1)
#define PSC_I2SPCR_TS (1 << 0)
/* I2S Status register (read only). */
#define PSC_I2SSTAT_RF (1 << 13)
#define PSC_I2SSTAT_RE (1 << 12)
#define PSC_I2SSTAT_RR (1 << 11)
#define PSC_I2SSTAT_TF (1 << 10)
#define PSC_I2SSTAT_TE (1 << 9)
#define PSC_I2SSTAT_TR (1 << 8)
#define PSC_I2SSTAT_RB (1 << 5)
#define PSC_I2SSTAT_TB (1 << 4)
#define PSC_I2SSTAT_DI (1 << 2)
#define PSC_I2SSTAT_DR (1 << 1)
#define PSC_I2SSTAT_SR (1 << 0)
/* I2S Event Register. */
#define PSC_I2SEVNT_RR (1 << 13)
#define PSC_I2SEVNT_RO (1 << 12)
#define PSC_I2SEVNT_RU (1 << 11)
#define PSC_I2SEVNT_TR (1 << 10)
#define PSC_I2SEVNT_TO (1 << 9)
#define PSC_I2SEVNT_TU (1 << 8)
#define PSC_I2SEVNT_RD (1 << 5)
#define PSC_I2SEVNT_TD (1 << 4)
/* PSC in SPI Mode. */
typedef struct psc_spi {
u32 psc_sel;
u32 psc_ctrl;
u32 psc_spicfg;
u32 psc_spimsk;
u32 psc_spipcr;
u32 psc_spistat;
u32 psc_spievent;
u32 psc_spitxrx;
} psc_spi_t;
/* SPI Config Register. */
#define PSC_SPICFG_RT_MASK (3 << 30)
#define PSC_SPICFG_RT_FIFO1 (0 << 30)
#define PSC_SPICFG_RT_FIFO2 (1 << 30)
#define PSC_SPICFG_RT_FIFO4 (2 << 30)
#define PSC_SPICFG_RT_FIFO8 (3 << 30)
#define PSC_SPICFG_TT_MASK (3 << 28)
#define PSC_SPICFG_TT_FIFO1 (0 << 28)
#define PSC_SPICFG_TT_FIFO2 (1 << 28)
#define PSC_SPICFG_TT_FIFO4 (2 << 28)
#define PSC_SPICFG_TT_FIFO8 (3 << 28)
#define PSC_SPICFG_DD_DISABLE (1 << 27)
#define PSC_SPICFG_DE_ENABLE (1 << 26)
#define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15))
#define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15)
#define PSC_SPICFG_SET_DIV(x) (((x) & 0x03) << 13)
#define PSC_SPICFG_DIV2 0
#define PSC_SPICFG_DIV4 1
#define PSC_SPICFG_DIV8 2
#define PSC_SPICFG_DIV16 3
#define PSC_SPICFG_BI (1 << 12)
#define PSC_SPICFG_PSE (1 << 11)
#define PSC_SPICFG_CGE (1 << 10)
#define PSC_SPICFG_CDE (1 << 9)
#define PSC_SPICFG_CLR_LEN(x) ((x) & ~((0x1f) << 4))
#define PSC_SPICFG_SET_LEN(x) (((x-1) & 0x1f) << 4)
#define PSC_SPICFG_LB (1 << 3)
#define PSC_SPICFG_MLF (1 << 1)
#define PSC_SPICFG_MO (1 << 0)
/* SPI Mask Register. */
#define PSC_SPIMSK_MM (1 << 16)
#define PSC_SPIMSK_RR (1 << 13)
#define PSC_SPIMSK_RO (1 << 12)
#define PSC_SPIMSK_RU (1 << 11)
#define PSC_SPIMSK_TR (1 << 10)
#define PSC_SPIMSK_TO (1 << 9)
#define PSC_SPIMSK_TU (1 << 8)
#define PSC_SPIMSK_SD (1 << 5)
#define PSC_SPIMSK_MD (1 << 4)
#define PSC_SPIMSK_ALLMASK (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \
PSC_SPIMSK_RO | PSC_SPIMSK_TO | \
PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
PSC_SPIMSK_MD)
/* SPI Protocol Control Register. */
#define PSC_SPIPCR_RC (1 << 6)
#define PSC_SPIPCR_SP (1 << 5)
#define PSC_SPIPCR_SS (1 << 4)
#define PSC_SPIPCR_TC (1 << 2)
#define PSC_SPIPCR_MS (1 << 0)
/* SPI Status register (read only). */
#define PSC_SPISTAT_RF (1 << 13)
#define PSC_SPISTAT_RE (1 << 12)
#define PSC_SPISTAT_RR (1 << 11)
#define PSC_SPISTAT_TF (1 << 10)
#define PSC_SPISTAT_TE (1 << 9)
#define PSC_SPISTAT_TR (1 << 8)
#define PSC_SPISTAT_SB (1 << 5)
#define PSC_SPISTAT_MB (1 << 4)
#define PSC_SPISTAT_DI (1 << 2)
#define PSC_SPISTAT_DR (1 << 1)
#define PSC_SPISTAT_SR (1 << 0)
/* SPI Event Register. */
#define PSC_SPIEVNT_MM (1 << 16)
#define PSC_SPIEVNT_RR (1 << 13)
#define PSC_SPIEVNT_RO (1 << 12)
#define PSC_SPIEVNT_RU (1 << 11)
#define PSC_SPIEVNT_TR (1 << 10)
#define PSC_SPIEVNT_TO (1 << 9)
#define PSC_SPIEVNT_TU (1 << 8)
#define PSC_SPIEVNT_SD (1 << 5)
#define PSC_SPIEVNT_MD (1 << 4)
/* Transmit register control. */
#define PSC_SPITXRX_LC (1 << 29)
#define PSC_SPITXRX_SR (1 << 28)
/* PSC in SMBus (I2C) Mode. */
typedef struct psc_smb {
u32 psc_sel;
u32 psc_ctrl;
u32 psc_smbcfg;
u32 psc_smbmsk;
u32 psc_smbpcr;
u32 psc_smbstat;
u32 psc_smbevnt;
u32 psc_smbtxrx;
u32 psc_smbtmr;
} psc_smb_t;
/* SMBus Config Register. */
#define PSC_SMBCFG_RT_MASK (3 << 30)
#define PSC_SMBCFG_RT_FIFO1 (0 << 30)
#define PSC_SMBCFG_RT_FIFO2 (1 << 30)
#define PSC_SMBCFG_RT_FIFO4 (2 << 30)
#define PSC_SMBCFG_RT_FIFO8 (3 << 30)
#define PSC_SMBCFG_TT_MASK (3 << 28)
#define PSC_SMBCFG_TT_FIFO1 (0 << 28)
#define PSC_SMBCFG_TT_FIFO2 (1 << 28)
#define PSC_SMBCFG_TT_FIFO4 (2 << 28)
#define PSC_SMBCFG_TT_FIFO8 (3 << 28)
#define PSC_SMBCFG_DD_DISABLE (1 << 27)
#define PSC_SMBCFG_DE_ENABLE (1 << 26)
#define PSC_SMBCFG_SET_DIV(x) (((x) & 0x03) << 13)
#define PSC_SMBCFG_DIV2 0
#define PSC_SMBCFG_DIV4 1
#define PSC_SMBCFG_DIV8 2
#define PSC_SMBCFG_DIV16 3
#define PSC_SMBCFG_GCE (1 << 9)
#define PSC_SMBCFG_SFM (1 << 8)
#define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1)
/* SMBus Mask Register. */
#define PSC_SMBMSK_DN (1 << 30)
#define PSC_SMBMSK_AN (1 << 29)
#define PSC_SMBMSK_AL (1 << 28)
#define PSC_SMBMSK_RR (1 << 13)
#define PSC_SMBMSK_RO (1 << 12)
#define PSC_SMBMSK_RU (1 << 11)
#define PSC_SMBMSK_TR (1 << 10)
#define PSC_SMBMSK_TO (1 << 9)
#define PSC_SMBMSK_TU (1 << 8)
#define PSC_SMBMSK_SD (1 << 5)
#define PSC_SMBMSK_MD (1 << 4)
#define PSC_SMBMSK_ALLMASK (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \
PSC_SMBMSK_AL | PSC_SMBMSK_RR | \
PSC_SMBMSK_RO | PSC_SMBMSK_TO | \
PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
PSC_SMBMSK_MD)
/* SMBus Protocol Control Register. */
#define PSC_SMBPCR_DC (1 << 2)
#define PSC_SMBPCR_MS (1 << 0)
/* SMBus Status register (read only). */
#define PSC_SMBSTAT_BB (1 << 28)
#define PSC_SMBSTAT_RF (1 << 13)
#define PSC_SMBSTAT_RE (1 << 12)
#define PSC_SMBSTAT_RR (1 << 11)
#define PSC_SMBSTAT_TF (1 << 10)
#define PSC_SMBSTAT_TE (1 << 9)
#define PSC_SMBSTAT_TR (1 << 8)
#define PSC_SMBSTAT_SB (1 << 5)
#define PSC_SMBSTAT_MB (1 << 4)
#define PSC_SMBSTAT_DI (1 << 2)
#define PSC_SMBSTAT_DR (1 << 1)
#define PSC_SMBSTAT_SR (1 << 0)
/* SMBus Event Register. */
#define PSC_SMBEVNT_DN (1 << 30)
#define PSC_SMBEVNT_AN (1 << 29)
#define PSC_SMBEVNT_AL (1 << 28)
#define PSC_SMBEVNT_RR (1 << 13)
#define PSC_SMBEVNT_RO (1 << 12)
#define PSC_SMBEVNT_RU (1 << 11)
#define PSC_SMBEVNT_TR (1 << 10)
#define PSC_SMBEVNT_TO (1 << 9)
#define PSC_SMBEVNT_TU (1 << 8)
#define PSC_SMBEVNT_SD (1 << 5)
#define PSC_SMBEVNT_MD (1 << 4)
#define PSC_SMBEVNT_ALLCLR (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \
PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \
PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \
PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
PSC_SMBEVNT_MD)
/* Transmit register control. */
#define PSC_SMBTXRX_RSR (1 << 28)
#define PSC_SMBTXRX_STP (1 << 29)
#define PSC_SMBTXRX_DATAMASK 0xff
/* SMBus protocol timers register. */
#define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30)
#define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25)
#define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20)
#define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15)
#define PSC_SMBTMR_SET_SU(x) (((x) & 0x1f) << 10)
#define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5)
#define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0)
#endif /* _AU1000_PSC_H_ */

49
kernel/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h Normal file
View File

@@ -0,0 +1,49 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_tx39_cache 0
#define cpu_has_fpu 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_mcheck 1
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
#define cpu_has_mips16 0
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 1
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_vint 0
#define cpu_has_veic 0
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */

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kernel/arch/mips/include/asm/mach-au1x00/gpio-au1000.h Normal file
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/*
* GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
*
* Copyright (c) 2009 Manuel Lauss.
*
* Licensed under the terms outlined in the file COPYING.
*/
#ifndef _ALCHEMY_GPIO_AU1000_H_
#define _ALCHEMY_GPIO_AU1000_H_
#include <asm/mach-au1x00/au1000.h>
/* The default GPIO numberspace as documented in the Alchemy manuals.
* GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
*/
#define ALCHEMY_GPIO1_BASE 0
#define ALCHEMY_GPIO2_BASE 200
#define ALCHEMY_GPIO1_NUM 32
#define ALCHEMY_GPIO2_NUM 16
#define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
#define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
static inline int au1000_gpio1_to_irq(int gpio)
{
return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
}
static inline int au1000_gpio2_to_irq(int gpio)
{
return -ENXIO;
}
#ifdef CONFIG_SOC_AU1000
static inline int au1000_irq_to_gpio(int irq)
{
if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31))
return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
return -ENXIO;
}
#endif
static inline int au1500_gpio1_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO1_BASE;
switch (gpio) {
case 0 ... 15:
case 20:
case 23 ... 28: return MAKE_IRQ(1, gpio);
}
return -ENXIO;
}
static inline int au1500_gpio2_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO2_BASE;
switch (gpio) {
case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0);
case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4);
case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
}
return -ENXIO;
}
#ifdef CONFIG_SOC_AU1500
static inline int au1500_irq_to_gpio(int irq)
{
switch (irq) {
case AU1000_GPIO_0 ... AU1000_GPIO_15:
case AU1500_GPIO_20:
case AU1500_GPIO_23 ... AU1500_GPIO_28:
return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
case AU1500_GPIO_200 ... AU1500_GPIO_203:
return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0;
case AU1500_GPIO_204 ... AU1500_GPIO_205:
return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4;
case AU1500_GPIO_206 ... AU1500_GPIO_207:
return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
case AU1500_GPIO_208_215:
return ALCHEMY_GPIO2_BASE + 8;
}
return -ENXIO;
}
#endif
static inline int au1100_gpio1_to_irq(int gpio)
{
return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
}
static inline int au1100_gpio2_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO2_BASE;
if ((gpio >= 8) && (gpio <= 15))
return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
return -ENXIO;
}
#ifdef CONFIG_SOC_AU1100
static inline int au1100_irq_to_gpio(int irq)
{
switch (irq) {
case AU1000_GPIO_0 ... AU1000_GPIO_31:
return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
case AU1100_GPIO_208_215:
return ALCHEMY_GPIO2_BASE + 8;
}
return -ENXIO;
}
#endif
static inline int au1550_gpio1_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO1_BASE;
switch (gpio) {
case 0 ... 15:
case 20 ... 28: return MAKE_IRQ(1, gpio);
case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
}
return -ENXIO;
}
static inline int au1550_gpio2_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO2_BASE;
switch (gpio) {
case 0: return MAKE_IRQ(1, 16);
case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
}
return -ENXIO;
}
#ifdef CONFIG_SOC_AU1550
static inline int au1550_irq_to_gpio(int irq)
{
switch (irq) {
case AU1000_GPIO_0 ... AU1000_GPIO_15:
return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
case AU1550_GPIO_200:
case AU1500_GPIO_201_205:
return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0;
case AU1500_GPIO_16 ... AU1500_GPIO_28:
return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16;
case AU1500_GPIO_206 ... AU1500_GPIO_208_218:
return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
}
return -ENXIO;
}
#endif
static inline int au1200_gpio1_to_irq(int gpio)
{
return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
}
static inline int au1200_gpio2_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO2_BASE;
switch (gpio) {
case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0);
case 3: return MAKE_IRQ(0, 22);
case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4);
case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
}
return -ENXIO;
}
#ifdef CONFIG_SOC_AU1200
static inline int au1200_irq_to_gpio(int irq)
{
switch (irq) {
case AU1000_GPIO_0 ... AU1000_GPIO_31:
return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
case AU1200_GPIO_200 ... AU1200_GPIO_202:
return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0;
case AU1200_GPIO_203:
return ALCHEMY_GPIO2_BASE + 3;
case AU1200_GPIO_204 ... AU1200_GPIO_208_215:
return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4;
}
return -ENXIO;
}
#endif
/*
* GPIO1 block macros for common linux gpio functions.
*/
static inline void alchemy_gpio1_set_value(int gpio, int v)
{
unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
au_writel(mask, r);
au_sync();
}
static inline int alchemy_gpio1_get_value(int gpio)
{
unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
return au_readl(SYS_PINSTATERD) & mask;
}
static inline int alchemy_gpio1_direction_input(int gpio)
{
unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
au_writel(mask, SYS_TRIOUTCLR);
au_sync();
return 0;
}
static inline int alchemy_gpio1_direction_output(int gpio, int v)
{
/* hardware switches to "output" mode when one of the two
* "set_value" registers is accessed.
*/
alchemy_gpio1_set_value(gpio, v);
return 0;
}
static inline int alchemy_gpio1_is_valid(int gpio)
{
return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
}
static inline int alchemy_gpio1_to_irq(int gpio)
{
#if defined(CONFIG_SOC_AU1000)
return au1000_gpio1_to_irq(gpio);
#elif defined(CONFIG_SOC_AU1100)
return au1100_gpio1_to_irq(gpio);
#elif defined(CONFIG_SOC_AU1500)
return au1500_gpio1_to_irq(gpio);
#elif defined(CONFIG_SOC_AU1550)
return au1550_gpio1_to_irq(gpio);
#elif defined(CONFIG_SOC_AU1200)
return au1200_gpio1_to_irq(gpio);
#else
return -ENXIO;
#endif
}
/*
* GPIO2 block macros for common linux GPIO functions. The 'gpio'
* parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
*/
static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
{
unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
unsigned long d = au_readl(GPIO2_DIR);
if (to_out)
d |= mask;
else
d &= ~mask;
au_writel(d, GPIO2_DIR);
au_sync();
}
static inline void alchemy_gpio2_set_value(int gpio, int v)
{
unsigned long mask;
mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
au_writel(mask, GPIO2_OUTPUT);
au_sync();
}
static inline int alchemy_gpio2_get_value(int gpio)
{
return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
}
static inline int alchemy_gpio2_direction_input(int gpio)
{
unsigned long flags;
local_irq_save(flags);
__alchemy_gpio2_mod_dir(gpio, 0);
local_irq_restore(flags);
return 0;
}
static inline int alchemy_gpio2_direction_output(int gpio, int v)
{
unsigned long flags;
alchemy_gpio2_set_value(gpio, v);
local_irq_save(flags);
__alchemy_gpio2_mod_dir(gpio, 1);
local_irq_restore(flags);
return 0;
}
static inline int alchemy_gpio2_is_valid(int gpio)
{
return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
}
static inline int alchemy_gpio2_to_irq(int gpio)
{
#if defined(CONFIG_SOC_AU1000)
return au1000_gpio2_to_irq(gpio);
#elif defined(CONFIG_SOC_AU1100)
return au1100_gpio2_to_irq(gpio);
#elif defined(CONFIG_SOC_AU1500)
return au1500_gpio2_to_irq(gpio);
#elif defined(CONFIG_SOC_AU1550)
return au1550_gpio2_to_irq(gpio);
#elif defined(CONFIG_SOC_AU1200)
return au1200_gpio2_to_irq(gpio);
#else
return -ENXIO;
#endif
}
/**********************************************************************/
/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
* SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this
* register enables use of GPIOs as wake source.
*/
static inline void alchemy_gpio1_input_enable(void)
{
au_writel(0, SYS_PININPUTEN); /* the write op is key */
au_sync();
}
/* GPIO2 shared interrupts and control */
static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
{
unsigned long r = au_readl(GPIO2_INTENABLE);
if (en)
r |= 1 << gpio2;
else
r &= ~(1 << gpio2);
au_writel(r, GPIO2_INTENABLE);
au_sync();
}
/**
* alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
* @gpio2: The GPIO2 pin to activate (200...215).
*
* GPIO208-215 have one shared interrupt line to the INTC. They are
* and'ed with a per-pin enable bit and finally or'ed together to form
* a single irq request (useful for active-high sources).
* With this function, a pins' individual contribution to the int request
* can be enabled. As with all other GPIO-based interrupts, the INTC
* must be programmed to accept the GPIO208_215 interrupt as well.
*
* NOTE: Calling this macro is only necessary for GPIO208-215; all other
* GPIO2-based interrupts have their own request to the INTC. Please
* consult your Alchemy databook for more information!
*
* NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
* line to the INTC, GPIO201_205. This function can be used for those
* as well.
*
* NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
* (200-215 by default). No sanity checks are made,
*/
static inline void alchemy_gpio2_enable_int(int gpio2)
{
unsigned long flags;
gpio2 -= ALCHEMY_GPIO2_BASE;
#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
/* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
gpio2 -= 8;
#endif
local_irq_save(flags);
__alchemy_gpio2_mod_int(gpio2, 1);
local_irq_restore(flags);
}
/**
* alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
* @gpio2: The GPIO2 pin to activate (200...215).
*
* see function alchemy_gpio2_enable_int() for more information.
*/
static inline void alchemy_gpio2_disable_int(int gpio2)
{
unsigned long flags;
gpio2 -= ALCHEMY_GPIO2_BASE;
#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
/* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
gpio2 -= 8;
#endif
local_irq_save(flags);
__alchemy_gpio2_mod_int(gpio2, 0);
local_irq_restore(flags);
}
/**
* alchemy_gpio2_enable - Activate GPIO2 block.
*
* The GPIO2 block must be enabled excplicitly to work. On systems
* where this isn't done by the bootloader, this macro can be used.
*/
static inline void alchemy_gpio2_enable(void)
{
au_writel(3, GPIO2_ENABLE); /* reset, clock enabled */
au_sync();
au_writel(1, GPIO2_ENABLE); /* clock enabled */
au_sync();
}
/**
* alchemy_gpio2_disable - disable GPIO2 block.
*
* Disable and put GPIO2 block in low-power mode.
*/
static inline void alchemy_gpio2_disable(void)
{
au_writel(2, GPIO2_ENABLE); /* reset, clock disabled */
au_sync();
}
/**********************************************************************/
/* wrappers for on-chip gpios; can be used before gpio chips have been
* registered with gpiolib.
*/
static inline int alchemy_gpio_direction_input(int gpio)
{
return (gpio >= ALCHEMY_GPIO2_BASE) ?
alchemy_gpio2_direction_input(gpio) :
alchemy_gpio1_direction_input(gpio);
}
static inline int alchemy_gpio_direction_output(int gpio, int v)
{
return (gpio >= ALCHEMY_GPIO2_BASE) ?
alchemy_gpio2_direction_output(gpio, v) :
alchemy_gpio1_direction_output(gpio, v);
}
static inline int alchemy_gpio_get_value(int gpio)
{
return (gpio >= ALCHEMY_GPIO2_BASE) ?
alchemy_gpio2_get_value(gpio) :
alchemy_gpio1_get_value(gpio);
}
static inline void alchemy_gpio_set_value(int gpio, int v)
{
if (gpio >= ALCHEMY_GPIO2_BASE)
alchemy_gpio2_set_value(gpio, v);
else
alchemy_gpio1_set_value(gpio, v);
}
static inline int alchemy_gpio_is_valid(int gpio)
{
return (gpio >= ALCHEMY_GPIO2_BASE) ?
alchemy_gpio2_is_valid(gpio) :
alchemy_gpio1_is_valid(gpio);
}
static inline int alchemy_gpio_cansleep(int gpio)
{
return 0; /* Alchemy never gets tired */
}
static inline int alchemy_gpio_to_irq(int gpio)
{
return (gpio >= ALCHEMY_GPIO2_BASE) ?
alchemy_gpio2_to_irq(gpio) :
alchemy_gpio1_to_irq(gpio);
}
static inline int alchemy_irq_to_gpio(int irq)
{
#if defined(CONFIG_SOC_AU1000)
return au1000_irq_to_gpio(irq);
#elif defined(CONFIG_SOC_AU1100)
return au1100_irq_to_gpio(irq);
#elif defined(CONFIG_SOC_AU1500)
return au1500_irq_to_gpio(irq);
#elif defined(CONFIG_SOC_AU1550)
return au1550_irq_to_gpio(irq);
#elif defined(CONFIG_SOC_AU1200)
return au1200_irq_to_gpio(irq);
#else
return -ENXIO;
#endif
}
/**********************************************************************/
/* Linux gpio framework integration.
*
* 4 use cases of Au1000-Au1200 GPIOS:
*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
* Board must register gpiochips.
*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
* 2 (1 for Au1000) gpio_chips are registered.
*
*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
* the boards' gpio.h must provide the linux gpio wrapper functions,
*
*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
* inlinable gpio functions are provided which enable access to the
* Au1000 gpios only by using the numbers straight out of the data-
* sheets.
* Cases 1 and 3 are intended for boards which want to provide their own
* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
* which are in part provided by spare Au1000 GPIO pins and in part by
* an external FPGA but you still want them to be accssible in linux
* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
* as required).
*/
#ifndef CONFIG_GPIOLIB
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
static inline int gpio_direction_input(int gpio)
{
return alchemy_gpio_direction_input(gpio);
}
static inline int gpio_direction_output(int gpio, int v)
{
return alchemy_gpio_direction_output(gpio, v);
}
static inline int gpio_get_value(int gpio)
{
return alchemy_gpio_get_value(gpio);
}
static inline void gpio_set_value(int gpio, int v)
{
alchemy_gpio_set_value(gpio, v);
}
static inline int gpio_is_valid(int gpio)
{
return alchemy_gpio_is_valid(gpio);
}
static inline int gpio_cansleep(int gpio)
{
return alchemy_gpio_cansleep(gpio);
}
static inline int gpio_to_irq(int gpio)
{
return alchemy_gpio_to_irq(gpio);
}
static inline int irq_to_gpio(int irq)
{
return alchemy_irq_to_gpio(irq);
}
static inline int gpio_request(unsigned gpio, const char *label)
{
return 0;
}
static inline void gpio_free(unsigned gpio)
{
}
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
#else /* CONFIG GPIOLIB */
/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
/* get everything through gpiolib */
#define gpio_to_irq __gpio_to_irq
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define irq_to_gpio alchemy_irq_to_gpio
#include <asm-generic/gpio.h>
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
#endif /* !CONFIG_GPIOLIB */
#endif /* _ALCHEMY_GPIO_AU1000_H_ */

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kernel/arch/mips/include/asm/mach-au1x00/gpio.h Normal file
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#ifndef _ALCHEMY_GPIO_H_
#define _ALCHEMY_GPIO_H_
#if defined(CONFIG_ALCHEMY_GPIO_AU1000)
#include <asm/mach-au1x00/gpio-au1000.h>
#endif
#endif /* _ALCHEMY_GPIO_H_ */

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kernel/arch/mips/include/asm/mach-au1x00/ioremap.h Normal file
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/*
* include/asm-mips/mach-au1x00/ioremap.h
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MACH_AU1X00_IOREMAP_H
#define __ASM_MACH_AU1X00_IOREMAP_H
#include <linux/types.h>
#ifdef CONFIG_64BIT_PHYS_ADDR
extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
#else
static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
{
return phys_addr;
}
#endif
/*
* Allow physical addresses to be fixed up to help 36-bit peripherals.
*/
static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
{
return __fixup_bigphys_addr(phys_addr, size);
}
static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
unsigned long flags)
{
return NULL;
}
static inline int plat_iounmap(const volatile void __iomem *addr)
{
return 0;
}
#endif /* __ASM_MACH_AU1X00_IOREMAP_H */

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kernel/arch/mips/include/asm/mach-au1x00/prom.h Normal file
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#ifndef __AU1X00_PROM_H
#define __AU1X00_PROM_H
extern int prom_argc;
extern char **prom_argv;
extern char **prom_envp;
extern void prom_init_cmdline(void);
extern char *prom_getcmdline(void);
extern char *prom_getenv(char *envname);
extern int prom_get_ethernet_addr(char *ethernet_addr);
#endif

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kernel/arch/mips/include/asm/mach-au1x00/war.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H
#define __ASM_MIPS_MACH_AU1X00_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define RM9000_CDEX_SMP_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */