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add idl4k kernel firmware version 1.13.0.105

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This commit is contained in:
Jaroslav Kysela
2015-03-26 17:22:37 +01:00
parent 5194d2792e
commit e9070cdc77
31064 changed files with 12769984 additions and 0 deletions
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34
kernel/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998, 2001, 03 by Ralf Baechle
*
* RTC routines for PC style attached Dallas chip.
*/
#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
#define __ASM_MACH_AU1XX_MC146818RTC_H
#include <asm/io.h>
#include <asm/mach-au1x00/au1000.h>
#define RTC_PORT(x) (0x0c000000 + (x))
#define RTC_IRQ 8
#define PB1500_RTC_ADDR 0x0c000000
static inline unsigned char CMOS_READ(unsigned long offset)
{
offset <<= 2;
return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
}
static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
{
offset <<= 2;
au_writel(data, offset + PB1500_RTC_ADDR);
}
#define RTC_ALWAYS_BCD 1
#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */

87
kernel/arch/mips/include/asm/mach-pb1x00/pb1000.h Normal file
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/*
* Alchemy Semi Pb1000 Referrence Board
*
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
*
*/
#ifndef __ASM_PB1000_H
#define __ASM_PB1000_H
/* PCMCIA PB1000 specific defines */
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
#define PB1000_PCR 0xBE000000
# define PCR_SLOT_0_VPP0 (1 << 0)
# define PCR_SLOT_0_VPP1 (1 << 1)
# define PCR_SLOT_0_VCC0 (1 << 2)
# define PCR_SLOT_0_VCC1 (1 << 3)
# define PCR_SLOT_0_RST (1 << 4)
# define PCR_SLOT_1_VPP0 (1 << 8)
# define PCR_SLOT_1_VPP1 (1 << 9)
# define PCR_SLOT_1_VCC0 (1 << 10)
# define PCR_SLOT_1_VCC1 (1 << 11)
# define PCR_SLOT_1_RST (1 << 12)
#define PB1000_MDR 0xBE000004
# define MDR_PI (1 << 5) /* PCMCIA int latch */
# define MDR_EPI (1 << 14) /* enable PCMCIA int */
# define MDR_CPI (1 << 15) /* clear PCMCIA int */
#define PB1000_ACR1 0xBE000008
# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
# define ACR1_SLOT_0_READY (1 << 2) /* ready */
# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
# define ACR1_SLOT_1_READY (1 << 10) /* ready */
# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
#define CPLD_AUX0 0xBE00000C
#define CPLD_AUX1 0xBE000010
#define CPLD_AUX2 0xBE000014
/* Voltage levels */
/* VPPEN1 - VPPEN0 */
#define VPP_GND ((0 << 1) | (0 << 0))
#define VPP_5V ((1 << 1) | (0 << 0))
#define VPP_3V ((0 << 1) | (1 << 0))
#define VPP_12V ((0 << 1) | (1 << 0))
#define VPP_HIZ ((1 << 1) | (1 << 0))
/* VCCEN1 - VCCEN0 */
#define VCC_3V ((0 << 1) | (1 << 0))
#define VCC_5V ((1 << 1) | (0 << 0))
#define VCC_HIZ ((0 << 1) | (0 << 0))
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT) \
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
#endif /* __ASM_PB1000_H */

85
kernel/arch/mips/include/asm/mach-pb1x00/pb1100.h Normal file
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/*
* Alchemy Semi Pb1100 Referrence Board
*
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
*
*/
#ifndef __ASM_PB1100_H
#define __ASM_PB1100_H
#define PB1100_IDENT 0xAE000000
#define BOARD_STATUS_REG 0xAE000004
# define PB1100_ROM_SEL (1 << 15)
# define PB1100_ROM_SIZ (1 << 14)
# define PB1100_SWAP_BOOT (1 << 13)
# define PB1100_FLASH_WP (1 << 12)
# define PB1100_ROM_H_STS (1 << 11)
# define PB1100_ROM_L_STS (1 << 10)
# define PB1100_FLASH_H_STS (1 << 9)
# define PB1100_FLASH_L_STS (1 << 8)
# define PB1100_SRAM_SIZ (1 << 7)
# define PB1100_TSC_BUSY (1 << 6)
# define PB1100_PCMCIA_VS_MASK (3 << 4)
# define PB1100_RS232_CD (1 << 3)
# define PB1100_RS232_CTS (1 << 2)
# define PB1100_RS232_DSR (1 << 1)
# define PB1100_RS232_RI (1 << 0)
#define PB1100_IRDA_RS232 0xAE00000C
# define PB1100_IRDA_FULL (0 << 14) /* full power */
# define PB1100_IRDA_SHUTDOWN (1 << 14)
# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */
# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */
# define PB1100_IRDA_FIR (1 << 13)
#define PCMCIA_BOARD_REG 0xAE000010
# define PB1100_SD_WP1_RO (1 << 15) /* read only */
# define PB1100_SD_WP0_RO (1 << 14) /* read only */
# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */
# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */
# define PB1100_SEL_SD_CONN1 (1 << 9)
# define PB1100_SEL_SD_CONN0 (1 << 8)
# define PC_DEASSERT_RST (1 << 7)
# define PC_DRV_EN (1 << 4)
#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
#define PB1100_RST_VDDI 0xAE00001C
# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */
# define PB1100_VDDI_MASK 0x1F
#define PB1100_LEDS 0xAE000018
/*
* 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
* 7:0 is the LED Display's decimal points.
*/
#define PB1100_HEX_LED 0xAE000018
/* PCMCIA Pb1100 specific defines */
#define PCMCIA_MAX_SOCK 0
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
#endif /* __ASM_PB1100_H */

259
kernel/arch/mips/include/asm/mach-pb1x00/pb1200.h Normal file
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/*
* AMD Alchemy Pb1200 Referrence Board
* Board Registers defines.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
*
*/
#ifndef __ASM_PB1200_H
#define __ASM_PB1200_H
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
/*
* SPI and SMB are muxed on the Pb1200 board.
* Refer to board documentation.
*/
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define SMBUS_PSC_BASE PSC0_BASE_ADDR
/*
* AC97 and I2S are muxed on the Pb1200 board.
* Refer to board documentation.
*/
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define I2S_PSC_BASE PSC1_BASE_ADDR
#define BCSR_KSEG1_ADDR 0xAD800000
typedef volatile struct
{
/*00*/ u16 whoami;
u16 reserved0;
/*04*/ u16 status;
u16 reserved1;
/*08*/ u16 switches;
u16 reserved2;
/*0C*/ u16 resets;
u16 reserved3;
/*10*/ u16 pcmcia;
u16 reserved4;
/*14*/ u16 board;
u16 reserved5;
/*18*/ u16 disk_leds;
u16 reserved6;
/*1C*/ u16 system;
u16 reserved7;
/*20*/ u16 intclr;
u16 reserved8;
/*24*/ u16 intset;
u16 reserved9;
/*28*/ u16 intclr_mask;
u16 reserved10;
/*2C*/ u16 intset_mask;
u16 reserved11;
/*30*/ u16 sig_status;
u16 reserved12;
/*34*/ u16 int_status;
u16 reserved13;
/*38*/ u16 reserved14;
u16 reserved15;
/*3C*/ u16 reserved16;
u16 reserved17;
} BCSR;
static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
/*
* Register bit definitions for the BCSRs
*/
#define BCSR_WHOAMI_DCID 0x000F
#define BCSR_WHOAMI_CPLD 0x00F0
#define BCSR_WHOAMI_BOARD 0x0F00
#define BCSR_STATUS_PCMCIA0VS 0x0003
#define BCSR_STATUS_PCMCIA1VS 0x000C
#define BCSR_STATUS_SWAPBOOT 0x0040
#define BCSR_STATUS_FLASHBUSY 0x0100
#define BCSR_STATUS_IDECBLID 0x0200
#define BCSR_STATUS_SD0WP 0x0400
#define BCSR_STATUS_SD1WP 0x0800
#define BCSR_STATUS_U0RXD 0x1000
#define BCSR_STATUS_U1RXD 0x2000
#define BCSR_SWITCHES_OCTAL 0x00FF
#define BCSR_SWITCHES_DIP_1 0x0080
#define BCSR_SWITCHES_DIP_2 0x0040
#define BCSR_SWITCHES_DIP_3 0x0020
#define BCSR_SWITCHES_DIP_4 0x0010
#define BCSR_SWITCHES_DIP_5 0x0008
#define BCSR_SWITCHES_DIP_6 0x0004
#define BCSR_SWITCHES_DIP_7 0x0002
#define BCSR_SWITCHES_DIP_8 0x0001
#define BCSR_SWITCHES_ROTARY 0x0F00
#define BCSR_RESETS_ETH 0x0001
#define BCSR_RESETS_CAMERA 0x0002
#define BCSR_RESETS_DC 0x0004
#define BCSR_RESETS_IDE 0x0008
/* not resets but in the same register */
#define BCSR_RESETS_WSCFSM 0x0800
#define BCSR_RESETS_PCS0MUX 0x1000
#define BCSR_RESETS_PCS1MUX 0x2000
#define BCSR_RESETS_SPISEL 0x4000
#define BCSR_RESETS_SD1MUX 0x8000
#define BCSR_PCMCIA_PC0VPP 0x0003
#define BCSR_PCMCIA_PC0VCC 0x000C
#define BCSR_PCMCIA_PC0DRVEN 0x0010
#define BCSR_PCMCIA_PC0RST 0x0080
#define BCSR_PCMCIA_PC1VPP 0x0300
#define BCSR_PCMCIA_PC1VCC 0x0C00
#define BCSR_PCMCIA_PC1DRVEN 0x1000
#define BCSR_PCMCIA_PC1RST 0x8000
#define BCSR_BOARD_LCDVEE 0x0001
#define BCSR_BOARD_LCDVDD 0x0002
#define BCSR_BOARD_LCDBL 0x0004
#define BCSR_BOARD_CAMSNAP 0x0010
#define BCSR_BOARD_CAMPWR 0x0020
#define BCSR_BOARD_SD0PWR 0x0040
#define BCSR_BOARD_SD1PWR 0x0080
#define BCSR_LEDS_DECIMALS 0x00FF
#define BCSR_LEDS_LED0 0x0100
#define BCSR_LEDS_LED1 0x0200
#define BCSR_LEDS_LED2 0x0400
#define BCSR_LEDS_LED3 0x0800
#define BCSR_SYSTEM_VDDI 0x001F
#define BCSR_SYSTEM_POWEROFF 0x4000
#define BCSR_SYSTEM_RESET 0x8000
/* Bit positions for the different interrupt sources */
#define BCSR_INT_IDE 0x0001
#define BCSR_INT_ETH 0x0002
#define BCSR_INT_PC0 0x0004
#define BCSR_INT_PC0STSCHG 0x0008
#define BCSR_INT_PC1 0x0010
#define BCSR_INT_PC1STSCHG 0x0020
#define BCSR_INT_DC 0x0040
#define BCSR_INT_FLASHBUSY 0x0080
#define BCSR_INT_PC0INSERT 0x0100
#define BCSR_INT_PC0EJECT 0x0200
#define BCSR_INT_PC1INSERT 0x0400
#define BCSR_INT_PC1EJECT 0x0800
#define BCSR_INT_SD0INSERT 0x1000
#define BCSR_INT_SD0EJECT 0x2000
#define BCSR_INT_SD1INSERT 0x4000
#define BCSR_INT_SD1EJECT 0x8000
#define SMC91C111_PHYS_ADDR 0x0D000300
#define SMC91C111_INT PB1200_ETH_INT
#define IDE_PHYS_ADDR 0x0C800000
#define IDE_REG_SHIFT 5
#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
#define IDE_INT PB1200_IDE_INT
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
#define IDE_RQSIZE 128
#define NAND_PHYS_ADDR 0x1C000000
/*
* Timing values as described in databook, * ns value stripped of
* lower 2 bits.
* These defines are here rather than an Au1200 generic file because
* the parts chosen on another board may be different and may require
* different timings.
*/
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
/* Bitfield shift amounts */
#define NAND_T_H_SHIFT 0
#define NAND_T_PUL_SHIFT 4
#define NAND_T_SU_SHIFT 8
#define NAND_T_WH_SHIFT 12
#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
/*
* External Interrupts for Pb1200 as of 8/6/2004.
* Bit positions in the CPLD registers can be calculated by taking
* the interrupt define and subtracting the PB1200_INT_BEGIN value.
*
* Example: IDE bis pos is = 64 - 64
* ETH bit pos is = 65 - 64
*/
enum external_pb1200_ints {
PB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
PB1200_IDE_INT = PB1200_INT_BEGIN,
PB1200_ETH_INT,
PB1200_PC0_INT,
PB1200_PC0_STSCHG_INT,
PB1200_PC1_INT,
PB1200_PC1_STSCHG_INT,
PB1200_DC_INT,
PB1200_FLASHBUSY_INT,
PB1200_PC0_INSERT_INT,
PB1200_PC0_EJECT_INT,
PB1200_PC1_INSERT_INT,
PB1200_PC1_EJECT_INT,
PB1200_SD0_INSERT_INT,
PB1200_SD0_EJECT_INT,
PB1200_SD1_INSERT_INT,
PB1200_SD1_EJECT_INT,
PB1200_INT_END = PB1200_INT_BEGIN + 15
};
/*
* Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
*/
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT) \
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
#define BOARD_PC0_INT PB1200_PC0_INT
#define BOARD_PC1_INT PB1200_PC1_INT
#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
/* NAND chip select */
#define NAND_CS 1
#endif /* __ASM_PB1200_H */

49
kernel/arch/mips/include/asm/mach-pb1x00/pb1500.h Normal file
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/*
* Alchemy Semi Pb1500 Referrence Board
*
* Copyright 2001, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
*
*/
#ifndef __ASM_PB1500_H
#define __ASM_PB1500_H
#define IDENT_BOARD_REG 0xAE000000
#define BOARD_STATUS_REG 0xAE000004
#define PCI_BOARD_REG 0xAE000010
#define PCMCIA_BOARD_REG 0xAE000010
# define PC_DEASSERT_RST 0x80
# define PC_DRV_EN 0x10
#define PB1500_G_CONTROL 0xAE000014
#define PB1500_RST_VDDI 0xAE00001C
#define PB1500_LEDS 0xAE000018
#define PB1500_HEX_LED 0xAF000004
#define PB1500_HEX_LED_BLANK 0xAF000008
/* PCMCIA Pb1500 specific defines */
#define PCMCIA_MAX_SOCK 0
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
#endif /* __ASM_PB1500_H */

177
kernel/arch/mips/include/asm/mach-pb1x00/pb1550.h Normal file
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/*
* AMD Alchemy Semi PB1550 Referrence Board
* Board Registers defines.
*
* Copyright 2004 Embedded Edge LLC.
* Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
*
*/
#ifndef __ASM_PB1550_H
#define __ASM_PB1550_H
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
#define SPI_PSC_BASE PSC0_BASE_ADDR
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define SMBUS_PSC_BASE PSC2_BASE_ADDR
#define I2S_PSC_BASE PSC3_BASE_ADDR
#define BCSR_PHYS_ADDR 0xAF000000
typedef volatile struct
{
/*00*/ u16 whoami;
u16 reserved0;
/*04*/ u16 status;
u16 reserved1;
/*08*/ u16 switches;
u16 reserved2;
/*0C*/ u16 resets;
u16 reserved3;
/*10*/ u16 pcmcia;
u16 reserved4;
/*14*/ u16 pci;
u16 reserved5;
/*18*/ u16 leds;
u16 reserved6;
/*1C*/ u16 system;
u16 reserved7;
} BCSR;
static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
/*
* Register bit definitions for the BCSRs
*/
#define BCSR_WHOAMI_DCID 0x000F
#define BCSR_WHOAMI_CPLD 0x00F0
#define BCSR_WHOAMI_BOARD 0x0F00
#define BCSR_STATUS_PCMCIA0VS 0x0003
#define BCSR_STATUS_PCMCIA1VS 0x000C
#define BCSR_STATUS_PCMCIA0FI 0x0010
#define BCSR_STATUS_PCMCIA1FI 0x0020
#define BCSR_STATUS_SWAPBOOT 0x0040
#define BCSR_STATUS_SRAMWIDTH 0x0080
#define BCSR_STATUS_FLASHBUSY 0x0100
#define BCSR_STATUS_ROMBUSY 0x0200
#define BCSR_STATUS_USBOTGID 0x0800
#define BCSR_STATUS_U0RXD 0x1000
#define BCSR_STATUS_U1RXD 0x2000
#define BCSR_STATUS_U3RXD 0x8000
#define BCSR_SWITCHES_OCTAL 0x00FF
#define BCSR_SWITCHES_DIP_1 0x0080
#define BCSR_SWITCHES_DIP_2 0x0040
#define BCSR_SWITCHES_DIP_3 0x0020
#define BCSR_SWITCHES_DIP_4 0x0010
#define BCSR_SWITCHES_DIP_5 0x0008
#define BCSR_SWITCHES_DIP_6 0x0004
#define BCSR_SWITCHES_DIP_7 0x0002
#define BCSR_SWITCHES_DIP_8 0x0001
#define BCSR_SWITCHES_ROTARY 0x0F00
#define BCSR_RESETS_PHY0 0x0001
#define BCSR_RESETS_PHY1 0x0002
#define BCSR_RESETS_DC 0x0004
#define BCSR_RESETS_WSC 0x2000
#define BCSR_RESETS_SPISEL 0x4000
#define BCSR_RESETS_DMAREQ 0x8000
#define BCSR_PCMCIA_PC0VPP 0x0003
#define BCSR_PCMCIA_PC0VCC 0x000C
#define BCSR_PCMCIA_PC0DRVEN 0x0010
#define BCSR_PCMCIA_PC0RST 0x0080
#define BCSR_PCMCIA_PC1VPP 0x0300
#define BCSR_PCMCIA_PC1VCC 0x0C00
#define BCSR_PCMCIA_PC1DRVEN 0x1000
#define BCSR_PCMCIA_PC1RST 0x8000
#define BCSR_PCI_M66EN 0x0001
#define BCSR_PCI_M33 0x0100
#define BCSR_PCI_EXTERNARB 0x0200
#define BCSR_PCI_GPIO200RST 0x0400
#define BCSR_PCI_CLKOUT 0x0800
#define BCSR_PCI_CFGHOST 0x1000
#define BCSR_LEDS_DECIMALS 0x00FF
#define BCSR_LEDS_LED0 0x0100
#define BCSR_LEDS_LED1 0x0200
#define BCSR_LEDS_LED2 0x0400
#define BCSR_LEDS_LED3 0x0800
#define BCSR_SYSTEM_VDDI 0x001F
#define BCSR_SYSTEM_POWEROFF 0x4000
#define BCSR_SYSTEM_RESET 0x8000
#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT) \
((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
#define PB1550_BOTH_BANKS
#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
#define PB1550_BOOT_ONLY
#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
#define PB1550_USER_ONLY
#endif
/*
* Timing values as described in databook, * ns value stripped of
* lower 2 bits.
* These defines are here rather than an SOC1550 generic file because
* the parts chosen on another board may be different and may require
* different timings.
*/
#define NAND_T_H (18 >> 2)
#define NAND_T_PUL (30 >> 2)
#define NAND_T_SU (30 >> 2)
#define NAND_T_WH (30 >> 2)
/* Bitfield shift amounts */
#define NAND_T_H_SHIFT 0
#define NAND_T_PUL_SHIFT 4
#define NAND_T_SU_SHIFT 8
#define NAND_T_WH_SHIFT 12
#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
#define NAND_CS 1
/* Should be done by YAMON */
#define NAND_STCFG 0x00400005 /* 8-bit NAND */
#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
#endif /* __ASM_PB1550_H */