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add idl4k kernel firmware version 1.13.0.105

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This commit is contained in:
Jaroslav Kysela
2015-03-26 17:22:37 +01:00
parent 5194d2792e
commit e9070cdc77
31064 changed files with 12769984 additions and 0 deletions
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21
kernel/drivers/media/video/cx18/Kconfig Normal file
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config VIDEO_CX18
tristate "Conexant cx23418 MPEG encoder support"
depends on VIDEO_V4L2 && DVB_CORE && PCI && I2C && EXPERIMENTAL
depends on INPUT # due to VIDEO_IR
select I2C_ALGOBIT
select VIDEO_IR
select VIDEO_TUNER
select VIDEO_TVEEPROM
select VIDEO_CX2341X
select VIDEO_CS5345
select DVB_S5H1409 if !DVB_FE_CUSTOMISE
select MEDIA_TUNER_MXL5005S if !MEDIA_TUNER_CUSTOMISE
---help---
This is a video4linux driver for Conexant cx23418 based
PCI combo video recorder devices.
This is used in devices such as the Hauppauge HVR-1600
cards.
To compile this driver as a module, choose M here: the
module will be called cx18.

11
kernel/drivers/media/video/cx18/Makefile Normal file
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cx18-objs := cx18-driver.o cx18-cards.o cx18-i2c.o cx18-firmware.o cx18-gpio.o \
cx18-queue.o cx18-streams.o cx18-fileops.o cx18-ioctl.o cx18-controls.o \
cx18-mailbox.o cx18-vbi.o cx18-audio.o cx18-video.o cx18-irq.o \
cx18-av-core.o cx18-av-audio.o cx18-av-firmware.o cx18-av-vbi.o cx18-scb.o \
cx18-dvb.o cx18-io.o
obj-$(CONFIG_VIDEO_CX18) += cx18.o
EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core
EXTRA_CFLAGS += -Idrivers/media/dvb/frontends
EXTRA_CFLAGS += -Idrivers/media/common/tuners

92
kernel/drivers/media/video/cx18/cx18-audio.c Normal file
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/*
* cx18 audio-related functions
*
* Derived from ivtv-audio.c
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-cards.h"
#include "cx18-audio.h"
#define CX18_AUDIO_ENABLE 0xc72014
#define CX18_AI1_MUX_MASK 0x30
#define CX18_AI1_MUX_I2S1 0x00
#define CX18_AI1_MUX_I2S2 0x10
#define CX18_AI1_MUX_843_I2S 0x20
/* Selects the audio input and output according to the current
settings. */
int cx18_audio_set_io(struct cx18 *cx)
{
const struct cx18_card_audio_input *in;
u32 u, v;
int err;
/* Determine which input to use */
if (test_bit(CX18_F_I_RADIO_USER, &cx->i_flags))
in = &cx->card->radio_input;
else
in = &cx->card->audio_inputs[cx->audio_input];
/* handle muxer chips */
v4l2_subdev_call(cx->sd_extmux, audio, s_routing,
(u32) in->muxer_input, 0, 0);
err = cx18_call_hw_err(cx, cx->card->hw_audio_ctrl,
audio, s_routing, in->audio_input, 0, 0);
if (err)
return err;
/* FIXME - this internal mux should be abstracted to a subdev */
u = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
v = u & ~CX18_AI1_MUX_MASK;
switch (in->audio_input) {
case CX18_AV_AUDIO_SERIAL1:
v |= CX18_AI1_MUX_I2S1;
break;
case CX18_AV_AUDIO_SERIAL2:
v |= CX18_AI1_MUX_I2S2;
break;
default:
v |= CX18_AI1_MUX_843_I2S;
break;
}
if (v == u) {
/* force a toggle of some AI1 MUX control bits */
u &= ~CX18_AI1_MUX_MASK;
switch (in->audio_input) {
case CX18_AV_AUDIO_SERIAL1:
u |= CX18_AI1_MUX_843_I2S;
break;
case CX18_AV_AUDIO_SERIAL2:
u |= CX18_AI1_MUX_843_I2S;
break;
default:
u |= CX18_AI1_MUX_I2S1;
break;
}
cx18_write_reg_expect(cx, u | 0xb00, CX18_AUDIO_ENABLE,
u, CX18_AI1_MUX_MASK);
}
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
v, CX18_AI1_MUX_MASK);
return 0;
}

24
kernel/drivers/media/video/cx18/cx18-audio.h Normal file
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/*
* cx18 audio-related functions
*
* Derived from ivtv-audio.c
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
int cx18_audio_set_io(struct cx18 *cx);

539
kernel/drivers/media/video/cx18/cx18-av-audio.c Normal file
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/*
* cx18 ADEC audio functions
*
* Derived from cx25840-audio.c
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include "cx18-driver.h"
static int set_audclk_freq(struct cx18 *cx, u32 freq)
{
struct cx18_av_state *state = &cx->av_state;
if (freq != 32000 && freq != 44100 && freq != 48000)
return -EINVAL;
/*
* The PLL parameters are based on the external crystal frequency that
* would ideally be:
*
* NTSC Color subcarrier freq * 8 =
* 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
*
* The accidents of history and rationale that explain from where this
* combination of magic numbers originate can be found in:
*
* [1] Abrahams, I. C., "Choice of Chrominance Subcarrier Frequency in
* the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80
*
* [2] Abrahams, I. C., "The 'Frequency Interleaving' Principle in the
* NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83
*
* As Mike Bradley has rightly pointed out, it's not the exact crystal
* frequency that matters, only that all parts of the driver and
* firmware are using the same value (close to the ideal value).
*
* Since I have a strong suspicion that, if the firmware ever assumes a
* crystal value at all, it will assume 28.636360 MHz, the crystal
* freq used in calculations in this driver will be:
*
* xtal_freq = 28.636360 MHz
*
* an error of less than 0.13 ppm which is way, way better than any off
* the shelf crystal will have for accuracy anyway.
*
* Below I aim to run the PLLs' VCOs near 400 MHz to minimze error.
*
* Many thanks to Jeff Campbell and Mike Bradley for their extensive
* investigation, experimentation, testing, and suggested solutions of
* of audio/video sync problems with SVideo and CVBS captures.
*/
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
switch (freq) {
case 32000:
/*
* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
* AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20
*/
cx18_av_write4(cx, 0x108, 0x200d040f);
/* VID_PLL Fraction = 0x2be2fe */
/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
cx18_av_write4(cx, 0x10c, 0x002be2fe);
/* AUX_PLL Fraction = 0x176740c */
/* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/
cx18_av_write4(cx, 0x110, 0x0176740c);
/* src3/4/6_ctl */
/* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */
cx18_av_write4(cx, 0x900, 0x0801f77f);
cx18_av_write4(cx, 0x904, 0x0801f77f);
cx18_av_write4(cx, 0x90c, 0x0801f77f);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x20 */
cx18_av_write(cx, 0x127, 0x60);
/* AUD_COUNT = 0x2fff = 8 samples * 4 * 384 - 1 */
cx18_av_write4(cx, 0x12c, 0x11202fff);
/*
* EN_AV_LOCK = 0
* VID_COUNT = 0x0d2ef8 = 107999.000 * 8 =
* ((8 samples/32,000) * (13,500,000 * 8) * 4 - 1) * 8
*/
cx18_av_write4(cx, 0x128, 0xa00d2ef8);
break;
case 44100:
/*
* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
* AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x18
*/
cx18_av_write4(cx, 0x108, 0x180e040f);
/* VID_PLL Fraction = 0x2be2fe */
/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
cx18_av_write4(cx, 0x10c, 0x002be2fe);
/* AUX_PLL Fraction = 0x062a1f2 */
/* xtal * 0xe.3150f90/0x18 = 44100 * 384: 406 MHz p-pd*/
cx18_av_write4(cx, 0x110, 0x0062a1f2);
/* src3/4/6_ctl */
/* 0x1.6d59 = (4 * xtal/8*2/455) / 44100 */
cx18_av_write4(cx, 0x900, 0x08016d59);
cx18_av_write4(cx, 0x904, 0x08016d59);
cx18_av_write4(cx, 0x90c, 0x08016d59);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x18 */
cx18_av_write(cx, 0x127, 0x58);
/* AUD_COUNT = 0x92ff = 49 samples * 2 * 384 - 1 */
cx18_av_write4(cx, 0x12c, 0x112092ff);
/*
* EN_AV_LOCK = 0
* VID_COUNT = 0x1d4bf8 = 239999.000 * 8 =
* ((49 samples/44,100) * (13,500,000 * 8) * 2 - 1) * 8
*/
cx18_av_write4(cx, 0x128, 0xa01d4bf8);
break;
case 48000:
/*
* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
* AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x16
*/
cx18_av_write4(cx, 0x108, 0x160e040f);
/* VID_PLL Fraction = 0x2be2fe */
/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
cx18_av_write4(cx, 0x10c, 0x002be2fe);
/* AUX_PLL Fraction = 0x05227ad */
/* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz p-pd*/
cx18_av_write4(cx, 0x110, 0x005227ad);
/* src3/4/6_ctl */
/* 0x1.4faa = (4 * xtal/8*2/455) / 48000 */
cx18_av_write4(cx, 0x900, 0x08014faa);
cx18_av_write4(cx, 0x904, 0x08014faa);
cx18_av_write4(cx, 0x90c, 0x08014faa);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
cx18_av_write(cx, 0x127, 0x56);
/* AUD_COUNT = 0x5fff = 4 samples * 16 * 384 - 1 */
cx18_av_write4(cx, 0x12c, 0x11205fff);
/*
* EN_AV_LOCK = 0
* VID_COUNT = 0x1193f8 = 143999.000 * 8 =
* ((4 samples/48,000) * (13,500,000 * 8) * 16 - 1) * 8
*/
cx18_av_write4(cx, 0x128, 0xa01193f8);
break;
}
} else {
switch (freq) {
case 32000:
/*
* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
* AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x30
*/
cx18_av_write4(cx, 0x108, 0x300d040f);
/* VID_PLL Fraction = 0x2be2fe */
/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
cx18_av_write4(cx, 0x10c, 0x002be2fe);
/* AUX_PLL Fraction = 0x176740c */
/* xtal * 0xd.bb3a060/0x30 = 32000 * 256: 393 MHz p-pd*/
cx18_av_write4(cx, 0x110, 0x0176740c);
/* src1_ctl */
/* 0x1.0000 = 32000/32000 */
cx18_av_write4(cx, 0x8f8, 0x08010000);
/* src3/4/6_ctl */
/* 0x2.0000 = 2 * (32000/32000) */
cx18_av_write4(cx, 0x900, 0x08020000);
cx18_av_write4(cx, 0x904, 0x08020000);
cx18_av_write4(cx, 0x90c, 0x08020000);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x30 */
cx18_av_write(cx, 0x127, 0x70);
/* AUD_COUNT = 0x1fff = 8 samples * 4 * 256 - 1 */
cx18_av_write4(cx, 0x12c, 0x11201fff);
/*
* EN_AV_LOCK = 0
* VID_COUNT = 0x0d2ef8 = 107999.000 * 8 =
* ((8 samples/32,000) * (13,500,000 * 8) * 4 - 1) * 8
*/
cx18_av_write4(cx, 0x128, 0xa00d2ef8);
break;
case 44100:
/*
* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
* AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x24
*/
cx18_av_write4(cx, 0x108, 0x240e040f);
/* VID_PLL Fraction = 0x2be2fe */
/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
cx18_av_write4(cx, 0x10c, 0x002be2fe);
/* AUX_PLL Fraction = 0x062a1f2 */
/* xtal * 0xe.3150f90/0x24 = 44100 * 256: 406 MHz p-pd*/
cx18_av_write4(cx, 0x110, 0x0062a1f2);
/* src1_ctl */
/* 0x1.60cd = 44100/32000 */
cx18_av_write4(cx, 0x8f8, 0x080160cd);
/* src3/4/6_ctl */
/* 0x1.7385 = 2 * (32000/44100) */
cx18_av_write4(cx, 0x900, 0x08017385);
cx18_av_write4(cx, 0x904, 0x08017385);
cx18_av_write4(cx, 0x90c, 0x08017385);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x24 */
cx18_av_write(cx, 0x127, 0x64);
/* AUD_COUNT = 0x61ff = 49 samples * 2 * 256 - 1 */
cx18_av_write4(cx, 0x12c, 0x112061ff);
/*
* EN_AV_LOCK = 0
* VID_COUNT = 0x1d4bf8 = 239999.000 * 8 =
* ((49 samples/44,100) * (13,500,000 * 8) * 2 - 1) * 8
*/
cx18_av_write4(cx, 0x128, 0xa01d4bf8);
break;
case 48000:
/*
* VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
* AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20
*/
cx18_av_write4(cx, 0x108, 0x200d040f);
/* VID_PLL Fraction = 0x2be2fe */
/* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
cx18_av_write4(cx, 0x10c, 0x002be2fe);
/* AUX_PLL Fraction = 0x176740c */
/* xtal * 0xd.bb3a060/0x20 = 48000 * 256: 393 MHz p-pd*/
cx18_av_write4(cx, 0x110, 0x0176740c);
/* src1_ctl */
/* 0x1.8000 = 48000/32000 */
cx18_av_write4(cx, 0x8f8, 0x08018000);
/* src3/4/6_ctl */
/* 0x1.5555 = 2 * (32000/48000) */
cx18_av_write4(cx, 0x900, 0x08015555);
cx18_av_write4(cx, 0x904, 0x08015555);
cx18_av_write4(cx, 0x90c, 0x08015555);
/* SA_MCLK_SEL=1, SA_MCLK_DIV=0x20 */
cx18_av_write(cx, 0x127, 0x60);
/* AUD_COUNT = 0x3fff = 4 samples * 16 * 256 - 1 */
cx18_av_write4(cx, 0x12c, 0x11203fff);
/*
* EN_AV_LOCK = 0
* VID_COUNT = 0x1193f8 = 143999.000 * 8 =
* ((4 samples/48,000) * (13,500,000 * 8) * 16 - 1) * 8
*/
cx18_av_write4(cx, 0x128, 0xa01193f8);
break;
}
}
state->audclk_freq = freq;
return 0;
}
void cx18_av_audio_set_path(struct cx18 *cx)
{
struct cx18_av_state *state = &cx->av_state;
u8 v;
/* stop microcontroller */
v = cx18_av_read(cx, 0x803) & ~0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
/* assert soft reset */
v = cx18_av_read(cx, 0x810) | 0x01;
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
/* Mute everything to prevent the PFFT! */
cx18_av_write(cx, 0x8d3, 0x1f);
if (state->aud_input <= CX18_AV_AUDIO_SERIAL2) {
/* Set Path1 to Serial Audio Input */
cx18_av_write4(cx, 0x8d0, 0x01011012);
/* The microcontroller should not be started for the
* non-tuner inputs: autodetection is specific for
* TV audio. */
} else {
/* Set Path1 to Analog Demod Main Channel */
cx18_av_write4(cx, 0x8d0, 0x1f063870);
}
set_audclk_freq(cx, state->audclk_freq);
/* deassert soft reset */
v = cx18_av_read(cx, 0x810) & ~0x01;
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
/* When the microcontroller detects the
* audio format, it will unmute the lines */
v = cx18_av_read(cx, 0x803) | 0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
}
}
static int get_volume(struct cx18 *cx)
{
/* Volume runs +18dB to -96dB in 1/2dB steps
* change to fit the msp3400 -114dB to +12dB range */
/* check PATH1_VOLUME */
int vol = 228 - cx18_av_read(cx, 0x8d4);
vol = (vol / 2) + 23;
return vol << 9;
}
static void set_volume(struct cx18 *cx, int volume)
{
/* First convert the volume to msp3400 values (0-127) */
int vol = volume >> 9;
/* now scale it up to cx18_av values
* -114dB to -96dB maps to 0
* this should be 19, but in my testing that was 4dB too loud */
if (vol <= 23)
vol = 0;
else
vol -= 23;
/* PATH1_VOLUME */
cx18_av_write(cx, 0x8d4, 228 - (vol * 2));
}
static int get_bass(struct cx18 *cx)
{
/* bass is 49 steps +12dB to -12dB */
/* check PATH1_EQ_BASS_VOL */
int bass = cx18_av_read(cx, 0x8d9) & 0x3f;
bass = (((48 - bass) * 0xffff) + 47) / 48;
return bass;
}
static void set_bass(struct cx18 *cx, int bass)
{
/* PATH1_EQ_BASS_VOL */
cx18_av_and_or(cx, 0x8d9, ~0x3f, 48 - (bass * 48 / 0xffff));
}
static int get_treble(struct cx18 *cx)
{
/* treble is 49 steps +12dB to -12dB */
/* check PATH1_EQ_TREBLE_VOL */
int treble = cx18_av_read(cx, 0x8db) & 0x3f;
treble = (((48 - treble) * 0xffff) + 47) / 48;
return treble;
}
static void set_treble(struct cx18 *cx, int treble)
{
/* PATH1_EQ_TREBLE_VOL */
cx18_av_and_or(cx, 0x8db, ~0x3f, 48 - (treble * 48 / 0xffff));
}
static int get_balance(struct cx18 *cx)
{
/* balance is 7 bit, 0 to -96dB */
/* check PATH1_BAL_LEVEL */
int balance = cx18_av_read(cx, 0x8d5) & 0x7f;
/* check PATH1_BAL_LEFT */
if ((cx18_av_read(cx, 0x8d5) & 0x80) == 0)
balance = 0x80 - balance;
else
balance = 0x80 + balance;
return balance << 8;
}
static void set_balance(struct cx18 *cx, int balance)
{
int bal = balance >> 8;
if (bal > 0x80) {
/* PATH1_BAL_LEFT */
cx18_av_and_or(cx, 0x8d5, 0x7f, 0x80);
/* PATH1_BAL_LEVEL */
cx18_av_and_or(cx, 0x8d5, ~0x7f, bal & 0x7f);
} else {
/* PATH1_BAL_LEFT */
cx18_av_and_or(cx, 0x8d5, 0x7f, 0x00);
/* PATH1_BAL_LEVEL */
cx18_av_and_or(cx, 0x8d5, ~0x7f, 0x80 - bal);
}
}
static int get_mute(struct cx18 *cx)
{
/* check SRC1_MUTE_EN */
return cx18_av_read(cx, 0x8d3) & 0x2 ? 1 : 0;
}
static void set_mute(struct cx18 *cx, int mute)
{
struct cx18_av_state *state = &cx->av_state;
u8 v;
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
/* Must turn off microcontroller in order to mute sound.
* Not sure if this is the best method, but it does work.
* If the microcontroller is running, then it will undo any
* changes to the mute register. */
v = cx18_av_read(cx, 0x803);
if (mute) {
/* disable microcontroller */
v &= ~0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
cx18_av_write(cx, 0x8d3, 0x1f);
} else {
/* enable microcontroller */
v |= 0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
}
} else {
/* SRC1_MUTE_EN */
cx18_av_and_or(cx, 0x8d3, ~0x2, mute ? 0x02 : 0x00);
}
}
int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
struct cx18_av_state *state = &cx->av_state;
int retval;
u8 v;
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
v = cx18_av_read(cx, 0x803) & ~0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
cx18_av_write(cx, 0x8d3, 0x1f);
}
v = cx18_av_read(cx, 0x810) | 0x1;
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
retval = set_audclk_freq(cx, freq);
v = cx18_av_read(cx, 0x810) & ~0x1;
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
v = cx18_av_read(cx, 0x803) | 0x10;
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
}
return retval;
}
int cx18_av_audio_g_ctrl(struct cx18 *cx, struct v4l2_control *ctrl)
{
switch (ctrl->id) {
case V4L2_CID_AUDIO_VOLUME:
ctrl->value = get_volume(cx);
break;
case V4L2_CID_AUDIO_BASS:
ctrl->value = get_bass(cx);
break;
case V4L2_CID_AUDIO_TREBLE:
ctrl->value = get_treble(cx);
break;
case V4L2_CID_AUDIO_BALANCE:
ctrl->value = get_balance(cx);
break;
case V4L2_CID_AUDIO_MUTE:
ctrl->value = get_mute(cx);
break;
default:
return -EINVAL;
}
return 0;
}
int cx18_av_audio_s_ctrl(struct cx18 *cx, struct v4l2_control *ctrl)
{
switch (ctrl->id) {
case V4L2_CID_AUDIO_VOLUME:
set_volume(cx, ctrl->value);
break;
case V4L2_CID_AUDIO_BASS:
set_bass(cx, ctrl->value);
break;
case V4L2_CID_AUDIO_TREBLE:
set_treble(cx, ctrl->value);
break;
case V4L2_CID_AUDIO_BALANCE:
set_balance(cx, ctrl->value);
break;
case V4L2_CID_AUDIO_MUTE:
set_mute(cx, ctrl->value);
break;
default:
return -EINVAL;
}
return 0;
}

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kernel/drivers/media/video/cx18/cx18-av-core.c Normal file
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/*
* cx18 ADEC header
*
* Derived from cx25840-core.h
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#ifndef _CX18_AV_CORE_H_
#define _CX18_AV_CORE_H_
#include <media/v4l2-device.h>
struct cx18;
enum cx18_av_video_input {
/* Composite video inputs In1-In8 */
CX18_AV_COMPOSITE1 = 1,
CX18_AV_COMPOSITE2,
CX18_AV_COMPOSITE3,
CX18_AV_COMPOSITE4,
CX18_AV_COMPOSITE5,
CX18_AV_COMPOSITE6,
CX18_AV_COMPOSITE7,
CX18_AV_COMPOSITE8,
/* S-Video inputs consist of one luma input (In1-In8) ORed with one
chroma input (In5-In8) */
CX18_AV_SVIDEO_LUMA1 = 0x10,
CX18_AV_SVIDEO_LUMA2 = 0x20,
CX18_AV_SVIDEO_LUMA3 = 0x30,
CX18_AV_SVIDEO_LUMA4 = 0x40,
CX18_AV_SVIDEO_LUMA5 = 0x50,
CX18_AV_SVIDEO_LUMA6 = 0x60,
CX18_AV_SVIDEO_LUMA7 = 0x70,
CX18_AV_SVIDEO_LUMA8 = 0x80,
CX18_AV_SVIDEO_CHROMA4 = 0x400,
CX18_AV_SVIDEO_CHROMA5 = 0x500,
CX18_AV_SVIDEO_CHROMA6 = 0x600,
CX18_AV_SVIDEO_CHROMA7 = 0x700,
CX18_AV_SVIDEO_CHROMA8 = 0x800,
/* S-Video aliases for common luma/chroma combinations */
CX18_AV_SVIDEO1 = 0x510,
CX18_AV_SVIDEO2 = 0x620,
CX18_AV_SVIDEO3 = 0x730,
CX18_AV_SVIDEO4 = 0x840,
};
enum cx18_av_audio_input {
/* Audio inputs: serial or In4-In8 */
CX18_AV_AUDIO_SERIAL1,
CX18_AV_AUDIO_SERIAL2,
CX18_AV_AUDIO4 = 4,
CX18_AV_AUDIO5,
CX18_AV_AUDIO6,
CX18_AV_AUDIO7,
CX18_AV_AUDIO8,
};
struct cx18_av_state {
struct v4l2_subdev sd;
int radio;
v4l2_std_id std;
enum cx18_av_video_input vid_input;
enum cx18_av_audio_input aud_input;
u32 audclk_freq;
int audmode;
int default_volume;
u32 id;
u32 rev;
int is_initialized;
/*
* The VBI slicer starts operating and counting lines, begining at
* slicer line count of 1, at D lines after the deassertion of VRESET.
* This staring field line, S, is 6 (& 319) or 10 (& 273) for 625 or 525
* line systems respectively. Sliced ancillary data captured on VBI
* slicer line M is inserted after the VBI slicer is done with line M,
* when VBI slicer line count is N = M+1. Thus when the VBI slicer
* reports a VBI slicer line number with ancillary data, the IDID0 byte
* indicates VBI slicer line N. The actual field line that the captured
* data comes from is
*
* L = M+(S+D-1) = N-1+(S+D-1) = N + (S+D-2).
*
* L is the line in the field, not frame, from which the VBI data came.
* N is the line reported by the slicer in the ancillary data.
* D is the slicer_line_delay value programmed into register 0x47f.
* S is 6 for 625 line systems or 10 for 525 line systems
* (S+D-2) is the slicer_line_offset used to convert slicer reported
* line counts to actual field lines.
*/
int slicer_line_delay;
int slicer_line_offset;
};
/* Registers */
#define CXADEC_CHIP_TYPE_TIGER 0x837
#define CXADEC_CHIP_TYPE_MAKO 0x843
#define CXADEC_HOST_REG1 0x000
#define CXADEC_HOST_REG2 0x001
#define CXADEC_CHIP_CTRL 0x100
#define CXADEC_AFE_CTRL 0x104
#define CXADEC_PLL_CTRL1 0x108
#define CXADEC_VID_PLL_FRAC 0x10C
#define CXADEC_AUX_PLL_FRAC 0x110
#define CXADEC_PIN_CTRL1 0x114
#define CXADEC_PIN_CTRL2 0x118
#define CXADEC_PIN_CFG1 0x11C
#define CXADEC_PIN_CFG2 0x120
#define CXADEC_PIN_CFG3 0x124
#define CXADEC_I2S_MCLK 0x127
#define CXADEC_AUD_LOCK1 0x128
#define CXADEC_AUD_LOCK2 0x12C
#define CXADEC_POWER_CTRL 0x130
#define CXADEC_AFE_DIAG_CTRL1 0x134
#define CXADEC_AFE_DIAG_CTRL2 0x138
#define CXADEC_AFE_DIAG_CTRL3 0x13C
#define CXADEC_PLL_DIAG_CTRL 0x140
#define CXADEC_TEST_CTRL1 0x144
#define CXADEC_TEST_CTRL2 0x148
#define CXADEC_BIST_STAT 0x14C
#define CXADEC_DLL1_DIAG_CTRL 0x158
#define CXADEC_DLL2_DIAG_CTRL 0x15C
/* IR registers */
#define CXADEC_IR_CTRL_REG 0x200
#define CXADEC_IR_TXCLK_REG 0x204
#define CXADEC_IR_RXCLK_REG 0x208
#define CXADEC_IR_CDUTY_REG 0x20C
#define CXADEC_IR_STAT_REG 0x210
#define CXADEC_IR_IRQEN_REG 0x214
#define CXADEC_IR_FILTER_REG 0x218
#define CXADEC_IR_FIFO_REG 0x21C
/* Video Registers */
#define CXADEC_MODE_CTRL 0x400
#define CXADEC_OUT_CTRL1 0x404
#define CXADEC_OUT_CTRL2 0x408
#define CXADEC_GEN_STAT 0x40C
#define CXADEC_INT_STAT_MASK 0x410
#define CXADEC_LUMA_CTRL 0x414
#define CXADEC_BRIGHTNESS_CTRL_BYTE 0x414
#define CXADEC_CONTRAST_CTRL_BYTE 0x415
#define CXADEC_LUMA_CTRL_BYTE_3 0x416
#define CXADEC_HSCALE_CTRL 0x418
#define CXADEC_VSCALE_CTRL 0x41C
#define CXADEC_CHROMA_CTRL 0x420
#define CXADEC_USAT_CTRL_BYTE 0x420
#define CXADEC_VSAT_CTRL_BYTE 0x421
#define CXADEC_HUE_CTRL_BYTE 0x422
#define CXADEC_VBI_LINE_CTRL1 0x424
#define CXADEC_VBI_LINE_CTRL2 0x428
#define CXADEC_VBI_LINE_CTRL3 0x42C
#define CXADEC_VBI_LINE_CTRL4 0x430
#define CXADEC_VBI_LINE_CTRL5 0x434
#define CXADEC_VBI_FC_CFG 0x438
#define CXADEC_VBI_MISC_CFG1 0x43C
#define CXADEC_VBI_MISC_CFG2 0x440
#define CXADEC_VBI_PAY1 0x444
#define CXADEC_VBI_PAY2 0x448
#define CXADEC_VBI_CUST1_CFG1 0x44C
#define CXADEC_VBI_CUST1_CFG2 0x450
#define CXADEC_VBI_CUST1_CFG3 0x454
#define CXADEC_VBI_CUST2_CFG1 0x458
#define CXADEC_VBI_CUST2_CFG2 0x45C
#define CXADEC_VBI_CUST2_CFG3 0x460
#define CXADEC_VBI_CUST3_CFG1 0x464
#define CXADEC_VBI_CUST3_CFG2 0x468
#define CXADEC_VBI_CUST3_CFG3 0x46C
#define CXADEC_HORIZ_TIM_CTRL 0x470
#define CXADEC_VERT_TIM_CTRL 0x474
#define CXADEC_SRC_COMB_CFG 0x478
#define CXADEC_CHROMA_VBIOFF_CFG 0x47C
#define CXADEC_FIELD_COUNT 0x480
#define CXADEC_MISC_TIM_CTRL 0x484
#define CXADEC_DFE_CTRL1 0x488
#define CXADEC_DFE_CTRL2 0x48C
#define CXADEC_DFE_CTRL3 0x490
#define CXADEC_PLL_CTRL2 0x494
#define CXADEC_HTL_CTRL 0x498
#define CXADEC_COMB_CTRL 0x49C
#define CXADEC_CRUSH_CTRL 0x4A0
#define CXADEC_SOFT_RST_CTRL 0x4A4
#define CXADEC_MV_DT_CTRL2 0x4A8
#define CXADEC_MV_DT_CTRL3 0x4AC
#define CXADEC_MISC_DIAG_CTRL 0x4B8
#define CXADEC_DL_CTL 0x800
#define CXADEC_DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */
#define CXADEC_DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */
#define CXADEC_DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */
#define CXADEC_DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */
#define CXADEC_STD_DET_STATUS 0x804
#define CXADEC_STD_DET_CTL 0x808
#define CXADEC_STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */
#define CXADEC_STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */
#define CXADEC_DW8051_INT 0x80C
#define CXADEC_GENERAL_CTL 0x810
#define CXADEC_AAGC_CTL 0x814
#define CXADEC_IF_SRC_CTL 0x818
#define CXADEC_ANLOG_DEMOD_CTL 0x81C
#define CXADEC_ROT_FREQ_CTL 0x820
#define CXADEC_FM1_CTL 0x824
#define CXADEC_PDF_CTL 0x828
#define CXADEC_DFT1_CTL1 0x82C
#define CXADEC_DFT1_CTL2 0x830
#define CXADEC_DFT_STATUS 0x834
#define CXADEC_DFT2_CTL1 0x838
#define CXADEC_DFT2_CTL2 0x83C
#define CXADEC_DFT2_STATUS 0x840
#define CXADEC_DFT3_CTL1 0x844
#define CXADEC_DFT3_CTL2 0x848
#define CXADEC_DFT3_STATUS 0x84C
#define CXADEC_DFT4_CTL1 0x850
#define CXADEC_DFT4_CTL2 0x854
#define CXADEC_DFT4_STATUS 0x858
#define CXADEC_AM_MTS_DET 0x85C
#define CXADEC_ANALOG_MUX_CTL 0x860
#define CXADEC_DIG_PLL_CTL1 0x864
#define CXADEC_DIG_PLL_CTL2 0x868
#define CXADEC_DIG_PLL_CTL3 0x86C
#define CXADEC_DIG_PLL_CTL4 0x870
#define CXADEC_DIG_PLL_CTL5 0x874
#define CXADEC_DEEMPH_GAIN_CTL 0x878
#define CXADEC_DEEMPH_COEF1 0x87C
#define CXADEC_DEEMPH_COEF2 0x880
#define CXADEC_DBX1_CTL1 0x884
#define CXADEC_DBX1_CTL2 0x888
#define CXADEC_DBX1_STATUS 0x88C
#define CXADEC_DBX2_CTL1 0x890
#define CXADEC_DBX2_CTL2 0x894
#define CXADEC_DBX2_STATUS 0x898
#define CXADEC_AM_FM_DIFF 0x89C
/* NICAM registers go here */
#define CXADEC_NICAM_STATUS 0x8C8
#define CXADEC_DEMATRIX_CTL 0x8CC
#define CXADEC_PATH1_CTL1 0x8D0
#define CXADEC_PATH1_VOL_CTL 0x8D4
#define CXADEC_PATH1_EQ_CTL 0x8D8
#define CXADEC_PATH1_SC_CTL 0x8DC
#define CXADEC_PATH2_CTL1 0x8E0
#define CXADEC_PATH2_VOL_CTL 0x8E4
#define CXADEC_PATH2_EQ_CTL 0x8E8
#define CXADEC_PATH2_SC_CTL 0x8EC
#define CXADEC_SRC_CTL 0x8F0
#define CXADEC_SRC_LF_COEF 0x8F4
#define CXADEC_SRC1_CTL 0x8F8
#define CXADEC_SRC2_CTL 0x8FC
#define CXADEC_SRC3_CTL 0x900
#define CXADEC_SRC4_CTL 0x904
#define CXADEC_SRC5_CTL 0x908
#define CXADEC_SRC6_CTL 0x90C
#define CXADEC_BASEBAND_OUT_SEL 0x910
#define CXADEC_I2S_IN_CTL 0x914
#define CXADEC_I2S_OUT_CTL 0x918
#define CXADEC_AC97_CTL 0x91C
#define CXADEC_QAM_PDF 0x920
#define CXADEC_QAM_CONST_DEC 0x924
#define CXADEC_QAM_ROTATOR_FREQ 0x948
/* Bit defintions / settings used in Mako Audio */
#define CXADEC_PREF_MODE_MONO_LANGA 0
#define CXADEC_PREF_MODE_MONO_LANGB 1
#define CXADEC_PREF_MODE_MONO_LANGC 2
#define CXADEC_PREF_MODE_FALLBACK 3
#define CXADEC_PREF_MODE_STEREO 4
#define CXADEC_PREF_MODE_DUAL_LANG_AC 5
#define CXADEC_PREF_MODE_DUAL_LANG_BC 6
#define CXADEC_PREF_MODE_DUAL_LANG_AB 7
#define CXADEC_DETECT_STEREO 1
#define CXADEC_DETECT_DUAL 2
#define CXADEC_DETECT_TRI 4
#define CXADEC_DETECT_SAP 0x10
#define CXADEC_DETECT_NO_SIGNAL 0xFF
#define CXADEC_SELECT_AUDIO_STANDARD_BG 0xF0 /* NICAM BG and A2 BG */
#define CXADEC_SELECT_AUDIO_STANDARD_DK1 0xF1 /* NICAM DK and A2 DK */
#define CXADEC_SELECT_AUDIO_STANDARD_DK2 0xF2
#define CXADEC_SELECT_AUDIO_STANDARD_DK3 0xF3
#define CXADEC_SELECT_AUDIO_STANDARD_I 0xF4 /* NICAM I and A1 */
#define CXADEC_SELECT_AUDIO_STANDARD_L 0xF5 /* NICAM L and System L AM */
#define CXADEC_SELECT_AUDIO_STANDARD_BTSC 0xF6
#define CXADEC_SELECT_AUDIO_STANDARD_EIAJ 0xF7
#define CXADEC_SELECT_AUDIO_STANDARD_A2_M 0xF8 /* A2 M */
#define CXADEC_SELECT_AUDIO_STANDARD_FM 0xF9 /* FM radio */
#define CXADEC_SELECT_AUDIO_STANDARD_AUTO 0xFF /* Auto detect */
static inline struct cx18_av_state *to_cx18_av_state(struct v4l2_subdev *sd)
{
return container_of(sd, struct cx18_av_state, sd);
}
/* ----------------------------------------------------------------------- */
/* cx18_av-core.c */
int cx18_av_write(struct cx18 *cx, u16 addr, u8 value);
int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value);
int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value);
int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask);
int cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval,
u32 mask);
u8 cx18_av_read(struct cx18 *cx, u16 addr);
u32 cx18_av_read4(struct cx18 *cx, u16 addr);
int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value);
int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value);
void cx18_av_std_setup(struct cx18 *cx);
int cx18_av_probe(struct cx18 *cx);
/* ----------------------------------------------------------------------- */
/* cx18_av-firmware.c */
int cx18_av_loadfw(struct cx18 *cx);
/* ----------------------------------------------------------------------- */
/* cx18_av-audio.c */
int cx18_av_audio_g_ctrl(struct cx18 *cx, struct v4l2_control *ctrl);
int cx18_av_audio_s_ctrl(struct cx18 *cx, struct v4l2_control *ctrl);
int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
void cx18_av_audio_set_path(struct cx18 *cx);
/* ----------------------------------------------------------------------- */
/* cx18_av-vbi.c */
int cx18_av_decode_vbi_line(struct v4l2_subdev *sd,
struct v4l2_decode_vbi_line *vbi);
int cx18_av_vbi_g_fmt(struct cx18 *cx, struct v4l2_format *fmt);
int cx18_av_vbi_s_fmt(struct cx18 *cx, struct v4l2_format *fmt);
#endif

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/*
* cx18 ADEC firmware functions
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include <linux/firmware.h>
#define CX18_AUDIO_ENABLE 0xc72014
#define CX18_AI1_MUX_MASK 0x30
#define CX18_AI1_MUX_I2S1 0x00
#define CX18_AI1_MUX_I2S2 0x10
#define CX18_AI1_MUX_843_I2S 0x20
#define CX18_AI1_MUX_INVALID 0x30
#define FWFILE "v4l-cx23418-dig.fw"
static int cx18_av_verifyfw(struct cx18 *cx, const struct firmware *fw)
{
struct v4l2_subdev *sd = &cx->av_state.sd;
int ret = 0;
const u8 *data;
u32 size;
int addr;
u32 expected, dl_control;
/* Ensure we put the 8051 in reset and enable firmware upload mode */
dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
do {
dl_control &= 0x00ffffff;
dl_control |= 0x0f000000;
cx18_av_write4_noretry(cx, CXADEC_DL_CTL, dl_control);
dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
} while ((dl_control & 0xff000000) != 0x0f000000);
/* Read and auto increment until at address 0x0000 */
while (dl_control & 0x3fff)
dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
data = fw->data;
size = fw->size;
for (addr = 0; addr < size; addr++) {
dl_control &= 0xffff3fff; /* ignore top 2 bits of address */
expected = 0x0f000000 | ((u32)data[addr] << 16) | addr;
if (expected != dl_control) {
CX18_ERR_DEV(sd, "verification of %s firmware load "
"failed: expected %#010x got %#010x\n",
FWFILE, expected, dl_control);
ret = -EIO;
break;
}
dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
}
if (ret == 0)
CX18_INFO_DEV(sd, "verified load of %s firmware (%d bytes)\n",
FWFILE, size);
return ret;
}
int cx18_av_loadfw(struct cx18 *cx)
{
struct v4l2_subdev *sd = &cx->av_state.sd;
const struct firmware *fw = NULL;
u32 size;
u32 u, v;
const u8 *ptr;
int i;
int retries1 = 0;
if (request_firmware(&fw, FWFILE, &cx->pci_dev->dev) != 0) {
CX18_ERR_DEV(sd, "unable to open firmware %s\n", FWFILE);
return -EINVAL;
}
/* The firmware load often has byte errors, so allow for several
retries, both at byte level and at the firmware load level. */
while (retries1 < 5) {
cx18_av_write4_expect(cx, CXADEC_CHIP_CTRL, 0x00010000,
0x00008430, 0xffffffff); /* cx25843 */
cx18_av_write_expect(cx, CXADEC_STD_DET_CTL, 0xf6, 0xf6, 0xff);
/* Reset the Mako core, Register is alias of CXADEC_CHIP_CTRL */
cx18_av_write4_expect(cx, 0x8100, 0x00010000,
0x00008430, 0xffffffff); /* cx25843 */
/* Put the 8051 in reset and enable firmware upload */
cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000);
ptr = fw->data;
size = fw->size;
for (i = 0; i < size; i++) {
u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16);
u32 value = 0;
int retries2;
int unrec_err = 0;
for (retries2 = 0; retries2 < CX18_MAX_MMIO_WR_RETRIES;
retries2++) {
cx18_av_write4_noretry(cx, CXADEC_DL_CTL,
dl_control);
udelay(10);
value = cx18_av_read4(cx, CXADEC_DL_CTL);
if (value == dl_control)
break;
/* Check if we can correct the byte by changing
the address. We can only write the lower
address byte of the address. */
if ((value & 0x3F00) != (dl_control & 0x3F00)) {
unrec_err = 1;
break;
}
}
if (unrec_err || retries2 >= CX18_MAX_MMIO_WR_RETRIES)
break;
}
if (i == size)
break;
retries1++;
}
if (retries1 >= 5) {
CX18_ERR_DEV(sd, "unable to load firmware %s\n", FWFILE);
release_firmware(fw);
return -EIO;
}
cx18_av_write4_expect(cx, CXADEC_DL_CTL,
0x03000000 | fw->size, 0x03000000, 0x13000000);
CX18_INFO_DEV(sd, "loaded %s firmware (%d bytes)\n", FWFILE, size);
if (cx18_av_verifyfw(cx, fw) == 0)
cx18_av_write4_expect(cx, CXADEC_DL_CTL,
0x13000000 | fw->size, 0x13000000, 0x13000000);
/* Output to the 416 */
cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x78000);
/* Audio input control 1 set to Sony mode */
/* Audio output input 2 is 0 for slave operation input */
/* 0xC4000914[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
/* 0xC4000914[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
after WS transition for first bit of audio word. */
cx18_av_write4(cx, CXADEC_I2S_IN_CTL, 0x000000A0);
/* Audio output control 1 is set to Sony mode */
/* Audio output control 2 is set to 1 for master mode */
/* 0xC4000918[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
/* 0xC4000918[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
after WS transition for first bit of audio word. */
/* 0xC4000918[8]: 0 = slave operation, 1 = master (SCK_OUT and WS_OUT
are generated) */
cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0);
/* set alt I2s master clock to /0x16 and enable alt divider i2s
passthrough */
cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687);
cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6,
0x3F00FFFF);
/* CxDevWrReg(CXADEC_STD_DET_CTL, 0x000000FF); */
/* Set bit 0 in register 0x9CC to signify that this is MiniMe. */
/* Register 0x09CC is defined by the Merlin firmware, and doesn't
have a name in the spec. */
cx18_av_write4(cx, 0x09CC, 1);
v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
/* If bit 11 is 1, clear bit 10 */
if (v & 0x800)
cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE,
0, 0x400);
/* Toggle the AI1 MUX */
v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
u = v & CX18_AI1_MUX_MASK;
v &= ~CX18_AI1_MUX_MASK;
if (u == CX18_AI1_MUX_843_I2S || u == CX18_AI1_MUX_INVALID) {
/* Switch to I2S1 */
v |= CX18_AI1_MUX_I2S1;
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
v, CX18_AI1_MUX_MASK);
/* Switch back to the A/V decoder core I2S output */
v = (v & ~CX18_AI1_MUX_MASK) | CX18_AI1_MUX_843_I2S;
} else {
/* Switch to the A/V decoder core I2S output */
v |= CX18_AI1_MUX_843_I2S;
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
v, CX18_AI1_MUX_MASK);
/* Switch back to I2S1 or I2S2 */
v = (v & ~CX18_AI1_MUX_MASK) | u;
}
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
v, CX18_AI1_MUX_MASK);
/* Enable WW auto audio standard detection */
v = cx18_av_read4(cx, CXADEC_STD_DET_CTL);
v |= 0xFF; /* Auto by default */
v |= 0x400; /* Stereo by default */
v |= 0x14000000;
cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, v, v, 0x3F00FFFF);
release_firmware(fw);
return 0;
}

317
kernel/drivers/media/video/cx18/cx18-av-vbi.c Normal file
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/*
* cx18 ADEC VBI functions
*
* Derived from cx25840-vbi.c
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include "cx18-driver.h"
/*
* For sliced VBI output, we set up to use VIP-1.1, 8-bit mode,
* NN counts 1 byte Dwords, an IDID with the VBI line # in it.
* Thus, according to the VIP-2 Spec, our VBI ancillary data lines
* (should!) look like:
* 4 byte EAV code: 0xff 0x00 0x00 0xRP
* unknown number of possible idle bytes
* 3 byte Anc data preamble: 0x00 0xff 0xff
* 1 byte data identifier: ne010iii (parity bits, 010, DID bits)
* 1 byte secondary data id: nessssss (parity bits, SDID bits)
* 1 byte data word count: necccccc (parity bits, NN Dword count)
* 2 byte Internal DID: VBI-line-# 0x80
* NN data bytes
* 1 byte checksum
* Fill bytes needed to fil out to 4*NN bytes of payload
*
* The RP codes for EAVs when in VIP-1.1 mode, not in raw mode, &
* in the vertical blanking interval are:
* 0xb0 (Task 0 VerticalBlank HorizontalBlank 0 0 0 0)
* 0xf0 (Task EvenField VerticalBlank HorizontalBlank 0 0 0 0)
*
* Since the V bit is only allowed to toggle in the EAV RP code, just
* before the first active region line and for active lines, they are:
* 0x90 (Task 0 0 HorizontalBlank 0 0 0 0)
* 0xd0 (Task EvenField 0 HorizontalBlank 0 0 0 0)
*
* The user application DID bytes we care about are:
* 0x91 (1 0 010 0 !ActiveLine AncDataPresent)
* 0x55 (0 1 010 2ndField !ActiveLine AncDataPresent)
*
*/
static const u8 sliced_vbi_did[2] = { 0x91, 0x55 };
struct vbi_anc_data {
/* u8 eav[4]; */
/* u8 idle[]; Variable number of idle bytes */
u8 preamble[3];
u8 did;
u8 sdid;
u8 data_count;
u8 idid[2];
u8 payload[1]; /* data_count of payload */
/* u8 checksum; */
/* u8 fill[]; Variable number of fill bytes */
};
static int odd_parity(u8 c)
{
c ^= (c >> 4);
c ^= (c >> 2);
c ^= (c >> 1);
return c & 1;
}
static int decode_vps(u8 *dst, u8 *p)
{
static const u8 biphase_tbl[] = {
0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
};
u8 c, err = 0;
int i;
for (i = 0; i < 2 * 13; i += 2) {
err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
c = (biphase_tbl[p[i + 1]] & 0xf) |
((biphase_tbl[p[i]] & 0xf) << 4);
dst[i / 2] = c;
}
return err & 0xf0;
}
int cx18_av_vbi_g_fmt(struct cx18 *cx, struct v4l2_format *fmt)
{
struct cx18_av_state *state = &cx->av_state;
struct v4l2_sliced_vbi_format *svbi;
static const u16 lcr2vbi[] = {
0, V4L2_SLICED_TELETEXT_B, 0, /* 1 */
0, V4L2_SLICED_WSS_625, 0, /* 4 */
V4L2_SLICED_CAPTION_525, /* 6 */
0, 0, V4L2_SLICED_VPS, 0, 0, /* 9 */
0, 0, 0, 0
};
int is_pal = !(state->std & V4L2_STD_525_60);
int i;
if (fmt->type != V4L2_BUF_TYPE_SLICED_VBI_CAPTURE)
return -EINVAL;
svbi = &fmt->fmt.sliced;
memset(svbi, 0, sizeof(*svbi));
/* we're done if raw VBI is active */
if ((cx18_av_read(cx, 0x404) & 0x10) == 0)
return 0;
if (is_pal) {
for (i = 7; i <= 23; i++) {
u8 v = cx18_av_read(cx, 0x424 + i - 7);
svbi->service_lines[0][i] = lcr2vbi[v >> 4];
svbi->service_lines[1][i] = lcr2vbi[v & 0xf];
svbi->service_set |= svbi->service_lines[0][i] |
svbi->service_lines[1][i];
}
} else {
for (i = 10; i <= 21; i++) {
u8 v = cx18_av_read(cx, 0x424 + i - 10);
svbi->service_lines[0][i] = lcr2vbi[v >> 4];
svbi->service_lines[1][i] = lcr2vbi[v & 0xf];
svbi->service_set |= svbi->service_lines[0][i] |
svbi->service_lines[1][i];
}
}
return 0;
}
int cx18_av_vbi_s_fmt(struct cx18 *cx, struct v4l2_format *fmt)
{
struct cx18_av_state *state = &cx->av_state;
struct v4l2_sliced_vbi_format *svbi;
int is_pal = !(state->std & V4L2_STD_525_60);
int i, x;
u8 lcr[24];
if (fmt->type != V4L2_BUF_TYPE_SLICED_VBI_CAPTURE &&
fmt->type != V4L2_BUF_TYPE_VBI_CAPTURE)
return -EINVAL;
svbi = &fmt->fmt.sliced;
if (fmt->type == V4L2_BUF_TYPE_VBI_CAPTURE) {
/* raw VBI */
memset(svbi, 0, sizeof(*svbi));
/* Setup standard */
cx18_av_std_setup(cx);
/* VBI Offset */
cx18_av_write(cx, 0x47f, state->slicer_line_delay);
cx18_av_write(cx, 0x404, 0x2e);
return 0;
}
for (x = 0; x <= 23; x++)
lcr[x] = 0x00;
/* Setup standard */
cx18_av_std_setup(cx);
/* Sliced VBI */
cx18_av_write(cx, 0x404, 0x32); /* Ancillary data */
cx18_av_write(cx, 0x406, 0x13);
cx18_av_write(cx, 0x47f, state->slicer_line_delay);
/* Force impossible lines to 0 */
if (is_pal) {
for (i = 0; i <= 6; i++)
svbi->service_lines[0][i] =
svbi->service_lines[1][i] = 0;
} else {
for (i = 0; i <= 9; i++)
svbi->service_lines[0][i] =
svbi->service_lines[1][i] = 0;
for (i = 22; i <= 23; i++)
svbi->service_lines[0][i] =
svbi->service_lines[1][i] = 0;
}
/* Build register values for requested service lines */
for (i = 7; i <= 23; i++) {
for (x = 0; x <= 1; x++) {
switch (svbi->service_lines[1-x][i]) {
case V4L2_SLICED_TELETEXT_B:
lcr[i] |= 1 << (4 * x);
break;
case V4L2_SLICED_WSS_625:
lcr[i] |= 4 << (4 * x);
break;
case V4L2_SLICED_CAPTION_525:
lcr[i] |= 6 << (4 * x);
break;
case V4L2_SLICED_VPS:
lcr[i] |= 9 << (4 * x);
break;
}
}
}
if (is_pal) {
for (x = 1, i = 0x424; i <= 0x434; i++, x++)
cx18_av_write(cx, i, lcr[6 + x]);
} else {
for (x = 1, i = 0x424; i <= 0x430; i++, x++)
cx18_av_write(cx, i, lcr[9 + x]);
for (i = 0x431; i <= 0x434; i++)
cx18_av_write(cx, i, 0);
}
cx18_av_write(cx, 0x43c, 0x16);
/* Should match vblank set in cx18_av_std_setup() */
cx18_av_write(cx, 0x474, is_pal ? 38 : 26);
return 0;
}
int cx18_av_decode_vbi_line(struct v4l2_subdev *sd,
struct v4l2_decode_vbi_line *vbi)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
struct cx18_av_state *state = &cx->av_state;
struct vbi_anc_data *anc = (struct vbi_anc_data *)vbi->p;
u8 *p;
int did, sdid, l, err = 0;
/*
* Check for the ancillary data header for sliced VBI
*/
if (anc->preamble[0] ||
anc->preamble[1] != 0xff || anc->preamble[2] != 0xff ||
(anc->did != sliced_vbi_did[0] &&
anc->did != sliced_vbi_did[1])) {
vbi->line = vbi->type = 0;
return 0;
}
did = anc->did;
sdid = anc->sdid & 0xf;
l = anc->idid[0] & 0x3f;
l += state->slicer_line_offset;
p = anc->payload;
/* Decode the SDID set by the slicer */
switch (sdid) {
case 1:
sdid = V4L2_SLICED_TELETEXT_B;
break;
case 4:
sdid = V4L2_SLICED_WSS_625;
break;
case 6:
sdid = V4L2_SLICED_CAPTION_525;
err = !odd_parity(p[0]) || !odd_parity(p[1]);
break;
case 9:
sdid = V4L2_SLICED_VPS;
if (decode_vps(p, p) != 0)
err = 1;
break;
default:
sdid = 0;
err = 1;
break;
}
vbi->type = err ? 0 : sdid;
vbi->line = err ? 0 : l;
vbi->is_second_field = err ? 0 : (did == sliced_vbi_did[1]);
vbi->p = p;
return 0;
}

518
kernel/drivers/media/video/cx18/cx18-cards.c Normal file
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/*
* cx18 functions to query card hardware
*
* Derived from ivtv-cards.c
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include "cx18-driver.h"
#include "cx18-cards.h"
#include "cx18-av-core.h"
#include "cx18-i2c.h"
#include <media/cs5345.h>
#define V4L2_STD_PAL_SECAM (V4L2_STD_PAL|V4L2_STD_SECAM)
/********************** card configuration *******************************/
/* usual i2c tuner addresses to probe */
static struct cx18_card_tuner_i2c cx18_i2c_std = {
.radio = { I2C_CLIENT_END },
.demod = { 0x43, I2C_CLIENT_END },
.tv = { 0x61, 0x60, I2C_CLIENT_END },
};
/* Please add new PCI IDs to: http://pci-ids.ucw.cz/iii
This keeps the PCI ID database up to date. Note that the entries
must be added under vendor 0x4444 (Conexant) as subsystem IDs.
New vendor IDs should still be added to the vendor ID list. */
/* Hauppauge HVR-1600 cards */
/* Note: for Hauppauge cards the tveeprom information is used instead
of PCI IDs */
static const struct cx18_card cx18_card_hvr1600_esmt = {
.type = CX18_CARD_HVR_1600_ESMT,
.name = "Hauppauge HVR-1600",
.comment = "Simultaneous Digital and Analog TV capture supported\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_CS5345,
.hw_all = CX18_HW_TVEEPROM | CX18_HW_418_AV | CX18_HW_TUNER |
CX18_HW_CS5345 | CX18_HW_DVB | CX18_HW_GPIO_RESET_CTRL |
CX18_HW_Z8F0811_IR_HAUP,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE7 },
{ CX18_CARD_INPUT_SVIDEO1, 1, CX18_AV_SVIDEO1 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE3 },
{ CX18_CARD_INPUT_SVIDEO2, 2, CX18_AV_SVIDEO2 },
{ CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE4 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO8, CS5345_IN_1 | CS5345_MCLK_1_5 },
{ CX18_CARD_INPUT_LINE_IN1,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_2 },
{ CX18_CARD_INPUT_LINE_IN2,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_3 },
},
.radio_input = { CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_4 },
.ddr = {
/* ESMT M13S128324A-5B memory */
.chip_config = 0x003,
.refresh = 0x30c,
.timing1 = 0x44220e82,
.timing2 = 0x08,
.tune_lane = 0,
.initial_emrs = 0,
},
.gpio_init.initial_value = 0x3001,
.gpio_init.direction = 0x3001,
.gpio_i2c_slave_reset = {
.active_lo_mask = 0x3001,
.msecs_asserted = 10,
.msecs_recovery = 40,
.ir_reset_mask = 0x0001,
},
.i2c = &cx18_i2c_std,
};
static const struct cx18_card cx18_card_hvr1600_samsung = {
.type = CX18_CARD_HVR_1600_SAMSUNG,
.name = "Hauppauge HVR-1600 (Preproduction)",
.comment = "Simultaneous Digital and Analog TV capture supported\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_CS5345,
.hw_all = CX18_HW_TVEEPROM | CX18_HW_418_AV | CX18_HW_TUNER |
CX18_HW_CS5345 | CX18_HW_DVB | CX18_HW_GPIO_RESET_CTRL |
CX18_HW_Z8F0811_IR_HAUP,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE7 },
{ CX18_CARD_INPUT_SVIDEO1, 1, CX18_AV_SVIDEO1 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE3 },
{ CX18_CARD_INPUT_SVIDEO2, 2, CX18_AV_SVIDEO2 },
{ CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE4 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO8, CS5345_IN_1 | CS5345_MCLK_1_5 },
{ CX18_CARD_INPUT_LINE_IN1,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_2 },
{ CX18_CARD_INPUT_LINE_IN2,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_3 },
},
.radio_input = { CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO_SERIAL1, CS5345_IN_4 },
.ddr = {
/* Samsung K4D263238G-VC33 memory */
.chip_config = 0x003,
.refresh = 0x30c,
.timing1 = 0x23230b73,
.timing2 = 0x08,
.tune_lane = 0,
.initial_emrs = 2,
},
.gpio_init.initial_value = 0x3001,
.gpio_init.direction = 0x3001,
.gpio_i2c_slave_reset = {
.active_lo_mask = 0x3001,
.msecs_asserted = 10,
.msecs_recovery = 40,
.ir_reset_mask = 0x0001,
},
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
/* Compro VideoMate H900: note that this card is analog only! */
static const struct cx18_card_pci_info cx18_pci_h900[] = {
{ PCI_DEVICE_ID_CX23418, CX18_PCI_ID_COMPRO, 0xe100 },
{ 0, 0, 0 }
};
static const struct cx18_card cx18_card_h900 = {
.type = CX18_CARD_COMPRO_H900,
.name = "Compro VideoMate H900",
.comment = "Analog TV capture supported\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_all = CX18_HW_418_AV | CX18_HW_TUNER | CX18_HW_GPIO_RESET_CTRL,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE2 },
{ CX18_CARD_INPUT_SVIDEO1, 1,
CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE1 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO5, 0 },
{ CX18_CARD_INPUT_LINE_IN1,
CX18_AV_AUDIO_SERIAL1, 0 },
},
.radio_input = { CX18_CARD_INPUT_AUD_TUNER,
CX18_AV_AUDIO_SERIAL1, 0 },
.tuners = {
{ .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
},
.ddr = {
/* EtronTech EM6A9160TS-5G memory */
.chip_config = 0x50003,
.refresh = 0x753,
.timing1 = 0x24330e84,
.timing2 = 0x1f,
.tune_lane = 0,
.initial_emrs = 0,
},
.xceive_pin = 15,
.pci_list = cx18_pci_h900,
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
/* Yuan MPC718: not working at the moment! */
static const struct cx18_card_pci_info cx18_pci_mpc718[] = {
{ PCI_DEVICE_ID_CX23418, CX18_PCI_ID_YUAN, 0x0718 },
{ 0, 0, 0 }
};
static const struct cx18_card cx18_card_mpc718 = {
.type = CX18_CARD_YUAN_MPC718,
.name = "Yuan MPC718 MiniPCI DVB-T/Analog",
.comment = "Experimenters needed for device to work well.\n"
"\tTo help, mail the ivtv-devel list (www.ivtvdriver.org).\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_GPIO_MUX,
.hw_all = CX18_HW_TVEEPROM | CX18_HW_418_AV | CX18_HW_TUNER |
CX18_HW_GPIO_MUX | CX18_HW_DVB | CX18_HW_GPIO_RESET_CTRL,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE2 },
{ CX18_CARD_INPUT_SVIDEO1, 1,
CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE1 },
{ CX18_CARD_INPUT_SVIDEO2, 2,
CX18_AV_SVIDEO_LUMA7 | CX18_AV_SVIDEO_CHROMA8 },
{ CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE6 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 0 },
{ CX18_CARD_INPUT_LINE_IN1, CX18_AV_AUDIO_SERIAL1, 1 },
{ CX18_CARD_INPUT_LINE_IN2, CX18_AV_AUDIO_SERIAL2, 1 },
},
.tuners = {
/* XC3028 tuner */
{ .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
},
/* FIXME - the FM radio is just a guess and driver doesn't use SIF */
.radio_input = { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 2 },
.ddr = {
/* Hynix HY5DU283222B DDR RAM */
.chip_config = 0x303,
.refresh = 0x3bd,
.timing1 = 0x36320966,
.timing2 = 0x1f,
.tune_lane = 0,
.initial_emrs = 2,
},
.gpio_init.initial_value = 0x1,
.gpio_init.direction = 0x3,
/* FIXME - these GPIO's are just guesses */
.gpio_audio_input = { .mask = 0x3,
.tuner = 0x1,
.linein = 0x3,
.radio = 0x1 },
.xceive_pin = 0,
.pci_list = cx18_pci_mpc718,
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
/* Conexant Raptor PAL/SECAM: note that this card is analog only! */
static const struct cx18_card_pci_info cx18_pci_cnxt_raptor_pal[] = {
{ PCI_DEVICE_ID_CX23418, CX18_PCI_ID_CONEXANT, 0x0009 },
{ 0, 0, 0 }
};
static const struct cx18_card cx18_card_cnxt_raptor_pal = {
.type = CX18_CARD_CNXT_RAPTOR_PAL,
.name = "Conexant Raptor PAL/SECAM",
.comment = "Analog TV capture supported\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_GPIO_MUX,
.hw_all = CX18_HW_418_AV | CX18_HW_TUNER | CX18_HW_GPIO_MUX,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE2 },
{ CX18_CARD_INPUT_SVIDEO1, 1,
CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE1 },
{ CX18_CARD_INPUT_SVIDEO2, 2,
CX18_AV_SVIDEO_LUMA7 | CX18_AV_SVIDEO_CHROMA8 },
{ CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE6 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 0 },
{ CX18_CARD_INPUT_LINE_IN1, CX18_AV_AUDIO_SERIAL1, 1 },
{ CX18_CARD_INPUT_LINE_IN2, CX18_AV_AUDIO_SERIAL2, 1 },
},
.tuners = {
{ .std = V4L2_STD_PAL_SECAM, .tuner = TUNER_PHILIPS_FM1216ME_MK3 },
},
.radio_input = { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO_SERIAL1, 2 },
.ddr = {
/* MT 46V16M16 memory */
.chip_config = 0x50306,
.refresh = 0x753,
.timing1 = 0x33220953,
.timing2 = 0x09,
.tune_lane = 0,
.initial_emrs = 0,
},
.gpio_init.initial_value = 0x1002,
.gpio_init.direction = 0xf002,
.gpio_audio_input = { .mask = 0xf002,
.tuner = 0x1002, /* LED D1 Tuner AF */
.linein = 0x2000, /* LED D2 Line In 1 */
.radio = 0x4002 }, /* LED D3 Tuner AF */
.pci_list = cx18_pci_cnxt_raptor_pal,
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
/* Toshiba Qosmio laptop internal DVB-T/Analog Hybrid Tuner */
static const struct cx18_card_pci_info cx18_pci_toshiba_qosmio_dvbt[] = {
{ PCI_DEVICE_ID_CX23418, CX18_PCI_ID_TOSHIBA, 0x0110 },
{ 0, 0, 0 }
};
static const struct cx18_card cx18_card_toshiba_qosmio_dvbt = {
.type = CX18_CARD_TOSHIBA_QOSMIO_DVBT,
.name = "Toshiba Qosmio DVB-T/Analog",
.comment = "Experimenters and photos needed for device to work well.\n"
"\tTo help, mail the ivtv-devel list (www.ivtvdriver.org).\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_all = CX18_HW_418_AV | CX18_HW_TUNER | CX18_HW_GPIO_RESET_CTRL,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE6 },
{ CX18_CARD_INPUT_SVIDEO1, 1,
CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE1 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 0 },
{ CX18_CARD_INPUT_LINE_IN1, CX18_AV_AUDIO_SERIAL1, 1 },
},
.tuners = {
{ .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
},
.ddr = {
.chip_config = 0x202,
.refresh = 0x3bb,
.timing1 = 0x33320a63,
.timing2 = 0x0a,
.tune_lane = 0,
.initial_emrs = 0x42,
},
.xceive_pin = 15,
.pci_list = cx18_pci_toshiba_qosmio_dvbt,
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
/* Leadtek WinFast PVR2100 */
static const struct cx18_card_pci_info cx18_pci_leadtek_pvr2100[] = {
{ PCI_DEVICE_ID_CX23418, CX18_PCI_ID_LEADTEK, 0x6f27 }, /* PVR2100 */
{ 0, 0, 0 }
};
static const struct cx18_card cx18_card_leadtek_pvr2100 = {
.type = CX18_CARD_LEADTEK_PVR2100,
.name = "Leadtek WinFast PVR2100",
.comment = "Experimenters and photos needed for device to work well.\n"
"\tTo help, mail the ivtv-devel list (www.ivtvdriver.org).\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_GPIO_MUX,
.hw_all = CX18_HW_418_AV | CX18_HW_TUNER | CX18_HW_GPIO_MUX |
CX18_HW_GPIO_RESET_CTRL,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE2 },
{ CX18_CARD_INPUT_SVIDEO1, 1,
CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE7 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 0 },
{ CX18_CARD_INPUT_LINE_IN1, CX18_AV_AUDIO_SERIAL1, 1 },
},
.tuners = {
/* XC2028 tuner */
{ .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
},
.radio_input = { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 2 },
.ddr = {
/* Pointer to proper DDR config values provided by Terry Wu */
.chip_config = 0x303,
.refresh = 0x3bb,
.timing1 = 0x24220e83,
.timing2 = 0x1f,
.tune_lane = 0,
.initial_emrs = 0x2,
},
.gpio_init.initial_value = 0x6,
.gpio_init.direction = 0x7,
.gpio_audio_input = { .mask = 0x7,
.tuner = 0x6, .linein = 0x2, .radio = 0x2 },
.xceive_pin = 15,
.pci_list = cx18_pci_leadtek_pvr2100,
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
/* Leadtek WinFast DVR3100 H */
static const struct cx18_card_pci_info cx18_pci_leadtek_dvr3100h[] = {
{ PCI_DEVICE_ID_CX23418, CX18_PCI_ID_LEADTEK, 0x6690 }, /* DVR3100 H */
{ 0, 0, 0 }
};
static const struct cx18_card cx18_card_leadtek_dvr3100h = {
.type = CX18_CARD_LEADTEK_DVR3100H,
.name = "Leadtek WinFast DVR3100 H",
.comment = "Simultaneous DVB-T and Analog capture supported,\n"
"\texcept when capturing Analog from the antenna input.\n",
.v4l2_capabilities = CX18_CAP_ENCODER,
.hw_audio_ctrl = CX18_HW_418_AV,
.hw_muxer = CX18_HW_GPIO_MUX,
.hw_all = CX18_HW_418_AV | CX18_HW_TUNER | CX18_HW_GPIO_MUX |
CX18_HW_DVB | CX18_HW_GPIO_RESET_CTRL,
.video_inputs = {
{ CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE2 },
{ CX18_CARD_INPUT_SVIDEO1, 1,
CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
{ CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE7 },
},
.audio_inputs = {
{ CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 0 },
{ CX18_CARD_INPUT_LINE_IN1, CX18_AV_AUDIO_SERIAL1, 1 },
},
.tuners = {
/* XC3028 tuner */
{ .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
},
.radio_input = { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 2 },
.ddr = {
/* Pointer to proper DDR config values provided by Terry Wu */
.chip_config = 0x303,
.refresh = 0x3bb,
.timing1 = 0x24220e83,
.timing2 = 0x1f,
.tune_lane = 0,
.initial_emrs = 0x2,
},
.gpio_init.initial_value = 0x6,
.gpio_init.direction = 0x7,
.gpio_audio_input = { .mask = 0x7,
.tuner = 0x6, .linein = 0x2, .radio = 0x2 },
.xceive_pin = 1,
.pci_list = cx18_pci_leadtek_dvr3100h,
.i2c = &cx18_i2c_std,
};
/* ------------------------------------------------------------------------- */
static const struct cx18_card *cx18_card_list[] = {
&cx18_card_hvr1600_esmt,
&cx18_card_hvr1600_samsung,
&cx18_card_h900,
&cx18_card_mpc718,
&cx18_card_cnxt_raptor_pal,
&cx18_card_toshiba_qosmio_dvbt,
&cx18_card_leadtek_pvr2100,
&cx18_card_leadtek_dvr3100h,
};
const struct cx18_card *cx18_get_card(u16 index)
{
if (index >= ARRAY_SIZE(cx18_card_list))
return NULL;
return cx18_card_list[index];
}
int cx18_get_input(struct cx18 *cx, u16 index, struct v4l2_input *input)
{
const struct cx18_card_video_input *card_input =
cx->card->video_inputs + index;
static const char * const input_strs[] = {
"Tuner 1",
"S-Video 1",
"S-Video 2",
"Composite 1",
"Composite 2",
"Composite 3"
};
memset(input, 0, sizeof(*input));
if (index >= cx->nof_inputs)
return -EINVAL;
input->index = index;
strlcpy(input->name, input_strs[card_input->video_type - 1],
sizeof(input->name));
input->type = (card_input->video_type == CX18_CARD_INPUT_VID_TUNER ?
V4L2_INPUT_TYPE_TUNER : V4L2_INPUT_TYPE_CAMERA);
input->audioset = (1 << cx->nof_audio_inputs) - 1;
input->std = (input->type == V4L2_INPUT_TYPE_TUNER) ?
cx->tuner_std : V4L2_STD_ALL;
return 0;
}
int cx18_get_audio_input(struct cx18 *cx, u16 index, struct v4l2_audio *audio)
{
const struct cx18_card_audio_input *aud_input =
cx->card->audio_inputs + index;
static const char * const input_strs[] = {
"Tuner 1",
"Line In 1",
"Line In 2"
};
memset(audio, 0, sizeof(*audio));
if (index >= cx->nof_audio_inputs)
return -EINVAL;
strlcpy(audio->name, input_strs[aud_input->audio_type - 1],
sizeof(audio->name));
audio->index = index;
audio->capability = V4L2_AUDCAP_STEREO;
return 0;
}

154
kernel/drivers/media/video/cx18/cx18-cards.h Normal file
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/*
* cx18 functions to query card hardware
*
* Derived from ivtv-cards.c
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* hardware flags */
#define CX18_HW_TUNER (1 << 0)
#define CX18_HW_TVEEPROM (1 << 1)
#define CX18_HW_CS5345 (1 << 2)
#define CX18_HW_DVB (1 << 3)
#define CX18_HW_418_AV (1 << 4)
#define CX18_HW_GPIO_MUX (1 << 5)
#define CX18_HW_GPIO_RESET_CTRL (1 << 6)
#define CX18_HW_Z8F0811_IR_TX_HAUP (1 << 7)
#define CX18_HW_Z8F0811_IR_RX_HAUP (1 << 8)
#define CX18_HW_Z8F0811_IR_HAUP (CX18_HW_Z8F0811_IR_RX_HAUP | \
CX18_HW_Z8F0811_IR_TX_HAUP)
/* video inputs */
#define CX18_CARD_INPUT_VID_TUNER 1
#define CX18_CARD_INPUT_SVIDEO1 2
#define CX18_CARD_INPUT_SVIDEO2 3
#define CX18_CARD_INPUT_COMPOSITE1 4
#define CX18_CARD_INPUT_COMPOSITE2 5
#define CX18_CARD_INPUT_COMPOSITE3 6
/* audio inputs */
#define CX18_CARD_INPUT_AUD_TUNER 1
#define CX18_CARD_INPUT_LINE_IN1 2
#define CX18_CARD_INPUT_LINE_IN2 3
#define CX18_CARD_MAX_VIDEO_INPUTS 6
#define CX18_CARD_MAX_AUDIO_INPUTS 3
#define CX18_CARD_MAX_TUNERS 2
/* V4L2 capability aliases */
#define CX18_CAP_ENCODER (V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_TUNER | \
V4L2_CAP_AUDIO | V4L2_CAP_READWRITE | \
V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE)
struct cx18_card_video_input {
u8 video_type; /* video input type */
u8 audio_index; /* index in cx18_card_audio_input array */
u16 video_input; /* hardware video input */
};
struct cx18_card_audio_input {
u8 audio_type; /* audio input type */
u32 audio_input; /* hardware audio input */
u16 muxer_input; /* hardware muxer input for boards with a
multiplexer chip */
};
struct cx18_card_pci_info {
u16 device;
u16 subsystem_vendor;
u16 subsystem_device;
};
/* GPIO definitions */
/* The mask is the set of bits used by the operation */
struct cx18_gpio_init { /* set initial GPIO DIR and OUT values */
u32 direction; /* DIR setting. Leave to 0 if no init is needed */
u32 initial_value;
};
struct cx18_gpio_i2c_slave_reset {
u32 active_lo_mask; /* GPIO outputs that reset i2c chips when low */
u32 active_hi_mask; /* GPIO outputs that reset i2c chips when high */
int msecs_asserted; /* time period reset must remain asserted */
int msecs_recovery; /* time after deassert for chips to be ready */
u32 ir_reset_mask; /* GPIO to reset the Zilog Z8F0811 IR contoller */
};
struct cx18_gpio_audio_input { /* select tuner/line in input */
u32 mask; /* leave to 0 if not supported */
u32 tuner;
u32 linein;
u32 radio;
};
struct cx18_card_tuner {
v4l2_std_id std; /* standard for which the tuner is suitable */
int tuner; /* tuner ID (from tuner.h) */
};
struct cx18_card_tuner_i2c {
unsigned short radio[2];/* radio tuner i2c address to probe */
unsigned short demod[2];/* demodulator i2c address to probe */
unsigned short tv[4]; /* tv tuner i2c addresses to probe */
};
struct cx18_ddr { /* DDR config data */
u32 chip_config;
u32 refresh;
u32 timing1;
u32 timing2;
u32 tune_lane;
u32 initial_emrs;
};
/* for card information/parameters */
struct cx18_card {
int type;
char *name;
char *comment;
u32 v4l2_capabilities;
u32 hw_audio_ctrl; /* hardware used for the V4L2 controls (only
1 dev allowed currently) */
u32 hw_muxer; /* hardware used to multiplex audio input */
u32 hw_all; /* all hardware used by the board */
struct cx18_card_video_input video_inputs[CX18_CARD_MAX_VIDEO_INPUTS];
struct cx18_card_audio_input audio_inputs[CX18_CARD_MAX_AUDIO_INPUTS];
struct cx18_card_audio_input radio_input;
/* GPIO card-specific settings */
u8 xceive_pin; /* XCeive tuner GPIO reset pin */
struct cx18_gpio_init gpio_init;
struct cx18_gpio_i2c_slave_reset gpio_i2c_slave_reset;
struct cx18_gpio_audio_input gpio_audio_input;
struct cx18_card_tuner tuners[CX18_CARD_MAX_TUNERS];
struct cx18_card_tuner_i2c *i2c;
struct cx18_ddr ddr;
/* list of device and subsystem vendor/devices that
correspond to this card type. */
const struct cx18_card_pci_info *pci_list;
};
int cx18_get_input(struct cx18 *cx, u16 index, struct v4l2_input *input);
int cx18_get_audio_input(struct cx18 *cx, u16 index, struct v4l2_audio *input);
const struct cx18_card *cx18_get_card(u16 index);

350
kernel/drivers/media/video/cx18/cx18-controls.c Normal file
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/*
* cx18 ioctl control functions
*
* Derived from ivtv-controls.c
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include <linux/kernel.h>
#include "cx18-driver.h"
#include "cx18-cards.h"
#include "cx18-ioctl.h"
#include "cx18-audio.h"
#include "cx18-mailbox.h"
#include "cx18-controls.h"
/* Must be sorted from low to high control ID! */
static const u32 user_ctrls[] = {
V4L2_CID_USER_CLASS,
V4L2_CID_BRIGHTNESS,
V4L2_CID_CONTRAST,
V4L2_CID_SATURATION,
V4L2_CID_HUE,
V4L2_CID_AUDIO_VOLUME,
V4L2_CID_AUDIO_BALANCE,
V4L2_CID_AUDIO_BASS,
V4L2_CID_AUDIO_TREBLE,
V4L2_CID_AUDIO_MUTE,
V4L2_CID_AUDIO_LOUDNESS,
0
};
static const u32 *ctrl_classes[] = {
user_ctrls,
cx2341x_mpeg_ctrls,
NULL
};
int cx18_queryctrl(struct file *file, void *fh, struct v4l2_queryctrl *qctrl)
{
struct cx18 *cx = ((struct cx18_open_id *)fh)->cx;
const char *name;
qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
if (qctrl->id == 0)
return -EINVAL;
switch (qctrl->id) {
/* Standard V4L2 controls */
case V4L2_CID_USER_CLASS:
return v4l2_ctrl_query_fill(qctrl, 0, 0, 0, 0);
case V4L2_CID_BRIGHTNESS:
case V4L2_CID_HUE:
case V4L2_CID_SATURATION:
case V4L2_CID_CONTRAST:
if (v4l2_subdev_call(cx->sd_av, core, queryctrl, qctrl))
qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
return 0;
case V4L2_CID_AUDIO_VOLUME:
case V4L2_CID_AUDIO_MUTE:
case V4L2_CID_AUDIO_BALANCE:
case V4L2_CID_AUDIO_BASS:
case V4L2_CID_AUDIO_TREBLE:
case V4L2_CID_AUDIO_LOUDNESS:
if (v4l2_subdev_call(cx->sd_av, core, queryctrl, qctrl))
qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
return 0;
default:
if (cx2341x_ctrl_query(&cx->params, qctrl))
qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
return 0;
}
strncpy(qctrl->name, name, sizeof(qctrl->name) - 1);
qctrl->name[sizeof(qctrl->name) - 1] = 0;
return 0;
}
int cx18_querymenu(struct file *file, void *fh, struct v4l2_querymenu *qmenu)
{
struct cx18 *cx = ((struct cx18_open_id *)fh)->cx;
struct v4l2_queryctrl qctrl;
qctrl.id = qmenu->id;
cx18_queryctrl(file, fh, &qctrl);
return v4l2_ctrl_query_menu(qmenu, &qctrl,
cx2341x_ctrl_get_menu(&cx->params, qmenu->id));
}
static int cx18_try_ctrl(struct file *file, void *fh,
struct v4l2_ext_control *vctrl)
{
struct v4l2_queryctrl qctrl;
const char **menu_items = NULL;
int err;
qctrl.id = vctrl->id;
err = cx18_queryctrl(file, fh, &qctrl);
if (err)
return err;
if (qctrl.type == V4L2_CTRL_TYPE_MENU)
menu_items = v4l2_ctrl_get_menu(qctrl.id);
return v4l2_ctrl_check(vctrl, &qctrl, menu_items);
}
static int cx18_s_ctrl(struct cx18 *cx, struct v4l2_control *vctrl)
{
switch (vctrl->id) {
/* Standard V4L2 controls */
case V4L2_CID_BRIGHTNESS:
case V4L2_CID_HUE:
case V4L2_CID_SATURATION:
case V4L2_CID_CONTRAST:
return v4l2_subdev_call(cx->sd_av, core, s_ctrl, vctrl);
case V4L2_CID_AUDIO_VOLUME:
case V4L2_CID_AUDIO_MUTE:
case V4L2_CID_AUDIO_BALANCE:
case V4L2_CID_AUDIO_BASS:
case V4L2_CID_AUDIO_TREBLE:
case V4L2_CID_AUDIO_LOUDNESS:
return v4l2_subdev_call(cx->sd_av, core, s_ctrl, vctrl);
default:
CX18_DEBUG_IOCTL("invalid control 0x%x\n", vctrl->id);
return -EINVAL;
}
return 0;
}
static int cx18_g_ctrl(struct cx18 *cx, struct v4l2_control *vctrl)
{
switch (vctrl->id) {
/* Standard V4L2 controls */
case V4L2_CID_BRIGHTNESS:
case V4L2_CID_HUE:
case V4L2_CID_SATURATION:
case V4L2_CID_CONTRAST:
return v4l2_subdev_call(cx->sd_av, core, g_ctrl, vctrl);
case V4L2_CID_AUDIO_VOLUME:
case V4L2_CID_AUDIO_MUTE:
case V4L2_CID_AUDIO_BALANCE:
case V4L2_CID_AUDIO_BASS:
case V4L2_CID_AUDIO_TREBLE:
case V4L2_CID_AUDIO_LOUDNESS:
return v4l2_subdev_call(cx->sd_av, core, g_ctrl, vctrl);
default:
CX18_DEBUG_IOCTL("invalid control 0x%x\n", vctrl->id);
return -EINVAL;
}
return 0;
}
static int cx18_setup_vbi_fmt(struct cx18 *cx,
enum v4l2_mpeg_stream_vbi_fmt fmt,
enum v4l2_mpeg_stream_type type)
{
if (!(cx->v4l2_cap & V4L2_CAP_SLICED_VBI_CAPTURE))
return -EINVAL;
if (atomic_read(&cx->ana_capturing) > 0)
return -EBUSY;
if (fmt != V4L2_MPEG_STREAM_VBI_FMT_IVTV ||
!(type == V4L2_MPEG_STREAM_TYPE_MPEG2_PS ||
type == V4L2_MPEG_STREAM_TYPE_MPEG2_DVD ||
type == V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD)) {
/* Only IVTV fmt VBI insertion & only MPEG-2 PS type streams */
cx->vbi.insert_mpeg = V4L2_MPEG_STREAM_VBI_FMT_NONE;
CX18_DEBUG_INFO("disabled insertion of sliced VBI data into "
"the MPEG stream\n");
return 0;
}
/* Allocate sliced VBI buffers if needed. */
if (cx->vbi.sliced_mpeg_data[0] == NULL) {
int i;
for (i = 0; i < CX18_VBI_FRAMES; i++) {
cx->vbi.sliced_mpeg_data[i] =
kmalloc(CX18_SLICED_MPEG_DATA_BUFSZ, GFP_KERNEL);
if (cx->vbi.sliced_mpeg_data[i] == NULL) {
while (--i >= 0) {
kfree(cx->vbi.sliced_mpeg_data[i]);
cx->vbi.sliced_mpeg_data[i] = NULL;
}
cx->vbi.insert_mpeg =
V4L2_MPEG_STREAM_VBI_FMT_NONE;
CX18_WARN("Unable to allocate buffers for "
"sliced VBI data insertion\n");
return -ENOMEM;
}
}
}
cx->vbi.insert_mpeg = fmt;
CX18_DEBUG_INFO("enabled insertion of sliced VBI data into the MPEG PS,"
"when sliced VBI is enabled\n");
/*
* If our current settings have no lines set for capture, store a valid,
* default set of service lines to capture, in our current settings.
*/
if (cx18_get_service_set(cx->vbi.sliced_in) == 0) {
if (cx->is_60hz)
cx->vbi.sliced_in->service_set =
V4L2_SLICED_CAPTION_525;
else
cx->vbi.sliced_in->service_set = V4L2_SLICED_WSS_625;
cx18_expand_service_set(cx->vbi.sliced_in, cx->is_50hz);
}
return 0;
}
int cx18_g_ext_ctrls(struct file *file, void *fh, struct v4l2_ext_controls *c)
{
struct cx18 *cx = ((struct cx18_open_id *)fh)->cx;
struct v4l2_control ctrl;
if (c->ctrl_class == V4L2_CTRL_CLASS_USER) {
int i;
int err = 0;
for (i = 0; i < c->count; i++) {
ctrl.id = c->controls[i].id;
ctrl.value = c->controls[i].value;
err = cx18_g_ctrl(cx, &ctrl);
c->controls[i].value = ctrl.value;
if (err) {
c->error_idx = i;
break;
}
}
return err;
}
if (c->ctrl_class == V4L2_CTRL_CLASS_MPEG)
return cx2341x_ext_ctrls(&cx->params, 0, c, VIDIOC_G_EXT_CTRLS);
return -EINVAL;
}
int cx18_s_ext_ctrls(struct file *file, void *fh, struct v4l2_ext_controls *c)
{
struct cx18_open_id *id = fh;
struct cx18 *cx = id->cx;
int ret;
struct v4l2_control ctrl;
ret = v4l2_prio_check(&cx->prio, &id->prio);
if (ret)
return ret;
if (c->ctrl_class == V4L2_CTRL_CLASS_USER) {
int i;
int err = 0;
for (i = 0; i < c->count; i++) {
ctrl.id = c->controls[i].id;
ctrl.value = c->controls[i].value;
err = cx18_s_ctrl(cx, &ctrl);
c->controls[i].value = ctrl.value;
if (err) {
c->error_idx = i;
break;
}
}
return err;
}
if (c->ctrl_class == V4L2_CTRL_CLASS_MPEG) {
static u32 freqs[3] = { 44100, 48000, 32000 };
struct cx18_api_func_private priv;
struct cx2341x_mpeg_params p = cx->params;
int err = cx2341x_ext_ctrls(&p, atomic_read(&cx->ana_capturing),
c, VIDIOC_S_EXT_CTRLS);
unsigned int idx;
if (err)
return err;
if (p.video_encoding != cx->params.video_encoding) {
int is_mpeg1 = p.video_encoding ==
V4L2_MPEG_VIDEO_ENCODING_MPEG_1;
struct v4l2_format fmt;
/* fix videodecoder resolution */
fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
fmt.fmt.pix.width = cx->params.width
/ (is_mpeg1 ? 2 : 1);
fmt.fmt.pix.height = cx->params.height;
v4l2_subdev_call(cx->sd_av, video, s_fmt, &fmt);
}
priv.cx = cx;
priv.s = &cx->streams[id->type];
err = cx2341x_update(&priv, cx18_api_func, &cx->params, &p);
if (!err &&
(cx->params.stream_vbi_fmt != p.stream_vbi_fmt ||
cx->params.stream_type != p.stream_type))
err = cx18_setup_vbi_fmt(cx, p.stream_vbi_fmt,
p.stream_type);
cx->params = p;
cx->dualwatch_stereo_mode = p.audio_properties & 0x0300;
idx = p.audio_properties & 0x03;
/* The audio clock of the digitizer must match the codec sample
rate otherwise you get some very strange effects. */
if (idx < ARRAY_SIZE(freqs))
cx18_call_all(cx, audio, s_clock_freq, freqs[idx]);
return err;
}
return -EINVAL;
}
int cx18_try_ext_ctrls(struct file *file, void *fh, struct v4l2_ext_controls *c)
{
struct cx18 *cx = ((struct cx18_open_id *)fh)->cx;
if (c->ctrl_class == V4L2_CTRL_CLASS_USER) {
int i;
int err = 0;
for (i = 0; i < c->count; i++) {
err = cx18_try_ctrl(file, fh, &c->controls[i]);
if (err) {
c->error_idx = i;
break;
}
}
return err;
}
if (c->ctrl_class == V4L2_CTRL_CLASS_MPEG)
return cx2341x_ext_ctrls(&cx->params,
atomic_read(&cx->ana_capturing),
c, VIDIOC_TRY_EXT_CTRLS);
return -EINVAL;
}

29
kernel/drivers/media/video/cx18/cx18-controls.h Normal file
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@@ -0,0 +1,29 @@
/*
* cx18 ioctl control functions
*
* Derived from ivtv-controls.h
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
int cx18_queryctrl(struct file *file, void *fh, struct v4l2_queryctrl *a);
int cx18_g_ext_ctrls(struct file *file, void *fh, struct v4l2_ext_controls *a);
int cx18_s_ext_ctrls(struct file *file, void *fh, struct v4l2_ext_controls *a);
int cx18_try_ext_ctrls(struct file *file, void *fh,
struct v4l2_ext_controls *a);
int cx18_querymenu(struct file *file, void *fh, struct v4l2_querymenu *a);

1233
kernel/drivers/media/video/cx18/cx18-driver.c Normal file
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648
kernel/drivers/media/video/cx18/cx18-driver.h Normal file
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@@ -0,0 +1,648 @@
/*
* cx18 driver internal defines and structures
*
* Derived from ivtv-driver.h
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#ifndef CX18_DRIVER_H
#define CX18_DRIVER_H
#include <linux/version.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/fs.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/list.h>
#include <linux/unistd.h>
#include <linux/pagemap.h>
#include <linux/workqueue.h>
#include <linux/mutex.h>
#include <asm/byteorder.h>
#include <linux/dvb/video.h>
#include <linux/dvb/audio.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-device.h>
#include <media/tuner.h>
#include "cx18-mailbox.h"
#include "cx18-av-core.h"
#include "cx23418.h"
/* DVB */
#include "demux.h"
#include "dmxdev.h"
#include "dvb_demux.h"
#include "dvb_frontend.h"
#include "dvb_net.h"
#include "dvbdev.h"
#ifndef CONFIG_PCI
# error "This driver requires kernel PCI support."
#endif
#define CX18_MEM_OFFSET 0x00000000
#define CX18_MEM_SIZE 0x04000000
#define CX18_REG_OFFSET 0x02000000
/* Maximum cx18 driver instances. */
#define CX18_MAX_CARDS 32
/* Supported cards */
#define CX18_CARD_HVR_1600_ESMT 0 /* Hauppauge HVR 1600 (ESMT memory) */
#define CX18_CARD_HVR_1600_SAMSUNG 1 /* Hauppauge HVR 1600 (Samsung memory) */
#define CX18_CARD_COMPRO_H900 2 /* Compro VideoMate H900 */
#define CX18_CARD_YUAN_MPC718 3 /* Yuan MPC718 */
#define CX18_CARD_CNXT_RAPTOR_PAL 4 /* Conexant Raptor PAL */
#define CX18_CARD_TOSHIBA_QOSMIO_DVBT 5 /* Toshiba Qosmio Interal DVB-T/Analog*/
#define CX18_CARD_LEADTEK_PVR2100 6 /* Leadtek WinFast PVR2100 */
#define CX18_CARD_LEADTEK_DVR3100H 7 /* Leadtek WinFast DVR3100 H */
#define CX18_CARD_LAST 7
#define CX18_ENC_STREAM_TYPE_MPG 0
#define CX18_ENC_STREAM_TYPE_TS 1
#define CX18_ENC_STREAM_TYPE_YUV 2
#define CX18_ENC_STREAM_TYPE_VBI 3
#define CX18_ENC_STREAM_TYPE_PCM 4
#define CX18_ENC_STREAM_TYPE_IDX 5
#define CX18_ENC_STREAM_TYPE_RAD 6
#define CX18_MAX_STREAMS 7
/* system vendor and device IDs */
#define PCI_VENDOR_ID_CX 0x14f1
#define PCI_DEVICE_ID_CX23418 0x5b7a
/* subsystem vendor ID */
#define CX18_PCI_ID_HAUPPAUGE 0x0070
#define CX18_PCI_ID_COMPRO 0x185b
#define CX18_PCI_ID_YUAN 0x12ab
#define CX18_PCI_ID_CONEXANT 0x14f1
#define CX18_PCI_ID_TOSHIBA 0x1179
#define CX18_PCI_ID_LEADTEK 0x107D
/* ======================================================================== */
/* ========================== START USER SETTABLE DMA VARIABLES =========== */
/* ======================================================================== */
/* DMA Buffers, Default size in MB allocated */
#define CX18_DEFAULT_ENC_TS_BUFFERS 1
#define CX18_DEFAULT_ENC_MPG_BUFFERS 2
#define CX18_DEFAULT_ENC_IDX_BUFFERS 1
#define CX18_DEFAULT_ENC_YUV_BUFFERS 2
#define CX18_DEFAULT_ENC_VBI_BUFFERS 1
#define CX18_DEFAULT_ENC_PCM_BUFFERS 1
/* Maximum firmware DMA buffers per stream */
#define CX18_MAX_FW_MDLS_PER_STREAM 63
/* DMA buffer, default size in kB allocated */
#define CX18_DEFAULT_ENC_TS_BUFSIZE 32
#define CX18_DEFAULT_ENC_MPG_BUFSIZE 32
#define CX18_DEFAULT_ENC_IDX_BUFSIZE 32
#define CX18_DEFAULT_ENC_YUV_BUFSIZE 128
/* Default VBI bufsize based on standards supported by card tuner for now */
#define CX18_DEFAULT_ENC_PCM_BUFSIZE 4
/* i2c stuff */
#define I2C_CLIENTS_MAX 16
/* debugging */
/* Flag to turn on high volume debugging */
#define CX18_DBGFLG_WARN (1 << 0)
#define CX18_DBGFLG_INFO (1 << 1)
#define CX18_DBGFLG_API (1 << 2)
#define CX18_DBGFLG_DMA (1 << 3)
#define CX18_DBGFLG_IOCTL (1 << 4)
#define CX18_DBGFLG_FILE (1 << 5)
#define CX18_DBGFLG_I2C (1 << 6)
#define CX18_DBGFLG_IRQ (1 << 7)
/* Flag to turn on high volume debugging */
#define CX18_DBGFLG_HIGHVOL (1 << 8)
/* NOTE: extra space before comma in 'fmt , ## args' is required for
gcc-2.95, otherwise it won't compile. */
#define CX18_DEBUG(x, type, fmt, args...) \
do { \
if ((x) & cx18_debug) \
v4l2_info(&cx->v4l2_dev, " " type ": " fmt , ## args); \
} while (0)
#define CX18_DEBUG_WARN(fmt, args...) CX18_DEBUG(CX18_DBGFLG_WARN, "warning", fmt , ## args)
#define CX18_DEBUG_INFO(fmt, args...) CX18_DEBUG(CX18_DBGFLG_INFO, "info", fmt , ## args)
#define CX18_DEBUG_API(fmt, args...) CX18_DEBUG(CX18_DBGFLG_API, "api", fmt , ## args)
#define CX18_DEBUG_DMA(fmt, args...) CX18_DEBUG(CX18_DBGFLG_DMA, "dma", fmt , ## args)
#define CX18_DEBUG_IOCTL(fmt, args...) CX18_DEBUG(CX18_DBGFLG_IOCTL, "ioctl", fmt , ## args)
#define CX18_DEBUG_FILE(fmt, args...) CX18_DEBUG(CX18_DBGFLG_FILE, "file", fmt , ## args)
#define CX18_DEBUG_I2C(fmt, args...) CX18_DEBUG(CX18_DBGFLG_I2C, "i2c", fmt , ## args)
#define CX18_DEBUG_IRQ(fmt, args...) CX18_DEBUG(CX18_DBGFLG_IRQ, "irq", fmt , ## args)
#define CX18_DEBUG_HIGH_VOL(x, type, fmt, args...) \
do { \
if (((x) & cx18_debug) && (cx18_debug & CX18_DBGFLG_HIGHVOL)) \
v4l2_info(&cx->v4l2_dev, " " type ": " fmt , ## args); \
} while (0)
#define CX18_DEBUG_HI_WARN(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_WARN, "warning", fmt , ## args)
#define CX18_DEBUG_HI_INFO(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_INFO, "info", fmt , ## args)
#define CX18_DEBUG_HI_API(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_API, "api", fmt , ## args)
#define CX18_DEBUG_HI_DMA(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_DMA, "dma", fmt , ## args)
#define CX18_DEBUG_HI_IOCTL(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_IOCTL, "ioctl", fmt , ## args)
#define CX18_DEBUG_HI_FILE(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_FILE, "file", fmt , ## args)
#define CX18_DEBUG_HI_I2C(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_I2C, "i2c", fmt , ## args)
#define CX18_DEBUG_HI_IRQ(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_IRQ, "irq", fmt , ## args)
/* Standard kernel messages */
#define CX18_ERR(fmt, args...) v4l2_err(&cx->v4l2_dev, fmt , ## args)
#define CX18_WARN(fmt, args...) v4l2_warn(&cx->v4l2_dev, fmt , ## args)
#define CX18_INFO(fmt, args...) v4l2_info(&cx->v4l2_dev, fmt , ## args)
/* Messages for internal subdevs to use */
#define CX18_DEBUG_DEV(x, dev, type, fmt, args...) \
do { \
if ((x) & cx18_debug) \
v4l2_info(dev, " " type ": " fmt , ## args); \
} while (0)
#define CX18_DEBUG_WARN_DEV(dev, fmt, args...) \
CX18_DEBUG_DEV(CX18_DBGFLG_WARN, dev, "warning", fmt , ## args)
#define CX18_DEBUG_INFO_DEV(dev, fmt, args...) \
CX18_DEBUG_DEV(CX18_DBGFLG_INFO, dev, "info", fmt , ## args)
#define CX18_DEBUG_API_DEV(dev, fmt, args...) \
CX18_DEBUG_DEV(CX18_DBGFLG_API, dev, "api", fmt , ## args)
#define CX18_DEBUG_DMA_DEV(dev, fmt, args...) \
CX18_DEBUG_DEV(CX18_DBGFLG_DMA, dev, "dma", fmt , ## args)
#define CX18_DEBUG_IOCTL_DEV(dev, fmt, args...) \
CX18_DEBUG_DEV(CX18_DBGFLG_IOCTL, dev, "ioctl", fmt , ## args)
#define CX18_DEBUG_FILE_DEV(dev, fmt, args...) \
CX18_DEBUG_DEV(CX18_DBGFLG_FILE, dev, "file", fmt , ## args)
#define CX18_DEBUG_I2C_DEV(dev, fmt, args...) \
CX18_DEBUG_DEV(CX18_DBGFLG_I2C, dev, "i2c", fmt , ## args)
#define CX18_DEBUG_IRQ_DEV(dev, fmt, args...) \
CX18_DEBUG_DEV(CX18_DBGFLG_IRQ, dev, "irq", fmt , ## args)
#define CX18_DEBUG_HIGH_VOL_DEV(x, dev, type, fmt, args...) \
do { \
if (((x) & cx18_debug) && (cx18_debug & CX18_DBGFLG_HIGHVOL)) \
v4l2_info(dev, " " type ": " fmt , ## args); \
} while (0)
#define CX18_DEBUG_HI_WARN_DEV(dev, fmt, args...) \
CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_WARN, dev, "warning", fmt , ## args)
#define CX18_DEBUG_HI_INFO_DEV(dev, fmt, args...) \
CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_INFO, dev, "info", fmt , ## args)
#define CX18_DEBUG_HI_API_DEV(dev, fmt, args...) \
CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_API, dev, "api", fmt , ## args)
#define CX18_DEBUG_HI_DMA_DEV(dev, fmt, args...) \
CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_DMA, dev, "dma", fmt , ## args)
#define CX18_DEBUG_HI_IOCTL_DEV(dev, fmt, args...) \
CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_IOCTL, dev, "ioctl", fmt , ## args)
#define CX18_DEBUG_HI_FILE_DEV(dev, fmt, args...) \
CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_FILE, dev, "file", fmt , ## args)
#define CX18_DEBUG_HI_I2C_DEV(dev, fmt, args...) \
CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_I2C, dev, "i2c", fmt , ## args)
#define CX18_DEBUG_HI_IRQ_DEV(dev, fmt, args...) \
CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_IRQ, dev, "irq", fmt , ## args)
#define CX18_ERR_DEV(dev, fmt, args...) v4l2_err(dev, fmt , ## args)
#define CX18_WARN_DEV(dev, fmt, args...) v4l2_warn(dev, fmt , ## args)
#define CX18_INFO_DEV(dev, fmt, args...) v4l2_info(dev, fmt , ## args)
/* Values for CX18_API_DEC_PLAYBACK_SPEED mpeg_frame_type_mask parameter: */
#define MPEG_FRAME_TYPE_IFRAME 1
#define MPEG_FRAME_TYPE_IFRAME_PFRAME 3
#define MPEG_FRAME_TYPE_ALL 7
#define CX18_MAX_PGM_INDEX (400)
extern int cx18_debug;
struct cx18_options {
int megabytes[CX18_MAX_STREAMS]; /* Size in megabytes of each stream */
int cardtype; /* force card type on load */
int tuner; /* set tuner on load */
int radio; /* enable/disable radio */
};
/* per-buffer bit flags */
#define CX18_F_B_NEED_BUF_SWAP 0 /* this buffer should be byte swapped */
/* per-stream, s_flags */
#define CX18_F_S_CLAIMED 3 /* this stream is claimed */
#define CX18_F_S_STREAMING 4 /* the fw is decoding/encoding this stream */
#define CX18_F_S_INTERNAL_USE 5 /* this stream is used internally (sliced VBI processing) */
#define CX18_F_S_STREAMOFF 7 /* signal end of stream EOS */
#define CX18_F_S_APPL_IO 8 /* this stream is used read/written by an application */
#define CX18_F_S_STOPPING 9 /* telling the fw to stop capturing */
/* per-cx18, i_flags */
#define CX18_F_I_LOADED_FW 0 /* Loaded firmware 1st time */
#define CX18_F_I_EOS 4 /* End of encoder stream */
#define CX18_F_I_RADIO_USER 5 /* radio tuner is selected */
#define CX18_F_I_ENC_PAUSED 13 /* the encoder is paused */
#define CX18_F_I_INITED 21 /* set after first open */
#define CX18_F_I_FAILED 22 /* set if first open failed */
/* These are the VBI types as they appear in the embedded VBI private packets. */
#define CX18_SLICED_TYPE_TELETEXT_B (1)
#define CX18_SLICED_TYPE_CAPTION_525 (4)
#define CX18_SLICED_TYPE_WSS_625 (5)
#define CX18_SLICED_TYPE_VPS (7)
struct cx18_buffer {
struct list_head list;
dma_addr_t dma_handle;
u32 id;
unsigned long b_flags;
unsigned skipped;
char *buf;
u32 bytesused;
u32 readpos;
};
struct cx18_queue {
struct list_head list;
atomic_t buffers;
u32 bytesused;
spinlock_t lock;
};
struct cx18_dvb {
struct dmx_frontend hw_frontend;
struct dmx_frontend mem_frontend;
struct dmxdev dmxdev;
struct dvb_adapter dvb_adapter;
struct dvb_demux demux;
struct dvb_frontend *fe;
struct dvb_net dvbnet;
int enabled;
int feeding;
struct mutex feedlock;
};
struct cx18; /* forward reference */
struct cx18_scb; /* forward reference */
#define CX18_MAX_MDL_ACKS 2
#define CX18_MAX_IN_WORK_ORDERS (CX18_MAX_FW_MDLS_PER_STREAM + 7)
/* CPU_DE_RELEASE_MDL can burst CX18_MAX_FW_MDLS_PER_STREAM orders in a group */
#define CX18_F_EWO_MB_STALE_UPON_RECEIPT 0x1
#define CX18_F_EWO_MB_STALE_WHILE_PROC 0x2
#define CX18_F_EWO_MB_STALE \
(CX18_F_EWO_MB_STALE_UPON_RECEIPT | CX18_F_EWO_MB_STALE_WHILE_PROC)
struct cx18_in_work_order {
struct work_struct work;
atomic_t pending;
struct cx18 *cx;
unsigned long flags;
int rpu;
struct cx18_mailbox mb;
struct cx18_mdl_ack mdl_ack[CX18_MAX_MDL_ACKS];
char *str;
};
#define CX18_INVALID_TASK_HANDLE 0xffffffff
struct cx18_stream {
/* These first four fields are always set, even if the stream
is not actually created. */
struct video_device *video_dev; /* NULL when stream not created */
struct cx18 *cx; /* for ease of use */
const char *name; /* name of the stream */
int type; /* stream type */
u32 handle; /* task handle */
unsigned mdl_offset;
u32 id;
unsigned long s_flags; /* status flags, see above */
int dma; /* can be PCI_DMA_TODEVICE,
PCI_DMA_FROMDEVICE or
PCI_DMA_NONE */
wait_queue_head_t waitq;
/* Buffer Stats */
u32 buffers;
u32 buf_size;
/* Buffer Queues */
struct cx18_queue q_free; /* free buffers */
struct cx18_queue q_busy; /* busy buffers - in use by firmware */
struct cx18_queue q_full; /* full buffers - data for user apps */
struct work_struct out_work_order;
/* DVB / Digital Transport */
struct cx18_dvb dvb;
};
struct cx18_open_id {
u32 open_id;
int type;
enum v4l2_priority prio;
struct cx18 *cx;
};
/* forward declaration of struct defined in cx18-cards.h */
struct cx18_card;
/*
* A note about "sliced" VBI data as implemented in this driver:
*
* Currently we collect the sliced VBI in the form of Ancillary Data
* packets, inserted by the AV core decoder/digitizer/slicer in the
* horizontal blanking region of the VBI lines, in "raw" mode as far as
* the Encoder is concerned. We don't ever tell the Encoder itself
* to provide sliced VBI. (AV Core: sliced mode - Encoder: raw mode)
*
* We then process the ancillary data ourselves to send the sliced data
* to the user application directly or build up MPEG-2 private stream 1
* packets to splice into (only!) MPEG-2 PS streams for the user app.
*
* (That's how ivtv essentially does it.)
*
* The Encoder should be able to extract certain sliced VBI data for
* us and provide it in a separate stream or splice it into any type of
* MPEG PS or TS stream, but this isn't implemented yet.
*/
/*
* Number of "raw" VBI samples per horizontal line we tell the Encoder to
* grab from the decoder/digitizer/slicer output for raw or sliced VBI.
* It depends on the pixel clock and the horiz rate:
*
* (1/Fh)*(2*Fp) = Samples/line
* = 4 bytes EAV + Anc data in hblank + 4 bytes SAV + active samples
*
* Sliced VBI data is sent as ancillary data during horizontal blanking
* Raw VBI is sent as active video samples during vertcal blanking
*
* We use a BT.656 pxiel clock of 13.5 MHz and a BT.656 active line
* length of 720 pixels @ 4:2:2 sampling. Thus...
*
* For systems that use a 15.734 kHz horizontal rate, such as
* NTSC-M, PAL-M, PAL-60, and other 60 Hz/525 line systems, we have:
*
* (1/15.734 kHz) * 2 * 13.5 MHz = 1716 samples/line =
* 4 bytes SAV + 268 bytes anc data + 4 bytes SAV + 1440 active samples
*
* For systems that use a 15.625 kHz horizontal rate, such as
* PAL-B/G/H, PAL-I, SECAM-L and other 50 Hz/625 line systems, we have:
*
* (1/15.625 kHz) * 2 * 13.5 MHz = 1728 samples/line =
* 4 bytes SAV + 280 bytes anc data + 4 bytes SAV + 1440 active samples
*/
static const u32 vbi_active_samples = 1444; /* 4 byte SAV + 720 Y + 720 U/V */
static const u32 vbi_hblank_samples_60Hz = 272; /* 4 byte EAV + 268 anc/fill */
static const u32 vbi_hblank_samples_50Hz = 284; /* 4 byte EAV + 280 anc/fill */
#define CX18_VBI_FRAMES 32
struct vbi_info {
/* Current state of v4l2 VBI settings for this device */
struct v4l2_format in;
struct v4l2_sliced_vbi_format *sliced_in; /* pointer to in.fmt.sliced */
u32 count; /* Count of VBI data lines: 60 Hz: 12 or 50 Hz: 18 */
u32 start[2]; /* First VBI data line per field: 10 & 273 or 6 & 318 */
u32 frame; /* Count of VBI buffers/frames received from Encoder */
/*
* Vars for creation and insertion of MPEG Private Stream 1 packets
* of sliced VBI data into an MPEG PS
*/
/* Boolean: create and insert Private Stream 1 packets into the PS */
int insert_mpeg;
/*
* Buffer for the maximum of 2 * 18 * packet_size sliced VBI lines.
* Used in cx18-vbi.c only for collecting sliced data, and as a source
* during conversion of sliced VBI data into MPEG Priv Stream 1 packets.
* We don't need to save state here, but the array may have been a bit
* too big (2304 bytes) to alloc from the stack.
*/
struct v4l2_sliced_vbi_data sliced_data[36];
/*
* A ring buffer of driver-generated MPEG-2 PS
* Program Pack/Private Stream 1 packets for sliced VBI data insertion
* into the MPEG PS stream.
*
* In each sliced_mpeg_data[] buffer is:
* 16 byte MPEG-2 PS Program Pack Header
* 16 byte MPEG-2 Private Stream 1 PES Header
* 4 byte magic number: "itv0" or "ITV0"
* 4 byte first field line mask, if "itv0"
* 4 byte second field line mask, if "itv0"
* 36 lines, if "ITV0"; or <36 lines, if "itv0"; of sliced VBI data
*
* Each line in the payload is
* 1 byte line header derived from the SDID (WSS, CC, VPS, etc.)
* 42 bytes of line data
*
* That's a maximum 1552 bytes of payload in the Private Stream 1 packet
* which is the payload size a PVR-350 (CX23415) MPEG decoder will
* accept for VBI data. So, including the headers, it's a maximum 1584
* bytes total.
*/
#define CX18_SLICED_MPEG_DATA_MAXSZ 1584
/* copy_vbi_buf() needs 8 temp bytes on the end for the worst case */
#define CX18_SLICED_MPEG_DATA_BUFSZ (CX18_SLICED_MPEG_DATA_MAXSZ+8)
u8 *sliced_mpeg_data[CX18_VBI_FRAMES];
u32 sliced_mpeg_size[CX18_VBI_FRAMES];
/* Count of Program Pack/Program Stream 1 packets inserted into PS */
u32 inserted_frame;
/*
* A dummy driver stream transfer buffer with a copy of the next
* sliced_mpeg_data[] buffer for output to userland apps.
* Only used in cx18-fileops.c, but its state needs to persist at times.
*/
struct cx18_buffer sliced_mpeg_buf;
};
/* Per cx23418, per I2C bus private algo callback data */
struct cx18_i2c_algo_callback_data {
struct cx18 *cx;
int bus_index; /* 0 or 1 for the cx23418's 1st or 2nd I2C bus */
};
#define CX18_MAX_MMIO_WR_RETRIES 10
/* Struct to hold info about cx18 cards */
struct cx18 {
int instance;
struct pci_dev *pci_dev;
struct v4l2_device v4l2_dev;
struct v4l2_subdev *sd_av; /* A/V decoder/digitizer sub-device */
struct v4l2_subdev *sd_extmux; /* External multiplexer sub-dev */
const struct cx18_card *card; /* card information */
const char *card_name; /* full name of the card */
const struct cx18_card_tuner_i2c *card_i2c; /* i2c addresses to probe for tuner */
u8 is_50hz;
u8 is_60hz;
u8 nof_inputs; /* number of video inputs */
u8 nof_audio_inputs; /* number of audio inputs */
u16 buffer_id; /* buffer ID counter */
u32 v4l2_cap; /* V4L2 capabilities of card */
u32 hw_flags; /* Hardware description of the board */
unsigned mdl_offset;
struct cx18_scb __iomem *scb; /* pointer to SCB */
struct mutex epu2apu_mb_lock; /* protect driver to chip mailbox in SCB*/
struct mutex epu2cpu_mb_lock; /* protect driver to chip mailbox in SCB*/
struct cx18_av_state av_state;
/* codec settings */
struct cx2341x_mpeg_params params;
u32 filter_mode;
u32 temporal_strength;
u32 spatial_strength;
/* dualwatch */
unsigned long dualwatch_jiffies;
u32 dualwatch_stereo_mode;
struct mutex serialize_lock; /* mutex used to serialize open/close/start/stop/ioctl operations */
struct cx18_options options; /* User options */
int stream_buffers[CX18_MAX_STREAMS]; /* # of buffers for each stream */
int stream_buf_size[CX18_MAX_STREAMS]; /* Stream buffer size */
struct cx18_stream streams[CX18_MAX_STREAMS]; /* Stream data */
unsigned long i_flags; /* global cx18 flags */
atomic_t ana_capturing; /* count number of active analog capture streams */
atomic_t tot_capturing; /* total count number of active capture streams */
int search_pack_header;
int open_id; /* incremented each time an open occurs, used as
unique ID. Starts at 1, so 0 can be used as
uninitialized value in the stream->id. */
u32 base_addr;
struct v4l2_prio_state prio;
u8 card_rev;
void __iomem *enc_mem, *reg_mem;
struct vbi_info vbi;
u32 pgm_info_offset;
u32 pgm_info_num;
u32 pgm_info_write_idx;
u32 pgm_info_read_idx;
struct v4l2_enc_idx_entry pgm_info[CX18_MAX_PGM_INDEX];
u64 mpg_data_received;
u64 vbi_data_inserted;
wait_queue_head_t mb_apu_waitq;
wait_queue_head_t mb_cpu_waitq;
wait_queue_head_t cap_w;
/* when the current DMA is finished this queue is woken up */
wait_queue_head_t dma_waitq;
u32 sw1_irq_mask;
u32 sw2_irq_mask;
u32 hw2_irq_mask;
struct workqueue_struct *in_work_queue;
char in_workq_name[11]; /* "cx18-NN-in" */
struct cx18_in_work_order in_work_order[CX18_MAX_IN_WORK_ORDERS];
char epu_debug_str[256]; /* CX18_EPU_DEBUG is rare: use shared space */
struct workqueue_struct *out_work_queue;
char out_workq_name[12]; /* "cx18-NN-out" */
/* i2c */
struct i2c_adapter i2c_adap[2];
struct i2c_algo_bit_data i2c_algo[2];
struct cx18_i2c_algo_callback_data i2c_algo_cb_data[2];
/* gpio */
u32 gpio_dir;
u32 gpio_val;
struct mutex gpio_lock;
struct v4l2_subdev sd_gpiomux;
struct v4l2_subdev sd_resetctrl;
/* v4l2 and User settings */
/* codec settings */
u32 audio_input;
u32 active_input;
v4l2_std_id std;
v4l2_std_id tuner_std; /* The norm of the tuner (fixed) */
};
static inline struct cx18 *to_cx18(struct v4l2_device *v4l2_dev)
{
return container_of(v4l2_dev, struct cx18, v4l2_dev);
}
/* Globals */
extern int cx18_first_minor;
/*==============Prototypes==================*/
/* Return non-zero if a signal is pending */
int cx18_msleep_timeout(unsigned int msecs, int intr);
/* Read Hauppauge eeprom */
struct tveeprom; /* forward reference */
void cx18_read_eeprom(struct cx18 *cx, struct tveeprom *tv);
/* First-open initialization: load firmware, etc. */
int cx18_init_on_first_open(struct cx18 *cx);
/* Test if the current VBI mode is raw (1) or sliced (0) */
static inline int cx18_raw_vbi(const struct cx18 *cx)
{
return cx->vbi.in.type == V4L2_BUF_TYPE_VBI_CAPTURE;
}
/* Call the specified callback for all subdevs with a grp_id bit matching the
* mask in hw (if 0, then match them all). Ignore any errors. */
#define cx18_call_hw(cx, hw, o, f, args...) \
__v4l2_device_call_subdevs(&(cx)->v4l2_dev, \
!(hw) || (sd->grp_id & (hw)), o, f , ##args)
#define cx18_call_all(cx, o, f, args...) cx18_call_hw(cx, 0, o, f , ##args)
/* Call the specified callback for all subdevs with a grp_id bit matching the
* mask in hw (if 0, then match them all). If the callback returns an error
* other than 0 or -ENOIOCTLCMD, then return with that error code. */
#define cx18_call_hw_err(cx, hw, o, f, args...) \
__v4l2_device_call_subdevs_until_err( \
&(cx)->v4l2_dev, !(hw) || (sd->grp_id & (hw)), o, f , ##args)
#define cx18_call_all_err(cx, o, f, args...) \
cx18_call_hw_err(cx, 0, o, f , ##args)
#endif /* CX18_DRIVER_H */

520
kernel/drivers/media/video/cx18/cx18-dvb.c Normal file
View File

@@ -0,0 +1,520 @@
/*
* cx18 functions for DVB support
*
* Copyright (c) 2008 Steven Toth <stoth@linuxtv.org>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include "cx18-version.h"
#include "cx18-dvb.h"
#include "cx18-io.h"
#include "cx18-queue.h"
#include "cx18-streams.h"
#include "cx18-cards.h"
#include "cx18-gpio.h"
#include "s5h1409.h"
#include "mxl5005s.h"
#include "zl10353.h"
#include <linux/firmware.h>
#include "mt352.h"
#include "mt352_priv.h"
#include "tuner-xc2028.h"
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
#define CX18_REG_DMUX_NUM_PORT_0_CONTROL 0xd5a000
#define CX18_CLOCK_ENABLE2 0xc71024
#define CX18_DMUX_CLK_MASK 0x0080
/*
* CX18_CARD_HVR_1600_ESMT
* CX18_CARD_HVR_1600_SAMSUNG
*/
static struct mxl5005s_config hauppauge_hvr1600_tuner = {
.i2c_address = 0xC6 >> 1,
.if_freq = IF_FREQ_5380000HZ,
.xtal_freq = CRYSTAL_FREQ_16000000HZ,
.agc_mode = MXL_SINGLE_AGC,
.tracking_filter = MXL_TF_C_H,
.rssi_enable = MXL_RSSI_ENABLE,
.cap_select = MXL_CAP_SEL_ENABLE,
.div_out = MXL_DIV_OUT_4,
.clock_out = MXL_CLOCK_OUT_DISABLE,
.output_load = MXL5005S_IF_OUTPUT_LOAD_200_OHM,
.top = MXL5005S_TOP_25P2,
.mod_mode = MXL_DIGITAL_MODE,
.if_mode = MXL_ZERO_IF,
.AgcMasterByte = 0x00,
};
static struct s5h1409_config hauppauge_hvr1600_config = {
.demod_address = 0x32 >> 1,
.output_mode = S5H1409_SERIAL_OUTPUT,
.gpio = S5H1409_GPIO_ON,
.qam_if = 44000,
.inversion = S5H1409_INVERSION_OFF,
.status_mode = S5H1409_DEMODLOCKING,
.mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK
};
/*
* CX18_CARD_LEADTEK_DVR3100H
*/
/* Information/confirmation of proper config values provided by Terry Wu */
static struct zl10353_config leadtek_dvr3100h_demod = {
.demod_address = 0x1e >> 1, /* Datasheet suggested straps */
.if2 = 45600, /* 4.560 MHz IF from the XC3028 */
.parallel_ts = 1, /* Not a serial TS */
.no_tuner = 1, /* XC3028 is not behind the gate */
.disable_i2c_gate_ctrl = 1, /* Disable the I2C gate */
};
/*
* CX18_CARD_YUAN_MPC718
*/
/*
* Due to
*
* 1. an absence of information on how to prgram the MT352
* 2. the Linux mt352 module pushing MT352 initialzation off onto us here
*
* We have to use an init sequence that *you* must extract from the Windows
* driver (yuanrap.sys) and which we load as a firmware.
*
* If someone can provide me with a Zarlink MT352 (Intel CE6352?) Design Manual
* with chip programming details, then I can remove this annoyance.
*/
static int yuan_mpc718_mt352_reqfw(struct cx18_stream *stream,
const struct firmware **fw)
{
struct cx18 *cx = stream->cx;
const char *fn = "dvb-cx18-mpc718-mt352.fw";
int ret;
ret = request_firmware(fw, fn, &cx->pci_dev->dev);
if (ret)
CX18_ERR("Unable to open firmware file %s\n", fn);
else {
size_t sz = (*fw)->size;
if (sz < 2 || sz > 64 || (sz % 2) != 0) {
CX18_ERR("Firmware %s has a bad size: %lu bytes\n",
fn, (unsigned long) sz);
ret = -EILSEQ;
release_firmware(*fw);
*fw = NULL;
}
}
if (ret) {
CX18_ERR("The MPC718 board variant with the MT352 DVB-T"
"demodualtor will not work without it\n");
CX18_ERR("Run 'linux/Documentation/dvb/get_dvb_firmware "
"mpc718' if you need the firmware\n");
}
return ret;
}
static int yuan_mpc718_mt352_init(struct dvb_frontend *fe)
{
struct cx18_dvb *dvb = container_of(fe->dvb,
struct cx18_dvb, dvb_adapter);
struct cx18_stream *stream = container_of(dvb, struct cx18_stream, dvb);
const struct firmware *fw = NULL;
int ret;
int i;
u8 buf[3];
ret = yuan_mpc718_mt352_reqfw(stream, &fw);
if (ret)
return ret;
/* Loop through all the register-value pairs in the firmware file */
for (i = 0; i < fw->size; i += 2) {
buf[0] = fw->data[i];
/* Intercept a few registers we want to set ourselves */
switch (buf[0]) {
case TRL_NOMINAL_RATE_0:
/* Set our custom OFDM bandwidth in the case below */
break;
case TRL_NOMINAL_RATE_1:
/* 6 MHz: 64/7 * 6/8 / 20.48 * 2^16 = 0x55b6.db6 */
/* 7 MHz: 64/7 * 7/8 / 20.48 * 2^16 = 0x6400 */
/* 8 MHz: 64/7 * 8/8 / 20.48 * 2^16 = 0x7249.249 */
buf[1] = 0x72;
buf[2] = 0x49;
mt352_write(fe, buf, 3);
break;
case INPUT_FREQ_0:
/* Set our custom IF in the case below */
break;
case INPUT_FREQ_1:
/* 4.56 MHz IF: (20.48 - 4.56)/20.48 * 2^14 = 0x31c0 */
buf[1] = 0x31;
buf[2] = 0xc0;
mt352_write(fe, buf, 3);
break;
default:
/* Pass through the register-value pair from the fw */
buf[1] = fw->data[i+1];
mt352_write(fe, buf, 2);
break;
}
}
buf[0] = (u8) TUNER_GO;
buf[1] = 0x01; /* Go */
mt352_write(fe, buf, 2);
release_firmware(fw);
return 0;
}
static struct mt352_config yuan_mpc718_mt352_demod = {
.demod_address = 0x1e >> 1,
.adc_clock = 20480, /* 20.480 MHz */
.if2 = 4560, /* 4.560 MHz */
.no_tuner = 1, /* XC3028 is not behind the gate */
.demod_init = yuan_mpc718_mt352_init,
};
static struct zl10353_config yuan_mpc718_zl10353_demod = {
.demod_address = 0x1e >> 1, /* Datasheet suggested straps */
.if2 = 45600, /* 4.560 MHz IF from the XC3028 */
.parallel_ts = 1, /* Not a serial TS */
.no_tuner = 1, /* XC3028 is not behind the gate */
.disable_i2c_gate_ctrl = 1, /* Disable the I2C gate */
};
static int dvb_register(struct cx18_stream *stream);
/* Kernel DVB framework calls this when the feed needs to start.
* The CX18 framework should enable the transport DMA handling
* and queue processing.
*/
static int cx18_dvb_start_feed(struct dvb_demux_feed *feed)
{
struct dvb_demux *demux = feed->demux;
struct cx18_stream *stream = (struct cx18_stream *) demux->priv;
struct cx18 *cx = stream->cx;
int ret;
u32 v;
CX18_DEBUG_INFO("Start feed: pid = 0x%x index = %d\n",
feed->pid, feed->index);
mutex_lock(&cx->serialize_lock);
ret = cx18_init_on_first_open(cx);
mutex_unlock(&cx->serialize_lock);
if (ret) {
CX18_ERR("Failed to initialize firmware starting DVB feed\n");
return ret;
}
ret = -EINVAL;
switch (cx->card->type) {
case CX18_CARD_HVR_1600_ESMT:
case CX18_CARD_HVR_1600_SAMSUNG:
v = cx18_read_reg(cx, CX18_REG_DMUX_NUM_PORT_0_CONTROL);
v |= 0x00400000; /* Serial Mode */
v |= 0x00002000; /* Data Length - Byte */
v |= 0x00010000; /* Error - Polarity */
v |= 0x00020000; /* Error - Passthru */
v |= 0x000c0000; /* Error - Ignore */
cx18_write_reg(cx, v, CX18_REG_DMUX_NUM_PORT_0_CONTROL);
break;
case CX18_CARD_LEADTEK_DVR3100H:
case CX18_CARD_YUAN_MPC718:
default:
/* Assumption - Parallel transport - Signalling
* undefined or default.
*/
break;
}
if (!demux->dmx.frontend)
return -EINVAL;
if (!stream)
return -EINVAL;
mutex_lock(&stream->dvb.feedlock);
if (stream->dvb.feeding++ == 0) {
CX18_DEBUG_INFO("Starting Transport DMA\n");
set_bit(CX18_F_S_STREAMING, &stream->s_flags);
ret = cx18_start_v4l2_encode_stream(stream);
if (ret < 0) {
CX18_DEBUG_INFO("Failed to start Transport DMA\n");
stream->dvb.feeding--;
if (stream->dvb.feeding == 0)
clear_bit(CX18_F_S_STREAMING, &stream->s_flags);
}
} else
ret = 0;
mutex_unlock(&stream->dvb.feedlock);
return ret;
}
/* Kernel DVB framework calls this when the feed needs to stop. */
static int cx18_dvb_stop_feed(struct dvb_demux_feed *feed)
{
struct dvb_demux *demux = feed->demux;
struct cx18_stream *stream = (struct cx18_stream *)demux->priv;
struct cx18 *cx = stream->cx;
int ret = -EINVAL;
CX18_DEBUG_INFO("Stop feed: pid = 0x%x index = %d\n",
feed->pid, feed->index);
if (stream) {
mutex_lock(&stream->dvb.feedlock);
if (--stream->dvb.feeding == 0) {
CX18_DEBUG_INFO("Stopping Transport DMA\n");
ret = cx18_stop_v4l2_encode_stream(stream, 0);
} else
ret = 0;
mutex_unlock(&stream->dvb.feedlock);
}
return ret;
}
int cx18_dvb_register(struct cx18_stream *stream)
{
struct cx18 *cx = stream->cx;
struct cx18_dvb *dvb = &stream->dvb;
struct dvb_adapter *dvb_adapter;
struct dvb_demux *dvbdemux;
struct dmx_demux *dmx;
int ret;
if (!dvb)
return -EINVAL;
ret = dvb_register_adapter(&dvb->dvb_adapter,
CX18_DRIVER_NAME,
THIS_MODULE, &cx->pci_dev->dev, adapter_nr);
if (ret < 0)
goto err_out;
dvb_adapter = &dvb->dvb_adapter;
dvbdemux = &dvb->demux;
dvbdemux->priv = (void *)stream;
dvbdemux->filternum = 256;
dvbdemux->feednum = 256;
dvbdemux->start_feed = cx18_dvb_start_feed;
dvbdemux->stop_feed = cx18_dvb_stop_feed;
dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING);
ret = dvb_dmx_init(dvbdemux);
if (ret < 0)
goto err_dvb_unregister_adapter;
dmx = &dvbdemux->dmx;
dvb->hw_frontend.source = DMX_FRONTEND_0;
dvb->mem_frontend.source = DMX_MEMORY_FE;
dvb->dmxdev.filternum = 256;
dvb->dmxdev.demux = dmx;
ret = dvb_dmxdev_init(&dvb->dmxdev, dvb_adapter);
if (ret < 0)
goto err_dvb_dmx_release;
ret = dmx->add_frontend(dmx, &dvb->hw_frontend);
if (ret < 0)
goto err_dvb_dmxdev_release;
ret = dmx->add_frontend(dmx, &dvb->mem_frontend);
if (ret < 0)
goto err_remove_hw_frontend;
ret = dmx->connect_frontend(dmx, &dvb->hw_frontend);
if (ret < 0)
goto err_remove_mem_frontend;
ret = dvb_register(stream);
if (ret < 0)
goto err_disconnect_frontend;
dvb_net_init(dvb_adapter, &dvb->dvbnet, dmx);
CX18_INFO("DVB Frontend registered\n");
CX18_INFO("Registered DVB adapter%d for %s (%d x %d kB)\n",
stream->dvb.dvb_adapter.num, stream->name,
stream->buffers, stream->buf_size/1024);
mutex_init(&dvb->feedlock);
dvb->enabled = 1;
return ret;
err_disconnect_frontend:
dmx->disconnect_frontend(dmx);
err_remove_mem_frontend:
dmx->remove_frontend(dmx, &dvb->mem_frontend);
err_remove_hw_frontend:
dmx->remove_frontend(dmx, &dvb->hw_frontend);
err_dvb_dmxdev_release:
dvb_dmxdev_release(&dvb->dmxdev);
err_dvb_dmx_release:
dvb_dmx_release(dvbdemux);
err_dvb_unregister_adapter:
dvb_unregister_adapter(dvb_adapter);
err_out:
return ret;
}
void cx18_dvb_unregister(struct cx18_stream *stream)
{
struct cx18 *cx = stream->cx;
struct cx18_dvb *dvb = &stream->dvb;
struct dvb_adapter *dvb_adapter;
struct dvb_demux *dvbdemux;
struct dmx_demux *dmx;
CX18_INFO("unregister DVB\n");
dvb_adapter = &dvb->dvb_adapter;
dvbdemux = &dvb->demux;
dmx = &dvbdemux->dmx;
dmx->close(dmx);
dvb_net_release(&dvb->dvbnet);
dmx->remove_frontend(dmx, &dvb->mem_frontend);
dmx->remove_frontend(dmx, &dvb->hw_frontend);
dvb_dmxdev_release(&dvb->dmxdev);
dvb_dmx_release(dvbdemux);
dvb_unregister_frontend(dvb->fe);
dvb_frontend_detach(dvb->fe);
dvb_unregister_adapter(dvb_adapter);
}
/* All the DVB attach calls go here, this function get's modified
* for each new card. cx18_dvb_start_feed() will also need changes.
*/
static int dvb_register(struct cx18_stream *stream)
{
struct cx18_dvb *dvb = &stream->dvb;
struct cx18 *cx = stream->cx;
int ret = 0;
switch (cx->card->type) {
case CX18_CARD_HVR_1600_ESMT:
case CX18_CARD_HVR_1600_SAMSUNG:
dvb->fe = dvb_attach(s5h1409_attach,
&hauppauge_hvr1600_config,
&cx->i2c_adap[0]);
if (dvb->fe != NULL) {
dvb_attach(mxl5005s_attach, dvb->fe,
&cx->i2c_adap[0],
&hauppauge_hvr1600_tuner);
ret = 0;
}
break;
case CX18_CARD_LEADTEK_DVR3100H:
dvb->fe = dvb_attach(zl10353_attach,
&leadtek_dvr3100h_demod,
&cx->i2c_adap[1]);
if (dvb->fe != NULL) {
struct dvb_frontend *fe;
struct xc2028_config cfg = {
.i2c_adap = &cx->i2c_adap[1],
.i2c_addr = 0xc2 >> 1,
.ctrl = NULL,
};
static struct xc2028_ctrl ctrl = {
.fname = XC2028_DEFAULT_FIRMWARE,
.max_len = 64,
.demod = XC3028_FE_ZARLINK456,
.type = XC2028_AUTO,
};
fe = dvb_attach(xc2028_attach, dvb->fe, &cfg);
if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
fe->ops.tuner_ops.set_config(fe, &ctrl);
}
break;
case CX18_CARD_YUAN_MPC718:
/*
* TODO
* Apparently, these cards also could instead have a
* DiBcom demod supported by one of the db7000 drivers
*/
dvb->fe = dvb_attach(mt352_attach,
&yuan_mpc718_mt352_demod,
&cx->i2c_adap[1]);
if (dvb->fe == NULL)
dvb->fe = dvb_attach(zl10353_attach,
&yuan_mpc718_zl10353_demod,
&cx->i2c_adap[1]);
if (dvb->fe != NULL) {
struct dvb_frontend *fe;
struct xc2028_config cfg = {
.i2c_adap = &cx->i2c_adap[1],
.i2c_addr = 0xc2 >> 1,
.ctrl = NULL,
};
static struct xc2028_ctrl ctrl = {
.fname = XC2028_DEFAULT_FIRMWARE,
.max_len = 64,
.demod = XC3028_FE_ZARLINK456,
.type = XC2028_AUTO,
};
fe = dvb_attach(xc2028_attach, dvb->fe, &cfg);
if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
fe->ops.tuner_ops.set_config(fe, &ctrl);
}
break;
default:
/* No Digital Tv Support */
break;
}
if (dvb->fe == NULL) {
CX18_ERR("frontend initialization failed\n");
return -1;
}
dvb->fe->callback = cx18_reset_tuner_gpio;
ret = dvb_register_frontend(&dvb->dvb_adapter, dvb->fe);
if (ret < 0) {
if (dvb->fe->ops.release)
dvb->fe->ops.release(dvb->fe);
return ret;
}
/*
* The firmware seems to enable the TS DMUX clock
* under various circumstances. However, since we know we
* might use it, let's just turn it on ourselves here.
*/
cx18_write_reg_expect(cx,
(CX18_DMUX_CLK_MASK << 16) | CX18_DMUX_CLK_MASK,
CX18_CLOCK_ENABLE2,
CX18_DMUX_CLK_MASK,
(CX18_DMUX_CLK_MASK << 16) | CX18_DMUX_CLK_MASK);
return ret;
}

25
kernel/drivers/media/video/cx18/cx18-dvb.h Normal file
View File

@@ -0,0 +1,25 @@
/*
* cx18 functions for DVB support
*
* Copyright (c) 2008 Steven Toth <stoth@linuxtv.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include "cx18-driver.h"
int cx18_dvb_register(struct cx18_stream *stream);
void cx18_dvb_unregister(struct cx18_stream *stream);

733
kernel/drivers/media/video/cx18/cx18-fileops.c Normal file
View File

@@ -0,0 +1,733 @@
/*
* cx18 file operation functions
*
* Derived from ivtv-fileops.c
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include "cx18-driver.h"
#include "cx18-fileops.h"
#include "cx18-i2c.h"
#include "cx18-queue.h"
#include "cx18-vbi.h"
#include "cx18-audio.h"
#include "cx18-mailbox.h"
#include "cx18-scb.h"
#include "cx18-streams.h"
#include "cx18-controls.h"
#include "cx18-ioctl.h"
#include "cx18-cards.h"
/* This function tries to claim the stream for a specific file descriptor.
If no one else is using this stream then the stream is claimed and
associated VBI streams are also automatically claimed.
Possible error returns: -EBUSY if someone else has claimed
the stream or 0 on success. */
static int cx18_claim_stream(struct cx18_open_id *id, int type)
{
struct cx18 *cx = id->cx;
struct cx18_stream *s = &cx->streams[type];
struct cx18_stream *s_vbi;
int vbi_type;
if (test_and_set_bit(CX18_F_S_CLAIMED, &s->s_flags)) {
/* someone already claimed this stream */
if (s->id == id->open_id) {
/* yes, this file descriptor did. So that's OK. */
return 0;
}
if (s->id == -1 && type == CX18_ENC_STREAM_TYPE_VBI) {
/* VBI is handled already internally, now also assign
the file descriptor to this stream for external
reading of the stream. */
s->id = id->open_id;
CX18_DEBUG_INFO("Start Read VBI\n");
return 0;
}
/* someone else is using this stream already */
CX18_DEBUG_INFO("Stream %d is busy\n", type);
return -EBUSY;
}
s->id = id->open_id;
/* CX18_ENC_STREAM_TYPE_MPG needs to claim CX18_ENC_STREAM_TYPE_VBI
(provided VBI insertion is on and sliced VBI is selected), for all
other streams we're done */
if (type == CX18_ENC_STREAM_TYPE_MPG &&
cx->vbi.insert_mpeg && !cx18_raw_vbi(cx)) {
vbi_type = CX18_ENC_STREAM_TYPE_VBI;
} else {
return 0;
}
s_vbi = &cx->streams[vbi_type];
set_bit(CX18_F_S_CLAIMED, &s_vbi->s_flags);
/* mark that it is used internally */
set_bit(CX18_F_S_INTERNAL_USE, &s_vbi->s_flags);
return 0;
}
/* This function releases a previously claimed stream. It will take into
account associated VBI streams. */
static void cx18_release_stream(struct cx18_stream *s)
{
struct cx18 *cx = s->cx;
struct cx18_stream *s_vbi;
s->id = -1;
if (s->type == CX18_ENC_STREAM_TYPE_VBI &&
test_bit(CX18_F_S_INTERNAL_USE, &s->s_flags)) {
/* this stream is still in use internally */
return;
}
if (!test_and_clear_bit(CX18_F_S_CLAIMED, &s->s_flags)) {
CX18_DEBUG_WARN("Release stream %s not in use!\n", s->name);
return;
}
cx18_flush_queues(s);
/* CX18_ENC_STREAM_TYPE_MPG needs to release CX18_ENC_STREAM_TYPE_VBI,
for all other streams we're done */
if (s->type == CX18_ENC_STREAM_TYPE_MPG)
s_vbi = &cx->streams[CX18_ENC_STREAM_TYPE_VBI];
else
return;
/* clear internal use flag */
if (!test_and_clear_bit(CX18_F_S_INTERNAL_USE, &s_vbi->s_flags)) {
/* was already cleared */
return;
}
if (s_vbi->id != -1) {
/* VBI stream still claimed by a file descriptor */
return;
}
clear_bit(CX18_F_S_CLAIMED, &s_vbi->s_flags);
cx18_flush_queues(s_vbi);
}
static void cx18_dualwatch(struct cx18 *cx)
{
struct v4l2_tuner vt;
u32 new_bitmap;
u32 new_stereo_mode;
const u32 stereo_mask = 0x0300;
const u32 dual = 0x0200;
u32 h;
new_stereo_mode = cx->params.audio_properties & stereo_mask;
memset(&vt, 0, sizeof(vt));
cx18_call_all(cx, tuner, g_tuner, &vt);
if (vt.audmode == V4L2_TUNER_MODE_LANG1_LANG2 &&
(vt.rxsubchans & V4L2_TUNER_SUB_LANG2))
new_stereo_mode = dual;
if (new_stereo_mode == cx->dualwatch_stereo_mode)
return;
new_bitmap = new_stereo_mode
| (cx->params.audio_properties & ~stereo_mask);
CX18_DEBUG_INFO("dualwatch: change stereo flag from 0x%x to 0x%x. "
"new audio_bitmask=0x%ux\n",
cx->dualwatch_stereo_mode, new_stereo_mode, new_bitmap);
h = cx18_find_handle(cx);
if (h == CX18_INVALID_TASK_HANDLE) {
CX18_DEBUG_INFO("dualwatch: can't find valid task handle\n");
return;
}
if (cx18_vapi(cx,
CX18_CPU_SET_AUDIO_PARAMETERS, 2, h, new_bitmap) == 0) {
cx->dualwatch_stereo_mode = new_stereo_mode;
return;
}
CX18_DEBUG_INFO("dualwatch: changing stereo flag failed\n");
}
static struct cx18_buffer *cx18_get_buffer(struct cx18_stream *s, int non_block, int *err)
{
struct cx18 *cx = s->cx;
struct cx18_stream *s_vbi = &cx->streams[CX18_ENC_STREAM_TYPE_VBI];
struct cx18_buffer *buf;
DEFINE_WAIT(wait);
*err = 0;
while (1) {
if (s->type == CX18_ENC_STREAM_TYPE_MPG) {
/* Process pending program info updates and pending
VBI data */
if (time_after(jiffies, cx->dualwatch_jiffies + msecs_to_jiffies(1000))) {
cx->dualwatch_jiffies = jiffies;
cx18_dualwatch(cx);
}
if (test_bit(CX18_F_S_INTERNAL_USE, &s_vbi->s_flags) &&
!test_bit(CX18_F_S_APPL_IO, &s_vbi->s_flags)) {
while ((buf = cx18_dequeue(s_vbi, &s_vbi->q_full))) {
/* byteswap and process VBI data */
cx18_process_vbi_data(cx, buf,
s_vbi->type);
cx18_stream_put_buf_fw(s_vbi, buf);
}
}
buf = &cx->vbi.sliced_mpeg_buf;
if (buf->readpos != buf->bytesused)
return buf;
}
/* do we have new data? */
buf = cx18_dequeue(s, &s->q_full);
if (buf) {
if (!test_and_clear_bit(CX18_F_B_NEED_BUF_SWAP,
&buf->b_flags))
return buf;
if (s->type == CX18_ENC_STREAM_TYPE_MPG)
/* byteswap MPG data */
cx18_buf_swap(buf);
else {
/* byteswap and process VBI data */
cx18_process_vbi_data(cx, buf, s->type);
}
return buf;
}
/* return if end of stream */
if (!test_bit(CX18_F_S_STREAMING, &s->s_flags)) {
CX18_DEBUG_INFO("EOS %s\n", s->name);
return NULL;
}
/* return if file was opened with O_NONBLOCK */
if (non_block) {
*err = -EAGAIN;
return NULL;
}
/* wait for more data to arrive */
prepare_to_wait(&s->waitq, &wait, TASK_INTERRUPTIBLE);
/* New buffers might have become available before we were added
to the waitqueue */
if (!atomic_read(&s->q_full.buffers))
schedule();
finish_wait(&s->waitq, &wait);
if (signal_pending(current)) {
/* return if a signal was received */
CX18_DEBUG_INFO("User stopped %s\n", s->name);
*err = -EINTR;
return NULL;
}
}
}
static void cx18_setup_sliced_vbi_buf(struct cx18 *cx)
{
int idx = cx->vbi.inserted_frame % CX18_VBI_FRAMES;
cx->vbi.sliced_mpeg_buf.buf = cx->vbi.sliced_mpeg_data[idx];
cx->vbi.sliced_mpeg_buf.bytesused = cx->vbi.sliced_mpeg_size[idx];
cx->vbi.sliced_mpeg_buf.readpos = 0;
}
static size_t cx18_copy_buf_to_user(struct cx18_stream *s,
struct cx18_buffer *buf, char __user *ubuf, size_t ucount)
{
struct cx18 *cx = s->cx;
size_t len = buf->bytesused - buf->readpos;
if (len > ucount)
len = ucount;
if (cx->vbi.insert_mpeg && s->type == CX18_ENC_STREAM_TYPE_MPG &&
!cx18_raw_vbi(cx) && buf != &cx->vbi.sliced_mpeg_buf) {
/*
* Try to find a good splice point in the PS, just before
* an MPEG-2 Program Pack start code, and provide only
* up to that point to the user, so it's easy to insert VBI data
* the next time around.
*
* This will not work for an MPEG-2 TS and has only been
* verified by analysis to work for an MPEG-2 PS. Helen Buus
* pointed out this works for the CX23416 MPEG-2 DVD compatible
* stream, and research indicates both the MPEG 2 SVCD and DVD
* stream types use an MPEG-2 PS container.
*/
/*
* An MPEG-2 Program Stream (PS) is a series of
* MPEG-2 Program Packs terminated by an
* MPEG Program End Code after the last Program Pack.
* A Program Pack may hold a PS System Header packet and any
* number of Program Elementary Stream (PES) Packets
*/
const char *start = buf->buf + buf->readpos;
const char *p = start + 1;
const u8 *q;
u8 ch = cx->search_pack_header ? 0xba : 0xe0;
int stuffing, i;
while (start + len > p) {
/* Scan for a 0 to find a potential MPEG-2 start code */
q = memchr(p, 0, start + len - p);
if (q == NULL)
break;
p = q + 1;
/*
* Keep looking if not a
* MPEG-2 Pack header start code: 0x00 0x00 0x01 0xba
* or MPEG-2 video PES start code: 0x00 0x00 0x01 0xe0
*/
if ((char *)q + 15 >= buf->buf + buf->bytesused ||
q[1] != 0 || q[2] != 1 || q[3] != ch)
continue;
/* If expecting the primary video PES */
if (!cx->search_pack_header) {
/* Continue if it couldn't be a PES packet */
if ((q[6] & 0xc0) != 0x80)
continue;
/* Check if a PTS or PTS & DTS follow */
if (((q[7] & 0xc0) == 0x80 && /* PTS only */
(q[9] & 0xf0) == 0x20) || /* PTS only */
((q[7] & 0xc0) == 0xc0 && /* PTS & DTS */
(q[9] & 0xf0) == 0x30)) { /* DTS follows */
/* Assume we found the video PES hdr */
ch = 0xba; /* next want a Program Pack*/
cx->search_pack_header = 1;
p = q + 9; /* Skip this video PES hdr */
}
continue;
}
/* We may have found a Program Pack start code */
/* Get the count of stuffing bytes & verify them */
stuffing = q[13] & 7;
/* all stuffing bytes must be 0xff */
for (i = 0; i < stuffing; i++)
if (q[14 + i] != 0xff)
break;
if (i == stuffing && /* right number of stuffing bytes*/
(q[4] & 0xc4) == 0x44 && /* marker check */
(q[12] & 3) == 3 && /* marker check */
q[14 + stuffing] == 0 && /* PES Pack or Sys Hdr */
q[15 + stuffing] == 0 &&
q[16 + stuffing] == 1) {
/* We declare we actually found a Program Pack*/
cx->search_pack_header = 0; /* expect vid PES */
len = (char *)q - start;
cx18_setup_sliced_vbi_buf(cx);
break;
}
}
}
if (copy_to_user(ubuf, (u8 *)buf->buf + buf->readpos, len)) {
CX18_DEBUG_WARN("copy %zd bytes to user failed for %s\n",
len, s->name);
return -EFAULT;
}
buf->readpos += len;
if (s->type == CX18_ENC_STREAM_TYPE_MPG &&
buf != &cx->vbi.sliced_mpeg_buf)
cx->mpg_data_received += len;
return len;
}
static ssize_t cx18_read(struct cx18_stream *s, char __user *ubuf,
size_t tot_count, int non_block)
{
struct cx18 *cx = s->cx;
size_t tot_written = 0;
int single_frame = 0;
if (atomic_read(&cx->ana_capturing) == 0 && s->id == -1) {
/* shouldn't happen */
CX18_DEBUG_WARN("Stream %s not initialized before read\n",
s->name);
return -EIO;
}
/* Each VBI buffer is one frame, the v4l2 API says that for VBI the
frames should arrive one-by-one, so make sure we never output more
than one VBI frame at a time */
if (s->type == CX18_ENC_STREAM_TYPE_VBI && !cx18_raw_vbi(cx))
single_frame = 1;
for (;;) {
struct cx18_buffer *buf;
int rc;
buf = cx18_get_buffer(s, non_block, &rc);
/* if there is no data available... */
if (buf == NULL) {
/* if we got data, then return that regardless */
if (tot_written)
break;
/* EOS condition */
if (rc == 0) {
clear_bit(CX18_F_S_STREAMOFF, &s->s_flags);
clear_bit(CX18_F_S_APPL_IO, &s->s_flags);
cx18_release_stream(s);
}
/* set errno */
return rc;
}
rc = cx18_copy_buf_to_user(s, buf, ubuf + tot_written,
tot_count - tot_written);
if (buf != &cx->vbi.sliced_mpeg_buf) {
if (buf->readpos == buf->bytesused)
cx18_stream_put_buf_fw(s, buf);
else
cx18_push(s, buf, &s->q_full);
} else if (buf->readpos == buf->bytesused) {
int idx = cx->vbi.inserted_frame % CX18_VBI_FRAMES;
cx->vbi.sliced_mpeg_size[idx] = 0;
cx->vbi.inserted_frame++;
cx->vbi_data_inserted += buf->bytesused;
}
if (rc < 0)
return rc;
tot_written += rc;
if (tot_written == tot_count || single_frame)
break;
}
return tot_written;
}
static ssize_t cx18_read_pos(struct cx18_stream *s, char __user *ubuf,
size_t count, loff_t *pos, int non_block)
{
ssize_t rc = count ? cx18_read(s, ubuf, count, non_block) : 0;
struct cx18 *cx = s->cx;
CX18_DEBUG_HI_FILE("read %zd from %s, got %zd\n", count, s->name, rc);
if (rc > 0)
pos += rc;
return rc;
}
int cx18_start_capture(struct cx18_open_id *id)
{
struct cx18 *cx = id->cx;
struct cx18_stream *s = &cx->streams[id->type];
struct cx18_stream *s_vbi;
if (s->type == CX18_ENC_STREAM_TYPE_RAD) {
/* you cannot read from these stream types. */
return -EPERM;
}
/* Try to claim this stream. */
if (cx18_claim_stream(id, s->type))
return -EBUSY;
/* If capture is already in progress, then we also have to
do nothing extra. */
if (test_bit(CX18_F_S_STREAMOFF, &s->s_flags) ||
test_and_set_bit(CX18_F_S_STREAMING, &s->s_flags)) {
set_bit(CX18_F_S_APPL_IO, &s->s_flags);
return 0;
}
/* Start VBI capture if required */
s_vbi = &cx->streams[CX18_ENC_STREAM_TYPE_VBI];
if (s->type == CX18_ENC_STREAM_TYPE_MPG &&
test_bit(CX18_F_S_INTERNAL_USE, &s_vbi->s_flags) &&
!test_and_set_bit(CX18_F_S_STREAMING, &s_vbi->s_flags)) {
/* Note: the CX18_ENC_STREAM_TYPE_VBI is claimed
automatically when the MPG stream is claimed.
We only need to start the VBI capturing. */
if (cx18_start_v4l2_encode_stream(s_vbi)) {
CX18_DEBUG_WARN("VBI capture start failed\n");
/* Failure, clean up and return an error */
clear_bit(CX18_F_S_STREAMING, &s_vbi->s_flags);
clear_bit(CX18_F_S_STREAMING, &s->s_flags);
/* also releases the associated VBI stream */
cx18_release_stream(s);
return -EIO;
}
CX18_DEBUG_INFO("VBI insertion started\n");
}
/* Tell the card to start capturing */
if (!cx18_start_v4l2_encode_stream(s)) {
/* We're done */
set_bit(CX18_F_S_APPL_IO, &s->s_flags);
/* Resume a possibly paused encoder */
if (test_and_clear_bit(CX18_F_I_ENC_PAUSED, &cx->i_flags))
cx18_vapi(cx, CX18_CPU_CAPTURE_PAUSE, 1, s->handle);
return 0;
}
/* failure, clean up */
CX18_DEBUG_WARN("Failed to start capturing for stream %s\n", s->name);
/* Note: the CX18_ENC_STREAM_TYPE_VBI is released
automatically when the MPG stream is released.
We only need to stop the VBI capturing. */
if (s->type == CX18_ENC_STREAM_TYPE_MPG &&
test_bit(CX18_F_S_STREAMING, &s_vbi->s_flags)) {
cx18_stop_v4l2_encode_stream(s_vbi, 0);
clear_bit(CX18_F_S_STREAMING, &s_vbi->s_flags);
}
clear_bit(CX18_F_S_STREAMING, &s->s_flags);
cx18_release_stream(s);
return -EIO;
}
ssize_t cx18_v4l2_read(struct file *filp, char __user *buf, size_t count,
loff_t *pos)
{
struct cx18_open_id *id = filp->private_data;
struct cx18 *cx = id->cx;
struct cx18_stream *s = &cx->streams[id->type];
int rc;
CX18_DEBUG_HI_FILE("read %zd bytes from %s\n", count, s->name);
mutex_lock(&cx->serialize_lock);
rc = cx18_start_capture(id);
mutex_unlock(&cx->serialize_lock);
if (rc)
return rc;
return cx18_read_pos(s, buf, count, pos, filp->f_flags & O_NONBLOCK);
}
unsigned int cx18_v4l2_enc_poll(struct file *filp, poll_table *wait)
{
struct cx18_open_id *id = filp->private_data;
struct cx18 *cx = id->cx;
struct cx18_stream *s = &cx->streams[id->type];
int eof = test_bit(CX18_F_S_STREAMOFF, &s->s_flags);
/* Start a capture if there is none */
if (!eof && !test_bit(CX18_F_S_STREAMING, &s->s_flags)) {
int rc;
mutex_lock(&cx->serialize_lock);
rc = cx18_start_capture(id);
mutex_unlock(&cx->serialize_lock);
if (rc) {
CX18_DEBUG_INFO("Could not start capture for %s (%d)\n",
s->name, rc);
return POLLERR;
}
CX18_DEBUG_FILE("Encoder poll started capture\n");
}
/* add stream's waitq to the poll list */
CX18_DEBUG_HI_FILE("Encoder poll\n");
poll_wait(filp, &s->waitq, wait);
if (atomic_read(&s->q_full.buffers))
return POLLIN | POLLRDNORM;
if (eof)
return POLLHUP;
return 0;
}
void cx18_stop_capture(struct cx18_open_id *id, int gop_end)
{
struct cx18 *cx = id->cx;
struct cx18_stream *s = &cx->streams[id->type];
CX18_DEBUG_IOCTL("close() of %s\n", s->name);
/* 'Unclaim' this stream */
/* Stop capturing */
if (test_bit(CX18_F_S_STREAMING, &s->s_flags)) {
struct cx18_stream *s_vbi =
&cx->streams[CX18_ENC_STREAM_TYPE_VBI];
CX18_DEBUG_INFO("close stopping capture\n");
/* Special case: a running VBI capture for VBI insertion
in the mpeg stream. Need to stop that too. */
if (id->type == CX18_ENC_STREAM_TYPE_MPG &&
test_bit(CX18_F_S_STREAMING, &s_vbi->s_flags) &&
!test_bit(CX18_F_S_APPL_IO, &s_vbi->s_flags)) {
CX18_DEBUG_INFO("close stopping embedded VBI capture\n");
cx18_stop_v4l2_encode_stream(s_vbi, 0);
}
if (id->type == CX18_ENC_STREAM_TYPE_VBI &&
test_bit(CX18_F_S_INTERNAL_USE, &s->s_flags))
/* Also used internally, don't stop capturing */
s->id = -1;
else
cx18_stop_v4l2_encode_stream(s, gop_end);
}
if (!gop_end) {
clear_bit(CX18_F_S_APPL_IO, &s->s_flags);
clear_bit(CX18_F_S_STREAMOFF, &s->s_flags);
cx18_release_stream(s);
}
}
int cx18_v4l2_close(struct file *filp)
{
struct cx18_open_id *id = filp->private_data;
struct cx18 *cx = id->cx;
struct cx18_stream *s = &cx->streams[id->type];
CX18_DEBUG_IOCTL("close() of %s\n", s->name);
v4l2_prio_close(&cx->prio, &id->prio);
/* Easy case first: this stream was never claimed by us */
if (s->id != id->open_id) {
kfree(id);
return 0;
}
/* 'Unclaim' this stream */
/* Stop radio */
mutex_lock(&cx->serialize_lock);
if (id->type == CX18_ENC_STREAM_TYPE_RAD) {
/* Closing radio device, return to TV mode */
cx18_mute(cx);
/* Mark that the radio is no longer in use */
clear_bit(CX18_F_I_RADIO_USER, &cx->i_flags);
/* Switch tuner to TV */
cx18_call_all(cx, core, s_std, cx->std);
/* Select correct audio input (i.e. TV tuner or Line in) */
cx18_audio_set_io(cx);
if (atomic_read(&cx->ana_capturing) > 0) {
/* Undo video mute */
cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, s->handle,
cx->params.video_mute |
(cx->params.video_mute_yuv << 8));
}
/* Done! Unmute and continue. */
cx18_unmute(cx);
cx18_release_stream(s);
} else {
cx18_stop_capture(id, 0);
}
kfree(id);
mutex_unlock(&cx->serialize_lock);
return 0;
}
static int cx18_serialized_open(struct cx18_stream *s, struct file *filp)
{
struct cx18 *cx = s->cx;
struct cx18_open_id *item;
CX18_DEBUG_FILE("open %s\n", s->name);
/* Allocate memory */
item = kmalloc(sizeof(struct cx18_open_id), GFP_KERNEL);
if (NULL == item) {
CX18_DEBUG_WARN("nomem on v4l2 open\n");
return -ENOMEM;
}
item->cx = cx;
item->type = s->type;
v4l2_prio_open(&cx->prio, &item->prio);
item->open_id = cx->open_id++;
filp->private_data = item;
if (item->type == CX18_ENC_STREAM_TYPE_RAD) {
/* Try to claim this stream */
if (cx18_claim_stream(item, item->type)) {
/* No, it's already in use */
kfree(item);
return -EBUSY;
}
if (!test_bit(CX18_F_I_RADIO_USER, &cx->i_flags)) {
if (atomic_read(&cx->ana_capturing) > 0) {
/* switching to radio while capture is
in progress is not polite */
cx18_release_stream(s);
kfree(item);
return -EBUSY;
}
}
/* Mark that the radio is being used. */
set_bit(CX18_F_I_RADIO_USER, &cx->i_flags);
/* We have the radio */
cx18_mute(cx);
/* Switch tuner to radio */
cx18_call_all(cx, tuner, s_radio);
/* Select the correct audio input (i.e. radio tuner) */
cx18_audio_set_io(cx);
/* Done! Unmute and continue. */
cx18_unmute(cx);
}
return 0;
}
int cx18_v4l2_open(struct file *filp)
{
int res;
struct video_device *video_dev = video_devdata(filp);
struct cx18_stream *s = video_get_drvdata(video_dev);
struct cx18 *cx = s->cx;
mutex_lock(&cx->serialize_lock);
if (cx18_init_on_first_open(cx)) {
CX18_ERR("Failed to initialize on minor %d\n",
video_dev->minor);
mutex_unlock(&cx->serialize_lock);
return -ENXIO;
}
res = cx18_serialized_open(s, filp);
mutex_unlock(&cx->serialize_lock);
return res;
}
void cx18_mute(struct cx18 *cx)
{
u32 h;
if (atomic_read(&cx->ana_capturing)) {
h = cx18_find_handle(cx);
if (h != CX18_INVALID_TASK_HANDLE)
cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2, h, 1);
else
CX18_ERR("Can't find valid task handle for mute\n");
}
CX18_DEBUG_INFO("Mute\n");
}
void cx18_unmute(struct cx18 *cx)
{
u32 h;
if (atomic_read(&cx->ana_capturing)) {
h = cx18_find_handle(cx);
if (h != CX18_INVALID_TASK_HANDLE) {
cx18_msleep_timeout(100, 0);
cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 2, h, 12);
cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2, h, 0);
} else
CX18_ERR("Can't find valid task handle for unmute\n");
}
CX18_DEBUG_INFO("Unmute\n");
}

36
kernel/drivers/media/video/cx18/cx18-fileops.h Normal file
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@@ -0,0 +1,36 @@
/*
* cx18 file operation functions
*
* Derived from ivtv-fileops.h
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
/* Testing/Debugging */
int cx18_v4l2_open(struct file *filp);
ssize_t cx18_v4l2_read(struct file *filp, char __user *buf, size_t count,
loff_t *pos);
ssize_t cx18_v4l2_write(struct file *filp, const char __user *buf, size_t count,
loff_t *pos);
int cx18_v4l2_close(struct file *filp);
unsigned int cx18_v4l2_enc_poll(struct file *filp, poll_table *wait);
int cx18_start_capture(struct cx18_open_id *id);
void cx18_stop_capture(struct cx18_open_id *id, int gop_end);
void cx18_mute(struct cx18 *cx);
void cx18_unmute(struct cx18 *cx);

448
kernel/drivers/media/video/cx18/cx18-firmware.c Normal file
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@@ -0,0 +1,448 @@
/*
* cx18 firmware functions
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-scb.h"
#include "cx18-irq.h"
#include "cx18-firmware.h"
#include "cx18-cards.h"
#include <linux/firmware.h>
#define CX18_PROC_SOFT_RESET 0xc70010
#define CX18_DDR_SOFT_RESET 0xc70014
#define CX18_CLOCK_SELECT1 0xc71000
#define CX18_CLOCK_SELECT2 0xc71004
#define CX18_HALF_CLOCK_SELECT1 0xc71008
#define CX18_HALF_CLOCK_SELECT2 0xc7100C
#define CX18_CLOCK_POLARITY1 0xc71010
#define CX18_CLOCK_POLARITY2 0xc71014
#define CX18_ADD_DELAY_ENABLE1 0xc71018
#define CX18_ADD_DELAY_ENABLE2 0xc7101C
#define CX18_CLOCK_ENABLE1 0xc71020
#define CX18_CLOCK_ENABLE2 0xc71024
#define CX18_REG_BUS_TIMEOUT_EN 0xc72024
#define CX18_FAST_CLOCK_PLL_INT 0xc78000
#define CX18_FAST_CLOCK_PLL_FRAC 0xc78004
#define CX18_FAST_CLOCK_PLL_POST 0xc78008
#define CX18_FAST_CLOCK_PLL_PRESCALE 0xc7800C
#define CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH 0xc78010
#define CX18_SLOW_CLOCK_PLL_INT 0xc78014
#define CX18_SLOW_CLOCK_PLL_FRAC 0xc78018
#define CX18_SLOW_CLOCK_PLL_POST 0xc7801C
#define CX18_MPEG_CLOCK_PLL_INT 0xc78040
#define CX18_MPEG_CLOCK_PLL_FRAC 0xc78044
#define CX18_MPEG_CLOCK_PLL_POST 0xc78048
#define CX18_PLL_POWER_DOWN 0xc78088
#define CX18_SW1_INT_STATUS 0xc73104
#define CX18_SW1_INT_ENABLE_PCI 0xc7311C
#define CX18_SW2_INT_SET 0xc73140
#define CX18_SW2_INT_STATUS 0xc73144
#define CX18_ADEC_CONTROL 0xc78120
#define CX18_DDR_REQUEST_ENABLE 0xc80000
#define CX18_DDR_CHIP_CONFIG 0xc80004
#define CX18_DDR_REFRESH 0xc80008
#define CX18_DDR_TIMING1 0xc8000C
#define CX18_DDR_TIMING2 0xc80010
#define CX18_DDR_POWER_REG 0xc8001C
#define CX18_DDR_TUNE_LANE 0xc80048
#define CX18_DDR_INITIAL_EMRS 0xc80054
#define CX18_DDR_MB_PER_ROW_7 0xc8009C
#define CX18_DDR_BASE_63_ADDR 0xc804FC
#define CX18_WMB_CLIENT02 0xc90108
#define CX18_WMB_CLIENT05 0xc90114
#define CX18_WMB_CLIENT06 0xc90118
#define CX18_WMB_CLIENT07 0xc9011C
#define CX18_WMB_CLIENT08 0xc90120
#define CX18_WMB_CLIENT09 0xc90124
#define CX18_WMB_CLIENT10 0xc90128
#define CX18_WMB_CLIENT11 0xc9012C
#define CX18_WMB_CLIENT12 0xc90130
#define CX18_WMB_CLIENT13 0xc90134
#define CX18_WMB_CLIENT14 0xc90138
#define CX18_DSP0_INTERRUPT_MASK 0xd0004C
#define APU_ROM_SYNC1 0x6D676553 /* "mgeS" */
#define APU_ROM_SYNC2 0x72646548 /* "rdeH" */
struct cx18_apu_rom_seghdr {
u32 sync1;
u32 sync2;
u32 addr;
u32 size;
};
static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx)
{
const struct firmware *fw = NULL;
int i, j;
unsigned size;
u32 __iomem *dst = (u32 __iomem *)mem;
const u32 *src;
if (request_firmware(&fw, fn, &cx->pci_dev->dev)) {
CX18_ERR("Unable to open firmware %s\n", fn);
CX18_ERR("Did you put the firmware in the hotplug firmware directory?\n");
return -ENOMEM;
}
src = (const u32 *)fw->data;
for (i = 0; i < fw->size; i += 4096) {
cx18_setup_page(cx, i);
for (j = i; j < fw->size && j < i + 4096; j += 4) {
/* no need for endianness conversion on the ppc */
cx18_raw_writel(cx, *src, dst);
if (cx18_raw_readl(cx, dst) != *src) {
CX18_ERR("Mismatch at offset %x\n", i);
release_firmware(fw);
cx18_setup_page(cx, 0);
return -EIO;
}
dst++;
src++;
}
}
if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
CX18_INFO("loaded %s firmware (%zd bytes)\n", fn, fw->size);
size = fw->size;
release_firmware(fw);
cx18_setup_page(cx, SCB_OFFSET);
return size;
}
static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx,
u32 *entry_addr)
{
const struct firmware *fw = NULL;
int i, j;
unsigned size;
const u32 *src;
struct cx18_apu_rom_seghdr seghdr;
const u8 *vers;
u32 offset = 0;
u32 apu_version = 0;
int sz;
if (request_firmware(&fw, fn, &cx->pci_dev->dev)) {
CX18_ERR("unable to open firmware %s\n", fn);
CX18_ERR("did you put the firmware in the hotplug firmware directory?\n");
cx18_setup_page(cx, 0);
return -ENOMEM;
}
*entry_addr = 0;
src = (const u32 *)fw->data;
vers = fw->data + sizeof(seghdr);
sz = fw->size;
apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];
while (offset + sizeof(seghdr) < fw->size) {
/* TODO: byteswapping */
memcpy(&seghdr, src + offset / 4, sizeof(seghdr));
offset += sizeof(seghdr);
if (seghdr.sync1 != APU_ROM_SYNC1 ||
seghdr.sync2 != APU_ROM_SYNC2) {
offset += seghdr.size;
continue;
}
CX18_DEBUG_INFO("load segment %x-%x\n", seghdr.addr,
seghdr.addr + seghdr.size - 1);
if (*entry_addr == 0)
*entry_addr = seghdr.addr;
if (offset + seghdr.size > sz)
break;
for (i = 0; i < seghdr.size; i += 4096) {
cx18_setup_page(cx, seghdr.addr + i);
for (j = i; j < seghdr.size && j < i + 4096; j += 4) {
/* no need for endianness conversion on the ppc */
cx18_raw_writel(cx, src[(offset + j) / 4],
dst + seghdr.addr + j);
if (cx18_raw_readl(cx, dst + seghdr.addr + j)
!= src[(offset + j) / 4]) {
CX18_ERR("Mismatch at offset %x\n",
offset + j);
release_firmware(fw);
cx18_setup_page(cx, 0);
return -EIO;
}
}
}
offset += seghdr.size;
}
if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
CX18_INFO("loaded %s firmware V%08x (%zd bytes)\n",
fn, apu_version, fw->size);
size = fw->size;
release_firmware(fw);
cx18_setup_page(cx, 0);
return size;
}
void cx18_halt_firmware(struct cx18 *cx)
{
CX18_DEBUG_INFO("Preparing for firmware halt.\n");
cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
0x0000000F, 0x000F000F);
cx18_write_reg_expect(cx, 0x00020002, CX18_ADEC_CONTROL,
0x00000002, 0x00020002);
}
void cx18_init_power(struct cx18 *cx, int lowpwr)
{
/* power-down Spare and AOM PLLs */
/* power-up fast, slow and mpeg PLLs */
cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN);
/* ADEC out of sleep */
cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL,
0x00000000, 0x00020002);
/*
* The PLL parameters are based on the external crystal frequency that
* would ideally be:
*
* NTSC Color subcarrier freq * 8 =
* 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
*
* The accidents of history and rationale that explain from where this
* combination of magic numbers originate can be found in:
*
* [1] Abrahams, I. C., "Choice of Chrominance Subcarrier Frequency in
* the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80
*
* [2] Abrahams, I. C., "The 'Frequency Interleaving' Principle in the
* NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83
*
* As Mike Bradley has rightly pointed out, it's not the exact crystal
* frequency that matters, only that all parts of the driver and
* firmware are using the same value (close to the ideal value).
*
* Since I have a strong suspicion that, if the firmware ever assumes a
* crystal value at all, it will assume 28.636360 MHz, the crystal
* freq used in calculations in this driver will be:
*
* xtal_freq = 28.636360 MHz
*
* an error of less than 0.13 ppm which is way, way better than any off
* the shelf crystal will have for accuracy anyway.
*
* Below I aim to run the PLLs' VCOs near 400 MHz to minimze errors.
*
* Many thanks to Jeff Campbell and Mike Bradley for their extensive
* investigation, experimentation, testing, and suggested solutions of
* of audio/video sync problems with SVideo and CVBS captures.
*/
/* the fast clock is at 200/245 MHz */
/* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/
/* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/
cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,
CX18_FAST_CLOCK_PLL_FRAC);
cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST);
cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE);
cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
/* set slow clock to 125/120 MHz */
/* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */
/* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */
cx18_write_reg(cx, lowpwr ? 0xD : 0xC, CX18_SLOW_CLOCK_PLL_INT);
cx18_write_reg(cx, lowpwr ? 0x30C344 : 0x124927F,
CX18_SLOW_CLOCK_PLL_FRAC);
cx18_write_reg(cx, 3, CX18_SLOW_CLOCK_PLL_POST);
/* mpeg clock pll 54MHz */
/* xtal_freq * 0xf.15f17f0 / 8 = 54 MHz: 432 MHz before post-divide */
cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT);
cx18_write_reg(cx, 0x2BE2FE, CX18_MPEG_CLOCK_PLL_FRAC);
cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST);
/* Defaults */
/* APU = SC or SC/2 = 125/62.5 */
/* EPU = SC = 125 */
/* DDR = FC = 180 */
/* ENC = SC = 125 */
/* AI1 = SC = 125 */
/* VIM2 = disabled */
/* PCI = FC/2 = 90 */
/* AI2 = disabled */
/* DEMUX = disabled */
/* AO = SC/2 = 62.5 */
/* SER = 54MHz */
/* VFC = disabled */
/* USB = disabled */
if (lowpwr) {
cx18_write_reg_expect(cx, 0xFFFF0020, CX18_CLOCK_SELECT1,
0x00000020, 0xFFFFFFFF);
cx18_write_reg_expect(cx, 0xFFFF0004, CX18_CLOCK_SELECT2,
0x00000004, 0xFFFFFFFF);
} else {
/* This doesn't explicitly set every clock select */
cx18_write_reg_expect(cx, 0x00060004, CX18_CLOCK_SELECT1,
0x00000004, 0x00060006);
cx18_write_reg_expect(cx, 0x00060006, CX18_CLOCK_SELECT2,
0x00000006, 0x00060006);
}
cx18_write_reg_expect(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1,
0x00000002, 0xFFFFFFFF);
cx18_write_reg_expect(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2,
0x00000104, 0xFFFFFFFF);
cx18_write_reg_expect(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1,
0x00009026, 0xFFFFFFFF);
cx18_write_reg_expect(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2,
0x00003105, 0xFFFFFFFF);
}
void cx18_init_memory(struct cx18 *cx)
{
cx18_msleep_timeout(10, 0);
cx18_write_reg_expect(cx, 0x00010000, CX18_DDR_SOFT_RESET,
0x00000000, 0x00010001);
cx18_msleep_timeout(10, 0);
cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
cx18_msleep_timeout(10, 0);
cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH);
cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1);
cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2);
cx18_msleep_timeout(10, 0);
/* Initialize DQS pad time */
cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
cx18_msleep_timeout(10, 0);
cx18_write_reg_expect(cx, 0x00020000, CX18_DDR_SOFT_RESET,
0x00000000, 0x00020002);
cx18_msleep_timeout(10, 0);
/* use power-down mode when idle */
cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG);
cx18_write_reg_expect(cx, 0x00010001, CX18_REG_BUS_TIMEOUT_EN,
0x00000001, 0x00010001);
cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7);
cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR);
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02); /* AO */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09); /* AI2 */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05); /* VIM1 */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06); /* AI1 */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07); /* 3D comb */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10); /* ME */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12); /* ENC */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13); /* PK */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11); /* RC */
cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14); /* AVO */
}
int cx18_firmware_init(struct cx18 *cx)
{
u32 fw_entry_addr;
int sz, retries;
u32 api_args[MAX_MB_ARGUMENTS];
/* Allow chip to control CLKRUN */
cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK);
/* Stop the firmware */
cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
0x0000000F, 0x000F000F);
cx18_msleep_timeout(1, 0);
/* If the CPU is still running */
if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) == 0) {
CX18_ERR("%s: couldn't stop CPU to load firmware\n", __func__);
return -EIO;
}
cx18_sw1_irq_enable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
cx18_sw2_irq_enable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
sz = load_cpu_fw_direct("v4l-cx23418-cpu.fw", cx->enc_mem, cx);
if (sz <= 0)
return sz;
/* The SCB & IPC area *must* be correct before starting the firmwares */
cx18_init_scb(cx);
fw_entry_addr = 0;
sz = load_apu_fw_direct("v4l-cx23418-apu.fw", cx->enc_mem, cx,
&fw_entry_addr);
if (sz <= 0)
return sz;
/* Start the CPU. The CPU will take care of the APU for us. */
cx18_write_reg_expect(cx, 0x00080000, CX18_PROC_SOFT_RESET,
0x00000000, 0x00080008);
/* Wait up to 500 ms for the APU to come out of reset */
for (retries = 0;
retries < 50 && (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1;
retries++)
cx18_msleep_timeout(10, 0);
cx18_msleep_timeout(200, 0);
if (retries == 50 &&
(cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1) {
CX18_ERR("Could not start the CPU\n");
return -EIO;
}
/*
* The CPU had once before set up to receive an interrupt for it's
* outgoing IRQ_CPU_TO_EPU_ACK to us. If it ever does this, we get an
* interrupt when it sends us an ack, but by the time we process it,
* that flag in the SW2 status register has been cleared by the CPU
* firmware. We'll prevent that not so useful condition from happening
* by clearing the CPU's interrupt enables for Ack IRQ's we want to
* process.
*/
cx18_sw2_irq_disable_cpu(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
/* Try a benign command to see if the CPU is alive and well */
sz = cx18_vapi_result(cx, api_args, CX18_CPU_DEBUG_PEEK32, 1, 0);
if (sz < 0)
return sz;
/* initialize GPIO */
cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400);
return 0;
}

25
kernel/drivers/media/video/cx18/cx18-firmware.h Normal file
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/*
* cx18 firmware functions
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
int cx18_firmware_init(struct cx18 *cx);
void cx18_halt_firmware(struct cx18 *cx);
void cx18_init_memory(struct cx18 *cx);
void cx18_init_power(struct cx18 *cx, int lowpwr);

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kernel/drivers/media/video/cx18/cx18-gpio.c Normal file
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/*
* cx18 gpio functions
*
* Derived from ivtv-gpio.c
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-cards.h"
#include "cx18-gpio.h"
#include "tuner-xc2028.h"
/********************* GPIO stuffs *********************/
/* GPIO registers */
#define CX18_REG_GPIO_IN 0xc72010
#define CX18_REG_GPIO_OUT1 0xc78100
#define CX18_REG_GPIO_DIR1 0xc78108
#define CX18_REG_GPIO_OUT2 0xc78104
#define CX18_REG_GPIO_DIR2 0xc7810c
/*
* HVR-1600 GPIO pins, courtesy of Hauppauge:
*
* gpio0: zilog ir process reset pin
* gpio1: zilog programming pin (you should never use this)
* gpio12: cx24227 reset pin
* gpio13: cs5345 reset pin
*/
/*
* File scope utility functions
*/
static void gpio_write(struct cx18 *cx)
{
u32 dir_lo = cx->gpio_dir & 0xffff;
u32 val_lo = cx->gpio_val & 0xffff;
u32 dir_hi = cx->gpio_dir >> 16;
u32 val_hi = cx->gpio_val >> 16;
cx18_write_reg_expect(cx, dir_lo << 16,
CX18_REG_GPIO_DIR1, ~dir_lo, dir_lo);
cx18_write_reg_expect(cx, (dir_lo << 16) | val_lo,
CX18_REG_GPIO_OUT1, val_lo, dir_lo);
cx18_write_reg_expect(cx, dir_hi << 16,
CX18_REG_GPIO_DIR2, ~dir_hi, dir_hi);
cx18_write_reg_expect(cx, (dir_hi << 16) | val_hi,
CX18_REG_GPIO_OUT2, val_hi, dir_hi);
}
static void gpio_update(struct cx18 *cx, u32 mask, u32 data)
{
if (mask == 0)
return;
mutex_lock(&cx->gpio_lock);
cx->gpio_val = (cx->gpio_val & ~mask) | (data & mask);
gpio_write(cx);
mutex_unlock(&cx->gpio_lock);
}
static void gpio_reset_seq(struct cx18 *cx, u32 active_lo, u32 active_hi,
unsigned int assert_msecs,
unsigned int recovery_msecs)
{
u32 mask;
mask = active_lo | active_hi;
if (mask == 0)
return;
/*
* Assuming that active_hi and active_lo are a subsets of the bits in
* gpio_dir. Also assumes that active_lo and active_hi don't overlap
* in any bit position
*/
/* Assert */
gpio_update(cx, mask, ~active_lo);
schedule_timeout_uninterruptible(msecs_to_jiffies(assert_msecs));
/* Deassert */
gpio_update(cx, mask, ~active_hi);
schedule_timeout_uninterruptible(msecs_to_jiffies(recovery_msecs));
}
/*
* GPIO Multiplexer - logical device
*/
static int gpiomux_log_status(struct v4l2_subdev *sd)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
mutex_lock(&cx->gpio_lock);
CX18_INFO_DEV(sd, "GPIO: direction 0x%08x, value 0x%08x\n",
cx->gpio_dir, cx->gpio_val);
mutex_unlock(&cx->gpio_lock);
return 0;
}
static int gpiomux_s_radio(struct v4l2_subdev *sd)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
/*
* FIXME - work out the cx->active/audio_input mess - this is
* intended to handle the switch to radio mode and set the
* audio routing, but we need to update the state in cx
*/
gpio_update(cx, cx->card->gpio_audio_input.mask,
cx->card->gpio_audio_input.radio);
return 0;
}
static int gpiomux_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
u32 data;
switch (cx->card->audio_inputs[cx->audio_input].muxer_input) {
case 1:
data = cx->card->gpio_audio_input.linein;
break;
case 0:
data = cx->card->gpio_audio_input.tuner;
break;
default:
/*
* FIXME - work out the cx->active/audio_input mess - this is
* intended to handle the switch from radio mode and set the
* audio routing, but we need to update the state in cx
*/
data = cx->card->gpio_audio_input.tuner;
break;
}
gpio_update(cx, cx->card->gpio_audio_input.mask, data);
return 0;
}
static int gpiomux_s_audio_routing(struct v4l2_subdev *sd,
u32 input, u32 output, u32 config)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
u32 data;
switch (input) {
case 0:
data = cx->card->gpio_audio_input.tuner;
break;
case 1:
data = cx->card->gpio_audio_input.linein;
break;
case 2:
data = cx->card->gpio_audio_input.radio;
break;
default:
return -EINVAL;
}
gpio_update(cx, cx->card->gpio_audio_input.mask, data);
return 0;
}
static const struct v4l2_subdev_core_ops gpiomux_core_ops = {
.log_status = gpiomux_log_status,
.s_std = gpiomux_s_std,
};
static const struct v4l2_subdev_tuner_ops gpiomux_tuner_ops = {
.s_radio = gpiomux_s_radio,
};
static const struct v4l2_subdev_audio_ops gpiomux_audio_ops = {
.s_routing = gpiomux_s_audio_routing,
};
static const struct v4l2_subdev_ops gpiomux_ops = {
.core = &gpiomux_core_ops,
.tuner = &gpiomux_tuner_ops,
.audio = &gpiomux_audio_ops,
};
/*
* GPIO Reset Controller - logical device
*/
static int resetctrl_log_status(struct v4l2_subdev *sd)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
mutex_lock(&cx->gpio_lock);
CX18_INFO_DEV(sd, "GPIO: direction 0x%08x, value 0x%08x\n",
cx->gpio_dir, cx->gpio_val);
mutex_unlock(&cx->gpio_lock);
return 0;
}
static int resetctrl_reset(struct v4l2_subdev *sd, u32 val)
{
struct cx18 *cx = v4l2_get_subdevdata(sd);
const struct cx18_gpio_i2c_slave_reset *p;
p = &cx->card->gpio_i2c_slave_reset;
switch (val) {
case CX18_GPIO_RESET_I2C:
gpio_reset_seq(cx, p->active_lo_mask, p->active_hi_mask,
p->msecs_asserted, p->msecs_recovery);
break;
case CX18_GPIO_RESET_Z8F0811:
/*
* Assert timing for the Z8F0811 on HVR-1600 boards:
* 1. Assert RESET for min of 4 clock cycles at 18.432 MHz to
* initiate
* 2. Reset then takes 66 WDT cycles at 10 kHz + 16 xtal clock
* cycles (6,601,085 nanoseconds ~= 7 milliseconds)
* 3. DBG pin must be high before chip exits reset for normal
* operation. DBG is open drain and hopefully pulled high
* since we don't normally drive it (GPIO 1?) for the
* HVR-1600
* 4. Z8F0811 won't exit reset until RESET is deasserted
* 5. Zilog comes out of reset, loads reset vector address and
* executes from there. Required recovery delay unknown.
*/
gpio_reset_seq(cx, p->ir_reset_mask, 0,
p->msecs_asserted, p->msecs_recovery);
break;
case CX18_GPIO_RESET_XC2028:
if (cx->card->tuners[0].tuner == TUNER_XC2028)
gpio_reset_seq(cx, (1 << cx->card->xceive_pin), 0,
1, 1);
break;
}
return 0;
}
static const struct v4l2_subdev_core_ops resetctrl_core_ops = {
.log_status = resetctrl_log_status,
.reset = resetctrl_reset,
};
static const struct v4l2_subdev_ops resetctrl_ops = {
.core = &resetctrl_core_ops,
};
/*
* External entry points
*/
void cx18_gpio_init(struct cx18 *cx)
{
mutex_lock(&cx->gpio_lock);
cx->gpio_dir = cx->card->gpio_init.direction;
cx->gpio_val = cx->card->gpio_init.initial_value;
if (cx->card->tuners[0].tuner == TUNER_XC2028) {
cx->gpio_dir |= 1 << cx->card->xceive_pin;
cx->gpio_val |= 1 << cx->card->xceive_pin;
}
if (cx->gpio_dir == 0) {
mutex_unlock(&cx->gpio_lock);
return;
}
CX18_DEBUG_INFO("GPIO initial dir: %08x/%08x out: %08x/%08x\n",
cx18_read_reg(cx, CX18_REG_GPIO_DIR1),
cx18_read_reg(cx, CX18_REG_GPIO_DIR2),
cx18_read_reg(cx, CX18_REG_GPIO_OUT1),
cx18_read_reg(cx, CX18_REG_GPIO_OUT2));
gpio_write(cx);
mutex_unlock(&cx->gpio_lock);
}
int cx18_gpio_register(struct cx18 *cx, u32 hw)
{
struct v4l2_subdev *sd;
const struct v4l2_subdev_ops *ops;
char *str;
switch (hw) {
case CX18_HW_GPIO_MUX:
sd = &cx->sd_gpiomux;
ops = &gpiomux_ops;
str = "gpio-mux";
break;
case CX18_HW_GPIO_RESET_CTRL:
sd = &cx->sd_resetctrl;
ops = &resetctrl_ops;
str = "gpio-reset-ctrl";
break;
default:
return -EINVAL;
}
v4l2_subdev_init(sd, ops);
v4l2_set_subdevdata(sd, cx);
snprintf(sd->name, sizeof(sd->name), "%s %s", cx->v4l2_dev.name, str);
sd->grp_id = hw;
return v4l2_device_register_subdev(&cx->v4l2_dev, sd);
}
void cx18_reset_ir_gpio(void *data)
{
struct cx18 *cx = to_cx18((struct v4l2_device *)data);
if (cx->card->gpio_i2c_slave_reset.ir_reset_mask == 0)
return;
CX18_DEBUG_INFO("Resetting IR microcontroller\n");
v4l2_subdev_call(&cx->sd_resetctrl,
core, reset, CX18_GPIO_RESET_Z8F0811);
}
EXPORT_SYMBOL(cx18_reset_ir_gpio);
/* This symbol is exported for use by lirc_pvr150 for the IR-blaster */
/* Xceive tuner reset function */
int cx18_reset_tuner_gpio(void *dev, int component, int cmd, int value)
{
struct i2c_algo_bit_data *algo = dev;
struct cx18_i2c_algo_callback_data *cb_data = algo->data;
struct cx18 *cx = cb_data->cx;
if (cmd != XC2028_TUNER_RESET ||
cx->card->tuners[0].tuner != TUNER_XC2028)
return 0;
CX18_DEBUG_INFO("Resetting XCeive tuner\n");
return v4l2_subdev_call(&cx->sd_resetctrl,
core, reset, CX18_GPIO_RESET_XC2028);
}

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kernel/drivers/media/video/cx18/cx18-gpio.h Normal file
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/*
* cx18 gpio functions
*
* Derived from ivtv-gpio.h
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
void cx18_gpio_init(struct cx18 *cx);
int cx18_gpio_register(struct cx18 *cx, u32 hw);
enum cx18_gpio_reset_type {
CX18_GPIO_RESET_I2C = 0,
CX18_GPIO_RESET_Z8F0811 = 1,
CX18_GPIO_RESET_XC2028 = 2,
};
void cx18_reset_ir_gpio(void *data);
int cx18_reset_tuner_gpio(void *dev, int component, int cmd, int value);

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kernel/drivers/media/video/cx18/cx18-i2c.c Normal file
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/*
* cx18 I2C functions
*
* Derived from ivtv-i2c.c
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-cards.h"
#include "cx18-gpio.h"
#include "cx18-i2c.h"
#include "cx18-irq.h"
#include <media/ir-kbd-i2c.h>
#define CX18_REG_I2C_1_WR 0xf15000
#define CX18_REG_I2C_1_RD 0xf15008
#define CX18_REG_I2C_2_WR 0xf25100
#define CX18_REG_I2C_2_RD 0xf25108
#define SETSCL_BIT 0x0001
#define SETSDL_BIT 0x0002
#define GETSCL_BIT 0x0004
#define GETSDL_BIT 0x0008
#define CX18_CS5345_I2C_ADDR 0x4c
#define CX18_Z8F0811_IR_TX_I2C_ADDR 0x70
#define CX18_Z8F0811_IR_RX_I2C_ADDR 0x71
/* This array should match the CX18_HW_ defines */
static const u8 hw_addrs[] = {
0, /* CX18_HW_TUNER */
0, /* CX18_HW_TVEEPROM */
CX18_CS5345_I2C_ADDR, /* CX18_HW_CS5345 */
0, /* CX18_HW_DVB */
0, /* CX18_HW_418_AV */
0, /* CX18_HW_GPIO_MUX */
0, /* CX18_HW_GPIO_RESET_CTRL */
CX18_Z8F0811_IR_TX_I2C_ADDR, /* CX18_HW_Z8F0811_IR_TX_HAUP */
CX18_Z8F0811_IR_RX_I2C_ADDR, /* CX18_HW_Z8F0811_IR_RX_HAUP */
};
/* This array should match the CX18_HW_ defines */
/* This might well become a card-specific array */
static const u8 hw_bus[] = {
1, /* CX18_HW_TUNER */
0, /* CX18_HW_TVEEPROM */
0, /* CX18_HW_CS5345 */
0, /* CX18_HW_DVB */
0, /* CX18_HW_418_AV */
0, /* CX18_HW_GPIO_MUX */
0, /* CX18_HW_GPIO_RESET_CTRL */
0, /* CX18_HW_Z8F0811_IR_TX_HAUP */
0, /* CX18_HW_Z8F0811_IR_RX_HAUP */
};
/* This array should match the CX18_HW_ defines */
static const char * const hw_modules[] = {
"tuner", /* CX18_HW_TUNER */
NULL, /* CX18_HW_TVEEPROM */
"cs5345", /* CX18_HW_CS5345 */
NULL, /* CX18_HW_DVB */
NULL, /* CX18_HW_418_AV */
NULL, /* CX18_HW_GPIO_MUX */
NULL, /* CX18_HW_GPIO_RESET_CTRL */
NULL, /* CX18_HW_Z8F0811_IR_TX_HAUP */
NULL, /* CX18_HW_Z8F0811_IR_RX_HAUP */
};
/* This array should match the CX18_HW_ defines */
static const char * const hw_devicenames[] = {
"tuner",
"tveeprom",
"cs5345",
"cx23418_DTV",
"cx23418_AV",
"gpio_mux",
"gpio_reset_ctrl",
"ir_tx_z8f0811_haup",
"ir_rx_z8f0811_haup",
};
static const struct IR_i2c_init_data z8f0811_ir_init_data = {
.ir_codes = &ir_codes_hauppauge_new_table,
.internal_get_key_func = IR_KBD_GET_KEY_HAUP_XVR,
.type = IR_TYPE_RC5,
.name = "CX23418 Z8F0811 Hauppauge",
};
static int cx18_i2c_new_ir(struct i2c_adapter *adap, u32 hw, const char *type,
u8 addr)
{
struct i2c_board_info info;
unsigned short addr_list[2] = { addr, I2C_CLIENT_END };
memset(&info, 0, sizeof(struct i2c_board_info));
strlcpy(info.type, type, I2C_NAME_SIZE);
/* Our default information for ir-kbd-i2c.c to use */
switch (hw) {
case CX18_HW_Z8F0811_IR_RX_HAUP:
info.platform_data = (void *) &z8f0811_ir_init_data;
break;
default:
break;
}
return i2c_new_probed_device(adap, &info, addr_list) == NULL ? -1 : 0;
}
int cx18_i2c_register(struct cx18 *cx, unsigned idx)
{
struct v4l2_subdev *sd;
int bus = hw_bus[idx];
struct i2c_adapter *adap = &cx->i2c_adap[bus];
const char *mod = hw_modules[idx];
const char *type = hw_devicenames[idx];
u32 hw = 1 << idx;
if (idx >= ARRAY_SIZE(hw_addrs))
return -1;
if (hw == CX18_HW_TUNER) {
/* special tuner group handling */
sd = v4l2_i2c_new_subdev(&cx->v4l2_dev,
adap, mod, type, 0, cx->card_i2c->radio);
if (sd != NULL)
sd->grp_id = hw;
sd = v4l2_i2c_new_subdev(&cx->v4l2_dev,
adap, mod, type, 0, cx->card_i2c->demod);
if (sd != NULL)
sd->grp_id = hw;
sd = v4l2_i2c_new_subdev(&cx->v4l2_dev,
adap, mod, type, 0, cx->card_i2c->tv);
if (sd != NULL)
sd->grp_id = hw;
return sd != NULL ? 0 : -1;
}
if (hw & CX18_HW_Z8F0811_IR_HAUP)
return cx18_i2c_new_ir(adap, hw, type, hw_addrs[idx]);
/* Is it not an I2C device or one we do not wish to register? */
if (!hw_addrs[idx])
return -1;
/* It's an I2C device other than an analog tuner or IR chip */
sd = v4l2_i2c_new_subdev(&cx->v4l2_dev, adap, mod, type, hw_addrs[idx], NULL);
if (sd != NULL)
sd->grp_id = hw;
return sd != NULL ? 0 : -1;
}
/* Find the first member of the subdev group id in hw */
struct v4l2_subdev *cx18_find_hw(struct cx18 *cx, u32 hw)
{
struct v4l2_subdev *result = NULL;
struct v4l2_subdev *sd;
spin_lock(&cx->v4l2_dev.lock);
v4l2_device_for_each_subdev(sd, &cx->v4l2_dev) {
if (sd->grp_id == hw) {
result = sd;
break;
}
}
spin_unlock(&cx->v4l2_dev.lock);
return result;
}
static void cx18_setscl(void *data, int state)
{
struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx;
int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index;
u32 addr = bus_index ? CX18_REG_I2C_2_WR : CX18_REG_I2C_1_WR;
u32 r = cx18_read_reg(cx, addr);
if (state)
cx18_write_reg(cx, r | SETSCL_BIT, addr);
else
cx18_write_reg(cx, r & ~SETSCL_BIT, addr);
}
static void cx18_setsda(void *data, int state)
{
struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx;
int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index;
u32 addr = bus_index ? CX18_REG_I2C_2_WR : CX18_REG_I2C_1_WR;
u32 r = cx18_read_reg(cx, addr);
if (state)
cx18_write_reg(cx, r | SETSDL_BIT, addr);
else
cx18_write_reg(cx, r & ~SETSDL_BIT, addr);
}
static int cx18_getscl(void *data)
{
struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx;
int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index;
u32 addr = bus_index ? CX18_REG_I2C_2_RD : CX18_REG_I2C_1_RD;
return cx18_read_reg(cx, addr) & GETSCL_BIT;
}
static int cx18_getsda(void *data)
{
struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx;
int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index;
u32 addr = bus_index ? CX18_REG_I2C_2_RD : CX18_REG_I2C_1_RD;
return cx18_read_reg(cx, addr) & GETSDL_BIT;
}
/* template for i2c-bit-algo */
static struct i2c_adapter cx18_i2c_adap_template = {
.name = "cx18 i2c driver",
.algo = NULL, /* set by i2c-algo-bit */
.algo_data = NULL, /* filled from template */
.owner = THIS_MODULE,
};
#define CX18_SCL_PERIOD (10) /* usecs. 10 usec is period for a 100 KHz clock */
#define CX18_ALGO_BIT_TIMEOUT (2) /* seconds */
static struct i2c_algo_bit_data cx18_i2c_algo_template = {
.setsda = cx18_setsda,
.setscl = cx18_setscl,
.getsda = cx18_getsda,
.getscl = cx18_getscl,
.udelay = CX18_SCL_PERIOD/2, /* 1/2 clock period in usec*/
.timeout = CX18_ALGO_BIT_TIMEOUT*HZ /* jiffies */
};
/* init + register i2c algo-bit adapter */
int init_cx18_i2c(struct cx18 *cx)
{
int i, err;
CX18_DEBUG_I2C("i2c init\n");
for (i = 0; i < 2; i++) {
/* Setup algorithm for adapter */
memcpy(&cx->i2c_algo[i], &cx18_i2c_algo_template,
sizeof(struct i2c_algo_bit_data));
cx->i2c_algo_cb_data[i].cx = cx;
cx->i2c_algo_cb_data[i].bus_index = i;
cx->i2c_algo[i].data = &cx->i2c_algo_cb_data[i];
/* Setup adapter */
memcpy(&cx->i2c_adap[i], &cx18_i2c_adap_template,
sizeof(struct i2c_adapter));
cx->i2c_adap[i].algo_data = &cx->i2c_algo[i];
sprintf(cx->i2c_adap[i].name + strlen(cx->i2c_adap[i].name),
" #%d-%d", cx->instance, i);
i2c_set_adapdata(&cx->i2c_adap[i], &cx->v4l2_dev);
cx->i2c_adap[i].dev.parent = &cx->pci_dev->dev;
}
if (cx18_read_reg(cx, CX18_REG_I2C_2_WR) != 0x0003c02f) {
/* Reset/Unreset I2C hardware block */
/* Clock select 220MHz */
cx18_write_reg_expect(cx, 0x10000000, 0xc71004,
0x00000000, 0x10001000);
/* Clock Enable */
cx18_write_reg_expect(cx, 0x10001000, 0xc71024,
0x00001000, 0x10001000);
}
/* courtesy of Steven Toth <stoth@hauppauge.com> */
cx18_write_reg_expect(cx, 0x00c00000, 0xc7001c, 0x00000000, 0x00c000c0);
mdelay(10);
cx18_write_reg_expect(cx, 0x00c000c0, 0xc7001c, 0x000000c0, 0x00c000c0);
mdelay(10);
cx18_write_reg_expect(cx, 0x00c00000, 0xc7001c, 0x00000000, 0x00c000c0);
mdelay(10);
/* Set to edge-triggered intrs. */
cx18_write_reg(cx, 0x00c00000, 0xc730c8);
/* Clear any stale intrs */
cx18_write_reg_expect(cx, HW2_I2C1_INT|HW2_I2C2_INT, HW2_INT_CLR_STATUS,
~(HW2_I2C1_INT|HW2_I2C2_INT), HW2_I2C1_INT|HW2_I2C2_INT);
/* Hw I2C1 Clock Freq ~100kHz */
cx18_write_reg(cx, 0x00021c0f & ~4, CX18_REG_I2C_1_WR);
cx18_setscl(&cx->i2c_algo_cb_data[0], 1);
cx18_setsda(&cx->i2c_algo_cb_data[0], 1);
/* Hw I2C2 Clock Freq ~100kHz */
cx18_write_reg(cx, 0x00021c0f & ~4, CX18_REG_I2C_2_WR);
cx18_setscl(&cx->i2c_algo_cb_data[1], 1);
cx18_setsda(&cx->i2c_algo_cb_data[1], 1);
cx18_call_hw(cx, CX18_HW_GPIO_RESET_CTRL,
core, reset, (u32) CX18_GPIO_RESET_I2C);
err = i2c_bit_add_bus(&cx->i2c_adap[0]);
if (err)
goto err;
err = i2c_bit_add_bus(&cx->i2c_adap[1]);
if (err)
goto err_del_bus_0;
return 0;
err_del_bus_0:
i2c_del_adapter(&cx->i2c_adap[0]);
err:
return err;
}
void exit_cx18_i2c(struct cx18 *cx)
{
int i;
CX18_DEBUG_I2C("i2c exit\n");
cx18_write_reg(cx, cx18_read_reg(cx, CX18_REG_I2C_1_WR) | 4,
CX18_REG_I2C_1_WR);
cx18_write_reg(cx, cx18_read_reg(cx, CX18_REG_I2C_2_WR) | 4,
CX18_REG_I2C_2_WR);
for (i = 0; i < 2; i++) {
i2c_del_adapter(&cx->i2c_adap[i]);
}
}
/*
Hauppauge HVR1600 should have:
32 cx24227
98 unknown
a0 eeprom
c2 tuner
e? zilog ir
*/

29
kernel/drivers/media/video/cx18/cx18-i2c.h Normal file
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@@ -0,0 +1,29 @@
/*
* cx18 I2C functions
*
* Derived from ivtv-i2c.h
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
int cx18_i2c_register(struct cx18 *cx, unsigned idx);
struct v4l2_subdev *cx18_find_hw(struct cx18 *cx, u32 hw);
/* init + register i2c algo-bit adapter */
int init_cx18_i2c(struct cx18 *cx);
void exit_cx18_i2c(struct cx18 *cx);

97
kernel/drivers/media/video/cx18/cx18-io.c Normal file
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@@ -0,0 +1,97 @@
/*
* cx18 driver PCI memory mapped IO access routines
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-irq.h"
void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
{
u8 __iomem *dst = addr;
u16 val2 = val | (val << 8);
u32 val4 = val2 | (val2 << 16);
/* Align writes on the CX23418's addresses */
if ((count > 0) && ((unsigned long)dst & 1)) {
cx18_writeb(cx, (u8) val, dst);
count--;
dst++;
}
if ((count > 1) && ((unsigned long)dst & 2)) {
cx18_writew(cx, val2, dst);
count -= 2;
dst += 2;
}
while (count > 3) {
cx18_writel(cx, val4, dst);
count -= 4;
dst += 4;
}
if (count > 1) {
cx18_writew(cx, val2, dst);
count -= 2;
dst += 2;
}
if (count > 0)
cx18_writeb(cx, (u8) val, dst);
}
void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
{
cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
}
void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
{
cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
}
void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
{
cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val;
cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
}
void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
{
cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
}
void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
{
u32 r;
r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
}
void cx18_setup_page(struct cx18 *cx, u32 addr)
{
u32 val;
val = cx18_read_reg(cx, 0xD000F8);
val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
cx18_write_reg(cx, val, 0xD000F8);
}

191
kernel/drivers/media/video/cx18/cx18-io.h Normal file
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@@ -0,0 +1,191 @@
/*
* cx18 driver PCI memory mapped IO access routines
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#ifndef CX18_IO_H
#define CX18_IO_H
#include "cx18-driver.h"
/*
* Readback and retry of MMIO access for reliability:
* The concept was suggested by Steve Toth <stoth@linuxtv.org>.
* The implmentation is the fault of Andy Walls <awalls@radix.net>.
*
* *write* functions are implied to retry the mmio unless suffixed with _noretry
* *read* functions never retry the mmio (it never helps to do so)
*/
/* Non byteswapping memory mapped IO */
static inline u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr)
{
return __raw_readl(addr);
}
static inline
void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
{
__raw_writel(val, addr);
}
static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr)
{
int i;
for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_raw_writel_noretry(cx, val, addr);
if (val == cx18_raw_readl(cx, addr))
break;
}
}
/* Normal memory mapped IO */
static inline u32 cx18_readl(struct cx18 *cx, const void __iomem *addr)
{
return readl(addr);
}
static inline
void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
{
writel(val, addr);
}
static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
{
int i;
for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_writel_noretry(cx, val, addr);
if (val == cx18_readl(cx, addr))
break;
}
}
static inline
void cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
u32 eval, u32 mask)
{
int i;
u32 r;
eval &= mask;
for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_writel_noretry(cx, val, addr);
r = cx18_readl(cx, addr);
if (r == 0xffffffff && eval != 0xffffffff)
continue;
if (eval == (r & mask))
break;
}
}
static inline u16 cx18_readw(struct cx18 *cx, const void __iomem *addr)
{
return readw(addr);
}
static inline
void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr)
{
writew(val, addr);
}
static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr)
{
int i;
for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_writew_noretry(cx, val, addr);
if (val == cx18_readw(cx, addr))
break;
}
}
static inline u8 cx18_readb(struct cx18 *cx, const void __iomem *addr)
{
return readb(addr);
}
static inline
void cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr)
{
writeb(val, addr);
}
static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr)
{
int i;
for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_writeb_noretry(cx, val, addr);
if (val == cx18_readb(cx, addr))
break;
}
}
static inline
void cx18_memcpy_fromio(struct cx18 *cx, void *to,
const void __iomem *from, unsigned int len)
{
memcpy_fromio(to, from, len);
}
void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count);
/* Access "register" region of CX23418 memory mapped I/O */
static inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg)
{
cx18_writel_noretry(cx, val, cx->reg_mem + reg);
}
static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg)
{
cx18_writel(cx, val, cx->reg_mem + reg);
}
static inline void cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg,
u32 eval, u32 mask)
{
cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask);
}
static inline u32 cx18_read_reg(struct cx18 *cx, u32 reg)
{
return cx18_readl(cx, cx->reg_mem + reg);
}
/* Access "encoder memory" region of CX23418 memory mapped I/O */
static inline void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr)
{
cx18_writel(cx, val, cx->enc_mem + addr);
}
static inline u32 cx18_read_enc(struct cx18 *cx, u32 addr)
{
return cx18_readl(cx, cx->enc_mem + addr);
}
void cx18_sw1_irq_enable(struct cx18 *cx, u32 val);
void cx18_sw1_irq_disable(struct cx18 *cx, u32 val);
void cx18_sw2_irq_enable(struct cx18 *cx, u32 val);
void cx18_sw2_irq_disable(struct cx18 *cx, u32 val);
void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val);
void cx18_setup_page(struct cx18 *cx, u32 addr);
#endif /* CX18_IO_H */

1014
kernel/drivers/media/video/cx18/cx18-ioctl.c Normal file
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File diff suppressed because it is too large Load Diff

33
kernel/drivers/media/video/cx18/cx18-ioctl.h Normal file
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@@ -0,0 +1,33 @@
/*
* cx18 ioctl system call
*
* Derived from ivtv-ioctl.h
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
u16 cx18_service2vbi(int type);
void cx18_expand_service_set(struct v4l2_sliced_vbi_format *fmt, int is_pal);
u16 cx18_get_service_set(struct v4l2_sliced_vbi_format *fmt);
void cx18_set_funcs(struct video_device *vdev);
int cx18_s_std(struct file *file, void *fh, v4l2_std_id *std);
int cx18_s_frequency(struct file *file, void *fh, struct v4l2_frequency *vf);
int cx18_s_input(struct file *file, void *fh, unsigned int inp);
long cx18_v4l2_ioctl(struct file *filp, unsigned int cmd,
unsigned long arg);

81
kernel/drivers/media/video/cx18/cx18-irq.c Normal file
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@@ -0,0 +1,81 @@
/*
* cx18 interrupt handling
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-irq.h"
#include "cx18-mailbox.h"
#include "cx18-scb.h"
static void xpu_ack(struct cx18 *cx, u32 sw2)
{
if (sw2 & IRQ_CPU_TO_EPU_ACK)
wake_up(&cx->mb_cpu_waitq);
if (sw2 & IRQ_APU_TO_EPU_ACK)
wake_up(&cx->mb_apu_waitq);
}
static void epu_cmd(struct cx18 *cx, u32 sw1)
{
if (sw1 & IRQ_CPU_TO_EPU)
cx18_api_epu_cmd_irq(cx, CPU);
if (sw1 & IRQ_APU_TO_EPU)
cx18_api_epu_cmd_irq(cx, APU);
}
irqreturn_t cx18_irq_handler(int irq, void *dev_id)
{
struct cx18 *cx = (struct cx18 *)dev_id;
u32 sw1, sw2, hw2;
sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & cx->sw1_irq_mask;
sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & cx->sw2_irq_mask;
hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & cx->hw2_irq_mask;
if (sw1)
cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1);
if (sw2)
cx18_write_reg_expect(cx, sw2, SW2_INT_STATUS, ~sw2, sw2);
if (hw2)
cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2);
if (sw1 || sw2 || hw2)
CX18_DEBUG_HI_IRQ("received interrupts "
"SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2);
/*
* SW1 responses have to happen first. The sending XPU times out the
* incoming mailboxes on us rather rapidly.
*/
if (sw1)
epu_cmd(cx, sw1);
/* To do: interrupt-based I2C handling
if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) {
}
*/
if (sw2)
xpu_ack(cx, sw2);
return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE;
}

35
kernel/drivers/media/video/cx18/cx18-irq.h Normal file
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@@ -0,0 +1,35 @@
/*
* cx18 interrupt handling
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#define HW2_I2C1_INT (1 << 22)
#define HW2_I2C2_INT (1 << 23)
#define HW2_INT_CLR_STATUS 0xc730c4
#define HW2_INT_MASK5_PCI 0xc730e4
#define SW1_INT_SET 0xc73100
#define SW1_INT_STATUS 0xc73104
#define SW1_INT_ENABLE_PCI 0xc7311c
#define SW2_INT_SET 0xc73140
#define SW2_INT_STATUS 0xc73144
#define SW2_INT_ENABLE_CPU 0xc73158
#define SW2_INT_ENABLE_PCI 0xc7315c
irqreturn_t cx18_irq_handler(int irq, void *dev_id);

749
kernel/drivers/media/video/cx18/cx18-mailbox.c Normal file
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@@ -0,0 +1,749 @@
/*
* cx18 mailbox functions
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include <stdarg.h>
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-scb.h"
#include "cx18-irq.h"
#include "cx18-mailbox.h"
#include "cx18-queue.h"
#include "cx18-streams.h"
static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
#define API_FAST (1 << 2) /* Short timeout */
#define API_SLOW (1 << 3) /* Additional 300ms timeout */
struct cx18_api_info {
u32 cmd;
u8 flags; /* Flags, see above */
u8 rpu; /* Processing unit */
const char *name; /* The name of the command */
};
#define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
static const struct cx18_api_info api_info[] = {
/* MPEG encoder API */
API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
API_ENTRY(CPU, CX18_EPU_DEBUG, 0),
API_ENTRY(CPU, CX18_CREATE_TASK, 0),
API_ENTRY(CPU, CX18_DESTROY_TASK, 0),
API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW),
API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW),
API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0),
API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0),
API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0),
API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0),
API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0),
API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0),
API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0),
API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0),
API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0),
API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0),
API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0),
API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0),
API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0),
API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0),
API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW),
API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0),
API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0),
API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0),
API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0),
API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0),
API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0),
API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0),
API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0),
API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0),
API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0),
API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0),
API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0),
API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0),
API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST),
API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW),
API_ENTRY(APU, CX18_APU_START, 0),
API_ENTRY(APU, CX18_APU_STOP, 0),
API_ENTRY(APU, CX18_APU_RESETAI, 0),
API_ENTRY(CPU, CX18_CPU_DEBUG_PEEK32, 0),
API_ENTRY(0, 0, 0),
};
static const struct cx18_api_info *find_api_info(u32 cmd)
{
int i;
for (i = 0; api_info[i].cmd; i++)
if (api_info[i].cmd == cmd)
return &api_info[i];
return NULL;
}
/* Call with buf of n*11+1 bytes */
static char *u32arr2hex(u32 data[], int n, char *buf)
{
char *p;
int i;
for (i = 0, p = buf; i < n; i++, p += 11) {
/* kernel snprintf() appends '\0' always */
snprintf(p, 12, " %#010x", data[i]);
}
*p = '\0';
return buf;
}
static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
{
char argstr[MAX_MB_ARGUMENTS*11+1];
if (!(cx18_debug & CX18_DBGFLG_API))
return;
CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s"
"\n", name, mb->request, mb->ack, mb->cmd, mb->error,
u32arr2hex(mb->args, MAX_MB_ARGUMENTS, argstr));
}
/*
* Functions that run in a work_queue work handling context
*/
static void epu_dma_done(struct cx18 *cx, struct cx18_in_work_order *order)
{
u32 handle, mdl_ack_count, id;
struct cx18_mailbox *mb;
struct cx18_mdl_ack *mdl_ack;
struct cx18_stream *s;
struct cx18_buffer *buf;
int i;
mb = &order->mb;
handle = mb->args[0];
s = cx18_handle_to_stream(cx, handle);
if (s == NULL) {
CX18_WARN("Got DMA done notification for unknown/inactive"
" handle %d, %s mailbox seq no %d\n", handle,
(order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) ?
"stale" : "good", mb->request);
return;
}
mdl_ack_count = mb->args[2];
mdl_ack = order->mdl_ack;
for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
id = mdl_ack->id;
/*
* Simple integrity check for processing a stale (and possibly
* inconsistent mailbox): make sure the buffer id is in the
* valid range for the stream.
*
* We go through the trouble of dealing with stale mailboxes
* because most of the time, the mailbox data is still valid and
* unchanged (and in practice the firmware ping-pongs the
* two mdl_ack buffers so mdl_acks are not stale).
*
* There are occasions when we get a half changed mailbox,
* which this check catches for a handle & id mismatch. If the
* handle and id do correspond, the worst case is that we
* completely lost the old buffer, but pick up the new buffer
* early (but the new mdl_ack is guaranteed to be good in this
* case as the firmware wouldn't point us to a new mdl_ack until
* it's filled in).
*
* cx18_queue_get buf() will detect the lost buffers
* and send them back to q_free for fw rotation eventually.
*/
if ((order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) &&
!(id >= s->mdl_offset &&
id < (s->mdl_offset + s->buffers))) {
CX18_WARN("Fell behind! Ignoring stale mailbox with "
" inconsistent data. Lost buffer for mailbox "
"seq no %d\n", mb->request);
break;
}
buf = cx18_queue_get_buf(s, id, mdl_ack->data_used);
CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, id);
if (buf == NULL) {
CX18_WARN("Could not find buf %d for stream %s\n",
id, s->name);
continue;
}
CX18_DEBUG_HI_DMA("%s recv bytesused = %d\n",
s->name, buf->bytesused);
if (s->type != CX18_ENC_STREAM_TYPE_TS)
cx18_enqueue(s, buf, &s->q_full);
else {
if (s->dvb.enabled)
dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
buf->bytesused);
cx18_enqueue(s, buf, &s->q_free);
}
}
/* Put as many buffers as possible back into fw use */
cx18_stream_load_fw_queue(s);
wake_up(&cx->dma_waitq);
if (s->id != -1)
wake_up(&s->waitq);
}
static void epu_debug(struct cx18 *cx, struct cx18_in_work_order *order)
{
char *p;
char *str = order->str;
CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
p = strchr(str, '.');
if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
CX18_INFO("FW version: %s\n", p - 1);
}
static void epu_cmd(struct cx18 *cx, struct cx18_in_work_order *order)
{
switch (order->rpu) {
case CPU:
{
switch (order->mb.cmd) {
case CX18_EPU_DMA_DONE:
epu_dma_done(cx, order);
break;
case CX18_EPU_DEBUG:
epu_debug(cx, order);
break;
default:
CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
order->mb.cmd);
break;
}
break;
}
case APU:
CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
order->mb.cmd);
break;
default:
break;
}
}
static
void free_in_work_order(struct cx18 *cx, struct cx18_in_work_order *order)
{
atomic_set(&order->pending, 0);
}
void cx18_in_work_handler(struct work_struct *work)
{
struct cx18_in_work_order *order =
container_of(work, struct cx18_in_work_order, work);
struct cx18 *cx = order->cx;
epu_cmd(cx, order);
free_in_work_order(cx, order);
}
/*
* Functions that run in an interrupt handling context
*/
static void mb_ack_irq(struct cx18 *cx, struct cx18_in_work_order *order)
{
struct cx18_mailbox __iomem *ack_mb;
u32 ack_irq, req;
switch (order->rpu) {
case APU:
ack_irq = IRQ_EPU_TO_APU_ACK;
ack_mb = &cx->scb->apu2epu_mb;
break;
case CPU:
ack_irq = IRQ_EPU_TO_CPU_ACK;
ack_mb = &cx->scb->cpu2epu_mb;
break;
default:
CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
order->rpu, order->mb.cmd);
return;
}
req = order->mb.request;
/* Don't ack if the RPU has gotten impatient and timed us out */
if (req != cx18_readl(cx, &ack_mb->request) ||
req == cx18_readl(cx, &ack_mb->ack)) {
CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
"incoming %s to EPU mailbox (sequence no. %u) "
"while processing\n",
rpu_str[order->rpu], rpu_str[order->rpu], req);
order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
return;
}
cx18_writel(cx, req, &ack_mb->ack);
cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
return;
}
static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order)
{
u32 handle, mdl_ack_offset, mdl_ack_count;
struct cx18_mailbox *mb;
mb = &order->mb;
handle = mb->args[0];
mdl_ack_offset = mb->args[1];
mdl_ack_count = mb->args[2];
if (handle == CX18_INVALID_TASK_HANDLE ||
mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
mb_ack_irq(cx, order);
return -1;
}
cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset,
sizeof(struct cx18_mdl_ack) * mdl_ack_count);
if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
mb_ack_irq(cx, order);
return 1;
}
static
int epu_debug_irq(struct cx18 *cx, struct cx18_in_work_order *order)
{
u32 str_offset;
char *str = order->str;
str[0] = '\0';
str_offset = order->mb.args[1];
if (str_offset) {
cx18_setup_page(cx, str_offset);
cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
str[252] = '\0';
cx18_setup_page(cx, SCB_OFFSET);
}
if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
mb_ack_irq(cx, order);
return str_offset ? 1 : 0;
}
static inline
int epu_cmd_irq(struct cx18 *cx, struct cx18_in_work_order *order)
{
int ret = -1;
switch (order->rpu) {
case CPU:
{
switch (order->mb.cmd) {
case CX18_EPU_DMA_DONE:
ret = epu_dma_done_irq(cx, order);
break;
case CX18_EPU_DEBUG:
ret = epu_debug_irq(cx, order);
break;
default:
CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
order->mb.cmd);
break;
}
break;
}
case APU:
CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
order->mb.cmd);
break;
default:
break;
}
return ret;
}
static inline
struct cx18_in_work_order *alloc_in_work_order_irq(struct cx18 *cx)
{
int i;
struct cx18_in_work_order *order = NULL;
for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++) {
/*
* We only need "pending" atomic to inspect its contents,
* and need not do a check and set because:
* 1. Any work handler thread only clears "pending" and only
* on one, particular work order at a time, per handler thread.
* 2. "pending" is only set here, and we're serialized because
* we're called in an IRQ handler context.
*/
if (atomic_read(&cx->in_work_order[i].pending) == 0) {
order = &cx->in_work_order[i];
atomic_set(&order->pending, 1);
break;
}
}
return order;
}
void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
{
struct cx18_mailbox __iomem *mb;
struct cx18_mailbox *order_mb;
struct cx18_in_work_order *order;
int submit;
switch (rpu) {
case CPU:
mb = &cx->scb->cpu2epu_mb;
break;
case APU:
mb = &cx->scb->apu2epu_mb;
break;
default:
return;
}
order = alloc_in_work_order_irq(cx);
if (order == NULL) {
CX18_WARN("Unable to find blank work order form to schedule "
"incoming mailbox command processing\n");
return;
}
order->flags = 0;
order->rpu = rpu;
order_mb = &order->mb;
/* mb->cmd and mb->args[0] through mb->args[2] */
cx18_memcpy_fromio(cx, &order_mb->cmd, &mb->cmd, 4 * sizeof(u32));
/* mb->request and mb->ack. N.B. we want to read mb->ack last */
cx18_memcpy_fromio(cx, &order_mb->request, &mb->request,
2 * sizeof(u32));
if (order_mb->request == order_mb->ack) {
CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
"incoming %s to EPU mailbox (sequence no. %u)"
"\n",
rpu_str[rpu], rpu_str[rpu], order_mb->request);
if (cx18_debug & CX18_DBGFLG_WARN)
dump_mb(cx, order_mb, "incoming");
order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
}
/*
* Individual EPU command processing is responsible for ack-ing
* a non-stale mailbox as soon as possible
*/
submit = epu_cmd_irq(cx, order);
if (submit > 0) {
queue_work(cx->in_work_queue, &order->work);
}
}
/*
* Functions called from a non-interrupt, non work_queue context
*/
static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
{
const struct cx18_api_info *info = find_api_info(cmd);
u32 state, irq, req, ack, err;
struct cx18_mailbox __iomem *mb;
u32 __iomem *xpu_state;
wait_queue_head_t *waitq;
struct mutex *mb_lock;
unsigned long int t0, timeout, ret;
int i;
char argstr[MAX_MB_ARGUMENTS*11+1];
DEFINE_WAIT(w);
if (info == NULL) {
CX18_WARN("unknown cmd %x\n", cmd);
return -EINVAL;
}
if (cx18_debug & CX18_DBGFLG_API) { /* only call u32arr2hex if needed */
if (cmd == CX18_CPU_DE_SET_MDL) {
if (cx18_debug & CX18_DBGFLG_HIGHVOL)
CX18_DEBUG_HI_API("%s\tcmd %#010x args%s\n",
info->name, cmd,
u32arr2hex(data, args, argstr));
} else
CX18_DEBUG_API("%s\tcmd %#010x args%s\n",
info->name, cmd,
u32arr2hex(data, args, argstr));
}
switch (info->rpu) {
case APU:
waitq = &cx->mb_apu_waitq;
mb_lock = &cx->epu2apu_mb_lock;
irq = IRQ_EPU_TO_APU;
mb = &cx->scb->epu2apu_mb;
xpu_state = &cx->scb->apu_state;
break;
case CPU:
waitq = &cx->mb_cpu_waitq;
mb_lock = &cx->epu2cpu_mb_lock;
irq = IRQ_EPU_TO_CPU;
mb = &cx->scb->epu2cpu_mb;
xpu_state = &cx->scb->cpu_state;
break;
default:
CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
return -EINVAL;
}
mutex_lock(mb_lock);
/*
* Wait for an in-use mailbox to complete
*
* If the XPU is responding with Ack's, the mailbox shouldn't be in
* a busy state, since we serialize access to it on our end.
*
* If the wait for ack after sending a previous command was interrupted
* by a signal, we may get here and find a busy mailbox. After waiting,
* mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
*/
state = cx18_readl(cx, xpu_state);
req = cx18_readl(cx, &mb->request);
timeout = msecs_to_jiffies(10);
ret = wait_event_timeout(*waitq,
(ack = cx18_readl(cx, &mb->ack)) == req,
timeout);
if (req != ack) {
/* waited long enough, make the mbox "not busy" from our end */
cx18_writel(cx, req, &mb->ack);
CX18_ERR("mbox was found stuck busy when setting up for %s; "
"clearing busy and trying to proceed\n", info->name);
} else if (ret != timeout)
CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n",
jiffies_to_msecs(timeout-ret));
/* Build the outgoing mailbox */
req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
cx18_writel(cx, cmd, &mb->cmd);
for (i = 0; i < args; i++)
cx18_writel(cx, data[i], &mb->args[i]);
cx18_writel(cx, 0, &mb->error);
cx18_writel(cx, req, &mb->request);
cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
/*
* Notify the XPU and wait for it to send an Ack back
*/
timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20);
CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
irq, info->name);
/* So we don't miss the wakeup, prepare to wait before notifying fw */
prepare_to_wait(waitq, &w, TASK_UNINTERRUPTIBLE);
cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
t0 = jiffies;
ack = cx18_readl(cx, &mb->ack);
if (ack != req) {
schedule_timeout(timeout);
ret = jiffies - t0;
ack = cx18_readl(cx, &mb->ack);
} else {
ret = jiffies - t0;
}
finish_wait(waitq, &w);
if (req != ack) {
mutex_unlock(mb_lock);
if (ret >= timeout) {
/* Timed out */
CX18_DEBUG_WARN("sending %s timed out waiting %d msecs "
"for RPU acknowledgement\n",
info->name, jiffies_to_msecs(ret));
} else {
CX18_DEBUG_WARN("woken up before mailbox ack was ready "
"after submitting %s to RPU. only "
"waited %d msecs on req %u but awakened"
" with unmatched ack %u\n",
info->name,
jiffies_to_msecs(ret),
req, ack);
}
return -EINVAL;
}
if (ret >= timeout)
CX18_DEBUG_WARN("failed to be awakened upon RPU acknowledgment "
"sending %s; timed out waiting %d msecs\n",
info->name, jiffies_to_msecs(ret));
else
CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
jiffies_to_msecs(ret), info->name);
/* Collect data returned by the XPU */
for (i = 0; i < MAX_MB_ARGUMENTS; i++)
data[i] = cx18_readl(cx, &mb->args[i]);
err = cx18_readl(cx, &mb->error);
mutex_unlock(mb_lock);
/*
* Wait for XPU to perform extra actions for the caller in some cases.
* e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all buffers
* back in a burst shortly thereafter
*/
if (info->flags & API_SLOW)
cx18_msleep_timeout(300, 0);
if (err)
CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
info->name);
return err ? -EIO : 0;
}
int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
{
return cx18_api_call(cx, cmd, args, data);
}
static int cx18_set_filter_param(struct cx18_stream *s)
{
struct cx18 *cx = s->cx;
u32 mode;
int ret;
mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
s->handle, 1, mode, cx->spatial_strength);
mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
s->handle, 0, mode, cx->temporal_strength);
ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
s->handle, 2, cx->filter_mode >> 2, 0);
return ret;
}
int cx18_api_func(void *priv, u32 cmd, int in, int out,
u32 data[CX2341X_MBOX_MAX_DATA])
{
struct cx18_api_func_private *api_priv = priv;
struct cx18 *cx = api_priv->cx;
struct cx18_stream *s = api_priv->s;
switch (cmd) {
case CX2341X_ENC_SET_OUTPUT_PORT:
return 0;
case CX2341X_ENC_SET_FRAME_RATE:
return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
s->handle, 0, 0, 0, 0, data[0]);
case CX2341X_ENC_SET_FRAME_SIZE:
return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
s->handle, data[1], data[0]);
case CX2341X_ENC_SET_STREAM_TYPE:
return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
s->handle, data[0]);
case CX2341X_ENC_SET_ASPECT_RATIO:
return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
s->handle, data[0]);
case CX2341X_ENC_SET_GOP_PROPERTIES:
return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
s->handle, data[0], data[1]);
case CX2341X_ENC_SET_GOP_CLOSURE:
return 0;
case CX2341X_ENC_SET_AUDIO_PROPERTIES:
return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
s->handle, data[0]);
case CX2341X_ENC_MUTE_AUDIO:
return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
s->handle, data[0]);
case CX2341X_ENC_SET_BIT_RATE:
return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
s->handle, data[0], data[1], data[2], data[3]);
case CX2341X_ENC_MUTE_VIDEO:
return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
s->handle, data[0]);
case CX2341X_ENC_SET_FRAME_DROP_RATE:
return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
s->handle, data[0]);
case CX2341X_ENC_MISC:
return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
s->handle, data[0], data[1], data[2]);
case CX2341X_ENC_SET_DNR_FILTER_MODE:
cx->filter_mode = (data[0] & 3) | (data[1] << 2);
return cx18_set_filter_param(s);
case CX2341X_ENC_SET_DNR_FILTER_PROPS:
cx->spatial_strength = data[0];
cx->temporal_strength = data[1];
return cx18_set_filter_param(s);
case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
s->handle, data[0], data[1]);
case CX2341X_ENC_SET_CORING_LEVELS:
return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
s->handle, data[0], data[1], data[2], data[3]);
}
CX18_WARN("Unknown cmd %x\n", cmd);
return 0;
}
int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
u32 cmd, int args, ...)
{
va_list ap;
int i;
va_start(ap, args);
for (i = 0; i < args; i++)
data[i] = va_arg(ap, u32);
va_end(ap);
return cx18_api(cx, cmd, args, data);
}
int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
{
u32 data[MAX_MB_ARGUMENTS];
va_list ap;
int i;
if (cx == NULL) {
CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
return 0;
}
if (args > MAX_MB_ARGUMENTS) {
CX18_ERR("args too big (cmd=%x)\n", cmd);
args = MAX_MB_ARGUMENTS;
}
va_start(ap, args);
for (i = 0; i < args; i++)
data[i] = va_arg(ap, u32);
va_end(ap);
return cx18_api(cx, cmd, args, data);
}

100
kernel/drivers/media/video/cx18/cx18-mailbox.h Normal file
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/*
* cx18 mailbox functions
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#ifndef _CX18_MAILBOX_H_
#define _CX18_MAILBOX_H_
/* mailbox max args */
#define MAX_MB_ARGUMENTS 6
/* compatibility, should be same as the define in cx2341x.h */
#define CX2341X_MBOX_MAX_DATA 16
#define MB_RESERVED_HANDLE_0 0
#define MB_RESERVED_HANDLE_1 0xFFFFFFFF
#define APU 0
#define CPU 1
#define EPU 2
#define HPU 3
struct cx18;
/*
* This structure is used by CPU to provide completed buffers information
* Its structure is dictrated by the layout of the SCB, required by the
* firmware, but its defintion needs to be here, instead of in cx18-scb.h,
* for mailbox work order scheduling
*/
struct cx18_mdl_ack {
u32 id; /* ID of a completed MDL */
u32 data_used; /* Total data filled in the MDL for buffer 'id' */
};
/* The cx18_mailbox struct is the mailbox structure which is used for passing
messages between processors */
struct cx18_mailbox {
/* The sender sets a handle in 'request' after he fills the command. The
'request' should be different than 'ack'. The sender, also, generates
an interrupt on XPU2YPU_irq where XPU is the sender and YPU is the
receiver. */
u32 request;
/* The receiver detects a new command when 'req' is different than 'ack'.
He sets 'ack' to the same value as 'req' to clear the command. He, also,
generates an interrupt on YPU2XPU_irq where XPU is the sender and YPU
is the receiver. */
u32 ack;
u32 reserved[6];
/* 'cmd' identifies the command. The list of these commands are in
cx23418.h */
u32 cmd;
/* Each command can have up to 6 arguments */
u32 args[MAX_MB_ARGUMENTS];
/* The return code can be one of the codes in the file cx23418.h. If the
command is completed successfuly, the error will be ERR_SYS_SUCCESS.
If it is pending, the code is ERR_SYS_PENDING. If it failed, the error
code would indicate the task from which the error originated and will
be one of the errors in cx23418.h. In that case, the following
applies ((error & 0xff) != 0).
If the command is pending, the return will be passed in a MB from the
receiver to the sender. 'req' will be returned in args[0] */
u32 error;
};
struct cx18_stream;
struct cx18_api_func_private {
struct cx18 *cx;
struct cx18_stream *s;
};
int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[]);
int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS], u32 cmd,
int args, ...);
int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...);
int cx18_api_func(void *priv, u32 cmd, int in, int out,
u32 data[CX2341X_MBOX_MAX_DATA]);
void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu);
void cx18_in_work_handler(struct work_struct *work);
#endif

252
kernel/drivers/media/video/cx18/cx18-queue.c Normal file
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/*
* cx18 buffer queues
*
* Derived from ivtv-queue.c
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include "cx18-driver.h"
#include "cx18-queue.h"
#include "cx18-streams.h"
#include "cx18-scb.h"
void cx18_buf_swap(struct cx18_buffer *buf)
{
int i;
for (i = 0; i < buf->bytesused; i += 4)
swab32s((u32 *)(buf->buf + i));
}
void cx18_queue_init(struct cx18_queue *q)
{
INIT_LIST_HEAD(&q->list);
atomic_set(&q->buffers, 0);
q->bytesused = 0;
}
struct cx18_queue *_cx18_enqueue(struct cx18_stream *s, struct cx18_buffer *buf,
struct cx18_queue *q, int to_front)
{
/* clear the buffer if it is not to be enqueued to the full queue */
if (q != &s->q_full) {
buf->bytesused = 0;
buf->readpos = 0;
buf->b_flags = 0;
buf->skipped = 0;
}
/* q_busy is restricted to a max buffer count imposed by firmware */
if (q == &s->q_busy &&
atomic_read(&q->buffers) >= CX18_MAX_FW_MDLS_PER_STREAM)
q = &s->q_free;
spin_lock(&q->lock);
if (to_front)
list_add(&buf->list, &q->list); /* LIFO */
else
list_add_tail(&buf->list, &q->list); /* FIFO */
q->bytesused += buf->bytesused - buf->readpos;
atomic_inc(&q->buffers);
spin_unlock(&q->lock);
return q;
}
struct cx18_buffer *cx18_dequeue(struct cx18_stream *s, struct cx18_queue *q)
{
struct cx18_buffer *buf = NULL;
spin_lock(&q->lock);
if (!list_empty(&q->list)) {
buf = list_first_entry(&q->list, struct cx18_buffer, list);
list_del_init(&buf->list);
q->bytesused -= buf->bytesused - buf->readpos;
buf->skipped = 0;
atomic_dec(&q->buffers);
}
spin_unlock(&q->lock);
return buf;
}
struct cx18_buffer *cx18_queue_get_buf(struct cx18_stream *s, u32 id,
u32 bytesused)
{
struct cx18 *cx = s->cx;
struct cx18_buffer *buf;
struct cx18_buffer *tmp;
struct cx18_buffer *ret = NULL;
LIST_HEAD(sweep_up);
/*
* We don't have to acquire multiple q locks here, because we are
* serialized by the single threaded work handler.
* Buffers from the firmware will thus remain in order as
* they are moved from q_busy to q_full or to the dvb ring buffer.
*/
spin_lock(&s->q_busy.lock);
list_for_each_entry_safe(buf, tmp, &s->q_busy.list, list) {
/*
* We should find what the firmware told us is done,
* right at the front of the queue. If we don't, we likely have
* missed a buffer done message from the firmware.
* Once we skip a buffer repeatedly, relative to the size of
* q_busy, we have high confidence we've missed it.
*/
if (buf->id != id) {
buf->skipped++;
if (buf->skipped >= atomic_read(&s->q_busy.buffers)-1) {
/* buffer must have fallen out of rotation */
CX18_WARN("Skipped %s, buffer %d, %d "
"times - it must have dropped out of "
"rotation\n", s->name, buf->id,
buf->skipped);
/* Sweep it up to put it back into rotation */
list_move_tail(&buf->list, &sweep_up);
atomic_dec(&s->q_busy.buffers);
}
continue;
}
/*
* We pull the desired buffer off of the queue here. Something
* will have to put it back on a queue later.
*/
list_del_init(&buf->list);
atomic_dec(&s->q_busy.buffers);
ret = buf;
break;
}
spin_unlock(&s->q_busy.lock);
/*
* We found the buffer for which we were looking. Get it ready for
* the caller to put on q_full or in the dvb ring buffer.
*/
if (ret != NULL) {
ret->bytesused = bytesused;
ret->skipped = 0;
/* readpos and b_flags were 0'ed when the buf went on q_busy */
cx18_buf_sync_for_cpu(s, ret);
if (s->type != CX18_ENC_STREAM_TYPE_TS)
set_bit(CX18_F_B_NEED_BUF_SWAP, &ret->b_flags);
}
/* Put any buffers the firmware is ignoring back into normal rotation */
list_for_each_entry_safe(buf, tmp, &sweep_up, list) {
list_del_init(&buf->list);
cx18_enqueue(s, buf, &s->q_free);
}
return ret;
}
/* Move all buffers of a queue to q_free, while flushing the buffers */
static void cx18_queue_flush(struct cx18_stream *s, struct cx18_queue *q)
{
struct cx18_buffer *buf;
if (q == &s->q_free)
return;
spin_lock(&q->lock);
while (!list_empty(&q->list)) {
buf = list_first_entry(&q->list, struct cx18_buffer, list);
list_move_tail(&buf->list, &s->q_free.list);
buf->bytesused = buf->readpos = buf->b_flags = buf->skipped = 0;
atomic_inc(&s->q_free.buffers);
}
cx18_queue_init(q);
spin_unlock(&q->lock);
}
void cx18_flush_queues(struct cx18_stream *s)
{
cx18_queue_flush(s, &s->q_busy);
cx18_queue_flush(s, &s->q_full);
}
int cx18_stream_alloc(struct cx18_stream *s)
{
struct cx18 *cx = s->cx;
int i;
if (s->buffers == 0)
return 0;
CX18_DEBUG_INFO("Allocate %s stream: %d x %d buffers (%dkB total)\n",
s->name, s->buffers, s->buf_size,
s->buffers * s->buf_size / 1024);
if (((char __iomem *)&cx->scb->cpu_mdl[cx->mdl_offset + s->buffers] -
(char __iomem *)cx->scb) > SCB_RESERVED_SIZE) {
unsigned bufsz = (((char __iomem *)cx->scb) + SCB_RESERVED_SIZE -
((char __iomem *)cx->scb->cpu_mdl));
CX18_ERR("Too many buffers, cannot fit in SCB area\n");
CX18_ERR("Max buffers = %zd\n",
bufsz / sizeof(struct cx18_mdl));
return -ENOMEM;
}
s->mdl_offset = cx->mdl_offset;
/* allocate stream buffers. Initially all buffers are in q_free. */
for (i = 0; i < s->buffers; i++) {
struct cx18_buffer *buf = kzalloc(sizeof(struct cx18_buffer),
GFP_KERNEL|__GFP_NOWARN);
if (buf == NULL)
break;
buf->buf = kmalloc(s->buf_size, GFP_KERNEL|__GFP_NOWARN);
if (buf->buf == NULL) {
kfree(buf);
break;
}
buf->id = cx->buffer_id++;
INIT_LIST_HEAD(&buf->list);
buf->dma_handle = pci_map_single(s->cx->pci_dev,
buf->buf, s->buf_size, s->dma);
cx18_buf_sync_for_cpu(s, buf);
cx18_enqueue(s, buf, &s->q_free);
}
if (i == s->buffers) {
cx->mdl_offset += s->buffers;
return 0;
}
CX18_ERR("Couldn't allocate buffers for %s stream\n", s->name);
cx18_stream_free(s);
return -ENOMEM;
}
void cx18_stream_free(struct cx18_stream *s)
{
struct cx18_buffer *buf;
/* move all buffers to q_free */
cx18_flush_queues(s);
/* empty q_free */
while ((buf = cx18_dequeue(s, &s->q_free))) {
pci_unmap_single(s->cx->pci_dev, buf->dma_handle,
s->buf_size, s->dma);
kfree(buf->buf);
kfree(buf);
}
}

71
kernel/drivers/media/video/cx18/cx18-queue.h Normal file
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/*
* cx18 buffer queues
*
* Derived from ivtv-queue.h
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#define CX18_DMA_UNMAPPED ((u32) -1)
/* cx18_buffer utility functions */
static inline void cx18_buf_sync_for_cpu(struct cx18_stream *s,
struct cx18_buffer *buf)
{
pci_dma_sync_single_for_cpu(s->cx->pci_dev, buf->dma_handle,
s->buf_size, s->dma);
}
static inline void cx18_buf_sync_for_device(struct cx18_stream *s,
struct cx18_buffer *buf)
{
pci_dma_sync_single_for_device(s->cx->pci_dev, buf->dma_handle,
s->buf_size, s->dma);
}
void cx18_buf_swap(struct cx18_buffer *buf);
/* cx18_queue utility functions */
struct cx18_queue *_cx18_enqueue(struct cx18_stream *s, struct cx18_buffer *buf,
struct cx18_queue *q, int to_front);
static inline
struct cx18_queue *cx18_enqueue(struct cx18_stream *s, struct cx18_buffer *buf,
struct cx18_queue *q)
{
return _cx18_enqueue(s, buf, q, 0); /* FIFO */
}
static inline
struct cx18_queue *cx18_push(struct cx18_stream *s, struct cx18_buffer *buf,
struct cx18_queue *q)
{
return _cx18_enqueue(s, buf, q, 1); /* LIFO */
}
void cx18_queue_init(struct cx18_queue *q);
struct cx18_buffer *cx18_dequeue(struct cx18_stream *s, struct cx18_queue *q);
struct cx18_buffer *cx18_queue_get_buf(struct cx18_stream *s, u32 id,
u32 bytesused);
void cx18_flush_queues(struct cx18_stream *s);
/* cx18_stream utility functions */
int cx18_stream_alloc(struct cx18_stream *s);
void cx18_stream_free(struct cx18_stream *s);

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kernel/drivers/media/video/cx18/cx18-scb.c Normal file
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/*
* cx18 System Control Block initialization
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-scb.h"
void cx18_init_scb(struct cx18 *cx)
{
cx18_setup_page(cx, SCB_OFFSET);
cx18_memset_io(cx, cx->scb, 0, 0x10000);
cx18_writel(cx, IRQ_APU_TO_CPU, &cx->scb->apu2cpu_irq);
cx18_writel(cx, IRQ_CPU_TO_APU_ACK, &cx->scb->cpu2apu_irq_ack);
cx18_writel(cx, IRQ_HPU_TO_CPU, &cx->scb->hpu2cpu_irq);
cx18_writel(cx, IRQ_CPU_TO_HPU_ACK, &cx->scb->cpu2hpu_irq_ack);
cx18_writel(cx, IRQ_PPU_TO_CPU, &cx->scb->ppu2cpu_irq);
cx18_writel(cx, IRQ_CPU_TO_PPU_ACK, &cx->scb->cpu2ppu_irq_ack);
cx18_writel(cx, IRQ_EPU_TO_CPU, &cx->scb->epu2cpu_irq);
cx18_writel(cx, IRQ_CPU_TO_EPU_ACK, &cx->scb->cpu2epu_irq_ack);
cx18_writel(cx, IRQ_CPU_TO_APU, &cx->scb->cpu2apu_irq);
cx18_writel(cx, IRQ_APU_TO_CPU_ACK, &cx->scb->apu2cpu_irq_ack);
cx18_writel(cx, IRQ_HPU_TO_APU, &cx->scb->hpu2apu_irq);
cx18_writel(cx, IRQ_APU_TO_HPU_ACK, &cx->scb->apu2hpu_irq_ack);
cx18_writel(cx, IRQ_PPU_TO_APU, &cx->scb->ppu2apu_irq);
cx18_writel(cx, IRQ_APU_TO_PPU_ACK, &cx->scb->apu2ppu_irq_ack);
cx18_writel(cx, IRQ_EPU_TO_APU, &cx->scb->epu2apu_irq);
cx18_writel(cx, IRQ_APU_TO_EPU_ACK, &cx->scb->apu2epu_irq_ack);
cx18_writel(cx, IRQ_CPU_TO_HPU, &cx->scb->cpu2hpu_irq);
cx18_writel(cx, IRQ_HPU_TO_CPU_ACK, &cx->scb->hpu2cpu_irq_ack);
cx18_writel(cx, IRQ_APU_TO_HPU, &cx->scb->apu2hpu_irq);
cx18_writel(cx, IRQ_HPU_TO_APU_ACK, &cx->scb->hpu2apu_irq_ack);
cx18_writel(cx, IRQ_PPU_TO_HPU, &cx->scb->ppu2hpu_irq);
cx18_writel(cx, IRQ_HPU_TO_PPU_ACK, &cx->scb->hpu2ppu_irq_ack);
cx18_writel(cx, IRQ_EPU_TO_HPU, &cx->scb->epu2hpu_irq);
cx18_writel(cx, IRQ_HPU_TO_EPU_ACK, &cx->scb->hpu2epu_irq_ack);
cx18_writel(cx, IRQ_CPU_TO_PPU, &cx->scb->cpu2ppu_irq);
cx18_writel(cx, IRQ_PPU_TO_CPU_ACK, &cx->scb->ppu2cpu_irq_ack);
cx18_writel(cx, IRQ_APU_TO_PPU, &cx->scb->apu2ppu_irq);
cx18_writel(cx, IRQ_PPU_TO_APU_ACK, &cx->scb->ppu2apu_irq_ack);
cx18_writel(cx, IRQ_HPU_TO_PPU, &cx->scb->hpu2ppu_irq);
cx18_writel(cx, IRQ_PPU_TO_HPU_ACK, &cx->scb->ppu2hpu_irq_ack);
cx18_writel(cx, IRQ_EPU_TO_PPU, &cx->scb->epu2ppu_irq);
cx18_writel(cx, IRQ_PPU_TO_EPU_ACK, &cx->scb->ppu2epu_irq_ack);
cx18_writel(cx, IRQ_CPU_TO_EPU, &cx->scb->cpu2epu_irq);
cx18_writel(cx, IRQ_EPU_TO_CPU_ACK, &cx->scb->epu2cpu_irq_ack);
cx18_writel(cx, IRQ_APU_TO_EPU, &cx->scb->apu2epu_irq);
cx18_writel(cx, IRQ_EPU_TO_APU_ACK, &cx->scb->epu2apu_irq_ack);
cx18_writel(cx, IRQ_HPU_TO_EPU, &cx->scb->hpu2epu_irq);
cx18_writel(cx, IRQ_EPU_TO_HPU_ACK, &cx->scb->epu2hpu_irq_ack);
cx18_writel(cx, IRQ_PPU_TO_EPU, &cx->scb->ppu2epu_irq);
cx18_writel(cx, IRQ_EPU_TO_PPU_ACK, &cx->scb->epu2ppu_irq_ack);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2cpu_mb),
&cx->scb->apu2cpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2cpu_mb),
&cx->scb->hpu2cpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2cpu_mb),
&cx->scb->ppu2cpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2cpu_mb),
&cx->scb->epu2cpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2apu_mb),
&cx->scb->cpu2apu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2apu_mb),
&cx->scb->hpu2apu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2apu_mb),
&cx->scb->ppu2apu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2apu_mb),
&cx->scb->epu2apu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2hpu_mb),
&cx->scb->cpu2hpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2hpu_mb),
&cx->scb->apu2hpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2hpu_mb),
&cx->scb->ppu2hpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2hpu_mb),
&cx->scb->epu2hpu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2ppu_mb),
&cx->scb->cpu2ppu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2ppu_mb),
&cx->scb->apu2ppu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2ppu_mb),
&cx->scb->hpu2ppu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2ppu_mb),
&cx->scb->epu2ppu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2epu_mb),
&cx->scb->cpu2epu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2epu_mb),
&cx->scb->apu2epu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2epu_mb),
&cx->scb->hpu2epu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2epu_mb),
&cx->scb->ppu2epu_mb_offset);
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu_state),
&cx->scb->ipc_offset);
cx18_writel(cx, 1, &cx->scb->epu_state);
}

280
kernel/drivers/media/video/cx18/cx18-scb.h Normal file
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/*
* cx18 System Control Block initialization
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#ifndef CX18_SCB_H
#define CX18_SCB_H
#include "cx18-mailbox.h"
/* NOTE: All ACK interrupts are in the SW2 register. All non-ACK interrupts
are in the SW1 register. */
#define IRQ_APU_TO_CPU 0x00000001
#define IRQ_CPU_TO_APU_ACK 0x00000001
#define IRQ_HPU_TO_CPU 0x00000002
#define IRQ_CPU_TO_HPU_ACK 0x00000002
#define IRQ_PPU_TO_CPU 0x00000004
#define IRQ_CPU_TO_PPU_ACK 0x00000004
#define IRQ_EPU_TO_CPU 0x00000008
#define IRQ_CPU_TO_EPU_ACK 0x00000008
#define IRQ_CPU_TO_APU 0x00000010
#define IRQ_APU_TO_CPU_ACK 0x00000010
#define IRQ_HPU_TO_APU 0x00000020
#define IRQ_APU_TO_HPU_ACK 0x00000020
#define IRQ_PPU_TO_APU 0x00000040
#define IRQ_APU_TO_PPU_ACK 0x00000040
#define IRQ_EPU_TO_APU 0x00000080
#define IRQ_APU_TO_EPU_ACK 0x00000080
#define IRQ_CPU_TO_HPU 0x00000100
#define IRQ_HPU_TO_CPU_ACK 0x00000100
#define IRQ_APU_TO_HPU 0x00000200
#define IRQ_HPU_TO_APU_ACK 0x00000200
#define IRQ_PPU_TO_HPU 0x00000400
#define IRQ_HPU_TO_PPU_ACK 0x00000400
#define IRQ_EPU_TO_HPU 0x00000800
#define IRQ_HPU_TO_EPU_ACK 0x00000800
#define IRQ_CPU_TO_PPU 0x00001000
#define IRQ_PPU_TO_CPU_ACK 0x00001000
#define IRQ_APU_TO_PPU 0x00002000
#define IRQ_PPU_TO_APU_ACK 0x00002000
#define IRQ_HPU_TO_PPU 0x00004000
#define IRQ_PPU_TO_HPU_ACK 0x00004000
#define IRQ_EPU_TO_PPU 0x00008000
#define IRQ_PPU_TO_EPU_ACK 0x00008000
#define IRQ_CPU_TO_EPU 0x00010000
#define IRQ_EPU_TO_CPU_ACK 0x00010000
#define IRQ_APU_TO_EPU 0x00020000
#define IRQ_EPU_TO_APU_ACK 0x00020000
#define IRQ_HPU_TO_EPU 0x00040000
#define IRQ_EPU_TO_HPU_ACK 0x00040000
#define IRQ_PPU_TO_EPU 0x00080000
#define IRQ_EPU_TO_PPU_ACK 0x00080000
#define SCB_OFFSET 0xDC0000
/* If Firmware uses fixed memory map, it shall not allocate the area
between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */
#define SCB_RESERVED_SIZE 0x10000
/* This structure is used by EPU to provide memory descriptors in its memory */
struct cx18_mdl {
u32 paddr; /* Physical address of a buffer segment */
u32 length; /* Length of the buffer segment */
};
struct cx18_scb {
/* These fields form the System Control Block which is used at boot time
for localizing the IPC data as well as the code positions for all
processors. The offsets are from the start of this struct. */
/* Offset where to find the Inter-Processor Communication data */
u32 ipc_offset;
u32 reserved01[7];
/* Offset where to find the start of the CPU code */
u32 cpu_code_offset;
u32 reserved02[3];
/* Offset where to find the start of the APU code */
u32 apu_code_offset;
u32 reserved03[3];
/* Offset where to find the start of the HPU code */
u32 hpu_code_offset;
u32 reserved04[3];
/* Offset where to find the start of the PPU code */
u32 ppu_code_offset;
u32 reserved05[3];
/* These fields form Inter-Processor Communication data which is used
by all processors to locate the information needed for communicating
with other processors */
/* Fields for CPU: */
/* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
u32 cpu_state;
u32 reserved1[7];
/* Offset to the mailbox used for sending commands from APU to CPU */
u32 apu2cpu_mb_offset;
/* Value to write to register SW1 register set (0xC7003100) after the
command is ready */
u32 apu2cpu_irq;
/* Value to write to register SW2 register set (0xC7003140) after the
command is cleared */
u32 cpu2apu_irq_ack;
u32 reserved2[13];
u32 hpu2cpu_mb_offset;
u32 hpu2cpu_irq;
u32 cpu2hpu_irq_ack;
u32 reserved3[13];
u32 ppu2cpu_mb_offset;
u32 ppu2cpu_irq;
u32 cpu2ppu_irq_ack;
u32 reserved4[13];
u32 epu2cpu_mb_offset;
u32 epu2cpu_irq;
u32 cpu2epu_irq_ack;
u32 reserved5[13];
u32 reserved6[8];
/* Fields for APU: */
u32 apu_state;
u32 reserved11[7];
u32 cpu2apu_mb_offset;
u32 cpu2apu_irq;
u32 apu2cpu_irq_ack;
u32 reserved12[13];
u32 hpu2apu_mb_offset;
u32 hpu2apu_irq;
u32 apu2hpu_irq_ack;
u32 reserved13[13];
u32 ppu2apu_mb_offset;
u32 ppu2apu_irq;
u32 apu2ppu_irq_ack;
u32 reserved14[13];
u32 epu2apu_mb_offset;
u32 epu2apu_irq;
u32 apu2epu_irq_ack;
u32 reserved15[13];
u32 reserved16[8];
/* Fields for HPU: */
u32 hpu_state;
u32 reserved21[7];
u32 cpu2hpu_mb_offset;
u32 cpu2hpu_irq;
u32 hpu2cpu_irq_ack;
u32 reserved22[13];
u32 apu2hpu_mb_offset;
u32 apu2hpu_irq;
u32 hpu2apu_irq_ack;
u32 reserved23[13];
u32 ppu2hpu_mb_offset;
u32 ppu2hpu_irq;
u32 hpu2ppu_irq_ack;
u32 reserved24[13];
u32 epu2hpu_mb_offset;
u32 epu2hpu_irq;
u32 hpu2epu_irq_ack;
u32 reserved25[13];
u32 reserved26[8];
/* Fields for PPU: */
u32 ppu_state;
u32 reserved31[7];
u32 cpu2ppu_mb_offset;
u32 cpu2ppu_irq;
u32 ppu2cpu_irq_ack;
u32 reserved32[13];
u32 apu2ppu_mb_offset;
u32 apu2ppu_irq;
u32 ppu2apu_irq_ack;
u32 reserved33[13];
u32 hpu2ppu_mb_offset;
u32 hpu2ppu_irq;
u32 ppu2hpu_irq_ack;
u32 reserved34[13];
u32 epu2ppu_mb_offset;
u32 epu2ppu_irq;
u32 ppu2epu_irq_ack;
u32 reserved35[13];
u32 reserved36[8];
/* Fields for EPU: */
u32 epu_state;
u32 reserved41[7];
u32 cpu2epu_mb_offset;
u32 cpu2epu_irq;
u32 epu2cpu_irq_ack;
u32 reserved42[13];
u32 apu2epu_mb_offset;
u32 apu2epu_irq;
u32 epu2apu_irq_ack;
u32 reserved43[13];
u32 hpu2epu_mb_offset;
u32 hpu2epu_irq;
u32 epu2hpu_irq_ack;
u32 reserved44[13];
u32 ppu2epu_mb_offset;
u32 ppu2epu_irq;
u32 epu2ppu_irq_ack;
u32 reserved45[13];
u32 reserved46[8];
u32 semaphores[8]; /* Semaphores */
u32 reserved50[32]; /* Reserved for future use */
struct cx18_mailbox apu2cpu_mb;
struct cx18_mailbox hpu2cpu_mb;
struct cx18_mailbox ppu2cpu_mb;
struct cx18_mailbox epu2cpu_mb;
struct cx18_mailbox cpu2apu_mb;
struct cx18_mailbox hpu2apu_mb;
struct cx18_mailbox ppu2apu_mb;
struct cx18_mailbox epu2apu_mb;
struct cx18_mailbox cpu2hpu_mb;
struct cx18_mailbox apu2hpu_mb;
struct cx18_mailbox ppu2hpu_mb;
struct cx18_mailbox epu2hpu_mb;
struct cx18_mailbox cpu2ppu_mb;
struct cx18_mailbox apu2ppu_mb;
struct cx18_mailbox hpu2ppu_mb;
struct cx18_mailbox epu2ppu_mb;
struct cx18_mailbox cpu2epu_mb;
struct cx18_mailbox apu2epu_mb;
struct cx18_mailbox hpu2epu_mb;
struct cx18_mailbox ppu2epu_mb;
struct cx18_mdl_ack cpu_mdl_ack[CX18_MAX_STREAMS][CX18_MAX_MDL_ACKS];
struct cx18_mdl cpu_mdl[1];
};
void cx18_init_scb(struct cx18 *cx);
#endif

756
kernel/drivers/media/video/cx18/cx18-streams.c Normal file
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/*
* cx18 init/start/stop/exit stream functions
*
* Derived from ivtv-streams.c
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-fileops.h"
#include "cx18-mailbox.h"
#include "cx18-i2c.h"
#include "cx18-queue.h"
#include "cx18-ioctl.h"
#include "cx18-streams.h"
#include "cx18-cards.h"
#include "cx18-scb.h"
#include "cx18-dvb.h"
#define CX18_DSP0_INTERRUPT_MASK 0xd0004C
static struct v4l2_file_operations cx18_v4l2_enc_fops = {
.owner = THIS_MODULE,
.read = cx18_v4l2_read,
.open = cx18_v4l2_open,
/* FIXME change to video_ioctl2 if serialization lock can be removed */
.ioctl = cx18_v4l2_ioctl,
.release = cx18_v4l2_close,
.poll = cx18_v4l2_enc_poll,
};
/* offset from 0 to register ts v4l2 minors on */
#define CX18_V4L2_ENC_TS_OFFSET 16
/* offset from 0 to register pcm v4l2 minors on */
#define CX18_V4L2_ENC_PCM_OFFSET 24
/* offset from 0 to register yuv v4l2 minors on */
#define CX18_V4L2_ENC_YUV_OFFSET 32
static struct {
const char *name;
int vfl_type;
int num_offset;
int dma;
enum v4l2_buf_type buf_type;
} cx18_stream_info[] = {
{ /* CX18_ENC_STREAM_TYPE_MPG */
"encoder MPEG",
VFL_TYPE_GRABBER, 0,
PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
},
{ /* CX18_ENC_STREAM_TYPE_TS */
"TS",
VFL_TYPE_GRABBER, -1,
PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
},
{ /* CX18_ENC_STREAM_TYPE_YUV */
"encoder YUV",
VFL_TYPE_GRABBER, CX18_V4L2_ENC_YUV_OFFSET,
PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
},
{ /* CX18_ENC_STREAM_TYPE_VBI */
"encoder VBI",
VFL_TYPE_VBI, 0,
PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VBI_CAPTURE,
},
{ /* CX18_ENC_STREAM_TYPE_PCM */
"encoder PCM audio",
VFL_TYPE_GRABBER, CX18_V4L2_ENC_PCM_OFFSET,
PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_PRIVATE,
},
{ /* CX18_ENC_STREAM_TYPE_IDX */
"encoder IDX",
VFL_TYPE_GRABBER, -1,
PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
},
{ /* CX18_ENC_STREAM_TYPE_RAD */
"encoder radio",
VFL_TYPE_RADIO, 0,
PCI_DMA_NONE, V4L2_BUF_TYPE_PRIVATE,
},
};
static void cx18_stream_init(struct cx18 *cx, int type)
{
struct cx18_stream *s = &cx->streams[type];
struct video_device *video_dev = s->video_dev;
/* we need to keep video_dev, so restore it afterwards */
memset(s, 0, sizeof(*s));
s->video_dev = video_dev;
/* initialize cx18_stream fields */
s->cx = cx;
s->type = type;
s->name = cx18_stream_info[type].name;
s->handle = CX18_INVALID_TASK_HANDLE;
s->dma = cx18_stream_info[type].dma;
s->buffers = cx->stream_buffers[type];
s->buf_size = cx->stream_buf_size[type];
init_waitqueue_head(&s->waitq);
s->id = -1;
spin_lock_init(&s->q_free.lock);
cx18_queue_init(&s->q_free);
spin_lock_init(&s->q_busy.lock);
cx18_queue_init(&s->q_busy);
spin_lock_init(&s->q_full.lock);
cx18_queue_init(&s->q_full);
INIT_WORK(&s->out_work_order, cx18_out_work_handler);
}
static int cx18_prep_dev(struct cx18 *cx, int type)
{
struct cx18_stream *s = &cx->streams[type];
u32 cap = cx->v4l2_cap;
int num_offset = cx18_stream_info[type].num_offset;
int num = cx->instance + cx18_first_minor + num_offset;
/* These four fields are always initialized. If video_dev == NULL, then
this stream is not in use. In that case no other fields but these
four can be used. */
s->video_dev = NULL;
s->cx = cx;
s->type = type;
s->name = cx18_stream_info[type].name;
/* Check whether the radio is supported */
if (type == CX18_ENC_STREAM_TYPE_RAD && !(cap & V4L2_CAP_RADIO))
return 0;
/* Check whether VBI is supported */
if (type == CX18_ENC_STREAM_TYPE_VBI &&
!(cap & (V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE)))
return 0;
/* User explicitly selected 0 buffers for these streams, so don't
create them. */
if (cx18_stream_info[type].dma != PCI_DMA_NONE &&
cx->stream_buffers[type] == 0) {
CX18_INFO("Disabled %s device\n", cx18_stream_info[type].name);
return 0;
}
cx18_stream_init(cx, type);
if (num_offset == -1)
return 0;
/* allocate and initialize the v4l2 video device structure */
s->video_dev = video_device_alloc();
if (s->video_dev == NULL) {
CX18_ERR("Couldn't allocate v4l2 video_device for %s\n",
s->name);
return -ENOMEM;
}
snprintf(s->video_dev->name, sizeof(s->video_dev->name), "%s %s",
cx->v4l2_dev.name, s->name);
s->video_dev->num = num;
s->video_dev->v4l2_dev = &cx->v4l2_dev;
s->video_dev->fops = &cx18_v4l2_enc_fops;
s->video_dev->release = video_device_release;
s->video_dev->tvnorms = V4L2_STD_ALL;
cx18_set_funcs(s->video_dev);
return 0;
}
/* Initialize v4l2 variables and register v4l2 devices */
int cx18_streams_setup(struct cx18 *cx)
{
int type, ret;
/* Setup V4L2 Devices */
for (type = 0; type < CX18_MAX_STREAMS; type++) {
/* Prepare device */
ret = cx18_prep_dev(cx, type);
if (ret < 0)
break;
/* Allocate Stream */
ret = cx18_stream_alloc(&cx->streams[type]);
if (ret < 0)
break;
}
if (type == CX18_MAX_STREAMS)
return 0;
/* One or more streams could not be initialized. Clean 'em all up. */
cx18_streams_cleanup(cx, 0);
return ret;
}
static int cx18_reg_dev(struct cx18 *cx, int type)
{
struct cx18_stream *s = &cx->streams[type];
int vfl_type = cx18_stream_info[type].vfl_type;
int num, ret;
/* TODO: Shouldn't this be a VFL_TYPE_TRANSPORT or something?
* We need a VFL_TYPE_TS defined.
*/
if (strcmp("TS", s->name) == 0) {
/* just return if no DVB is supported */
if ((cx->card->hw_all & CX18_HW_DVB) == 0)
return 0;
ret = cx18_dvb_register(s);
if (ret < 0) {
CX18_ERR("DVB failed to register\n");
return ret;
}
}
if (s->video_dev == NULL)
return 0;
num = s->video_dev->num;
/* card number + user defined offset + device offset */
if (type != CX18_ENC_STREAM_TYPE_MPG) {
struct cx18_stream *s_mpg = &cx->streams[CX18_ENC_STREAM_TYPE_MPG];
if (s_mpg->video_dev)
num = s_mpg->video_dev->num
+ cx18_stream_info[type].num_offset;
}
video_set_drvdata(s->video_dev, s);
/* Register device. First try the desired minor, then any free one. */
ret = video_register_device_no_warn(s->video_dev, vfl_type, num);
if (ret < 0) {
CX18_ERR("Couldn't register v4l2 device for %s (device node number %d)\n",
s->name, num);
video_device_release(s->video_dev);
s->video_dev = NULL;
return ret;
}
num = s->video_dev->num;
switch (vfl_type) {
case VFL_TYPE_GRABBER:
CX18_INFO("Registered device video%d for %s (%d x %d kB)\n",
num, s->name, cx->stream_buffers[type],
cx->stream_buf_size[type]/1024);
break;
case VFL_TYPE_RADIO:
CX18_INFO("Registered device radio%d for %s\n",
num, s->name);
break;
case VFL_TYPE_VBI:
if (cx->stream_buffers[type])
CX18_INFO("Registered device vbi%d for %s "
"(%d x %d bytes)\n",
num, s->name, cx->stream_buffers[type],
cx->stream_buf_size[type]);
else
CX18_INFO("Registered device vbi%d for %s\n",
num, s->name);
break;
}
return 0;
}
/* Register v4l2 devices */
int cx18_streams_register(struct cx18 *cx)
{
int type;
int err;
int ret = 0;
/* Register V4L2 devices */
for (type = 0; type < CX18_MAX_STREAMS; type++) {
err = cx18_reg_dev(cx, type);
if (err && ret == 0)
ret = err;
}
if (ret == 0)
return 0;
/* One or more streams could not be initialized. Clean 'em all up. */
cx18_streams_cleanup(cx, 1);
return ret;
}
/* Unregister v4l2 devices */
void cx18_streams_cleanup(struct cx18 *cx, int unregister)
{
struct video_device *vdev;
int type;
/* Teardown all streams */
for (type = 0; type < CX18_MAX_STREAMS; type++) {
if (cx->streams[type].dvb.enabled) {
cx18_dvb_unregister(&cx->streams[type]);
cx->streams[type].dvb.enabled = false;
}
vdev = cx->streams[type].video_dev;
cx->streams[type].video_dev = NULL;
if (vdev == NULL)
continue;
cx18_stream_free(&cx->streams[type]);
/* Unregister or release device */
if (unregister)
video_unregister_device(vdev);
else
video_device_release(vdev);
}
}
static void cx18_vbi_setup(struct cx18_stream *s)
{
struct cx18 *cx = s->cx;
int raw = cx18_raw_vbi(cx);
u32 data[CX2341X_MBOX_MAX_DATA];
int lines;
if (cx->is_60hz) {
cx->vbi.count = 12;
cx->vbi.start[0] = 10;
cx->vbi.start[1] = 273;
} else { /* PAL/SECAM */
cx->vbi.count = 18;
cx->vbi.start[0] = 6;
cx->vbi.start[1] = 318;
}
/* setup VBI registers */
v4l2_subdev_call(cx->sd_av, video, s_fmt, &cx->vbi.in);
/*
* Send the CX18_CPU_SET_RAW_VBI_PARAM API command to setup Encoder Raw
* VBI when the first analog capture channel starts, as once it starts
* (e.g. MPEG), we can't effect any change in the Encoder Raw VBI setup
* (i.e. for the VBI capture channels). We also send it for each
* analog capture channel anyway just to make sure we get the proper
* behavior
*/
if (raw) {
lines = cx->vbi.count * 2;
} else {
/*
* For 525/60 systems, according to the VIP 2 & BT.656 std:
* The EAV RP code's Field bit toggles on line 4, a few lines
* after the Vertcal Blank bit has already toggled.
* Tell the encoder to capture 21-4+1=18 lines per field,
* since we want lines 10 through 21.
*
* For 625/50 systems, according to the VIP 2 & BT.656 std:
* The EAV RP code's Field bit toggles on line 1, a few lines
* after the Vertcal Blank bit has already toggled.
* (We've actually set the digitizer so that the Field bit
* toggles on line 2.) Tell the encoder to capture 23-2+1=22
* lines per field, since we want lines 6 through 23.
*/
lines = cx->is_60hz ? (21 - 4 + 1) * 2 : (23 - 2 + 1) * 2;
}
data[0] = s->handle;
/* Lines per field */
data[1] = (lines / 2) | ((lines / 2) << 16);
/* bytes per line */
data[2] = (raw ? vbi_active_samples
: (cx->is_60hz ? vbi_hblank_samples_60Hz
: vbi_hblank_samples_50Hz));
/* Every X number of frames a VBI interrupt arrives
(frames as in 25 or 30 fps) */
data[3] = 1;
/*
* Set the SAV/EAV RP codes to look for as start/stop points
* when in VIP-1.1 mode
*/
if (raw) {
/*
* Start codes for beginning of "active" line in vertical blank
* 0x20 ( VerticalBlank )
* 0x60 ( EvenField VerticalBlank )
*/
data[4] = 0x20602060;
/*
* End codes for end of "active" raw lines and regular lines
* 0x30 ( VerticalBlank HorizontalBlank)
* 0x70 ( EvenField VerticalBlank HorizontalBlank)
* 0x90 (Task HorizontalBlank)
* 0xd0 (Task EvenField HorizontalBlank)
*/
data[5] = 0x307090d0;
} else {
/*
* End codes for active video, we want data in the hblank region
* 0xb0 (Task 0 VerticalBlank HorizontalBlank)
* 0xf0 (Task EvenField VerticalBlank HorizontalBlank)
*
* Since the V bit is only allowed to toggle in the EAV RP code,
* just before the first active region line, these two
* are problematic:
* 0x90 (Task HorizontalBlank)
* 0xd0 (Task EvenField HorizontalBlank)
*
* We have set the digitzer such that we don't have to worry
* about these problem codes.
*/
data[4] = 0xB0F0B0F0;
/*
* Start codes for beginning of active line in vertical blank
* 0xa0 (Task VerticalBlank )
* 0xe0 (Task EvenField VerticalBlank )
*/
data[5] = 0xA0E0A0E0;
}
CX18_DEBUG_INFO("Setup VBI h: %d lines %x bpl %d fr %d %x %x\n",
data[0], data[1], data[2], data[3], data[4], data[5]);
cx18_api(cx, CX18_CPU_SET_RAW_VBI_PARAM, 6, data);
}
static
struct cx18_queue *_cx18_stream_put_buf_fw(struct cx18_stream *s,
struct cx18_buffer *buf)
{
struct cx18 *cx = s->cx;
struct cx18_queue *q;
/* Don't give it to the firmware, if we're not running a capture */
if (s->handle == CX18_INVALID_TASK_HANDLE ||
test_bit(CX18_F_S_STOPPING, &s->s_flags) ||
!test_bit(CX18_F_S_STREAMING, &s->s_flags))
return cx18_enqueue(s, buf, &s->q_free);
q = cx18_enqueue(s, buf, &s->q_busy);
if (q != &s->q_busy)
return q; /* The firmware has the max buffers it can handle */
cx18_buf_sync_for_device(s, buf);
cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle,
(void __iomem *) &cx->scb->cpu_mdl[buf->id] - cx->enc_mem,
1, buf->id, s->buf_size);
return q;
}
static
void _cx18_stream_load_fw_queue(struct cx18_stream *s)
{
struct cx18_queue *q;
struct cx18_buffer *buf;
if (atomic_read(&s->q_free.buffers) == 0 ||
atomic_read(&s->q_busy.buffers) >= CX18_MAX_FW_MDLS_PER_STREAM)
return;
/* Move from q_free to q_busy notifying the firmware, until the limit */
do {
buf = cx18_dequeue(s, &s->q_free);
if (buf == NULL)
break;
q = _cx18_stream_put_buf_fw(s, buf);
} while (atomic_read(&s->q_busy.buffers) < CX18_MAX_FW_MDLS_PER_STREAM
&& q == &s->q_busy);
}
void cx18_out_work_handler(struct work_struct *work)
{
struct cx18_stream *s =
container_of(work, struct cx18_stream, out_work_order);
_cx18_stream_load_fw_queue(s);
}
int cx18_start_v4l2_encode_stream(struct cx18_stream *s)
{
u32 data[MAX_MB_ARGUMENTS];
struct cx18 *cx = s->cx;
struct cx18_buffer *buf;
int captype = 0;
struct cx18_api_func_private priv;
if (s->video_dev == NULL && s->dvb.enabled == 0)
return -EINVAL;
CX18_DEBUG_INFO("Start encoder stream %s\n", s->name);
switch (s->type) {
case CX18_ENC_STREAM_TYPE_MPG:
captype = CAPTURE_CHANNEL_TYPE_MPEG;
cx->mpg_data_received = cx->vbi_data_inserted = 0;
cx->dualwatch_jiffies = jiffies;
cx->dualwatch_stereo_mode = cx->params.audio_properties & 0x300;
cx->search_pack_header = 0;
break;
case CX18_ENC_STREAM_TYPE_TS:
captype = CAPTURE_CHANNEL_TYPE_TS;
break;
case CX18_ENC_STREAM_TYPE_YUV:
captype = CAPTURE_CHANNEL_TYPE_YUV;
break;
case CX18_ENC_STREAM_TYPE_PCM:
captype = CAPTURE_CHANNEL_TYPE_PCM;
break;
case CX18_ENC_STREAM_TYPE_VBI:
#ifdef CX18_ENCODER_PARSES_SLICED
captype = cx18_raw_vbi(cx) ?
CAPTURE_CHANNEL_TYPE_VBI : CAPTURE_CHANNEL_TYPE_SLICED_VBI;
#else
/*
* Currently we set things up so that Sliced VBI from the
* digitizer is handled as Raw VBI by the encoder
*/
captype = CAPTURE_CHANNEL_TYPE_VBI;
#endif
cx->vbi.frame = 0;
cx->vbi.inserted_frame = 0;
memset(cx->vbi.sliced_mpeg_size,
0, sizeof(cx->vbi.sliced_mpeg_size));
break;
default:
return -EINVAL;
}
/* Clear Streamoff flags in case left from last capture */
clear_bit(CX18_F_S_STREAMOFF, &s->s_flags);
cx18_vapi_result(cx, data, CX18_CREATE_TASK, 1, CPU_CMD_MASK_CAPTURE);
s->handle = data[0];
cx18_vapi(cx, CX18_CPU_SET_CHANNEL_TYPE, 2, s->handle, captype);
/*
* For everything but CAPTURE_CHANNEL_TYPE_TS, play it safe and
* set up all the parameters, as it is not obvious which parameters the
* firmware shares across capture channel types and which it does not.
*
* Some of the cx18_vapi() calls below apply to only certain capture
* channel types. We're hoping there's no harm in calling most of them
* anyway, as long as the values are all consistent. Setting some
* shared parameters will have no effect once an analog capture channel
* has started streaming.
*/
if (captype != CAPTURE_CHANNEL_TYPE_TS) {
cx18_vapi(cx, CX18_CPU_SET_VER_CROP_LINE, 2, s->handle, 0);
cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 3, 1);
cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 8, 0);
cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 4, 1);
/*
* Audio related reset according to
* Documentation/video4linux/cx2341x/fw-encoder-api.txt
*/
if (atomic_read(&cx->ana_capturing) == 0)
cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 2,
s->handle, 12);
/*
* Number of lines for Field 1 & Field 2 according to
* Documentation/video4linux/cx2341x/fw-encoder-api.txt
* Field 1 is 312 for 625 line systems in BT.656
* Field 2 is 313 for 625 line systems in BT.656
*/
cx18_vapi(cx, CX18_CPU_SET_CAPTURE_LINE_NO, 3,
s->handle, 312, 313);
if (cx->v4l2_cap & V4L2_CAP_VBI_CAPTURE)
cx18_vbi_setup(s);
/*
* assign program index info.
* Mask 7: select I/P/B, Num_req: 400 max
* FIXME - currently we have this hardcoded as disabled
*/
cx18_vapi_result(cx, data, CX18_CPU_SET_INDEXTABLE, 1, 0);
/* Call out to the common CX2341x API setup for user controls */
priv.cx = cx;
priv.s = s;
cx2341x_update(&priv, cx18_api_func, NULL, &cx->params);
/*
* When starting a capture and we're set for radio,
* ensure the video is muted, despite the user control.
*/
if (!cx->params.video_mute &&
test_bit(CX18_F_I_RADIO_USER, &cx->i_flags))
cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, s->handle,
(cx->params.video_mute_yuv << 8) | 1);
}
if (atomic_read(&cx->tot_capturing) == 0) {
clear_bit(CX18_F_I_EOS, &cx->i_flags);
cx18_write_reg(cx, 7, CX18_DSP0_INTERRUPT_MASK);
}
cx18_vapi(cx, CX18_CPU_DE_SET_MDL_ACK, 3, s->handle,
(void __iomem *)&cx->scb->cpu_mdl_ack[s->type][0] - cx->enc_mem,
(void __iomem *)&cx->scb->cpu_mdl_ack[s->type][1] - cx->enc_mem);
/* Init all the cpu_mdls for this stream */
cx18_flush_queues(s);
spin_lock(&s->q_free.lock);
list_for_each_entry(buf, &s->q_free.list, list) {
cx18_writel(cx, buf->dma_handle,
&cx->scb->cpu_mdl[buf->id].paddr);
cx18_writel(cx, s->buf_size, &cx->scb->cpu_mdl[buf->id].length);
}
spin_unlock(&s->q_free.lock);
_cx18_stream_load_fw_queue(s);
/* begin_capture */
if (cx18_vapi(cx, CX18_CPU_CAPTURE_START, 1, s->handle)) {
CX18_DEBUG_WARN("Error starting capture!\n");
/* Ensure we're really not capturing before releasing MDLs */
set_bit(CX18_F_S_STOPPING, &s->s_flags);
if (s->type == CX18_ENC_STREAM_TYPE_MPG)
cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, 1);
else
cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
clear_bit(CX18_F_S_STREAMING, &s->s_flags);
/* FIXME - CX18_F_S_STREAMOFF as well? */
cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
s->handle = CX18_INVALID_TASK_HANDLE;
clear_bit(CX18_F_S_STOPPING, &s->s_flags);
if (atomic_read(&cx->tot_capturing) == 0) {
set_bit(CX18_F_I_EOS, &cx->i_flags);
cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
}
return -EINVAL;
}
/* you're live! sit back and await interrupts :) */
if (captype != CAPTURE_CHANNEL_TYPE_TS)
atomic_inc(&cx->ana_capturing);
atomic_inc(&cx->tot_capturing);
return 0;
}
void cx18_stop_all_captures(struct cx18 *cx)
{
int i;
for (i = CX18_MAX_STREAMS - 1; i >= 0; i--) {
struct cx18_stream *s = &cx->streams[i];
if (s->video_dev == NULL && s->dvb.enabled == 0)
continue;
if (test_bit(CX18_F_S_STREAMING, &s->s_flags))
cx18_stop_v4l2_encode_stream(s, 0);
}
}
int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end)
{
struct cx18 *cx = s->cx;
unsigned long then;
if (s->video_dev == NULL && s->dvb.enabled == 0)
return -EINVAL;
/* This function assumes that you are allowed to stop the capture
and that we are actually capturing */
CX18_DEBUG_INFO("Stop Capture\n");
if (atomic_read(&cx->tot_capturing) == 0)
return 0;
set_bit(CX18_F_S_STOPPING, &s->s_flags);
if (s->type == CX18_ENC_STREAM_TYPE_MPG)
cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, !gop_end);
else
cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
then = jiffies;
if (s->type == CX18_ENC_STREAM_TYPE_MPG && gop_end) {
CX18_INFO("ignoring gop_end: not (yet?) supported by the firmware\n");
}
if (s->type != CX18_ENC_STREAM_TYPE_TS)
atomic_dec(&cx->ana_capturing);
atomic_dec(&cx->tot_capturing);
/* Clear capture and no-read bits */
clear_bit(CX18_F_S_STREAMING, &s->s_flags);
/* Tell the CX23418 it can't use our buffers anymore */
cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
s->handle = CX18_INVALID_TASK_HANDLE;
clear_bit(CX18_F_S_STOPPING, &s->s_flags);
if (atomic_read(&cx->tot_capturing) > 0)
return 0;
cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
wake_up(&s->waitq);
return 0;
}
u32 cx18_find_handle(struct cx18 *cx)
{
int i;
/* find first available handle to be used for global settings */
for (i = 0; i < CX18_MAX_STREAMS; i++) {
struct cx18_stream *s = &cx->streams[i];
if (s->video_dev && (s->handle != CX18_INVALID_TASK_HANDLE))
return s->handle;
}
return CX18_INVALID_TASK_HANDLE;
}
struct cx18_stream *cx18_handle_to_stream(struct cx18 *cx, u32 handle)
{
int i;
struct cx18_stream *s;
if (handle == CX18_INVALID_TASK_HANDLE)
return NULL;
for (i = 0; i < CX18_MAX_STREAMS; i++) {
s = &cx->streams[i];
if (s->handle != handle)
continue;
if (s->video_dev || s->dvb.enabled)
return s;
}
return NULL;
}

52
kernel/drivers/media/video/cx18/cx18-streams.h Normal file
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/*
* cx18 init/start/stop/exit stream functions
*
* Derived from ivtv-streams.h
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
u32 cx18_find_handle(struct cx18 *cx);
struct cx18_stream *cx18_handle_to_stream(struct cx18 *cx, u32 handle);
int cx18_streams_setup(struct cx18 *cx);
int cx18_streams_register(struct cx18 *cx);
void cx18_streams_cleanup(struct cx18 *cx, int unregister);
/* Related to submission of buffers to firmware */
static inline void cx18_stream_load_fw_queue(struct cx18_stream *s)
{
struct cx18 *cx = s->cx;
queue_work(cx->out_work_queue, &s->out_work_order);
}
static inline void cx18_stream_put_buf_fw(struct cx18_stream *s,
struct cx18_buffer *buf)
{
/* Put buf on q_free; the out work handler will move buf(s) to q_busy */
cx18_enqueue(s, buf, &s->q_free);
cx18_stream_load_fw_queue(s);
}
void cx18_out_work_handler(struct work_struct *work);
/* Capture related */
int cx18_start_v4l2_encode_stream(struct cx18_stream *s);
int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end);
void cx18_stop_all_captures(struct cx18 *cx);

252
kernel/drivers/media/video/cx18/cx18-vbi.c Normal file
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/*
* cx18 Vertical Blank Interval support functions
*
* Derived from ivtv-vbi.c
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include "cx18-driver.h"
#include "cx18-vbi.h"
#include "cx18-ioctl.h"
#include "cx18-queue.h"
/*
* Raster Reference/Protection (RP) bytes, used in Start/End Active
* Video codes emitted from the digitzer in VIP 1.x mode, that flag the start
* of VBI sample or VBI ancilliary data regions in the digitial ratser line.
*
* Task FieldEven VerticalBlank HorizontalBlank 0 0 0 0
*/
static const u8 raw_vbi_sav_rp[2] = { 0x20, 0x60 }; /* __V_, _FV_ */
static const u8 sliced_vbi_eav_rp[2] = { 0xb0, 0xf0 }; /* T_VH, TFVH */
static void copy_vbi_data(struct cx18 *cx, int lines, u32 pts_stamp)
{
int line = 0;
int i;
u32 linemask[2] = { 0, 0 };
unsigned short size;
static const u8 mpeg_hdr_data[] = {
/* MPEG-2 Program Pack */
0x00, 0x00, 0x01, 0xba, /* Prog Pack start code */
0x44, 0x00, 0x0c, 0x66, 0x24, 0x01, /* SCR, SCR Ext, markers */
0x01, 0xd1, 0xd3, /* Mux Rate, markers */
0xfa, 0xff, 0xff, /* Res, Suff cnt, Stuff */
/* MPEG-2 Private Stream 1 PES Packet */
0x00, 0x00, 0x01, 0xbd, /* Priv Stream 1 start */
0x00, 0x1a, /* length */
0x84, 0x80, 0x07, /* flags, hdr data len */
0x21, 0x00, 0x5d, 0x63, 0xa7, /* PTS, markers */
0xff, 0xff /* stuffing */
};
const int sd = sizeof(mpeg_hdr_data); /* start of vbi data */
int idx = cx->vbi.frame % CX18_VBI_FRAMES;
u8 *dst = &cx->vbi.sliced_mpeg_data[idx][0];
for (i = 0; i < lines; i++) {
struct v4l2_sliced_vbi_data *sdata = cx->vbi.sliced_data + i;
int f, l;
if (sdata->id == 0)
continue;
l = sdata->line - 6;
f = sdata->field;
if (f)
l += 18;
if (l < 32)
linemask[0] |= (1 << l);
else
linemask[1] |= (1 << (l - 32));
dst[sd + 12 + line * 43] = cx18_service2vbi(sdata->id);
memcpy(dst + sd + 12 + line * 43 + 1, sdata->data, 42);
line++;
}
memcpy(dst, mpeg_hdr_data, sizeof(mpeg_hdr_data));
if (line == 36) {
/* All lines are used, so there is no space for the linemask
(the max size of the VBI data is 36 * 43 + 4 bytes).
So in this case we use the magic number 'ITV0'. */
memcpy(dst + sd, "ITV0", 4);
memcpy(dst + sd + 4, dst + sd + 12, line * 43);
size = 4 + ((43 * line + 3) & ~3);
} else {
memcpy(dst + sd, "itv0", 4);
cpu_to_le32s(&linemask[0]);
cpu_to_le32s(&linemask[1]);
memcpy(dst + sd + 4, &linemask[0], 8);
size = 12 + ((43 * line + 3) & ~3);
}
dst[4+16] = (size + 10) >> 8;
dst[5+16] = (size + 10) & 0xff;
dst[9+16] = 0x21 | ((pts_stamp >> 29) & 0x6);
dst[10+16] = (pts_stamp >> 22) & 0xff;
dst[11+16] = 1 | ((pts_stamp >> 14) & 0xff);
dst[12+16] = (pts_stamp >> 7) & 0xff;
dst[13+16] = 1 | ((pts_stamp & 0x7f) << 1);
cx->vbi.sliced_mpeg_size[idx] = sd + size;
}
/* Compress raw VBI format, removes leading SAV codes and surplus space
after the frame. Returns new compressed size. */
static u32 compress_raw_buf(struct cx18 *cx, u8 *buf, u32 size, u32 hdr_size)
{
u32 line_size = vbi_active_samples;
u32 lines = cx->vbi.count * 2;
u8 *q = buf;
u8 *p;
int i;
/* Skip the header */
buf += hdr_size;
for (i = 0; i < lines; i++) {
p = buf + i * line_size;
/* Look for SAV code */
if (p[0] != 0xff || p[1] || p[2] ||
(p[3] != raw_vbi_sav_rp[0] &&
p[3] != raw_vbi_sav_rp[1]))
break;
if (i == lines - 1) {
/* last line is hdr_size bytes short - extrapolate it */
memcpy(q, p + 4, line_size - 4 - hdr_size);
q += line_size - 4 - hdr_size;
p += line_size - hdr_size - 1;
memset(q, (int) *p, hdr_size);
} else {
memcpy(q, p + 4, line_size - 4);
q += line_size - 4;
}
}
return lines * (line_size - 4);
}
static u32 compress_sliced_buf(struct cx18 *cx, u8 *buf, u32 size,
const u32 hdr_size)
{
struct v4l2_decode_vbi_line vbi;
int i;
u32 line = 0;
u32 line_size = cx->is_60hz ? vbi_hblank_samples_60Hz
: vbi_hblank_samples_50Hz;
/* find the first valid line */
for (i = hdr_size, buf += hdr_size; i < size; i++, buf++) {
if (buf[0] == 0xff && !buf[1] && !buf[2] &&
(buf[3] == sliced_vbi_eav_rp[0] ||
buf[3] == sliced_vbi_eav_rp[1]))
break;
}
/*
* The last line is short by hdr_size bytes, but for the remaining
* checks against size, we pretend that it is not, by counting the
* header bytes we knowingly skipped
*/
size -= (i - hdr_size);
if (size < line_size)
return line;
for (i = 0; i < size / line_size; i++) {
u8 *p = buf + i * line_size;
/* Look for EAV code */
if (p[0] != 0xff || p[1] || p[2] ||
(p[3] != sliced_vbi_eav_rp[0] &&
p[3] != sliced_vbi_eav_rp[1]))
continue;
vbi.p = p + 4;
v4l2_subdev_call(cx->sd_av, video, decode_vbi_line, &vbi);
if (vbi.type) {
cx->vbi.sliced_data[line].id = vbi.type;
cx->vbi.sliced_data[line].field = vbi.is_second_field;
cx->vbi.sliced_data[line].line = vbi.line;
memcpy(cx->vbi.sliced_data[line].data, vbi.p, 42);
line++;
}
}
return line;
}
void cx18_process_vbi_data(struct cx18 *cx, struct cx18_buffer *buf,
int streamtype)
{
/*
* The CX23418 provides a 12 byte header in its raw VBI buffers to us:
* 0x3fffffff [4 bytes of something] [4 byte presentation time stamp]
*/
struct vbi_data_hdr {
__be32 magic;
__be32 unknown;
__be32 pts;
} *hdr = (struct vbi_data_hdr *) buf->buf;
u8 *p = (u8 *) buf->buf;
u32 size = buf->bytesused;
u32 pts;
int lines;
if (streamtype != CX18_ENC_STREAM_TYPE_VBI)
return;
/*
* The CX23418 sends us data that is 32 bit little-endian swapped,
* but we want the raw VBI bytes in the order they were in the raster
* line. This has a side effect of making the header big endian
*/
cx18_buf_swap(buf);
/* Raw VBI data */
if (cx18_raw_vbi(cx)) {
size = buf->bytesused =
compress_raw_buf(cx, p, size, sizeof(struct vbi_data_hdr));
/*
* Hack needed for compatibility with old VBI software.
* Write the frame # at the last 4 bytes of the frame
*/
p += size - 4;
memcpy(p, &cx->vbi.frame, 4);
cx->vbi.frame++;
return;
}
/* Sliced VBI data with data insertion */
pts = (be32_to_cpu(hdr->magic) == 0x3fffffff) ? be32_to_cpu(hdr->pts)
: 0;
lines = compress_sliced_buf(cx, p, size, sizeof(struct vbi_data_hdr));
/* always return at least one empty line */
if (lines == 0) {
cx->vbi.sliced_data[0].id = 0;
cx->vbi.sliced_data[0].line = 0;
cx->vbi.sliced_data[0].field = 0;
lines = 1;
}
buf->bytesused = size = lines * sizeof(cx->vbi.sliced_data[0]);
memcpy(p, &cx->vbi.sliced_data[0], size);
if (cx->vbi.insert_mpeg)
copy_vbi_data(cx, lines, pts);
cx->vbi.frame++;
}

26
kernel/drivers/media/video/cx18/cx18-vbi.h Normal file
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/*
* cx18 Vertical Blank Interval support functions
*
* Derived from ivtv-vbi.h
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
void cx18_process_vbi_data(struct cx18 *cx, struct cx18_buffer *buf,
int streamtype);
int cx18_used_line(struct cx18 *cx, int line, int field);

34
kernel/drivers/media/video/cx18/cx18-version.h Normal file
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/*
* cx18 driver version information
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#ifndef CX18_VERSION_H
#define CX18_VERSION_H
#define CX18_DRIVER_NAME "cx18"
#define CX18_DRIVER_VERSION_MAJOR 1
#define CX18_DRIVER_VERSION_MINOR 2
#define CX18_DRIVER_VERSION_PATCHLEVEL 0
#define CX18_VERSION __stringify(CX18_DRIVER_VERSION_MAJOR) "." __stringify(CX18_DRIVER_VERSION_MINOR) "." __stringify(CX18_DRIVER_VERSION_PATCHLEVEL)
#define CX18_DRIVER_VERSION KERNEL_VERSION(CX18_DRIVER_VERSION_MAJOR, \
CX18_DRIVER_VERSION_MINOR, CX18_DRIVER_VERSION_PATCHLEVEL)
#endif

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kernel/drivers/media/video/cx18/cx18-video.c Normal file
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/*
* cx18 video interface functions
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#include "cx18-driver.h"
#include "cx18-video.h"
#include "cx18-cards.h"
void cx18_video_set_io(struct cx18 *cx)
{
int inp = cx->active_input;
v4l2_subdev_call(cx->sd_av, video, s_routing,
cx->card->video_inputs[inp].video_input, 0, 0);
}

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kernel/drivers/media/video/cx18/cx18-video.h Normal file
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/*
* cx18 video interface functions
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
void cx18_video_set_io(struct cx18 *cx);

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kernel/drivers/media/video/cx18/cx23418.h Normal file
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/*
* cx18 header containing common defines.
*
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA
*/
#ifndef CX23418_H
#define CX23418_H
#include <media/cx2341x.h>
#define MGR_CMD_MASK 0x40000000
/* The MSB of the command code indicates that this is the completion of a
command */
#define MGR_CMD_MASK_ACK (MGR_CMD_MASK | 0x80000000)
/* Description: This command creates a new instance of a certain task
IN[0] - Task ID. This is one of the XPU_CMD_MASK_YYY where XPU is
the processor on which the task YYY will be created
OUT[0] - Task handle. This handle is passed along with commands to
dispatch to the right instance of the task
ReturnCode - One of the ERR_SYS_... */
#define CX18_CREATE_TASK (MGR_CMD_MASK | 0x0001)
/* Description: This command destroys an instance of a task
IN[0] - Task handle. Hanlde of the task to destroy
ReturnCode - One of the ERR_SYS_... */
#define CX18_DESTROY_TASK (MGR_CMD_MASK | 0x0002)
/* All commands for CPU have the following mask set */
#define CPU_CMD_MASK 0x20000000
#define CPU_CMD_MASK_DEBUG (CPU_CMD_MASK | 0x00000000)
#define CPU_CMD_MASK_ACK (CPU_CMD_MASK | 0x80000000)
#define CPU_CMD_MASK_CAPTURE (CPU_CMD_MASK | 0x00020000)
#define CPU_CMD_MASK_TS (CPU_CMD_MASK | 0x00040000)
#define EPU_CMD_MASK 0x02000000
#define EPU_CMD_MASK_DEBUG (EPU_CMD_MASK | 0x000000)
#define EPU_CMD_MASK_DE (EPU_CMD_MASK | 0x040000)
#define APU_CMD_MASK 0x10000000
#define APU_CMD_MASK_ACK (APU_CMD_MASK | 0x80000000)
#define CX18_APU_ENCODING_METHOD_MPEG (0 << 28)
#define CX18_APU_ENCODING_METHOD_AC3 (1 << 28)
/* Description: Command APU to start audio
IN[0] - audio parameters (same as CX18_CPU_SET_AUDIO_PARAMETERS?)
IN[1] - caller buffer address, or 0
ReturnCode - ??? */
#define CX18_APU_START (APU_CMD_MASK | 0x01)
/* Description: Command APU to stop audio
IN[0] - encoding method to stop
ReturnCode - ??? */
#define CX18_APU_STOP (APU_CMD_MASK | 0x02)
/* Description: Command APU to reset the AI
ReturnCode - ??? */
#define CX18_APU_RESETAI (APU_CMD_MASK | 0x05)
/* Description: This command indicates that a Memory Descriptor List has been
filled with the requested channel type
IN[0] - Task handle. Handle of the task
IN[1] - Offset of the MDL_ACK from the beginning of the local DDR.
IN[2] - Number of CNXT_MDL_ACK structures in the array pointed to by IN[1]
ReturnCode - One of the ERR_DE_... */
#define CX18_EPU_DMA_DONE (EPU_CMD_MASK_DE | 0x0001)
/* Something interesting happened
IN[0] - A value to log
IN[1] - An offset of a string in the MiniMe memory;
0/zero/NULL means "I have nothing to say" */
#define CX18_EPU_DEBUG (EPU_CMD_MASK_DEBUG | 0x0003)
/* Reads memory/registers (32-bit)
IN[0] - Address
OUT[1] - Value */
#define CX18_CPU_DEBUG_PEEK32 (CPU_CMD_MASK_DEBUG | 0x0003)
/* Description: This command starts streaming with the set channel type
IN[0] - Task handle. Handle of the task to start
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_CAPTURE_START (CPU_CMD_MASK_CAPTURE | 0x0002)
/* Description: This command stops streaming with the set channel type
IN[0] - Task handle. Handle of the task to stop
IN[1] - 0 = stop at end of GOP, 1 = stop at end of frame (MPEG only)
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_CAPTURE_STOP (CPU_CMD_MASK_CAPTURE | 0x0003)
/* Description: This command pauses streaming with the set channel type
IN[0] - Task handle. Handle of the task to pause
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_CAPTURE_PAUSE (CPU_CMD_MASK_CAPTURE | 0x0007)
/* Description: This command resumes streaming with the set channel type
IN[0] - Task handle. Handle of the task to resume
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_CAPTURE_RESUME (CPU_CMD_MASK_CAPTURE | 0x0008)
#define CAPTURE_CHANNEL_TYPE_NONE 0
#define CAPTURE_CHANNEL_TYPE_MPEG 1
#define CAPTURE_CHANNEL_TYPE_INDEX 2
#define CAPTURE_CHANNEL_TYPE_YUV 3
#define CAPTURE_CHANNEL_TYPE_PCM 4
#define CAPTURE_CHANNEL_TYPE_VBI 5
#define CAPTURE_CHANNEL_TYPE_SLICED_VBI 6
#define CAPTURE_CHANNEL_TYPE_TS 7
#define CAPTURE_CHANNEL_TYPE_MAX 15
/* Description: This command sets the channel type. This can only be done
when stopped.
IN[0] - Task handle. Handle of the task to start
IN[1] - Channel Type. See Below.
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_CHANNEL_TYPE (CPU_CMD_MASK_CAPTURE + 1)
/* Description: Set stream output type
IN[0] - task handle. Handle of the task to start
IN[1] - type
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_STREAM_OUTPUT_TYPE (CPU_CMD_MASK_CAPTURE | 0x0012)
/* Description: Set video input resolution and frame rate
IN[0] - task handle
IN[1] - reserved
IN[2] - reserved
IN[3] - reserved
IN[4] - reserved
IN[5] - frame rate, 0 - 29.97f/s, 1 - 25f/s
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_VIDEO_IN (CPU_CMD_MASK_CAPTURE | 0x0004)
/* Description: Set video frame rate
IN[0] - task handle. Handle of the task to start
IN[1] - video bit rate mode
IN[2] - video average rate
IN[3] - video peak rate
IN[4] - system mux rate
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_VIDEO_RATE (CPU_CMD_MASK_CAPTURE | 0x0005)
/* Description: Set video output resolution
IN[0] - task handle
IN[1] - horizontal size
IN[2] - vertical size
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_VIDEO_RESOLUTION (CPU_CMD_MASK_CAPTURE | 0x0006)
/* Description: This command set filter parameters
IN[0] - Task handle. Handle of the task
IN[1] - type, 0 - temporal, 1 - spatial, 2 - median
IN[2] - mode, temporal/spatial: 0 - disable, 1 - static, 2 - dynamic
median: 0 = disable, 1 = horizontal, 2 = vertical,
3 = horizontal/vertical, 4 = diagonal
IN[3] - strength, temporal 0 - 31, spatial 0 - 15
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_FILTER_PARAM (CPU_CMD_MASK_CAPTURE | 0x0009)
/* Description: This command set spatial filter type
IN[0] - Task handle.
IN[1] - luma type: 0 = disable, 1 = 1D horizontal only, 2 = 1D vertical only,
3 = 2D H/V separable, 4 = 2D symmetric non-separable
IN[2] - chroma type: 0 - diable, 1 = 1D horizontal
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_SPATIAL_FILTER_TYPE (CPU_CMD_MASK_CAPTURE | 0x000C)
/* Description: This command set coring levels for median filter
IN[0] - Task handle.
IN[1] - luma_high
IN[2] - luma_low
IN[3] - chroma_high
IN[4] - chroma_low
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_MEDIAN_CORING (CPU_CMD_MASK_CAPTURE | 0x000E)
/* Description: This command set the picture type mask for index file
IN[0] - 0 = disable index file output
1 = output I picture
2 = P picture
4 = B picture
other = illegal */
#define CX18_CPU_SET_INDEXTABLE (CPU_CMD_MASK_CAPTURE | 0x0010)
/* Description: Set audio parameters
IN[0] - task handle. Handle of the task to start
IN[1] - audio parameter
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_AUDIO_PARAMETERS (CPU_CMD_MASK_CAPTURE | 0x0011)
/* Description: Set video mute
IN[0] - task handle. Handle of the task to start
IN[1] - bit31-24: muteYvalue
bit23-16: muteUvalue
bit15-8: muteVvalue
bit0: 1:mute, 0: unmute
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_VIDEO_MUTE (CPU_CMD_MASK_CAPTURE | 0x0013)
/* Description: Set audio mute
IN[0] - task handle. Handle of the task to start
IN[1] - mute/unmute
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_AUDIO_MUTE (CPU_CMD_MASK_CAPTURE | 0x0014)
/* Description: Set stream output type
IN[0] - task handle. Handle of the task to start
IN[1] - subType
SET_INITIAL_SCR 1
SET_QUALITY_MODE 2
SET_VIM_PROTECT_MODE 3
SET_PTS_CORRECTION 4
SET_USB_FLUSH_MODE 5
SET_MERAQPAR_ENABLE 6
SET_NAV_PACK_INSERTION 7
SET_SCENE_CHANGE_ENABLE 8
IN[2] - parameter 1
IN[3] - parameter 2
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_MISC_PARAMETERS (CPU_CMD_MASK_CAPTURE | 0x0015)
/* Description: Set raw VBI parameters
IN[0] - Task handle
IN[1] - No. of input lines per field:
bit[15:0]: field 1,
bit[31:16]: field 2
IN[2] - No. of input bytes per line
IN[3] - No. of output frames per transfer
IN[4] - start code
IN[5] - stop code
ReturnCode */
#define CX18_CPU_SET_RAW_VBI_PARAM (CPU_CMD_MASK_CAPTURE | 0x0016)
/* Description: Set capture line No.
IN[0] - task handle. Handle of the task to start
IN[1] - height1
IN[2] - height2
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_CAPTURE_LINE_NO (CPU_CMD_MASK_CAPTURE | 0x0017)
/* Description: Set copyright
IN[0] - task handle. Handle of the task to start
IN[1] - copyright
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_COPYRIGHT (CPU_CMD_MASK_CAPTURE | 0x0018)
/* Description: Set audio PID
IN[0] - task handle. Handle of the task to start
IN[1] - PID
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_AUDIO_PID (CPU_CMD_MASK_CAPTURE | 0x0019)
/* Description: Set video PID
IN[0] - task handle. Handle of the task to start
IN[1] - PID
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_VIDEO_PID (CPU_CMD_MASK_CAPTURE | 0x001A)
/* Description: Set Vertical Crop Line
IN[0] - task handle. Handle of the task to start
IN[1] - Line
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_VER_CROP_LINE (CPU_CMD_MASK_CAPTURE | 0x001B)
/* Description: Set COP structure
IN[0] - task handle. Handle of the task to start
IN[1] - M
IN[2] - N
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_GOP_STRUCTURE (CPU_CMD_MASK_CAPTURE | 0x001C)
/* Description: Set Scene Change Detection
IN[0] - task handle. Handle of the task to start
IN[1] - scene change
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_SCENE_CHANGE_DETECTION (CPU_CMD_MASK_CAPTURE | 0x001D)
/* Description: Set Aspect Ratio
IN[0] - task handle. Handle of the task to start
IN[1] - AspectRatio
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_ASPECT_RATIO (CPU_CMD_MASK_CAPTURE | 0x001E)
/* Description: Set Skip Input Frame
IN[0] - task handle. Handle of the task to start
IN[1] - skip input frames
ReturnCode - One of the ERR_CAPTURE_... */
#define CX18_CPU_SET_SKIP_INPUT_FRAME (CPU_CMD_MASK_CAPTURE | 0x001F)
/* Description: Set sliced VBI parameters -
Note This API will only apply to MPEG and Sliced VBI Channels
IN[0] - Task handle
IN[1] - output type, 0 - CC, 1 - Moji, 2 - Teletext
IN[2] - start / stop line
bit[15:0] start line number
bit[31:16] stop line number
IN[3] - number of output frames per interrupt
IN[4] - VBI insertion mode
bit 0: output user data, 1 - enable
bit 1: output private stream, 1 - enable
bit 2: mux option, 0 - in GOP, 1 - in picture
bit[7:0] private stream ID
IN[5] - insertion period while mux option is in picture
ReturnCode - VBI data offset */
#define CX18_CPU_SET_SLICED_VBI_PARAM (CPU_CMD_MASK_CAPTURE | 0x0020)
/* Description: Set the user data place holder
IN[0] - type of data (0 for user)
IN[1] - Stuffing period
IN[2] - ID data size in word (less than 10)
IN[3] - Pointer to ID buffer */
#define CX18_CPU_SET_USERDATA_PLACE_HOLDER (CPU_CMD_MASK_CAPTURE | 0x0021)
/* Description:
In[0] Task Handle
return parameter:
Out[0] Reserved
Out[1] Video PTS bit[32:2] of last output video frame.
Out[2] Video PTS bit[ 1:0] of last output video frame.
Out[3] Hardware Video PTS counter bit[31:0],
these bits get incremented on every 90kHz clock tick.
Out[4] Hardware Video PTS counter bit32,
these bits get incremented on every 90kHz clock tick.
ReturnCode */
#define CX18_CPU_GET_ENC_PTS (CPU_CMD_MASK_CAPTURE | 0x0022)
/* Below is the list of commands related to the data exchange */
#define CPU_CMD_MASK_DE (CPU_CMD_MASK | 0x040000)
/* Description: This command provides the physical base address of the local
DDR as viewed by EPU
IN[0] - Physical offset where EPU has the local DDR mapped
ReturnCode - One of the ERR_DE_... */
#define CPU_CMD_DE_SetBase (CPU_CMD_MASK_DE | 0x0001)
/* Description: This command provides the offsets in the device memory where
the 2 cx18_mdl_ack blocks reside
IN[0] - Task handle. Handle of the task to start
IN[1] - Offset of the first cx18_mdl_ack from the beginning of the
local DDR.
IN[2] - Offset of the second cx18_mdl_ack from the beginning of the
local DDR.
ReturnCode - One of the ERR_DE_... */
#define CX18_CPU_DE_SET_MDL_ACK (CPU_CMD_MASK_DE | 0x0002)
/* Description: This command provides the offset to a Memory Descriptor List
IN[0] - Task handle. Handle of the task to start
IN[1] - Offset of the MDL from the beginning of the local DDR.
IN[2] - Number of cx18_mdl structures in the array pointed to by IN[1]
IN[3] - Buffer ID
IN[4] - Total buffer length
ReturnCode - One of the ERR_DE_... */
#define CX18_CPU_DE_SET_MDL (CPU_CMD_MASK_DE | 0x0005)
/* Description: This command requests return of all current Memory
Descriptor Lists to the driver
IN[0] - Task handle. Handle of the task to start
ReturnCode - One of the ERR_DE_... */
#define CX18_CPU_DE_RELEASE_MDL (CPU_CMD_MASK_DE | 0x0006)
/* Description: This command signals the cpu that the dat buffer has been
consumed and ready for re-use.
IN[0] - Task handle. Handle of the task
IN[1] - Offset of the data block from the beginning of the local DDR.
IN[2] - Number of bytes in the data block
ReturnCode - One of the ERR_DE_... */
/* #define CX18_CPU_DE_RELEASE_BUFFER (CPU_CMD_MASK_DE | 0x0007) */
/* No Error / Success */
#define CNXT_OK 0x000000
/* Received unknown command */
#define CXERR_UNK_CMD 0x000001
/* First parameter in the command is invalid */
#define CXERR_INVALID_PARAM1 0x000002
/* Second parameter in the command is invalid */
#define CXERR_INVALID_PARAM2 0x000003
/* Device interface is not open/found */
#define CXERR_DEV_NOT_FOUND 0x000004
/* Requested function is not implemented/available */
#define CXERR_NOTSUPPORTED 0x000005
/* Invalid pointer is provided */
#define CXERR_BADPTR 0x000006
/* Unable to allocate memory */
#define CXERR_NOMEM 0x000007
/* Object/Link not found */
#define CXERR_LINK 0x000008
/* Device busy, command cannot be executed */
#define CXERR_BUSY 0x000009
/* File/device/handle is not open. */
#define CXERR_NOT_OPEN 0x00000A
/* Value is out of range */
#define CXERR_OUTOFRANGE 0x00000B
/* Buffer overflow */
#define CXERR_OVERFLOW 0x00000C
/* Version mismatch */
#define CXERR_BADVER 0x00000D
/* Operation timed out */
#define CXERR_TIMEOUT 0x00000E
/* Operation aborted */
#define CXERR_ABORT 0x00000F
/* Specified I2C device not found for read/write */
#define CXERR_I2CDEV_NOTFOUND 0x000010
/* Error in I2C data xfer (but I2C device is present) */
#define CXERR_I2CDEV_XFERERR 0x000011
/* Chanel changing component not ready */
#define CXERR_CHANNELNOTREADY 0x000012
/* PPU (Presensation/Decoder) mail box is corrupted */
#define CXERR_PPU_MB_CORRUPT 0x000013
/* CPU (Capture/Encoder) mail box is corrupted */
#define CXERR_CPU_MB_CORRUPT 0x000014
/* APU (Audio) mail box is corrupted */
#define CXERR_APU_MB_CORRUPT 0x000015
/* Unable to open file for reading */
#define CXERR_FILE_OPEN_READ 0x000016
/* Unable to open file for writing */
#define CXERR_FILE_OPEN_WRITE 0x000017
/* Unable to find the I2C section specified */
#define CXERR_I2C_BADSECTION 0x000018
/* Error in I2C data xfer (but I2C device is present) */
#define CXERR_I2CDEV_DATALOW 0x000019
/* Error in I2C data xfer (but I2C device is present) */
#define CXERR_I2CDEV_CLOCKLOW 0x00001A
/* No Interrupt received from HW (for I2C access) */
#define CXERR_NO_HW_I2C_INTR 0x00001B
/* RPU is not ready to accept commands! */
#define CXERR_RPU_NOT_READY 0x00001C
/* RPU is not ready to accept commands! */
#define CXERR_RPU_NO_ACK 0x00001D
/* The are no buffers ready. Try again soon! */
#define CXERR_NODATA_AGAIN 0x00001E
/* The stream is stopping. Function not alllowed now! */
#define CXERR_STOPPING_STATUS 0x00001F
/* Trying to access hardware when the power is turned OFF */
#define CXERR_DEVPOWER_OFF 0x000020
#endif /* CX23418_H */