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add idl4k kernel firmware version 1.13.0.105

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This commit is contained in:
Jaroslav Kysela
2015-03-26 17:22:37 +01:00
parent 5194d2792e
commit e9070cdc77
31064 changed files with 12769984 additions and 0 deletions
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132
kernel/include/linux/mfd/ab3100.h Normal file
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/*
* Copyright (C) 2007-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* AB3100 core access functions
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#include <linux/device.h>
#include <linux/workqueue.h>
#include <linux/regulator/machine.h>
#ifndef MFD_AB3100_H
#define MFD_AB3100_H
#define ABUNKNOWN 0
#define AB3000 1
#define AB3100 2
/*
* AB3100, EVENTA1, A2 and A3 event register flags
* these are catenated into a single 32-bit flag in the code
* for event notification broadcasts.
*/
#define AB3100_EVENTA1_ONSWA (0x01<<16)
#define AB3100_EVENTA1_ONSWB (0x02<<16)
#define AB3100_EVENTA1_ONSWC (0x04<<16)
#define AB3100_EVENTA1_DCIO (0x08<<16)
#define AB3100_EVENTA1_OVER_TEMP (0x10<<16)
#define AB3100_EVENTA1_SIM_OFF (0x20<<16)
#define AB3100_EVENTA1_VBUS (0x40<<16)
#define AB3100_EVENTA1_VSET_USB (0x80<<16)
#define AB3100_EVENTA2_READY_TX (0x01<<8)
#define AB3100_EVENTA2_READY_RX (0x02<<8)
#define AB3100_EVENTA2_OVERRUN_ERROR (0x04<<8)
#define AB3100_EVENTA2_FRAMING_ERROR (0x08<<8)
#define AB3100_EVENTA2_CHARG_OVERCURRENT (0x10<<8)
#define AB3100_EVENTA2_MIDR (0x20<<8)
#define AB3100_EVENTA2_BATTERY_REM (0x40<<8)
#define AB3100_EVENTA2_ALARM (0x80<<8)
#define AB3100_EVENTA3_ADC_TRIG5 (0x01)
#define AB3100_EVENTA3_ADC_TRIG4 (0x02)
#define AB3100_EVENTA3_ADC_TRIG3 (0x04)
#define AB3100_EVENTA3_ADC_TRIG2 (0x08)
#define AB3100_EVENTA3_ADC_TRIGVBAT (0x10)
#define AB3100_EVENTA3_ADC_TRIGVTX (0x20)
#define AB3100_EVENTA3_ADC_TRIG1 (0x40)
#define AB3100_EVENTA3_ADC_TRIG0 (0x80)
/* AB3100, STR register flags */
#define AB3100_STR_ONSWA (0x01)
#define AB3100_STR_ONSWB (0x02)
#define AB3100_STR_ONSWC (0x04)
#define AB3100_STR_DCIO (0x08)
#define AB3100_STR_BOOT_MODE (0x10)
#define AB3100_STR_SIM_OFF (0x20)
#define AB3100_STR_BATT_REMOVAL (0x40)
#define AB3100_STR_VBUS (0x80)
/*
* AB3100 contains 8 regulators, one external regulator controller
* and a buck converter, further the LDO E and buck converter can
* have separate settings if they are in sleep mode, this is
* modeled as a separate regulator.
*/
#define AB3100_NUM_REGULATORS 10
/**
* struct ab3100
* @access_mutex: lock out concurrent accesses to the AB3100 registers
* @dev: pointer to the containing device
* @i2c_client: I2C client for this chip
* @testreg_client: secondary client for test registers
* @chip_name: name of this chip variant
* @chip_id: 8 bit chip ID for this chip variant
* @work: an event handling worker
* @event_subscribers: event subscribers are listed here
* @startup_events: a copy of the first reading of the event registers
* @startup_events_read: whether the first events have been read
*
* This struct is PRIVATE and devices using it should NOT
* access ANY fields. It is used as a token for calling the
* AB3100 functions.
*/
struct ab3100 {
struct mutex access_mutex;
struct device *dev;
struct i2c_client *i2c_client;
struct i2c_client *testreg_client;
char chip_name[32];
u8 chip_id;
struct work_struct work;
struct blocking_notifier_head event_subscribers;
u32 startup_events;
bool startup_events_read;
};
/**
* struct ab3100_platform_data
* Data supplied to initialize board connections to the AB3100
* @reg_constraints: regulator constraints for target board
* the order of these constraints are: LDO A, C, D, E,
* F, G, H, K, EXT and BUCK.
* @reg_initvals: initial values for the regulator registers
* plus two sleep settings for LDO E and the BUCK converter.
* exactly AB3100_NUM_REGULATORS+2 values must be sent in.
* Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK,
* BUCK sleep, LDO D. (LDO D need to be initialized last.)
* @external_voltage: voltage level of the external regulator.
*/
struct ab3100_platform_data {
struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS];
u8 reg_initvals[AB3100_NUM_REGULATORS+2];
int external_voltage;
};
int ab3100_set_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval);
int ab3100_get_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 *regval);
int ab3100_get_register_page_interruptible(struct ab3100 *ab3100,
u8 first_reg, u8 *regvals, u8 numregs);
int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100,
u8 reg, u8 andmask, u8 ormask);
u8 ab3100_get_chip_type(struct ab3100 *ab3100);
int ab3100_event_register(struct ab3100 *ab3100,
struct notifier_block *nb);
int ab3100_event_unregister(struct ab3100 *ab3100,
struct notifier_block *nb);
int ab3100_event_registers_startup_state_get(struct ab3100 *ab3100,
u32 *fatevent);
#endif

296
kernel/include/linux/mfd/asic3.h Normal file
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/*
* include/linux/mfd/asic3.h
*
* Compaq ASIC3 headers.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Copyright 2001 Compaq Computer Corporation.
* Copyright 2007-2008 OpenedHand Ltd.
*/
#ifndef __ASIC3_H__
#define __ASIC3_H__
#include <linux/types.h>
struct asic3_platform_data {
u16 *gpio_config;
unsigned int gpio_config_num;
unsigned int irq_base;
unsigned int gpio_base;
};
#define ASIC3_NUM_GPIO_BANKS 4
#define ASIC3_GPIOS_PER_BANK 16
#define ASIC3_NUM_GPIOS 64
#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
#define ASIC3_IRQ_LED0 64
#define ASIC3_IRQ_LED1 65
#define ASIC3_IRQ_LED2 66
#define ASIC3_IRQ_SPI 67
#define ASIC3_IRQ_SMBUS 68
#define ASIC3_IRQ_OWM 69
#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
#define ASIC3_GPIO_BANK_A 0
#define ASIC3_GPIO_BANK_B 1
#define ASIC3_GPIO_BANK_C 2
#define ASIC3_GPIO_BANK_D 3
#define ASIC3_GPIO(bank, gpio) \
((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio))
#define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf))
/* All offsets below are specified with this address bus shift */
#define ASIC3_DEFAULT_ADDR_SHIFT 2
#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg)
#define ASIC3_GPIO_OFFSET(base, reg) \
(ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg)
#define ASIC3_GPIO_A_BASE 0x0000
#define ASIC3_GPIO_B_BASE 0x0100
#define ASIC3_GPIO_C_BASE 0x0200
#define ASIC3_GPIO_D_BASE 0x0300
#define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
#define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \
(ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
#define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
#define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100))
#define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100))
#define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */
#define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */
#define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */
#define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */
#define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */
#define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */
#define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */
#define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */
#define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */
#define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */
#define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */
#define ASIC3_GPIO_SLEEP_CONF 0x2c /*
* R/W bit 1: autosleep
* 0: disable gposlpout in normal mode,
* enable gposlpout in sleep mode.
*/
#define ASIC3_GPIO_STATUS 0x30 /* R Pin status */
/*
* ASIC3 GPIO config
*
* Bits 0..6 gpio number
* Bits 7..13 Alternate function
* Bit 14 Direction
* Bit 15 Initial value
*
*/
#define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f)
#define ASIC3_CONFIG_GPIO_ALT(config) (((config) & (0x7f << 7)) >> 7)
#define ASIC3_CONFIG_GPIO_DIR(config) ((config & (1 << 14)) >> 14)
#define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15)
#define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \
| (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \
| (((init) & 0x1) << 15))
#define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \
ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init))
#define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \
ASIC3_CONFIG_GPIO((gpio), 0, 1, (init))
/*
* Alternate functions
*/
#define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0)
#define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0)
#define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0)
#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 1, 0)
#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 1, 0)
#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 1, 0)
#define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0)
#define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0)
#define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0)
#define ASIC3_GPIOC5_SPI_CLK ASIC3_CONFIG_GPIO(37, 1, 1, 0)
#define ASIC3_GPIOC5_nCIOW ASIC3_CONFIG_GPIO(37, 1, 1, 0)
#define ASIC3_GPIOC6_nCIOR ASIC3_CONFIG_GPIO(38, 1, 1, 0)
#define ASIC3_GPIOC7_nPCE_1 ASIC3_CONFIG_GPIO(39, 1, 0, 0)
#define ASIC3_GPIOC8_nPCE_2 ASIC3_CONFIG_GPIO(40, 1, 0, 0)
#define ASIC3_GPIOC9_nPOE ASIC3_CONFIG_GPIO(41, 1, 0, 0)
#define ASIC3_GPIOC10_nPWE ASIC3_CONFIG_GPIO(42, 1, 0, 0)
#define ASIC3_GPIOC11_PSKTSEL ASIC3_CONFIG_GPIO(43, 1, 0, 0)
#define ASIC3_GPIOC12_nPREG ASIC3_CONFIG_GPIO(44, 1, 0, 0)
#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0)
#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0)
#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0)
#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0)
#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0)
#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0)
#define ASIC3_SPI_Base 0x0400
#define ASIC3_SPI_Control 0x0000
#define ASIC3_SPI_TxData 0x0004
#define ASIC3_SPI_RxData 0x0008
#define ASIC3_SPI_Int 0x000c
#define ASIC3_SPI_Status 0x0010
#define SPI_CONTROL_SPR(clk) ((clk) & 0x0f) /* Clock rate */
#define ASIC3_PWM_0_Base 0x0500
#define ASIC3_PWM_1_Base 0x0600
#define ASIC3_PWM_TimeBase 0x0000
#define ASIC3_PWM_PeriodTime 0x0004
#define ASIC3_PWM_DutyTime 0x0008
#define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */
#define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */
#define ASIC3_LED_0_Base 0x0700
#define ASIC3_LED_1_Base 0x0800
#define ASIC3_LED_2_Base 0x0900
#define ASIC3_LED_TimeBase 0x0000 /* R/W 7 bits */
#define ASIC3_LED_PeriodTime 0x0004 /* R/W 12 bits */
#define ASIC3_LED_DutyTime 0x0008 /* R/W 12 bits */
#define ASIC3_LED_AutoStopCount 0x000c /* R/W 16 bits */
/* LED TimeBase bits - match ASIC2 */
#define LED_TBS 0x0f /* Low 4 bits sets time base, max = 13 */
/* Note: max = 5 on hx4700 */
/* 0: maximum time base */
/* 1: maximum time base / 2 */
/* n: maximum time base / 2^n */
#define LED_EN (1 << 4) /* LED ON/OFF 0:off, 1:on */
#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
#define ASIC3_CLOCK_BASE 0x0A00
#define ASIC3_CLOCK_CDEX 0x00
#define ASIC3_CLOCK_SEL 0x04
#define CLOCK_CDEX_SOURCE (1 << 0) /* 2 bits */
#define CLOCK_CDEX_SOURCE0 (1 << 0)
#define CLOCK_CDEX_SOURCE1 (1 << 1)
#define CLOCK_CDEX_SPI (1 << 2)
#define CLOCK_CDEX_OWM (1 << 3)
#define CLOCK_CDEX_PWM0 (1 << 4)
#define CLOCK_CDEX_PWM1 (1 << 5)
#define CLOCK_CDEX_LED0 (1 << 6)
#define CLOCK_CDEX_LED1 (1 << 7)
#define CLOCK_CDEX_LED2 (1 << 8)
/* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */
#define CLOCK_CDEX_SD_HOST (1 << 9) /* R/W: SD host clock source */
#define CLOCK_CDEX_SD_BUS (1 << 10) /* R/W: SD bus clock source ctrl */
#define CLOCK_CDEX_SMBUS (1 << 11)
#define CLOCK_CDEX_CONTROL_CX (1 << 12)
#define CLOCK_CDEX_EX0 (1 << 13) /* R/W: 32.768 kHz crystal */
#define CLOCK_CDEX_EX1 (1 << 14) /* R/W: 24.576 MHz crystal */
#define CLOCK_SEL_SD_HCLK_SEL (1 << 0) /* R/W: SDIO host clock select */
#define CLOCK_SEL_SD_BCLK_SEL (1 << 1) /* R/W: SDIO bus clock select */
/* R/W: INT clock source control (32.768 kHz) */
#define CLOCK_SEL_CX (1 << 2)
#define ASIC3_INTR_BASE 0x0B00
#define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */
#define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */
#define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */
#define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */
#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */
#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */
#define ASIC3_INTMASK_MASK0 (1 << 2)
#define ASIC3_INTMASK_MASK1 (1 << 3)
#define ASIC3_INTMASK_MASK2 (1 << 4)
#define ASIC3_INTMASK_MASK3 (1 << 5)
#define ASIC3_INTMASK_MASK4 (1 << 6)
#define ASIC3_INTMASK_MASK5 (1 << 7)
#define ASIC3_INTR_PERIPHERAL_A (1 << 0)
#define ASIC3_INTR_PERIPHERAL_B (1 << 1)
#define ASIC3_INTR_PERIPHERAL_C (1 << 2)
#define ASIC3_INTR_PERIPHERAL_D (1 << 3)
#define ASIC3_INTR_LED0 (1 << 4)
#define ASIC3_INTR_LED1 (1 << 5)
#define ASIC3_INTR_LED2 (1 << 6)
#define ASIC3_INTR_SPI (1 << 7)
#define ASIC3_INTR_SMBUS (1 << 8)
#define ASIC3_INTR_OWM (1 << 9)
#define ASIC3_INTR_CPS(x) ((x)&0x0f) /* 4 bits, max 14 */
#define ASIC3_INTR_CPS_SET (1 << 4) /* Time base enable */
/* Basic control of the SD ASIC */
#define ASIC3_SDHWCTRL_BASE 0x0E00
#define ASIC3_SDHWCTRL_SDCONF 0x00
#define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */
#define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */
#define ASIC3_SDHWCTRL_PCLR (1 << 2) /* All registers of SDIO cleared */
#define ASIC3_SDHWCTRL_LEVCD (1 << 3) /* SD card detection: 0:low */
/* SD card write protection: 0=high */
#define ASIC3_SDHWCTRL_LEVWP (1 << 4)
#define ASIC3_SDHWCTRL_SDLED (1 << 5) /* SD card LED signal 0=disable */
/* SD card power supply ctrl 1=enable */
#define ASIC3_SDHWCTRL_SDPWR (1 << 6)
#define ASIC3_EXTCF_BASE 0x1100
#define ASIC3_EXTCF_SELECT 0x00
#define ASIC3_EXTCF_RESET 0x04
#define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */
#define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */
#define ASIC3_EXTCF_SMOD2 (1 << 2) /* slot number of mode 2 */
#define ASIC3_EXTCF_OWM_EN (1 << 4) /* enable onewire module */
#define ASIC3_EXTCF_OWM_SMB (1 << 5) /* OWM bus selection */
#define ASIC3_EXTCF_OWM_RESET (1 << 6) /* ?? used by OWM and CF */
#define ASIC3_EXTCF_CF0_SLEEP_MODE (1 << 7) /* CF0 sleep state */
#define ASIC3_EXTCF_CF1_SLEEP_MODE (1 << 8) /* CF1 sleep state */
#define ASIC3_EXTCF_CF0_PWAIT_EN (1 << 10) /* CF0 PWAIT_n control */
#define ASIC3_EXTCF_CF1_PWAIT_EN (1 << 11) /* CF1 PWAIT_n control */
#define ASIC3_EXTCF_CF0_BUF_EN (1 << 12) /* CF0 buffer control */
#define ASIC3_EXTCF_CF1_BUF_EN (1 << 13) /* CF1 buffer control */
#define ASIC3_EXTCF_SD_MEM_ENABLE (1 << 14)
#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */
/*********************************************
* The Onewire interface (DS1WM) is handled
* by the ds1wm driver.
*
*********************************************/
#define ASIC3_OWM_BASE 0xC00
/*****************************************************************************
* The SD configuration registers are at a completely different location
* in memory. They are divided into three sets of registers:
*
* SD_CONFIG Core configuration register
* SD_CTRL Control registers for SD operations
* SDIO_CTRL Control registers for SDIO operations
*
*****************************************************************************/
#define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */
#define ASIC3_SD_CTRL_BASE 0x1000
#define ASIC3_SDIO_CTRL_BASE 0x1200
#define ASIC3_MAP_SIZE_32BIT 0x2000
#define ASIC3_MAP_SIZE_16BIT 0x1000
#endif /* __ASIC3_H__ */

56
kernel/include/linux/mfd/core.h Normal file
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/*
* drivers/mfd/mfd-core.h
*
* core MFD support
* Copyright (c) 2006 Ian Molton
* Copyright (c) 2007 Dmitry Baryshkov
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef MFD_CORE_H
#define MFD_CORE_H
#include <linux/platform_device.h>
/*
* This struct describes the MFD part ("cell").
* After registration the copy of this structure will become the platform data
* of the resulting platform_device
*/
struct mfd_cell {
const char *name;
int id;
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
/* driver-specific data for MFD-aware "cell" drivers */
void *driver_data;
/* platform_data can be used to either pass data to "generic"
driver or as a hook to mfd_cell for the "cell" drivers */
void *platform_data;
size_t data_size;
/*
* This resources can be specified relatievly to the parent device.
* For accessing device you should use resources from device
*/
int num_resources;
const struct resource *resources;
};
extern int mfd_add_devices(struct device *parent, int id,
const struct mfd_cell *cells, int n_devs,
struct resource *mem_base,
int irq_base);
extern void mfd_remove_devices(struct device *parent);
#endif

243
kernel/include/linux/mfd/da903x.h Normal file
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#ifndef __LINUX_PMIC_DA903X_H
#define __LINUX_PMIC_DA903X_H
/* Unified sub device IDs for DA9030/DA9034/DA9035 */
enum {
DA9030_ID_LED_1,
DA9030_ID_LED_2,
DA9030_ID_LED_3,
DA9030_ID_LED_4,
DA9030_ID_LED_PC,
DA9030_ID_VIBRA,
DA9030_ID_WLED,
DA9030_ID_BUCK1,
DA9030_ID_BUCK2,
DA9030_ID_LDO1,
DA9030_ID_LDO2,
DA9030_ID_LDO3,
DA9030_ID_LDO4,
DA9030_ID_LDO5,
DA9030_ID_LDO6,
DA9030_ID_LDO7,
DA9030_ID_LDO8,
DA9030_ID_LDO9,
DA9030_ID_LDO10,
DA9030_ID_LDO11,
DA9030_ID_LDO12,
DA9030_ID_LDO13,
DA9030_ID_LDO14,
DA9030_ID_LDO15,
DA9030_ID_LDO16,
DA9030_ID_LDO17,
DA9030_ID_LDO18,
DA9030_ID_LDO19,
DA9030_ID_LDO_INT, /* LDO Internal */
DA9030_ID_BAT, /* battery charger */
DA9034_ID_LED_1,
DA9034_ID_LED_2,
DA9034_ID_VIBRA,
DA9034_ID_WLED,
DA9034_ID_TOUCH,
DA9034_ID_BUCK1,
DA9034_ID_BUCK2,
DA9034_ID_LDO1,
DA9034_ID_LDO2,
DA9034_ID_LDO3,
DA9034_ID_LDO4,
DA9034_ID_LDO5,
DA9034_ID_LDO6,
DA9034_ID_LDO7,
DA9034_ID_LDO8,
DA9034_ID_LDO9,
DA9034_ID_LDO10,
DA9034_ID_LDO11,
DA9034_ID_LDO12,
DA9034_ID_LDO13,
DA9034_ID_LDO14,
DA9034_ID_LDO15,
DA9035_ID_BUCK3,
};
/*
* DA9030/DA9034 LEDs sub-devices uses generic "struct led_info"
* as the platform_data
*/
/* DA9030 flags for "struct led_info"
*/
#define DA9030_LED_RATE_ON (0 << 5)
#define DA9030_LED_RATE_052S (1 << 5)
#define DA9030_LED_DUTY_1_16 (0 << 3)
#define DA9030_LED_DUTY_1_8 (1 << 3)
#define DA9030_LED_DUTY_1_4 (2 << 3)
#define DA9030_LED_DUTY_1_2 (3 << 3)
#define DA9030_VIBRA_MODE_1P3V (0 << 1)
#define DA9030_VIBRA_MODE_2P7V (1 << 1)
#define DA9030_VIBRA_FREQ_1HZ (0 << 2)
#define DA9030_VIBRA_FREQ_2HZ (1 << 2)
#define DA9030_VIBRA_FREQ_4HZ (2 << 2)
#define DA9030_VIBRA_FREQ_8HZ (3 << 2)
#define DA9030_VIBRA_DUTY_ON (0 << 4)
#define DA9030_VIBRA_DUTY_75P (1 << 4)
#define DA9030_VIBRA_DUTY_50P (2 << 4)
#define DA9030_VIBRA_DUTY_25P (3 << 4)
/* DA9034 flags for "struct led_info" */
#define DA9034_LED_RAMP (1 << 7)
/* DA9034 touch screen platform data */
struct da9034_touch_pdata {
int interval_ms; /* sampling interval while pen down */
int x_inverted;
int y_inverted;
};
/* DA9030 battery charger data */
struct power_supply_info;
struct da9030_battery_info {
/* battery parameters */
struct power_supply_info *battery_info;
/* current and voltage to use for battery charging */
unsigned int charge_milliamp;
unsigned int charge_millivolt;
/* voltage thresholds (in millivolts) */
int vbat_low;
int vbat_crit;
int vbat_charge_start;
int vbat_charge_stop;
int vbat_charge_restart;
/* battery nominal minimal and maximal voltages in millivolts */
int vcharge_min;
int vcharge_max;
/* Temperature thresholds. These are DA9030 register values
"as is" and should be measured for each battery type */
int tbat_low;
int tbat_high;
int tbat_restart;
/* battery monitor interval (seconds) */
unsigned int batmon_interval;
/* platform callbacks for battery low and critical events */
void (*battery_low)(void);
void (*battery_critical)(void);
};
struct da903x_subdev_info {
int id;
const char *name;
void *platform_data;
};
struct da903x_platform_data {
int num_subdevs;
struct da903x_subdev_info *subdevs;
};
/* bit definitions for DA9030 events */
#define DA9030_EVENT_ONKEY (1 << 0)
#define DA9030_EVENT_PWREN (1 << 1)
#define DA9030_EVENT_EXTON (1 << 2)
#define DA9030_EVENT_CHDET (1 << 3)
#define DA9030_EVENT_TBAT (1 << 4)
#define DA9030_EVENT_VBATMON (1 << 5)
#define DA9030_EVENT_VBATMON_TXON (1 << 6)
#define DA9030_EVENT_CHIOVER (1 << 7)
#define DA9030_EVENT_TCTO (1 << 8)
#define DA9030_EVENT_CCTO (1 << 9)
#define DA9030_EVENT_ADC_READY (1 << 10)
#define DA9030_EVENT_VBUS_4P4 (1 << 11)
#define DA9030_EVENT_VBUS_4P0 (1 << 12)
#define DA9030_EVENT_SESS_VALID (1 << 13)
#define DA9030_EVENT_SRP_DETECT (1 << 14)
#define DA9030_EVENT_WATCHDOG (1 << 15)
#define DA9030_EVENT_LDO15 (1 << 16)
#define DA9030_EVENT_LDO16 (1 << 17)
#define DA9030_EVENT_LDO17 (1 << 18)
#define DA9030_EVENT_LDO18 (1 << 19)
#define DA9030_EVENT_LDO19 (1 << 20)
#define DA9030_EVENT_BUCK2 (1 << 21)
/* bit definitions for DA9034 events */
#define DA9034_EVENT_ONKEY (1 << 0)
#define DA9034_EVENT_EXTON (1 << 2)
#define DA9034_EVENT_CHDET (1 << 3)
#define DA9034_EVENT_TBAT (1 << 4)
#define DA9034_EVENT_VBATMON (1 << 5)
#define DA9034_EVENT_REV_IOVER (1 << 6)
#define DA9034_EVENT_CH_IOVER (1 << 7)
#define DA9034_EVENT_CH_TCTO (1 << 8)
#define DA9034_EVENT_CH_CCTO (1 << 9)
#define DA9034_EVENT_USB_DEV (1 << 10)
#define DA9034_EVENT_OTGCP_IOVER (1 << 11)
#define DA9034_EVENT_VBUS_4P55 (1 << 12)
#define DA9034_EVENT_VBUS_3P8 (1 << 13)
#define DA9034_EVENT_SESS_1P8 (1 << 14)
#define DA9034_EVENT_SRP_READY (1 << 15)
#define DA9034_EVENT_ADC_MAN (1 << 16)
#define DA9034_EVENT_ADC_AUTO4 (1 << 17)
#define DA9034_EVENT_ADC_AUTO5 (1 << 18)
#define DA9034_EVENT_ADC_AUTO6 (1 << 19)
#define DA9034_EVENT_PEN_DOWN (1 << 20)
#define DA9034_EVENT_TSI_READY (1 << 21)
#define DA9034_EVENT_UART_TX (1 << 22)
#define DA9034_EVENT_UART_RX (1 << 23)
#define DA9034_EVENT_HEADSET (1 << 25)
#define DA9034_EVENT_HOOKSWITCH (1 << 26)
#define DA9034_EVENT_WATCHDOG (1 << 27)
extern int da903x_register_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
extern int da903x_unregister_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
/* Status Query Interface */
#define DA9030_STATUS_ONKEY (1 << 0)
#define DA9030_STATUS_PWREN1 (1 << 1)
#define DA9030_STATUS_EXTON (1 << 2)
#define DA9030_STATUS_CHDET (1 << 3)
#define DA9030_STATUS_TBAT (1 << 4)
#define DA9030_STATUS_VBATMON (1 << 5)
#define DA9030_STATUS_VBATMON_TXON (1 << 6)
#define DA9030_STATUS_MCLKDET (1 << 7)
#define DA9034_STATUS_ONKEY (1 << 0)
#define DA9034_STATUS_EXTON (1 << 2)
#define DA9034_STATUS_CHDET (1 << 3)
#define DA9034_STATUS_TBAT (1 << 4)
#define DA9034_STATUS_VBATMON (1 << 5)
#define DA9034_STATUS_PEN_DOWN (1 << 6)
#define DA9034_STATUS_MCLKDET (1 << 7)
#define DA9034_STATUS_USB_DEV (1 << 8)
#define DA9034_STATUS_HEADSET (1 << 9)
#define DA9034_STATUS_HOOKSWITCH (1 << 10)
#define DA9034_STATUS_REMCON (1 << 11)
#define DA9034_STATUS_VBUS_VALID_4P55 (1 << 12)
#define DA9034_STATUS_VBUS_VALID_3P8 (1 << 13)
#define DA9034_STATUS_SESS_VALID_1P8 (1 << 14)
#define DA9034_STATUS_SRP_READY (1 << 15)
extern int da903x_query_status(struct device *dev, unsigned int status);
/* NOTE: the functions below are not intended for use outside
* of the DA903x sub-device drivers
*/
extern int da903x_write(struct device *dev, int reg, uint8_t val);
extern int da903x_writes(struct device *dev, int reg, int len, uint8_t *val);
extern int da903x_read(struct device *dev, int reg, uint8_t *val);
extern int da903x_reads(struct device *dev, int reg, int len, uint8_t *val);
extern int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask);
extern int da903x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int da903x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
#endif /* __LINUX_PMIC_DA903X_H */

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/* MFD cell driver data for the DS1WM driver */
struct ds1wm_driver_data {
int active_high;
int clock_rate;
};

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kernel/include/linux/mfd/ezx-pcap.h Normal file
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/*
* Copyright 2009 Daniel Ribeiro <drwyrm@gmail.com>
*
* For further information, please see http://wiki.openezx.org/PCAP2
*/
#ifndef EZX_PCAP_H
#define EZX_PCAP_H
struct pcap_subdev {
int id;
const char *name;
void *platform_data;
};
struct pcap_platform_data {
unsigned int irq_base;
unsigned int config;
void (*init) (void *); /* board specific init */
int num_subdevs;
struct pcap_subdev *subdevs;
};
struct pcap_chip;
int ezx_pcap_write(struct pcap_chip *, u8, u32);
int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32);
int pcap_to_irq(struct pcap_chip *, int);
int irq_to_pcap(struct pcap_chip *, int);
int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
void pcap_set_ts_bits(struct pcap_chip *, u32);
#define PCAP_SECOND_PORT 1
#define PCAP_CS_AH 2
#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
#define PCAP_REGISTER_READ_OP_BIT 0x00000000
#define PCAP_REGISTER_VALUE_MASK 0x01ffffff
#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
#define PCAP_REGISTER_ADDRESS_SHIFT 26
#define PCAP_REGISTER_NUMBER 32
#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
/* registers acessible by both pcap ports */
#define PCAP_REG_ISR 0x0 /* Interrupt Status */
#define PCAP_REG_MSR 0x1 /* Interrupt Mask */
#define PCAP_REG_PSTAT 0x2 /* Processor Status */
#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
#define PCAP_REG_BATT 0x8 /* Battery Control */
#define PCAP_REG_ADC 0x9 /* AD Control */
#define PCAP_REG_ADR 0xa /* AD Result */
#define PCAP_REG_CODEC 0xb /* Audio Codec Control */
#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */
#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */
#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */
#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */
#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */
#define PCAP_REG_GP 0x1b /* General Purpose */
#define PCAP_REG_TEST1 0x1c
#define PCAP_REG_TEST2 0x1d
#define PCAP_REG_VENDOR_TEST1 0x1e
#define PCAP_REG_VENDOR_TEST2 0x1f
/* registers acessible by pcap port 1 only (a1200, e2 & e6) */
#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */
#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */
#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */
#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */
#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */
#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */
#define PCAP_REG_PWR 0x13 /* Power Control */
#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
#define PCAP_REG_VENDOR_REV 0x17
#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */
/* PCAP2 Interrupts */
#define PCAP_NIRQS 23
#define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */
#define PCAP_IRQ_TS 1 /* Touch Screen */
#define PCAP_IRQ_1HZ 2 /* 1HZ timer */
#define PCAP_IRQ_WH 3 /* ADC above high limit */
#define PCAP_IRQ_WL 4 /* ADC below low limit */
#define PCAP_IRQ_TODA 5 /* Time of day alarm */
#define PCAP_IRQ_USB4V 6 /* USB above 4V */
#define PCAP_IRQ_ONOFF 7 /* On/Off button */
#define PCAP_IRQ_ONOFF2 8 /* On/Off button 2 */
#define PCAP_IRQ_USB1V 9 /* USB above 1V */
#define PCAP_IRQ_MOBPORT 10
#define PCAP_IRQ_MIC 11 /* Mic attach/HS button */
#define PCAP_IRQ_HS 12 /* Headset attach */
#define PCAP_IRQ_ST 13
#define PCAP_IRQ_PC 14 /* Power Cut */
#define PCAP_IRQ_WARM 15
#define PCAP_IRQ_EOL 16 /* Battery End Of Life */
#define PCAP_IRQ_CLK 17
#define PCAP_IRQ_SYSRST 18 /* System Reset */
#define PCAP_IRQ_DUMMY 19
#define PCAP_IRQ_ADCDONE2 20 /* ADC done port 2 */
#define PCAP_IRQ_SOFTRESET 21
#define PCAP_IRQ_MNEXB 22
/* voltage regulators */
#define V1 0
#define V2 1
#define V3 2
#define V4 3
#define V5 4
#define V6 5
#define V7 6
#define V8 7
#define V9 8
#define V10 9
#define VAUX1 10
#define VAUX2 11
#define VAUX3 12
#define VAUX4 13
#define VSIM 14
#define VSIM2 15
#define VVIB 16
#define SW1 17
#define SW2 18
#define SW3 19
#define SW1S 20
#define SW2S 21
#define PCAP_BATT_DAC_MASK 0x000000ff
#define PCAP_BATT_DAC_SHIFT 0
#define PCAP_BATT_B_FDBK (1 << 8)
#define PCAP_BATT_EXT_ISENSE (1 << 9)
#define PCAP_BATT_V_COIN_MASK 0x00003c00
#define PCAP_BATT_V_COIN_SHIFT 10
#define PCAP_BATT_I_COIN (1 << 14)
#define PCAP_BATT_COIN_CH_EN (1 << 15)
#define PCAP_BATT_EOL_SEL_MASK 0x000e0000
#define PCAP_BATT_EOL_SEL_SHIFT 17
#define PCAP_BATT_EOL_CMP_EN (1 << 20)
#define PCAP_BATT_BATT_DET_EN (1 << 21)
#define PCAP_BATT_THERMBIAS_CTRL (1 << 22)
#define PCAP_ADC_ADEN (1 << 0)
#define PCAP_ADC_RAND (1 << 1)
#define PCAP_ADC_AD_SEL1 (1 << 2)
#define PCAP_ADC_AD_SEL2 (1 << 3)
#define PCAP_ADC_ADA1_MASK 0x00000070
#define PCAP_ADC_ADA1_SHIFT 4
#define PCAP_ADC_ADA2_MASK 0x00000380
#define PCAP_ADC_ADA2_SHIFT 7
#define PCAP_ADC_ATO_MASK 0x00003c00
#define PCAP_ADC_ATO_SHIFT 10
#define PCAP_ADC_ATOX (1 << 14)
#define PCAP_ADC_MTR1 (1 << 15)
#define PCAP_ADC_MTR2 (1 << 16)
#define PCAP_ADC_TS_M_MASK 0x000e0000
#define PCAP_ADC_TS_M_SHIFT 17
#define PCAP_ADC_TS_REF_LOWPWR (1 << 20)
#define PCAP_ADC_TS_REFENB (1 << 21)
#define PCAP_ADC_BATT_I_POLARITY (1 << 22)
#define PCAP_ADC_BATT_I_ADC (1 << 23)
#define PCAP_ADC_BANK_0 0
#define PCAP_ADC_BANK_1 1
/* ADC bank 0 */
#define PCAP_ADC_CH_COIN 0
#define PCAP_ADC_CH_BATT 1
#define PCAP_ADC_CH_BPLUS 2
#define PCAP_ADC_CH_MOBPORTB 3
#define PCAP_ADC_CH_TEMPERATURE 4
#define PCAP_ADC_CH_CHARGER_ID 5
#define PCAP_ADC_CH_AD6 6
/* ADC bank 1 */
#define PCAP_ADC_CH_AD7 0
#define PCAP_ADC_CH_AD8 1
#define PCAP_ADC_CH_AD9 2
#define PCAP_ADC_CH_TS_X1 3
#define PCAP_ADC_CH_TS_X2 4
#define PCAP_ADC_CH_TS_Y1 5
#define PCAP_ADC_CH_TS_Y2 6
#define PCAP_ADC_T_NOW 0
#define PCAP_ADC_T_IN_BURST 1
#define PCAP_ADC_T_OUT_BURST 2
#define PCAP_ADC_ATO_IN_BURST 6
#define PCAP_ADC_ATO_OUT_BURST 0
#define PCAP_ADC_TS_M_XY 1
#define PCAP_ADC_TS_M_PRESSURE 2
#define PCAP_ADC_TS_M_PLATE_X 3
#define PCAP_ADC_TS_M_PLATE_Y 4
#define PCAP_ADC_TS_M_STANDBY 5
#define PCAP_ADC_TS_M_NONTS 6
#define PCAP_ADR_ADD1_MASK 0x000003ff
#define PCAP_ADR_ADD1_SHIFT 0
#define PCAP_ADR_ADD2_MASK 0x000ffc00
#define PCAP_ADR_ADD2_SHIFT 10
#define PCAP_ADR_ADINC1 (1 << 20)
#define PCAP_ADR_ADINC2 (1 << 21)
#define PCAP_ADR_ASC (1 << 22)
#define PCAP_ADR_ONESHOT (1 << 23)
#define PCAP_BUSCTRL_FSENB (1 << 0)
#define PCAP_BUSCTRL_USB_SUSPEND (1 << 1)
#define PCAP_BUSCTRL_USB_PU (1 << 2)
#define PCAP_BUSCTRL_USB_PD (1 << 3)
#define PCAP_BUSCTRL_VUSB_EN (1 << 4)
#define PCAP_BUSCTRL_USB_PS (1 << 5)
#define PCAP_BUSCTRL_VUSB_MSTR_EN (1 << 6)
#define PCAP_BUSCTRL_VBUS_PD_ENB (1 << 7)
#define PCAP_BUSCTRL_CURRLIM (1 << 8)
#define PCAP_BUSCTRL_RS232ENB (1 << 9)
#define PCAP_BUSCTRL_RS232_DIR (1 << 10)
#define PCAP_BUSCTRL_SE0_CONN (1 << 11)
#define PCAP_BUSCTRL_USB_PDM (1 << 12)
#define PCAP_BUSCTRL_BUS_PRI_ADJ (1 << 24)
/* leds */
#define PCAP_LED0 0
#define PCAP_LED1 1
#define PCAP_BL0 2
#define PCAP_BL1 3
#define PCAP_LED_3MA 0
#define PCAP_LED_4MA 1
#define PCAP_LED_5MA 2
#define PCAP_LED_9MA 3
#define PCAP_LED_GPIO_VAL_MASK 0x00ffffff
#define PCAP_LED_GPIO_EN 0x01000000
#define PCAP_LED_GPIO_INVERT 0x02000000
#define PCAP_LED_T_MASK 0xf
#define PCAP_LED_C_MASK 0x3
#define PCAP_BL_MASK 0x1f
#define PCAP_BL0_SHIFT 0
#define PCAP_LED0_EN (1 << 5)
#define PCAP_LED1_EN (1 << 6)
#define PCAP_LED0_T_SHIFT 7
#define PCAP_LED1_T_SHIFT 11
#define PCAP_LED0_C_SHIFT 15
#define PCAP_LED1_C_SHIFT 17
#define PCAP_BL1_SHIFT 20
/* RTC */
#define PCAP_RTC_DAY_MASK 0x3fff
#define PCAP_RTC_TOD_MASK 0xffff
#define PCAP_RTC_PC_MASK 0x7
#define SEC_PER_DAY 86400
#endif

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kernel/include/linux/mfd/htc-egpio.h Normal file
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/*
* HTC simple EGPIO irq and gpio extender
*/
#ifndef __HTC_EGPIO_H__
#define __HTC_EGPIO_H__
#include <linux/gpio.h>
/* Descriptive values for all-in or all-out htc_egpio_chip descriptors. */
#define HTC_EGPIO_OUTPUT (~0)
#define HTC_EGPIO_INPUT 0
/**
* struct htc_egpio_chip - descriptor to create gpio_chip for register range
* @reg_start: index of first register
* @gpio_base: gpio number of first pin in this register range
* @num_gpios: number of gpios in this register range, max BITS_PER_LONG
* (number of registers = DIV_ROUND_UP(num_gpios, reg_width))
* @direction: bitfield, '0' = input, '1' = output,
*/
struct htc_egpio_chip {
int reg_start;
int gpio_base;
int num_gpios;
unsigned long direction;
unsigned long initial_values;
};
/**
* struct htc_egpio_platform_data - description provided by the arch
* @irq_base: beginning of available IRQs (eg, IRQ_BOARD_START)
* @num_irqs: number of irqs
* @reg_width: number of bits per register, either 8 or 16 bit
* @bus_width: alignment of the registers, either 16 or 32 bit
* @invert_acks: set if chip requires writing '0' to ack an irq, instead of '1'
* @ack_register: location of the irq/ack register
* @chip: pointer to array of htc_egpio_chip descriptors
* @num_chips: number of egpio chip descriptors
*/
struct htc_egpio_platform_data {
int bus_width;
int reg_width;
int irq_base;
int num_irqs;
int invert_acks;
int ack_register;
struct htc_egpio_chip *chip;
int num_chips;
};
/* Determine the wakeup irq, to be called during early resume */
extern int htc_egpio_get_wakeup_irq(struct device *dev);
#endif

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kernel/include/linux/mfd/htc-pasic3.h Normal file
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/*
* HTC PASIC3 driver - LEDs and DS1WM
*
* Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
*/
#ifndef __PASIC3_H
#define __PASIC3_H
#include <linux/platform_device.h>
#include <linux/leds.h>
extern void pasic3_write_register(struct device *dev, u32 reg, u8 val);
extern u8 pasic3_read_register(struct device *dev, u32 reg);
/*
* mask for registers 0x20,0x21,0x22
*/
#define PASIC3_MASK_LED0 0x04
#define PASIC3_MASK_LED1 0x08
#define PASIC3_MASK_LED2 0x40
/*
* bits in register 0x06
*/
#define PASIC3_BIT2_LED0 0x08
#define PASIC3_BIT2_LED1 0x10
#define PASIC3_BIT2_LED2 0x20
struct pasic3_led {
struct led_classdev led;
unsigned int hw_num;
unsigned int bit2;
unsigned int mask;
struct pasic3_leds_machinfo *pdata;
};
struct pasic3_leds_machinfo {
unsigned int num_leds;
unsigned int power_gpio;
struct pasic3_led *leds;
};
struct pasic3_platform_data {
struct pasic3_leds_machinfo *led_pdata;
unsigned int clock_rate;
};
#endif

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kernel/include/linux/mfd/mc13783-private.h Normal file
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/*
* Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*
* Initial development of this code was funded by
* Phytec Messtechnik GmbH, http://www.phytec.de
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __LINUX_MFD_MC13783_PRIV_H
#define __LINUX_MFD_MC13783_PRIV_H
#include <linux/platform_device.h>
#include <linux/mfd/mc13783.h>
#include <linux/workqueue.h>
#include <linux/mutex.h>
struct mc13783_irq {
void (*handler)(int, void *);
void *data;
};
#define MC13783_NUM_IRQ 2
#define MC13783_IRQ_TS 0
#define MC13783_IRQ_REGULATOR 1
#define MC13783_ADC_MODE_TS 1
#define MC13783_ADC_MODE_SINGLE_CHAN 2
#define MC13783_ADC_MODE_MULT_CHAN 3
struct mc13783 {
int revision;
struct device *dev;
struct spi_device *spi_device;
int (*read_dev)(void *data, char reg, int count, u32 *dst);
int (*write_dev)(void *data, char reg, int count, const u32 *src);
struct mutex io_lock;
void *io_data;
int irq;
unsigned int flags;
struct mc13783_irq irq_handler[MC13783_NUM_IRQ];
struct work_struct work;
struct completion adc_done;
unsigned int ts_active;
struct mutex adc_conv_lock;
struct mc13783_regulator_init_data *regulators;
int num_regulators;
};
int mc13783_reg_read(struct mc13783 *, int reg_num, u32 *);
int mc13783_reg_write(struct mc13783 *, int, u32);
int mc13783_set_bits(struct mc13783 *, int, u32, u32);
int mc13783_free_irq(struct mc13783 *mc13783, int irq);
int mc13783_register_irq(struct mc13783 *mc13783, int irq,
void (*handler) (int, void *), void *data);
#define MC13783_REG_INTERRUPT_STATUS_0 0
#define MC13783_REG_INTERRUPT_MASK_0 1
#define MC13783_REG_INTERRUPT_SENSE_0 2
#define MC13783_REG_INTERRUPT_STATUS_1 3
#define MC13783_REG_INTERRUPT_MASK_1 4
#define MC13783_REG_INTERRUPT_SENSE_1 5
#define MC13783_REG_POWER_UP_MODE_SENSE 6
#define MC13783_REG_REVISION 7
#define MC13783_REG_SEMAPHORE 8
#define MC13783_REG_ARBITRATION_PERIPHERAL_AUDIO 9
#define MC13783_REG_ARBITRATION_SWITCHERS 10
#define MC13783_REG_ARBITRATION_REGULATORS_0 11
#define MC13783_REG_ARBITRATION_REGULATORS_1 12
#define MC13783_REG_POWER_CONTROL_0 13
#define MC13783_REG_POWER_CONTROL_1 14
#define MC13783_REG_POWER_CONTROL_2 15
#define MC13783_REG_REGEN_ASSIGNMENT 16
#define MC13783_REG_CONTROL_SPARE 17
#define MC13783_REG_MEMORY_A 18
#define MC13783_REG_MEMORY_B 19
#define MC13783_REG_RTC_TIME 20
#define MC13783_REG_RTC_ALARM 21
#define MC13783_REG_RTC_DAY 22
#define MC13783_REG_RTC_DAY_ALARM 23
#define MC13783_REG_SWITCHERS_0 24
#define MC13783_REG_SWITCHERS_1 25
#define MC13783_REG_SWITCHERS_2 26
#define MC13783_REG_SWITCHERS_3 27
#define MC13783_REG_SWITCHERS_4 28
#define MC13783_REG_SWITCHERS_5 29
#define MC13783_REG_REGULATOR_SETTING_0 30
#define MC13783_REG_REGULATOR_SETTING_1 31
#define MC13783_REG_REGULATOR_MODE_0 32
#define MC13783_REG_REGULATOR_MODE_1 33
#define MC13783_REG_POWER_MISCELLANEOUS 34
#define MC13783_REG_POWER_SPARE 35
#define MC13783_REG_AUDIO_RX_0 36
#define MC13783_REG_AUDIO_RX_1 37
#define MC13783_REG_AUDIO_TX 38
#define MC13783_REG_AUDIO_SSI_NETWORK 39
#define MC13783_REG_AUDIO_CODEC 40
#define MC13783_REG_AUDIO_STEREO_DAC 41
#define MC13783_REG_AUDIO_SPARE 42
#define MC13783_REG_ADC_0 43
#define MC13783_REG_ADC_1 44
#define MC13783_REG_ADC_2 45
#define MC13783_REG_ADC_3 46
#define MC13783_REG_ADC_4 47
#define MC13783_REG_CHARGER 48
#define MC13783_REG_USB 49
#define MC13783_REG_CHARGE_USB_SPARE 50
#define MC13783_REG_LED_CONTROL_0 51
#define MC13783_REG_LED_CONTROL_1 52
#define MC13783_REG_LED_CONTROL_2 53
#define MC13783_REG_LED_CONTROL_3 54
#define MC13783_REG_LED_CONTROL_4 55
#define MC13783_REG_LED_CONTROL_5 56
#define MC13783_REG_SPARE 57
#define MC13783_REG_TRIM_0 58
#define MC13783_REG_TRIM_1 59
#define MC13783_REG_TEST_0 60
#define MC13783_REG_TEST_1 61
#define MC13783_REG_TEST_2 62
#define MC13783_REG_TEST_3 63
#define MC13783_REG_NB 64
/*
* Interrupt Status
*/
#define MC13783_INT_STAT_ADCDONEI (1 << 0)
#define MC13783_INT_STAT_ADCBISDONEI (1 << 1)
#define MC13783_INT_STAT_TSI (1 << 2)
#define MC13783_INT_STAT_WHIGHI (1 << 3)
#define MC13783_INT_STAT_WLOWI (1 << 4)
#define MC13783_INT_STAT_CHGDETI (1 << 6)
#define MC13783_INT_STAT_CHGOVI (1 << 7)
#define MC13783_INT_STAT_CHGREVI (1 << 8)
#define MC13783_INT_STAT_CHGSHORTI (1 << 9)
#define MC13783_INT_STAT_CCCVI (1 << 10)
#define MC13783_INT_STAT_CHGCURRI (1 << 11)
#define MC13783_INT_STAT_BPONI (1 << 12)
#define MC13783_INT_STAT_LOBATLI (1 << 13)
#define MC13783_INT_STAT_LOBATHI (1 << 14)
#define MC13783_INT_STAT_UDPI (1 << 15)
#define MC13783_INT_STAT_USBI (1 << 16)
#define MC13783_INT_STAT_IDI (1 << 19)
#define MC13783_INT_STAT_Unused (1 << 20)
#define MC13783_INT_STAT_SE1I (1 << 21)
#define MC13783_INT_STAT_CKDETI (1 << 22)
#define MC13783_INT_STAT_UDMI (1 << 23)
/*
* Interrupt Mask
*/
#define MC13783_INT_MASK_ADCDONEM (1 << 0)
#define MC13783_INT_MASK_ADCBISDONEM (1 << 1)
#define MC13783_INT_MASK_TSM (1 << 2)
#define MC13783_INT_MASK_WHIGHM (1 << 3)
#define MC13783_INT_MASK_WLOWM (1 << 4)
#define MC13783_INT_MASK_CHGDETM (1 << 6)
#define MC13783_INT_MASK_CHGOVM (1 << 7)
#define MC13783_INT_MASK_CHGREVM (1 << 8)
#define MC13783_INT_MASK_CHGSHORTM (1 << 9)
#define MC13783_INT_MASK_CCCVM (1 << 10)
#define MC13783_INT_MASK_CHGCURRM (1 << 11)
#define MC13783_INT_MASK_BPONM (1 << 12)
#define MC13783_INT_MASK_LOBATLM (1 << 13)
#define MC13783_INT_MASK_LOBATHM (1 << 14)
#define MC13783_INT_MASK_UDPM (1 << 15)
#define MC13783_INT_MASK_USBM (1 << 16)
#define MC13783_INT_MASK_IDM (1 << 19)
#define MC13783_INT_MASK_SE1M (1 << 21)
#define MC13783_INT_MASK_CKDETM (1 << 22)
/*
* Reg Regulator Mode 0
*/
#define MC13783_REGCTRL_VAUDIO_EN (1 << 0)
#define MC13783_REGCTRL_VAUDIO_STBY (1 << 1)
#define MC13783_REGCTRL_VAUDIO_MODE (1 << 2)
#define MC13783_REGCTRL_VIOHI_EN (1 << 3)
#define MC13783_REGCTRL_VIOHI_STBY (1 << 4)
#define MC13783_REGCTRL_VIOHI_MODE (1 << 5)
#define MC13783_REGCTRL_VIOLO_EN (1 << 6)
#define MC13783_REGCTRL_VIOLO_STBY (1 << 7)
#define MC13783_REGCTRL_VIOLO_MODE (1 << 8)
#define MC13783_REGCTRL_VDIG_EN (1 << 9)
#define MC13783_REGCTRL_VDIG_STBY (1 << 10)
#define MC13783_REGCTRL_VDIG_MODE (1 << 11)
#define MC13783_REGCTRL_VGEN_EN (1 << 12)
#define MC13783_REGCTRL_VGEN_STBY (1 << 13)
#define MC13783_REGCTRL_VGEN_MODE (1 << 14)
#define MC13783_REGCTRL_VRFDIG_EN (1 << 15)
#define MC13783_REGCTRL_VRFDIG_STBY (1 << 16)
#define MC13783_REGCTRL_VRFDIG_MODE (1 << 17)
#define MC13783_REGCTRL_VRFREF_EN (1 << 18)
#define MC13783_REGCTRL_VRFREF_STBY (1 << 19)
#define MC13783_REGCTRL_VRFREF_MODE (1 << 20)
#define MC13783_REGCTRL_VRFCP_EN (1 << 21)
#define MC13783_REGCTRL_VRFCP_STBY (1 << 22)
#define MC13783_REGCTRL_VRFCP_MODE (1 << 23)
/*
* Reg Regulator Mode 1
*/
#define MC13783_REGCTRL_VSIM_EN (1 << 0)
#define MC13783_REGCTRL_VSIM_STBY (1 << 1)
#define MC13783_REGCTRL_VSIM_MODE (1 << 2)
#define MC13783_REGCTRL_VESIM_EN (1 << 3)
#define MC13783_REGCTRL_VESIM_STBY (1 << 4)
#define MC13783_REGCTRL_VESIM_MODE (1 << 5)
#define MC13783_REGCTRL_VCAM_EN (1 << 6)
#define MC13783_REGCTRL_VCAM_STBY (1 << 7)
#define MC13783_REGCTRL_VCAM_MODE (1 << 8)
#define MC13783_REGCTRL_VRFBG_EN (1 << 9)
#define MC13783_REGCTRL_VRFBG_STBY (1 << 10)
#define MC13783_REGCTRL_VVIB_EN (1 << 11)
#define MC13783_REGCTRL_VRF1_EN (1 << 12)
#define MC13783_REGCTRL_VRF1_STBY (1 << 13)
#define MC13783_REGCTRL_VRF1_MODE (1 << 14)
#define MC13783_REGCTRL_VRF2_EN (1 << 15)
#define MC13783_REGCTRL_VRF2_STBY (1 << 16)
#define MC13783_REGCTRL_VRF2_MODE (1 << 17)
#define MC13783_REGCTRL_VMMC1_EN (1 << 18)
#define MC13783_REGCTRL_VMMC1_STBY (1 << 19)
#define MC13783_REGCTRL_VMMC1_MODE (1 << 20)
#define MC13783_REGCTRL_VMMC2_EN (1 << 21)
#define MC13783_REGCTRL_VMMC2_STBY (1 << 22)
#define MC13783_REGCTRL_VMMC2_MODE (1 << 23)
/*
* Reg Regulator Misc.
*/
#define MC13783_REGCTRL_GPO1_EN (1 << 6)
#define MC13783_REGCTRL_GPO2_EN (1 << 8)
#define MC13783_REGCTRL_GPO3_EN (1 << 10)
#define MC13783_REGCTRL_GPO4_EN (1 << 12)
#define MC13783_REGCTRL_VIBPINCTRL (1 << 14)
/*
* Reg Switcher 4
*/
#define MC13783_SWCTRL_SW1A_MODE (1 << 0)
#define MC13783_SWCTRL_SW1A_STBY_MODE (1 << 2)
#define MC13783_SWCTRL_SW1A_DVS_SPEED (1 << 6)
#define MC13783_SWCTRL_SW1A_PANIC_MODE (1 << 8)
#define MC13783_SWCTRL_SW1A_SOFTSTART (1 << 9)
#define MC13783_SWCTRL_SW1B_MODE (1 << 10)
#define MC13783_SWCTRL_SW1B_STBY_MODE (1 << 12)
#define MC13783_SWCTRL_SW1B_DVS_SPEED (1 << 14)
#define MC13783_SWCTRL_SW1B_PANIC_MODE (1 << 16)
#define MC13783_SWCTRL_SW1B_SOFTSTART (1 << 17)
#define MC13783_SWCTRL_PLL_EN (1 << 18)
#define MC13783_SWCTRL_PLL_FACTOR (1 << 19)
/*
* Reg Switcher 5
*/
#define MC13783_SWCTRL_SW2A_MODE (1 << 0)
#define MC13783_SWCTRL_SW2A_STBY_MODE (1 << 2)
#define MC13783_SWCTRL_SW2A_DVS_SPEED (1 << 6)
#define MC13783_SWCTRL_SW2A_PANIC_MODE (1 << 8)
#define MC13783_SWCTRL_SW2A_SOFTSTART (1 << 9)
#define MC13783_SWCTRL_SW2B_MODE (1 << 10)
#define MC13783_SWCTRL_SW2B_STBY_MODE (1 << 12)
#define MC13783_SWCTRL_SW2B_DVS_SPEED (1 << 14)
#define MC13783_SWCTRL_SW2B_PANIC_MODE (1 << 16)
#define MC13783_SWCTRL_SW2B_SOFTSTART (1 << 17)
#define MC13783_SWSET_SW3 (1 << 18)
#define MC13783_SWCTRL_SW3_EN (1 << 20)
#define MC13783_SWCTRL_SW3_STBY (1 << 21)
#define MC13783_SWCTRL_SW3_MODE (1 << 22)
/*
* ADC/Touch
*/
#define MC13783_ADC0_LICELLCON (1 << 0)
#define MC13783_ADC0_CHRGICON (1 << 1)
#define MC13783_ADC0_BATICON (1 << 2)
#define MC13783_ADC0_RTHEN (1 << 3)
#define MC13783_ADC0_DTHEN (1 << 4)
#define MC13783_ADC0_UIDEN (1 << 5)
#define MC13783_ADC0_ADOUTEN (1 << 6)
#define MC13783_ADC0_ADOUTPER (1 << 7)
#define MC13783_ADC0_ADREFEN (1 << 10)
#define MC13783_ADC0_ADREFMODE (1 << 11)
#define MC13783_ADC0_TSMOD0 (1 << 12)
#define MC13783_ADC0_TSMOD1 (1 << 13)
#define MC13783_ADC0_TSMOD2 (1 << 14)
#define MC13783_ADC0_CHRGRAWDIV (1 << 15)
#define MC13783_ADC0_ADINC1 (1 << 16)
#define MC13783_ADC0_ADINC2 (1 << 17)
#define MC13783_ADC0_WCOMP (1 << 18)
#define MC13783_ADC0_ADCBIS0 (1 << 23)
#define MC13783_ADC1_ADEN (1 << 0)
#define MC13783_ADC1_RAND (1 << 1)
#define MC13783_ADC1_ADSEL (1 << 3)
#define MC13783_ADC1_TRIGMASK (1 << 4)
#define MC13783_ADC1_ADA10 (1 << 5)
#define MC13783_ADC1_ADA11 (1 << 6)
#define MC13783_ADC1_ADA12 (1 << 7)
#define MC13783_ADC1_ADA20 (1 << 8)
#define MC13783_ADC1_ADA21 (1 << 9)
#define MC13783_ADC1_ADA22 (1 << 10)
#define MC13783_ADC1_ATO0 (1 << 11)
#define MC13783_ADC1_ATO1 (1 << 12)
#define MC13783_ADC1_ATO2 (1 << 13)
#define MC13783_ADC1_ATO3 (1 << 14)
#define MC13783_ADC1_ATO4 (1 << 15)
#define MC13783_ADC1_ATO5 (1 << 16)
#define MC13783_ADC1_ATO6 (1 << 17)
#define MC13783_ADC1_ATO7 (1 << 18)
#define MC13783_ADC1_ATOX (1 << 19)
#define MC13783_ADC1_ASC (1 << 20)
#define MC13783_ADC1_ADTRIGIGN (1 << 21)
#define MC13783_ADC1_ADONESHOT (1 << 22)
#define MC13783_ADC1_ADCBIS1 (1 << 23)
#define MC13783_ADC1_CHAN0_SHIFT 5
#define MC13783_ADC1_CHAN1_SHIFT 8
#define MC13783_ADC2_ADD10 (1 << 2)
#define MC13783_ADC2_ADD11 (1 << 3)
#define MC13783_ADC2_ADD12 (1 << 4)
#define MC13783_ADC2_ADD13 (1 << 5)
#define MC13783_ADC2_ADD14 (1 << 6)
#define MC13783_ADC2_ADD15 (1 << 7)
#define MC13783_ADC2_ADD16 (1 << 8)
#define MC13783_ADC2_ADD17 (1 << 9)
#define MC13783_ADC2_ADD18 (1 << 10)
#define MC13783_ADC2_ADD19 (1 << 11)
#define MC13783_ADC2_ADD20 (1 << 14)
#define MC13783_ADC2_ADD21 (1 << 15)
#define MC13783_ADC2_ADD22 (1 << 16)
#define MC13783_ADC2_ADD23 (1 << 17)
#define MC13783_ADC2_ADD24 (1 << 18)
#define MC13783_ADC2_ADD25 (1 << 19)
#define MC13783_ADC2_ADD26 (1 << 20)
#define MC13783_ADC2_ADD27 (1 << 21)
#define MC13783_ADC2_ADD28 (1 << 22)
#define MC13783_ADC2_ADD29 (1 << 23)
#define MC13783_ADC3_WHIGH0 (1 << 0)
#define MC13783_ADC3_WHIGH1 (1 << 1)
#define MC13783_ADC3_WHIGH2 (1 << 2)
#define MC13783_ADC3_WHIGH3 (1 << 3)
#define MC13783_ADC3_WHIGH4 (1 << 4)
#define MC13783_ADC3_WHIGH5 (1 << 5)
#define MC13783_ADC3_ICID0 (1 << 6)
#define MC13783_ADC3_ICID1 (1 << 7)
#define MC13783_ADC3_ICID2 (1 << 8)
#define MC13783_ADC3_WLOW0 (1 << 9)
#define MC13783_ADC3_WLOW1 (1 << 10)
#define MC13783_ADC3_WLOW2 (1 << 11)
#define MC13783_ADC3_WLOW3 (1 << 12)
#define MC13783_ADC3_WLOW4 (1 << 13)
#define MC13783_ADC3_WLOW5 (1 << 14)
#define MC13783_ADC3_ADCBIS2 (1 << 23)
#define MC13783_ADC4_ADDBIS10 (1 << 2)
#define MC13783_ADC4_ADDBIS11 (1 << 3)
#define MC13783_ADC4_ADDBIS12 (1 << 4)
#define MC13783_ADC4_ADDBIS13 (1 << 5)
#define MC13783_ADC4_ADDBIS14 (1 << 6)
#define MC13783_ADC4_ADDBIS15 (1 << 7)
#define MC13783_ADC4_ADDBIS16 (1 << 8)
#define MC13783_ADC4_ADDBIS17 (1 << 9)
#define MC13783_ADC4_ADDBIS18 (1 << 10)
#define MC13783_ADC4_ADDBIS19 (1 << 11)
#define MC13783_ADC4_ADDBIS20 (1 << 14)
#define MC13783_ADC4_ADDBIS21 (1 << 15)
#define MC13783_ADC4_ADDBIS22 (1 << 16)
#define MC13783_ADC4_ADDBIS23 (1 << 17)
#define MC13783_ADC4_ADDBIS24 (1 << 18)
#define MC13783_ADC4_ADDBIS25 (1 << 19)
#define MC13783_ADC4_ADDBIS26 (1 << 20)
#define MC13783_ADC4_ADDBIS27 (1 << 21)
#define MC13783_ADC4_ADDBIS28 (1 << 22)
#define MC13783_ADC4_ADDBIS29 (1 << 23)
#endif /* __LINUX_MFD_MC13783_PRIV_H */

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/*
* Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*
* Initial development of this code was funded by
* Phytec Messtechnik GmbH, http://www.phytec.de
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __INCLUDE_LINUX_MFD_MC13783_H
#define __INCLUDE_LINUX_MFD_MC13783_H
struct mc13783;
struct regulator_init_data;
struct mc13783_regulator_init_data {
int id;
struct regulator_init_data *init_data;
};
struct mc13783_platform_data {
struct mc13783_regulator_init_data *regulators;
int num_regulators;
unsigned int flags;
};
/* mc13783_platform_data flags */
#define MC13783_USE_TOUCHSCREEN (1 << 0)
#define MC13783_USE_CODEC (1 << 1)
#define MC13783_USE_ADC (1 << 2)
#define MC13783_USE_RTC (1 << 3)
#define MC13783_USE_REGULATOR (1 << 4)
int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
unsigned int channel, unsigned int *sample);
void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status);
#define MC13783_SW_SW1A 0
#define MC13783_SW_SW1B 1
#define MC13783_SW_SW2A 2
#define MC13783_SW_SW2B 3
#define MC13783_SW_SW3 4
#define MC13783_SW_PLL 5
#define MC13783_REGU_VAUDIO 6
#define MC13783_REGU_VIOHI 7
#define MC13783_REGU_VIOLO 8
#define MC13783_REGU_VDIG 9
#define MC13783_REGU_VGEN 10
#define MC13783_REGU_VRFDIG 11
#define MC13783_REGU_VRFREF 12
#define MC13783_REGU_VRFCP 13
#define MC13783_REGU_VSIM 14
#define MC13783_REGU_VESIM 15
#define MC13783_REGU_VCAM 16
#define MC13783_REGU_VRFBG 17
#define MC13783_REGU_VVIB 18
#define MC13783_REGU_VRF1 19
#define MC13783_REGU_VRF2 20
#define MC13783_REGU_VMMC1 21
#define MC13783_REGU_VMMC2 22
#define MC13783_REGU_GPO1 23
#define MC13783_REGU_GPO2 24
#define MC13783_REGU_GPO3 25
#define MC13783_REGU_GPO4 26
#define MC13783_REGU_V1 27
#define MC13783_REGU_V2 28
#define MC13783_REGU_V3 29
#define MC13783_REGU_V4 30
#endif /* __INCLUDE_LINUX_MFD_MC13783_H */

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/*
* adc.h -- Driver for NXP PCF50633 ADC
*
* (C) 2006-2008 by Openmoko, Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_PCF50633_ADC_H
#define __LINUX_MFD_PCF50633_ADC_H
#include <linux/mfd/pcf50633/core.h>
#include <linux/platform_device.h>
/* ADC Registers */
#define PCF50633_REG_ADCC3 0x52
#define PCF50633_REG_ADCC2 0x53
#define PCF50633_REG_ADCC1 0x54
#define PCF50633_REG_ADCS1 0x55
#define PCF50633_REG_ADCS2 0x56
#define PCF50633_REG_ADCS3 0x57
#define PCF50633_ADCC1_ADCSTART 0x01
#define PCF50633_ADCC1_RES_8BIT 0x02
#define PCF50633_ADCC1_RES_10BIT 0x00
#define PCF50633_ADCC1_AVERAGE_NO 0x00
#define PCF50633_ADCC1_AVERAGE_4 0x04
#define PCF50633_ADCC1_AVERAGE_8 0x08
#define PCF50633_ADCC1_AVERAGE_16 0x0c
#define PCF50633_ADCC1_MUX_BATSNS_RES 0x00
#define PCF50633_ADCC1_MUX_BATSNS_SUBTR 0x10
#define PCF50633_ADCC1_MUX_ADCIN2_RES 0x20
#define PCF50633_ADCC1_MUX_ADCIN2_SUBTR 0x30
#define PCF50633_ADCC1_MUX_BATTEMP 0x60
#define PCF50633_ADCC1_MUX_ADCIN1 0x70
#define PCF50633_ADCC1_AVERAGE_MASK 0x0c
#define PCF50633_ADCC1_ADCMUX_MASK 0xf0
#define PCF50633_ADCC2_RATIO_NONE 0x00
#define PCF50633_ADCC2_RATIO_BATTEMP 0x01
#define PCF50633_ADCC2_RATIO_ADCIN1 0x02
#define PCF50633_ADCC2_RATIO_BOTH 0x03
#define PCF50633_ADCC2_RATIOSETTL_100US 0x04
#define PCF50633_ADCC3_ACCSW_EN 0x01
#define PCF50633_ADCC3_NTCSW_EN 0x04
#define PCF50633_ADCC3_RES_DIV_TWO 0x10
#define PCF50633_ADCC3_RES_DIV_THREE 0x00
#define PCF50633_ADCS3_REF_NTCSW 0x00
#define PCF50633_ADCS3_REF_ACCSW 0x10
#define PCF50633_ADCS3_REF_2V0 0x20
#define PCF50633_ADCS3_REF_VISA 0x30
#define PCF50633_ADCS3_REF_2V0_2 0x70
#define PCF50633_ADCS3_ADCRDY 0x80
#define PCF50633_ADCS3_ADCDAT1L_MASK 0x03
#define PCF50633_ADCS3_ADCDAT2L_MASK 0x0c
#define PCF50633_ADCS3_ADCDAT2L_SHIFT 2
#define PCF50633_ASCS3_REF_MASK 0x70
extern int
pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg,
void (*callback)(struct pcf50633 *, void *, int),
void *callback_param);
extern int
pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg);
#endif /* __LINUX_PCF50633_ADC_H */

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/*
* core.h -- Core driver for NXP PCF50633
*
* (C) 2006-2008 by Openmoko, Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_PCF50633_CORE_H
#define __LINUX_MFD_PCF50633_CORE_H
#include <linux/i2c.h>
#include <linux/workqueue.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/power_supply.h>
struct pcf50633;
#define PCF50633_NUM_REGULATORS 11
struct pcf50633_platform_data {
struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS];
char **batteries;
int num_batteries;
int charging_restart_interval;
/* Callbacks */
void (*probe_done)(struct pcf50633 *);
void (*mbc_event_callback)(struct pcf50633 *, int);
void (*regulator_registered)(struct pcf50633 *, int);
void (*force_shutdown)(struct pcf50633 *);
u8 resumers[5];
};
struct pcf50633_subdev_pdata {
struct pcf50633 *pcf;
};
struct pcf50633_irq {
void (*handler) (int, void *);
void *data;
};
int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
void (*handler) (int, void *), void *data);
int pcf50633_free_irq(struct pcf50633 *pcf, int irq);
int pcf50633_irq_mask(struct pcf50633 *pcf, int irq);
int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq);
int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq);
int pcf50633_read_block(struct pcf50633 *, u8 reg,
int nr_regs, u8 *data);
int pcf50633_write_block(struct pcf50633 *pcf, u8 reg,
int nr_regs, u8 *data);
u8 pcf50633_reg_read(struct pcf50633 *, u8 reg);
int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val);
int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val);
int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits);
/* Interrupt registers */
#define PCF50633_REG_INT1 0x02
#define PCF50633_REG_INT2 0x03
#define PCF50633_REG_INT3 0x04
#define PCF50633_REG_INT4 0x05
#define PCF50633_REG_INT5 0x06
#define PCF50633_REG_INT1M 0x07
#define PCF50633_REG_INT2M 0x08
#define PCF50633_REG_INT3M 0x09
#define PCF50633_REG_INT4M 0x0a
#define PCF50633_REG_INT5M 0x0b
enum {
/* Chip IRQs */
PCF50633_IRQ_ADPINS,
PCF50633_IRQ_ADPREM,
PCF50633_IRQ_USBINS,
PCF50633_IRQ_USBREM,
PCF50633_IRQ_RESERVED1,
PCF50633_IRQ_RESERVED2,
PCF50633_IRQ_ALARM,
PCF50633_IRQ_SECOND,
PCF50633_IRQ_ONKEYR,
PCF50633_IRQ_ONKEYF,
PCF50633_IRQ_EXTON1R,
PCF50633_IRQ_EXTON1F,
PCF50633_IRQ_EXTON2R,
PCF50633_IRQ_EXTON2F,
PCF50633_IRQ_EXTON3R,
PCF50633_IRQ_EXTON3F,
PCF50633_IRQ_BATFULL,
PCF50633_IRQ_CHGHALT,
PCF50633_IRQ_THLIMON,
PCF50633_IRQ_THLIMOFF,
PCF50633_IRQ_USBLIMON,
PCF50633_IRQ_USBLIMOFF,
PCF50633_IRQ_ADCRDY,
PCF50633_IRQ_ONKEY1S,
PCF50633_IRQ_LOWSYS,
PCF50633_IRQ_LOWBAT,
PCF50633_IRQ_HIGHTMP,
PCF50633_IRQ_AUTOPWRFAIL,
PCF50633_IRQ_DWN1PWRFAIL,
PCF50633_IRQ_DWN2PWRFAIL,
PCF50633_IRQ_LEDPWRFAIL,
PCF50633_IRQ_LEDOVP,
PCF50633_IRQ_LDO1PWRFAIL,
PCF50633_IRQ_LDO2PWRFAIL,
PCF50633_IRQ_LDO3PWRFAIL,
PCF50633_IRQ_LDO4PWRFAIL,
PCF50633_IRQ_LDO5PWRFAIL,
PCF50633_IRQ_LDO6PWRFAIL,
PCF50633_IRQ_HCLDOPWRFAIL,
PCF50633_IRQ_HCLDOOVL,
/* Always last */
PCF50633_NUM_IRQ,
};
struct pcf50633 {
struct device *dev;
struct i2c_client *i2c_client;
struct pcf50633_platform_data *pdata;
int irq;
struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
struct work_struct irq_work;
struct workqueue_struct *work_queue;
struct mutex lock;
u8 mask_regs[5];
u8 suspend_irq_masks[5];
u8 resume_reason[5];
int is_suspended;
int onkey1s_held;
struct platform_device *rtc_pdev;
struct platform_device *mbc_pdev;
struct platform_device *adc_pdev;
struct platform_device *input_pdev;
struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS];
};
enum pcf50633_reg_int1 {
PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */
PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */
PCF50633_INT1_USBINS = 0x04, /* USB inserted */
PCF50633_INT1_USBREM = 0x08, /* USB removed */
/* reserved */
PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */
PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */
};
enum pcf50633_reg_int2 {
PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */
PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */
PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */
PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */
PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */
PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */
PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */
PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */
};
enum pcf50633_reg_int3 {
PCF50633_INT3_BATFULL = 0x01, /* Battery full */
PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */
PCF50633_INT3_THLIMON = 0x04,
PCF50633_INT3_THLIMOFF = 0x08,
PCF50633_INT3_USBLIMON = 0x10,
PCF50633_INT3_USBLIMOFF = 0x20,
PCF50633_INT3_ADCRDY = 0x40, /* ADC result ready */
PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */
};
enum pcf50633_reg_int4 {
PCF50633_INT4_LOWSYS = 0x01,
PCF50633_INT4_LOWBAT = 0x02,
PCF50633_INT4_HIGHTMP = 0x04,
PCF50633_INT4_AUTOPWRFAIL = 0x08,
PCF50633_INT4_DWN1PWRFAIL = 0x10,
PCF50633_INT4_DWN2PWRFAIL = 0x20,
PCF50633_INT4_LEDPWRFAIL = 0x40,
PCF50633_INT4_LEDOVP = 0x80,
};
enum pcf50633_reg_int5 {
PCF50633_INT5_LDO1PWRFAIL = 0x01,
PCF50633_INT5_LDO2PWRFAIL = 0x02,
PCF50633_INT5_LDO3PWRFAIL = 0x04,
PCF50633_INT5_LDO4PWRFAIL = 0x08,
PCF50633_INT5_LDO5PWRFAIL = 0x10,
PCF50633_INT5_LDO6PWRFAIL = 0x20,
PCF50633_INT5_HCLDOPWRFAIL = 0x40,
PCF50633_INT5_HCLDOOVL = 0x80,
};
/* misc. registers */
#define PCF50633_REG_OOCSHDWN 0x0c
/* LED registers */
#define PCF50633_REG_LEDOUT 0x28
#define PCF50633_REG_LEDENA 0x29
#define PCF50633_REG_LEDCTL 0x2a
#define PCF50633_REG_LEDDIM 0x2b
#endif

52
kernel/include/linux/mfd/pcf50633/gpio.h Normal file
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/*
* gpio.h -- GPIO driver for NXP PCF50633
*
* (C) 2006-2008 by Openmoko, Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_PCF50633_GPIO_H
#define __LINUX_MFD_PCF50633_GPIO_H
#include <linux/mfd/pcf50633/core.h>
#define PCF50633_GPIO1 1
#define PCF50633_GPIO2 2
#define PCF50633_GPIO3 3
#define PCF50633_GPO 4
#define PCF50633_REG_GPIO1CFG 0x14
#define PCF50633_REG_GPIO2CFG 0x15
#define PCF50633_REG_GPIO3CFG 0x16
#define PCF50633_REG_GPOCFG 0x17
#define PCF50633_GPOCFG_GPOSEL_MASK 0x07
enum pcf50633_reg_gpocfg {
PCF50633_GPOCFG_GPOSEL_0 = 0x00,
PCF50633_GPOCFG_GPOSEL_LED_NFET = 0x01,
PCF50633_GPOCFG_GPOSEL_SYSxOK = 0x02,
PCF50633_GPOCFG_GPOSEL_CLK32K = 0x03,
PCF50633_GPOCFG_GPOSEL_ADAPUSB = 0x04,
PCF50633_GPOCFG_GPOSEL_USBxOK = 0x05,
PCF50633_GPOCFG_GPOSEL_ACTPH4 = 0x06,
PCF50633_GPOCFG_GPOSEL_1 = 0x07,
PCF50633_GPOCFG_GPOSEL_INVERSE = 0x08,
};
int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val);
u8 pcf50633_gpio_get(struct pcf50633 *pcf, int gpio);
int pcf50633_gpio_invert_set(struct pcf50633 *, int gpio, int invert);
int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio);
int pcf50633_gpio_power_supply_set(struct pcf50633 *,
int gpio, int regulator, int on);
#endif /* __LINUX_MFD_PCF50633_GPIO_H */

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kernel/include/linux/mfd/pcf50633/mbc.h Normal file
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/*
* mbc.h -- Driver for NXP PCF50633 Main Battery Charger
*
* (C) 2006-2008 by Openmoko, Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_PCF50633_MBC_H
#define __LINUX_MFD_PCF50633_MBC_H
#include <linux/mfd/pcf50633/core.h>
#include <linux/platform_device.h>
#define PCF50633_REG_MBCC1 0x43
#define PCF50633_REG_MBCC2 0x44
#define PCF50633_REG_MBCC3 0x45
#define PCF50633_REG_MBCC4 0x46
#define PCF50633_REG_MBCC5 0x47
#define PCF50633_REG_MBCC6 0x48
#define PCF50633_REG_MBCC7 0x49
#define PCF50633_REG_MBCC8 0x4a
#define PCF50633_REG_MBCS1 0x4b
#define PCF50633_REG_MBCS2 0x4c
#define PCF50633_REG_MBCS3 0x4d
enum pcf50633_reg_mbcc1 {
PCF50633_MBCC1_CHGENA = 0x01, /* Charger enable */
PCF50633_MBCC1_AUTOSTOP = 0x02,
PCF50633_MBCC1_AUTORES = 0x04, /* automatic resume */
PCF50633_MBCC1_RESUME = 0x08, /* explicit resume cmd */
PCF50633_MBCC1_RESTART = 0x10, /* restart charging */
PCF50633_MBCC1_PREWDTIME_60M = 0x20, /* max. precharging time */
PCF50633_MBCC1_WDTIME_1H = 0x00,
PCF50633_MBCC1_WDTIME_2H = 0x40,
PCF50633_MBCC1_WDTIME_4H = 0x80,
PCF50633_MBCC1_WDTIME_6H = 0xc0,
};
#define PCF50633_MBCC1_WDTIME_MASK 0xc0
enum pcf50633_reg_mbcc2 {
PCF50633_MBCC2_VBATCOND_2V7 = 0x00,
PCF50633_MBCC2_VBATCOND_2V85 = 0x01,
PCF50633_MBCC2_VBATCOND_3V0 = 0x02,
PCF50633_MBCC2_VBATCOND_3V15 = 0x03,
PCF50633_MBCC2_VMAX_4V = 0x00,
PCF50633_MBCC2_VMAX_4V20 = 0x28,
PCF50633_MBCC2_VRESDEBTIME_64S = 0x80, /* debounce time (32/64sec) */
};
enum pcf50633_reg_mbcc7 {
PCF50633_MBCC7_USB_100mA = 0x00,
PCF50633_MBCC7_USB_500mA = 0x01,
PCF50633_MBCC7_USB_1000mA = 0x02,
PCF50633_MBCC7_USB_SUSPEND = 0x03,
PCF50633_MBCC7_BATTEMP_EN = 0x04,
PCF50633_MBCC7_BATSYSIMAX_1A6 = 0x00,
PCF50633_MBCC7_BATSYSIMAX_1A8 = 0x40,
PCF50633_MBCC7_BATSYSIMAX_2A0 = 0x80,
PCF50633_MBCC7_BATSYSIMAX_2A2 = 0xc0,
};
#define PCF50633_MBCC7_USB_MASK 0x03
enum pcf50633_reg_mbcc8 {
PCF50633_MBCC8_USBENASUS = 0x10,
};
enum pcf50633_reg_mbcs1 {
PCF50633_MBCS1_USBPRES = 0x01,
PCF50633_MBCS1_USBOK = 0x02,
PCF50633_MBCS1_ADAPTPRES = 0x04,
PCF50633_MBCS1_ADAPTOK = 0x08,
PCF50633_MBCS1_TBAT_OK = 0x00,
PCF50633_MBCS1_TBAT_ABOVE = 0x10,
PCF50633_MBCS1_TBAT_BELOW = 0x20,
PCF50633_MBCS1_TBAT_UNDEF = 0x30,
PCF50633_MBCS1_PREWDTEXP = 0x40,
PCF50633_MBCS1_WDTEXP = 0x80,
};
enum pcf50633_reg_mbcs2_mbcmod {
PCF50633_MBCS2_MBC_PLAY = 0x00,
PCF50633_MBCS2_MBC_USB_PRE = 0x01,
PCF50633_MBCS2_MBC_USB_PRE_WAIT = 0x02,
PCF50633_MBCS2_MBC_USB_FAST = 0x03,
PCF50633_MBCS2_MBC_USB_FAST_WAIT = 0x04,
PCF50633_MBCS2_MBC_USB_SUSPEND = 0x05,
PCF50633_MBCS2_MBC_ADP_PRE = 0x06,
PCF50633_MBCS2_MBC_ADP_PRE_WAIT = 0x07,
PCF50633_MBCS2_MBC_ADP_FAST = 0x08,
PCF50633_MBCS2_MBC_ADP_FAST_WAIT = 0x09,
PCF50633_MBCS2_MBC_BAT_FULL = 0x0a,
PCF50633_MBCS2_MBC_HALT = 0x0b,
};
#define PCF50633_MBCS2_MBC_MASK 0x0f
enum pcf50633_reg_mbcs2_chgstat {
PCF50633_MBCS2_CHGS_NONE = 0x00,
PCF50633_MBCS2_CHGS_ADAPTER = 0x10,
PCF50633_MBCS2_CHGS_USB = 0x20,
PCF50633_MBCS2_CHGS_BOTH = 0x30,
};
#define PCF50633_MBCS2_RESSTAT_AUTO 0x40
enum pcf50633_reg_mbcs3 {
PCF50633_MBCS3_USBLIM_PLAY = 0x01,
PCF50633_MBCS3_USBLIM_CGH = 0x02,
PCF50633_MBCS3_TLIM_PLAY = 0x04,
PCF50633_MBCS3_TLIM_CHG = 0x08,
PCF50633_MBCS3_ILIM = 0x10, /* 1: Ibat > Icutoff */
PCF50633_MBCS3_VLIM = 0x20, /* 1: Vbat == Vmax */
PCF50633_MBCS3_VBATSTAT = 0x40, /* 1: Vbat > Vbatcond */
PCF50633_MBCS3_VRES = 0x80, /* 1: Vbat > Vth(RES) */
};
#define PCF50633_MBCC2_VBATCOND_MASK 0x03
#define PCF50633_MBCC2_VMAX_MASK 0x3c
/* Charger status */
#define PCF50633_MBC_USB_ONLINE 0x01
#define PCF50633_MBC_USB_ACTIVE 0x02
#define PCF50633_MBC_ADAPTER_ONLINE 0x04
#define PCF50633_MBC_ADAPTER_ACTIVE 0x08
int pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma);
int pcf50633_mbc_get_status(struct pcf50633 *);
#endif

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kernel/include/linux/mfd/pcf50633/pmic.h Normal file
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#ifndef __LINUX_MFD_PCF50633_PMIC_H
#define __LINUX_MFD_PCF50633_PMIC_H
#include <linux/mfd/pcf50633/core.h>
#include <linux/platform_device.h>
#define PCF50633_REG_AUTOOUT 0x1a
#define PCF50633_REG_AUTOENA 0x1b
#define PCF50633_REG_AUTOCTL 0x1c
#define PCF50633_REG_AUTOMXC 0x1d
#define PCF50633_REG_DOWN1OUT 0x1e
#define PCF50633_REG_DOWN1ENA 0x1f
#define PCF50633_REG_DOWN1CTL 0x20
#define PCF50633_REG_DOWN1MXC 0x21
#define PCF50633_REG_DOWN2OUT 0x22
#define PCF50633_REG_DOWN2ENA 0x23
#define PCF50633_REG_DOWN2CTL 0x24
#define PCF50633_REG_DOWN2MXC 0x25
#define PCF50633_REG_MEMLDOOUT 0x26
#define PCF50633_REG_MEMLDOENA 0x27
#define PCF50633_REG_LDO1OUT 0x2d
#define PCF50633_REG_LDO1ENA 0x2e
#define PCF50633_REG_LDO2OUT 0x2f
#define PCF50633_REG_LDO2ENA 0x30
#define PCF50633_REG_LDO3OUT 0x31
#define PCF50633_REG_LDO3ENA 0x32
#define PCF50633_REG_LDO4OUT 0x33
#define PCF50633_REG_LDO4ENA 0x34
#define PCF50633_REG_LDO5OUT 0x35
#define PCF50633_REG_LDO5ENA 0x36
#define PCF50633_REG_LDO6OUT 0x37
#define PCF50633_REG_LDO6ENA 0x38
#define PCF50633_REG_HCLDOOUT 0x39
#define PCF50633_REG_HCLDOENA 0x3a
#define PCF50633_REG_HCLDOOVL 0x40
enum pcf50633_regulator_enable {
PCF50633_REGULATOR_ON = 0x01,
PCF50633_REGULATOR_ON_GPIO1 = 0x02,
PCF50633_REGULATOR_ON_GPIO2 = 0x04,
PCF50633_REGULATOR_ON_GPIO3 = 0x08,
};
#define PCF50633_REGULATOR_ON_MASK 0x0f
enum pcf50633_regulator_phase {
PCF50633_REGULATOR_ACTPH1 = 0x00,
PCF50633_REGULATOR_ACTPH2 = 0x10,
PCF50633_REGULATOR_ACTPH3 = 0x20,
PCF50633_REGULATOR_ACTPH4 = 0x30,
};
#define PCF50633_REGULATOR_ACTPH_MASK 0x30
enum pcf50633_regulator_id {
PCF50633_REGULATOR_AUTO,
PCF50633_REGULATOR_DOWN1,
PCF50633_REGULATOR_DOWN2,
PCF50633_REGULATOR_LDO1,
PCF50633_REGULATOR_LDO2,
PCF50633_REGULATOR_LDO3,
PCF50633_REGULATOR_LDO4,
PCF50633_REGULATOR_LDO5,
PCF50633_REGULATOR_LDO6,
PCF50633_REGULATOR_HCLDO,
PCF50633_REGULATOR_MEMLDO,
};
#endif

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kernel/include/linux/mfd/t7l66xb.h Normal file
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/*
* This file contains the definitions for the T7L66XB
*
* (C) Copyright 2005 Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef MFD_T7L66XB_H
#define MFD_T7L66XB_H
#include <linux/mfd/core.h>
#include <linux/mfd/tmio.h>
struct t7l66xb_platform_data {
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
int irq_base; /* The base for subdevice irqs */
struct tmio_nand_data *nand_data;
};
#define IRQ_T7L66XB_MMC (1)
#define IRQ_T7L66XB_NAND (3)
#define T7L66XB_NR_IRQS 8
#endif

20
kernel/include/linux/mfd/tc6387xb.h Normal file
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/*
* This file contains the definitions for the TC6387XB
*
* (C) Copyright 2005 Ian Molton <spyro@f2s.com>
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
*/
#ifndef MFD_TC6387XB_H
#define MFD_TC6387XB_H
struct tc6387xb_platform_data {
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
};
#endif

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kernel/include/linux/mfd/tc6393xb.h Normal file
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/*
* Toshiba TC6393XB SoC support
*
* Copyright(c) 2005-2006 Chris Humbert
* Copyright(c) 2005 Dirk Opfer
* Copyright(c) 2005 Ian Molton <spyro@f2s.com>
* Copyright(c) 2007 Dmitry Baryshkov
*
* Based on code written by Sharp/Lineo for 2.4 kernels
* Based on locomo.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef MFD_TC6393XB_H
#define MFD_TC6393XB_H
#include <linux/fb.h>
/* Also one should provide the CK3P6MI clock */
struct tc6393xb_platform_data {
u16 scr_pll2cr; /* PLL2 Control */
u16 scr_gper; /* GP Enable */
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
int irq_base; /* base for subdevice irqs */
int gpio_base;
int (*setup)(struct platform_device *dev);
void (*teardown)(struct platform_device *dev);
struct tmio_nand_data *nand_data;
struct tmio_fb_data *fb_data;
unsigned resume_restore : 1; /* make special actions
to preserve the state
on suspend/resume */
};
extern int tc6393xb_lcd_mode(struct platform_device *fb,
const struct fb_videomode *mode);
extern int tc6393xb_lcd_set_power(struct platform_device *fb, bool on);
/*
* Relative to irq_base
*/
#define IRQ_TC6393_NAND 0
#define IRQ_TC6393_MMC 1
#define IRQ_TC6393_OHCI 2
#define IRQ_TC6393_FB 4
#define TC6393XB_NR_IRQS 8
#endif

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#ifndef MFD_TMIO_H
#define MFD_TMIO_H
#include <linux/fb.h>
#define tmio_ioread8(addr) readb(addr)
#define tmio_ioread16(addr) readw(addr)
#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
#define tmio_ioread32(addr) \
(((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16))
#define tmio_iowrite8(val, addr) writeb((val), (addr))
#define tmio_iowrite16(val, addr) writew((val), (addr))
#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
#define tmio_iowrite32(val, addr) \
do { \
writew((val), (addr)); \
writew((val) >> 16, (addr) + 2); \
} while (0)
/*
* data for the MMC controller
*/
struct tmio_mmc_data {
const unsigned int hclk;
};
/*
* data for the NAND controller
*/
struct tmio_nand_data {
struct nand_bbt_descr *badblock_pattern;
struct mtd_partition *partition;
unsigned int num_partitions;
};
#define FBIO_TMIO_ACC_WRITE 0x7C639300
#define FBIO_TMIO_ACC_SYNC 0x7C639301
struct tmio_fb_data {
int (*lcd_set_power)(struct platform_device *fb_dev,
bool on);
int (*lcd_mode)(struct platform_device *fb_dev,
const struct fb_videomode *mode);
int num_modes;
struct fb_videomode *modes;
/* in mm: size of screen */
int height;
int width;
};
#endif

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kernel/include/linux/mfd/wm831x/auxadc.h Normal file
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/*
* include/linux/mfd/wm831x/auxadc.h -- Auxiliary ADC interface for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_AUXADC_H__
#define __MFD_WM831X_AUXADC_H__
/*
* R16429 (0x402D) - AuxADC Data
*/
#define WM831X_AUX_DATA_SRC_MASK 0xF000 /* AUX_DATA_SRC - [15:12] */
#define WM831X_AUX_DATA_SRC_SHIFT 12 /* AUX_DATA_SRC - [15:12] */
#define WM831X_AUX_DATA_SRC_WIDTH 4 /* AUX_DATA_SRC - [15:12] */
#define WM831X_AUX_DATA_MASK 0x0FFF /* AUX_DATA - [11:0] */
#define WM831X_AUX_DATA_SHIFT 0 /* AUX_DATA - [11:0] */
#define WM831X_AUX_DATA_WIDTH 12 /* AUX_DATA - [11:0] */
/*
* R16430 (0x402E) - AuxADC Control
*/
#define WM831X_AUX_ENA 0x8000 /* AUX_ENA */
#define WM831X_AUX_ENA_MASK 0x8000 /* AUX_ENA */
#define WM831X_AUX_ENA_SHIFT 15 /* AUX_ENA */
#define WM831X_AUX_ENA_WIDTH 1 /* AUX_ENA */
#define WM831X_AUX_CVT_ENA 0x4000 /* AUX_CVT_ENA */
#define WM831X_AUX_CVT_ENA_MASK 0x4000 /* AUX_CVT_ENA */
#define WM831X_AUX_CVT_ENA_SHIFT 14 /* AUX_CVT_ENA */
#define WM831X_AUX_CVT_ENA_WIDTH 1 /* AUX_CVT_ENA */
#define WM831X_AUX_SLPENA 0x1000 /* AUX_SLPENA */
#define WM831X_AUX_SLPENA_MASK 0x1000 /* AUX_SLPENA */
#define WM831X_AUX_SLPENA_SHIFT 12 /* AUX_SLPENA */
#define WM831X_AUX_SLPENA_WIDTH 1 /* AUX_SLPENA */
#define WM831X_AUX_FRC_ENA 0x0800 /* AUX_FRC_ENA */
#define WM831X_AUX_FRC_ENA_MASK 0x0800 /* AUX_FRC_ENA */
#define WM831X_AUX_FRC_ENA_SHIFT 11 /* AUX_FRC_ENA */
#define WM831X_AUX_FRC_ENA_WIDTH 1 /* AUX_FRC_ENA */
#define WM831X_AUX_RATE_MASK 0x003F /* AUX_RATE - [5:0] */
#define WM831X_AUX_RATE_SHIFT 0 /* AUX_RATE - [5:0] */
#define WM831X_AUX_RATE_WIDTH 6 /* AUX_RATE - [5:0] */
/*
* R16431 (0x402F) - AuxADC Source
*/
#define WM831X_AUX_CAL_SEL 0x8000 /* AUX_CAL_SEL */
#define WM831X_AUX_CAL_SEL_MASK 0x8000 /* AUX_CAL_SEL */
#define WM831X_AUX_CAL_SEL_SHIFT 15 /* AUX_CAL_SEL */
#define WM831X_AUX_CAL_SEL_WIDTH 1 /* AUX_CAL_SEL */
#define WM831X_AUX_BKUP_BATT_SEL 0x0400 /* AUX_BKUP_BATT_SEL */
#define WM831X_AUX_BKUP_BATT_SEL_MASK 0x0400 /* AUX_BKUP_BATT_SEL */
#define WM831X_AUX_BKUP_BATT_SEL_SHIFT 10 /* AUX_BKUP_BATT_SEL */
#define WM831X_AUX_BKUP_BATT_SEL_WIDTH 1 /* AUX_BKUP_BATT_SEL */
#define WM831X_AUX_WALL_SEL 0x0200 /* AUX_WALL_SEL */
#define WM831X_AUX_WALL_SEL_MASK 0x0200 /* AUX_WALL_SEL */
#define WM831X_AUX_WALL_SEL_SHIFT 9 /* AUX_WALL_SEL */
#define WM831X_AUX_WALL_SEL_WIDTH 1 /* AUX_WALL_SEL */
#define WM831X_AUX_BATT_SEL 0x0100 /* AUX_BATT_SEL */
#define WM831X_AUX_BATT_SEL_MASK 0x0100 /* AUX_BATT_SEL */
#define WM831X_AUX_BATT_SEL_SHIFT 8 /* AUX_BATT_SEL */
#define WM831X_AUX_BATT_SEL_WIDTH 1 /* AUX_BATT_SEL */
#define WM831X_AUX_USB_SEL 0x0080 /* AUX_USB_SEL */
#define WM831X_AUX_USB_SEL_MASK 0x0080 /* AUX_USB_SEL */
#define WM831X_AUX_USB_SEL_SHIFT 7 /* AUX_USB_SEL */
#define WM831X_AUX_USB_SEL_WIDTH 1 /* AUX_USB_SEL */
#define WM831X_AUX_SYSVDD_SEL 0x0040 /* AUX_SYSVDD_SEL */
#define WM831X_AUX_SYSVDD_SEL_MASK 0x0040 /* AUX_SYSVDD_SEL */
#define WM831X_AUX_SYSVDD_SEL_SHIFT 6 /* AUX_SYSVDD_SEL */
#define WM831X_AUX_SYSVDD_SEL_WIDTH 1 /* AUX_SYSVDD_SEL */
#define WM831X_AUX_BATT_TEMP_SEL 0x0020 /* AUX_BATT_TEMP_SEL */
#define WM831X_AUX_BATT_TEMP_SEL_MASK 0x0020 /* AUX_BATT_TEMP_SEL */
#define WM831X_AUX_BATT_TEMP_SEL_SHIFT 5 /* AUX_BATT_TEMP_SEL */
#define WM831X_AUX_BATT_TEMP_SEL_WIDTH 1 /* AUX_BATT_TEMP_SEL */
#define WM831X_AUX_CHIP_TEMP_SEL 0x0010 /* AUX_CHIP_TEMP_SEL */
#define WM831X_AUX_CHIP_TEMP_SEL_MASK 0x0010 /* AUX_CHIP_TEMP_SEL */
#define WM831X_AUX_CHIP_TEMP_SEL_SHIFT 4 /* AUX_CHIP_TEMP_SEL */
#define WM831X_AUX_CHIP_TEMP_SEL_WIDTH 1 /* AUX_CHIP_TEMP_SEL */
#define WM831X_AUX_AUX4_SEL 0x0008 /* AUX_AUX4_SEL */
#define WM831X_AUX_AUX4_SEL_MASK 0x0008 /* AUX_AUX4_SEL */
#define WM831X_AUX_AUX4_SEL_SHIFT 3 /* AUX_AUX4_SEL */
#define WM831X_AUX_AUX4_SEL_WIDTH 1 /* AUX_AUX4_SEL */
#define WM831X_AUX_AUX3_SEL 0x0004 /* AUX_AUX3_SEL */
#define WM831X_AUX_AUX3_SEL_MASK 0x0004 /* AUX_AUX3_SEL */
#define WM831X_AUX_AUX3_SEL_SHIFT 2 /* AUX_AUX3_SEL */
#define WM831X_AUX_AUX3_SEL_WIDTH 1 /* AUX_AUX3_SEL */
#define WM831X_AUX_AUX2_SEL 0x0002 /* AUX_AUX2_SEL */
#define WM831X_AUX_AUX2_SEL_MASK 0x0002 /* AUX_AUX2_SEL */
#define WM831X_AUX_AUX2_SEL_SHIFT 1 /* AUX_AUX2_SEL */
#define WM831X_AUX_AUX2_SEL_WIDTH 1 /* AUX_AUX2_SEL */
#define WM831X_AUX_AUX1_SEL 0x0001 /* AUX_AUX1_SEL */
#define WM831X_AUX_AUX1_SEL_MASK 0x0001 /* AUX_AUX1_SEL */
#define WM831X_AUX_AUX1_SEL_SHIFT 0 /* AUX_AUX1_SEL */
#define WM831X_AUX_AUX1_SEL_WIDTH 1 /* AUX_AUX1_SEL */
/*
* R16432 (0x4030) - Comparator Control
*/
#define WM831X_DCOMP4_STS 0x0800 /* DCOMP4_STS */
#define WM831X_DCOMP4_STS_MASK 0x0800 /* DCOMP4_STS */
#define WM831X_DCOMP4_STS_SHIFT 11 /* DCOMP4_STS */
#define WM831X_DCOMP4_STS_WIDTH 1 /* DCOMP4_STS */
#define WM831X_DCOMP3_STS 0x0400 /* DCOMP3_STS */
#define WM831X_DCOMP3_STS_MASK 0x0400 /* DCOMP3_STS */
#define WM831X_DCOMP3_STS_SHIFT 10 /* DCOMP3_STS */
#define WM831X_DCOMP3_STS_WIDTH 1 /* DCOMP3_STS */
#define WM831X_DCOMP2_STS 0x0200 /* DCOMP2_STS */
#define WM831X_DCOMP2_STS_MASK 0x0200 /* DCOMP2_STS */
#define WM831X_DCOMP2_STS_SHIFT 9 /* DCOMP2_STS */
#define WM831X_DCOMP2_STS_WIDTH 1 /* DCOMP2_STS */
#define WM831X_DCOMP1_STS 0x0100 /* DCOMP1_STS */
#define WM831X_DCOMP1_STS_MASK 0x0100 /* DCOMP1_STS */
#define WM831X_DCOMP1_STS_SHIFT 8 /* DCOMP1_STS */
#define WM831X_DCOMP1_STS_WIDTH 1 /* DCOMP1_STS */
#define WM831X_DCMP4_ENA 0x0008 /* DCMP4_ENA */
#define WM831X_DCMP4_ENA_MASK 0x0008 /* DCMP4_ENA */
#define WM831X_DCMP4_ENA_SHIFT 3 /* DCMP4_ENA */
#define WM831X_DCMP4_ENA_WIDTH 1 /* DCMP4_ENA */
#define WM831X_DCMP3_ENA 0x0004 /* DCMP3_ENA */
#define WM831X_DCMP3_ENA_MASK 0x0004 /* DCMP3_ENA */
#define WM831X_DCMP3_ENA_SHIFT 2 /* DCMP3_ENA */
#define WM831X_DCMP3_ENA_WIDTH 1 /* DCMP3_ENA */
#define WM831X_DCMP2_ENA 0x0002 /* DCMP2_ENA */
#define WM831X_DCMP2_ENA_MASK 0x0002 /* DCMP2_ENA */
#define WM831X_DCMP2_ENA_SHIFT 1 /* DCMP2_ENA */
#define WM831X_DCMP2_ENA_WIDTH 1 /* DCMP2_ENA */
#define WM831X_DCMP1_ENA 0x0001 /* DCMP1_ENA */
#define WM831X_DCMP1_ENA_MASK 0x0001 /* DCMP1_ENA */
#define WM831X_DCMP1_ENA_SHIFT 0 /* DCMP1_ENA */
#define WM831X_DCMP1_ENA_WIDTH 1 /* DCMP1_ENA */
/*
* R16433 (0x4031) - Comparator 1
*/
#define WM831X_DCMP1_SRC_MASK 0xE000 /* DCMP1_SRC - [15:13] */
#define WM831X_DCMP1_SRC_SHIFT 13 /* DCMP1_SRC - [15:13] */
#define WM831X_DCMP1_SRC_WIDTH 3 /* DCMP1_SRC - [15:13] */
#define WM831X_DCMP1_GT 0x1000 /* DCMP1_GT */
#define WM831X_DCMP1_GT_MASK 0x1000 /* DCMP1_GT */
#define WM831X_DCMP1_GT_SHIFT 12 /* DCMP1_GT */
#define WM831X_DCMP1_GT_WIDTH 1 /* DCMP1_GT */
#define WM831X_DCMP1_THR_MASK 0x0FFF /* DCMP1_THR - [11:0] */
#define WM831X_DCMP1_THR_SHIFT 0 /* DCMP1_THR - [11:0] */
#define WM831X_DCMP1_THR_WIDTH 12 /* DCMP1_THR - [11:0] */
/*
* R16434 (0x4032) - Comparator 2
*/
#define WM831X_DCMP2_SRC_MASK 0xE000 /* DCMP2_SRC - [15:13] */
#define WM831X_DCMP2_SRC_SHIFT 13 /* DCMP2_SRC - [15:13] */
#define WM831X_DCMP2_SRC_WIDTH 3 /* DCMP2_SRC - [15:13] */
#define WM831X_DCMP2_GT 0x1000 /* DCMP2_GT */
#define WM831X_DCMP2_GT_MASK 0x1000 /* DCMP2_GT */
#define WM831X_DCMP2_GT_SHIFT 12 /* DCMP2_GT */
#define WM831X_DCMP2_GT_WIDTH 1 /* DCMP2_GT */
#define WM831X_DCMP2_THR_MASK 0x0FFF /* DCMP2_THR - [11:0] */
#define WM831X_DCMP2_THR_SHIFT 0 /* DCMP2_THR - [11:0] */
#define WM831X_DCMP2_THR_WIDTH 12 /* DCMP2_THR - [11:0] */
/*
* R16435 (0x4033) - Comparator 3
*/
#define WM831X_DCMP3_SRC_MASK 0xE000 /* DCMP3_SRC - [15:13] */
#define WM831X_DCMP3_SRC_SHIFT 13 /* DCMP3_SRC - [15:13] */
#define WM831X_DCMP3_SRC_WIDTH 3 /* DCMP3_SRC - [15:13] */
#define WM831X_DCMP3_GT 0x1000 /* DCMP3_GT */
#define WM831X_DCMP3_GT_MASK 0x1000 /* DCMP3_GT */
#define WM831X_DCMP3_GT_SHIFT 12 /* DCMP3_GT */
#define WM831X_DCMP3_GT_WIDTH 1 /* DCMP3_GT */
#define WM831X_DCMP3_THR_MASK 0x0FFF /* DCMP3_THR - [11:0] */
#define WM831X_DCMP3_THR_SHIFT 0 /* DCMP3_THR - [11:0] */
#define WM831X_DCMP3_THR_WIDTH 12 /* DCMP3_THR - [11:0] */
/*
* R16436 (0x4034) - Comparator 4
*/
#define WM831X_DCMP4_SRC_MASK 0xE000 /* DCMP4_SRC - [15:13] */
#define WM831X_DCMP4_SRC_SHIFT 13 /* DCMP4_SRC - [15:13] */
#define WM831X_DCMP4_SRC_WIDTH 3 /* DCMP4_SRC - [15:13] */
#define WM831X_DCMP4_GT 0x1000 /* DCMP4_GT */
#define WM831X_DCMP4_GT_MASK 0x1000 /* DCMP4_GT */
#define WM831X_DCMP4_GT_SHIFT 12 /* DCMP4_GT */
#define WM831X_DCMP4_GT_WIDTH 1 /* DCMP4_GT */
#define WM831X_DCMP4_THR_MASK 0x0FFF /* DCMP4_THR - [11:0] */
#define WM831X_DCMP4_THR_SHIFT 0 /* DCMP4_THR - [11:0] */
#define WM831X_DCMP4_THR_WIDTH 12 /* DCMP4_THR - [11:0] */
#define WM831X_AUX_CAL_FACTOR 0xfff
#define WM831X_AUX_CAL_NOMINAL 0x222
enum wm831x_auxadc {
WM831X_AUX_CAL = 15,
WM831X_AUX_BKUP_BATT = 10,
WM831X_AUX_WALL = 9,
WM831X_AUX_BATT = 8,
WM831X_AUX_USB = 7,
WM831X_AUX_SYSVDD = 6,
WM831X_AUX_BATT_TEMP = 5,
WM831X_AUX_CHIP_TEMP = 4,
WM831X_AUX_AUX4 = 3,
WM831X_AUX_AUX3 = 2,
WM831X_AUX_AUX2 = 1,
WM831X_AUX_AUX1 = 0,
};
int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input);
int wm831x_auxadc_read_uv(struct wm831x *wm831x, enum wm831x_auxadc input);
#endif

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/*
* include/linux/mfd/wm831x/core.h -- Core interface for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_CORE_H__
#define __MFD_WM831X_CORE_H__
#include <linux/interrupt.h>
#include <linux/workqueue.h>
/*
* Register values.
*/
#define WM831X_RESET_ID 0x00
#define WM831X_REVISION 0x01
#define WM831X_PARENT_ID 0x4000
#define WM831X_SYSVDD_CONTROL 0x4001
#define WM831X_THERMAL_MONITORING 0x4002
#define WM831X_POWER_STATE 0x4003
#define WM831X_WATCHDOG 0x4004
#define WM831X_ON_PIN_CONTROL 0x4005
#define WM831X_RESET_CONTROL 0x4006
#define WM831X_CONTROL_INTERFACE 0x4007
#define WM831X_SECURITY_KEY 0x4008
#define WM831X_SOFTWARE_SCRATCH 0x4009
#define WM831X_OTP_CONTROL 0x400A
#define WM831X_GPIO_LEVEL 0x400C
#define WM831X_SYSTEM_STATUS 0x400D
#define WM831X_ON_SOURCE 0x400E
#define WM831X_OFF_SOURCE 0x400F
#define WM831X_SYSTEM_INTERRUPTS 0x4010
#define WM831X_INTERRUPT_STATUS_1 0x4011
#define WM831X_INTERRUPT_STATUS_2 0x4012
#define WM831X_INTERRUPT_STATUS_3 0x4013
#define WM831X_INTERRUPT_STATUS_4 0x4014
#define WM831X_INTERRUPT_STATUS_5 0x4015
#define WM831X_IRQ_CONFIG 0x4017
#define WM831X_SYSTEM_INTERRUPTS_MASK 0x4018
#define WM831X_INTERRUPT_STATUS_1_MASK 0x4019
#define WM831X_INTERRUPT_STATUS_2_MASK 0x401A
#define WM831X_INTERRUPT_STATUS_3_MASK 0x401B
#define WM831X_INTERRUPT_STATUS_4_MASK 0x401C
#define WM831X_INTERRUPT_STATUS_5_MASK 0x401D
#define WM831X_RTC_WRITE_COUNTER 0x4020
#define WM831X_RTC_TIME_1 0x4021
#define WM831X_RTC_TIME_2 0x4022
#define WM831X_RTC_ALARM_1 0x4023
#define WM831X_RTC_ALARM_2 0x4024
#define WM831X_RTC_CONTROL 0x4025
#define WM831X_RTC_TRIM 0x4026
#define WM831X_TOUCH_CONTROL_1 0x4028
#define WM831X_TOUCH_CONTROL_2 0x4029
#define WM831X_TOUCH_DATA_X 0x402A
#define WM831X_TOUCH_DATA_Y 0x402B
#define WM831X_TOUCH_DATA_Z 0x402C
#define WM831X_AUXADC_DATA 0x402D
#define WM831X_AUXADC_CONTROL 0x402E
#define WM831X_AUXADC_SOURCE 0x402F
#define WM831X_COMPARATOR_CONTROL 0x4030
#define WM831X_COMPARATOR_1 0x4031
#define WM831X_COMPARATOR_2 0x4032
#define WM831X_COMPARATOR_3 0x4033
#define WM831X_COMPARATOR_4 0x4034
#define WM831X_GPIO1_CONTROL 0x4038
#define WM831X_GPIO2_CONTROL 0x4039
#define WM831X_GPIO3_CONTROL 0x403A
#define WM831X_GPIO4_CONTROL 0x403B
#define WM831X_GPIO5_CONTROL 0x403C
#define WM831X_GPIO6_CONTROL 0x403D
#define WM831X_GPIO7_CONTROL 0x403E
#define WM831X_GPIO8_CONTROL 0x403F
#define WM831X_GPIO9_CONTROL 0x4040
#define WM831X_GPIO10_CONTROL 0x4041
#define WM831X_GPIO11_CONTROL 0x4042
#define WM831X_GPIO12_CONTROL 0x4043
#define WM831X_GPIO13_CONTROL 0x4044
#define WM831X_GPIO14_CONTROL 0x4045
#define WM831X_GPIO15_CONTROL 0x4046
#define WM831X_GPIO16_CONTROL 0x4047
#define WM831X_CHARGER_CONTROL_1 0x4048
#define WM831X_CHARGER_CONTROL_2 0x4049
#define WM831X_CHARGER_STATUS 0x404A
#define WM831X_BACKUP_CHARGER_CONTROL 0x404B
#define WM831X_STATUS_LED_1 0x404C
#define WM831X_STATUS_LED_2 0x404D
#define WM831X_CURRENT_SINK_1 0x404E
#define WM831X_CURRENT_SINK_2 0x404F
#define WM831X_DCDC_ENABLE 0x4050
#define WM831X_LDO_ENABLE 0x4051
#define WM831X_DCDC_STATUS 0x4052
#define WM831X_LDO_STATUS 0x4053
#define WM831X_DCDC_UV_STATUS 0x4054
#define WM831X_LDO_UV_STATUS 0x4055
#define WM831X_DC1_CONTROL_1 0x4056
#define WM831X_DC1_CONTROL_2 0x4057
#define WM831X_DC1_ON_CONFIG 0x4058
#define WM831X_DC1_SLEEP_CONTROL 0x4059
#define WM831X_DC1_DVS_CONTROL 0x405A
#define WM831X_DC2_CONTROL_1 0x405B
#define WM831X_DC2_CONTROL_2 0x405C
#define WM831X_DC2_ON_CONFIG 0x405D
#define WM831X_DC2_SLEEP_CONTROL 0x405E
#define WM831X_DC2_DVS_CONTROL 0x405F
#define WM831X_DC3_CONTROL_1 0x4060
#define WM831X_DC3_CONTROL_2 0x4061
#define WM831X_DC3_ON_CONFIG 0x4062
#define WM831X_DC3_SLEEP_CONTROL 0x4063
#define WM831X_DC4_CONTROL 0x4064
#define WM831X_DC4_SLEEP_CONTROL 0x4065
#define WM831X_EPE1_CONTROL 0x4066
#define WM831X_EPE2_CONTROL 0x4067
#define WM831X_LDO1_CONTROL 0x4068
#define WM831X_LDO1_ON_CONTROL 0x4069
#define WM831X_LDO1_SLEEP_CONTROL 0x406A
#define WM831X_LDO2_CONTROL 0x406B
#define WM831X_LDO2_ON_CONTROL 0x406C
#define WM831X_LDO2_SLEEP_CONTROL 0x406D
#define WM831X_LDO3_CONTROL 0x406E
#define WM831X_LDO3_ON_CONTROL 0x406F
#define WM831X_LDO3_SLEEP_CONTROL 0x4070
#define WM831X_LDO4_CONTROL 0x4071
#define WM831X_LDO4_ON_CONTROL 0x4072
#define WM831X_LDO4_SLEEP_CONTROL 0x4073
#define WM831X_LDO5_CONTROL 0x4074
#define WM831X_LDO5_ON_CONTROL 0x4075
#define WM831X_LDO5_SLEEP_CONTROL 0x4076
#define WM831X_LDO6_CONTROL 0x4077
#define WM831X_LDO6_ON_CONTROL 0x4078
#define WM831X_LDO6_SLEEP_CONTROL 0x4079
#define WM831X_LDO7_CONTROL 0x407A
#define WM831X_LDO7_ON_CONTROL 0x407B
#define WM831X_LDO7_SLEEP_CONTROL 0x407C
#define WM831X_LDO8_CONTROL 0x407D
#define WM831X_LDO8_ON_CONTROL 0x407E
#define WM831X_LDO8_SLEEP_CONTROL 0x407F
#define WM831X_LDO9_CONTROL 0x4080
#define WM831X_LDO9_ON_CONTROL 0x4081
#define WM831X_LDO9_SLEEP_CONTROL 0x4082
#define WM831X_LDO10_CONTROL 0x4083
#define WM831X_LDO10_ON_CONTROL 0x4084
#define WM831X_LDO10_SLEEP_CONTROL 0x4085
#define WM831X_LDO11_ON_CONTROL 0x4087
#define WM831X_LDO11_SLEEP_CONTROL 0x4088
#define WM831X_POWER_GOOD_SOURCE_1 0x408E
#define WM831X_POWER_GOOD_SOURCE_2 0x408F
#define WM831X_CLOCK_CONTROL_1 0x4090
#define WM831X_CLOCK_CONTROL_2 0x4091
#define WM831X_FLL_CONTROL_1 0x4092
#define WM831X_FLL_CONTROL_2 0x4093
#define WM831X_FLL_CONTROL_3 0x4094
#define WM831X_FLL_CONTROL_4 0x4095
#define WM831X_FLL_CONTROL_5 0x4096
#define WM831X_UNIQUE_ID_1 0x7800
#define WM831X_UNIQUE_ID_2 0x7801
#define WM831X_UNIQUE_ID_3 0x7802
#define WM831X_UNIQUE_ID_4 0x7803
#define WM831X_UNIQUE_ID_5 0x7804
#define WM831X_UNIQUE_ID_6 0x7805
#define WM831X_UNIQUE_ID_7 0x7806
#define WM831X_UNIQUE_ID_8 0x7807
#define WM831X_FACTORY_OTP_ID 0x7808
#define WM831X_FACTORY_OTP_1 0x7809
#define WM831X_FACTORY_OTP_2 0x780A
#define WM831X_FACTORY_OTP_3 0x780B
#define WM831X_FACTORY_OTP_4 0x780C
#define WM831X_FACTORY_OTP_5 0x780D
#define WM831X_CUSTOMER_OTP_ID 0x7810
#define WM831X_DC1_OTP_CONTROL 0x7811
#define WM831X_DC2_OTP_CONTROL 0x7812
#define WM831X_DC3_OTP_CONTROL 0x7813
#define WM831X_LDO1_2_OTP_CONTROL 0x7814
#define WM831X_LDO3_4_OTP_CONTROL 0x7815
#define WM831X_LDO5_6_OTP_CONTROL 0x7816
#define WM831X_LDO7_8_OTP_CONTROL 0x7817
#define WM831X_LDO9_10_OTP_CONTROL 0x7818
#define WM831X_LDO11_EPE_CONTROL 0x7819
#define WM831X_GPIO1_OTP_CONTROL 0x781A
#define WM831X_GPIO2_OTP_CONTROL 0x781B
#define WM831X_GPIO3_OTP_CONTROL 0x781C
#define WM831X_GPIO4_OTP_CONTROL 0x781D
#define WM831X_GPIO5_OTP_CONTROL 0x781E
#define WM831X_GPIO6_OTP_CONTROL 0x781F
#define WM831X_DBE_CHECK_DATA 0x7827
/*
* R0 (0x00) - Reset ID
*/
#define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
#define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
#define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
/*
* R1 (0x01) - Revision
*/
#define WM831X_PARENT_REV_MASK 0xFF00 /* PARENT_REV - [15:8] */
#define WM831X_PARENT_REV_SHIFT 8 /* PARENT_REV - [15:8] */
#define WM831X_PARENT_REV_WIDTH 8 /* PARENT_REV - [15:8] */
#define WM831X_CHILD_REV_MASK 0x00FF /* CHILD_REV - [7:0] */
#define WM831X_CHILD_REV_SHIFT 0 /* CHILD_REV - [7:0] */
#define WM831X_CHILD_REV_WIDTH 8 /* CHILD_REV - [7:0] */
/*
* R16384 (0x4000) - Parent ID
*/
#define WM831X_PARENT_ID_MASK 0xFFFF /* PARENT_ID - [15:0] */
#define WM831X_PARENT_ID_SHIFT 0 /* PARENT_ID - [15:0] */
#define WM831X_PARENT_ID_WIDTH 16 /* PARENT_ID - [15:0] */
/*
* R16389 (0x4005) - ON Pin Control
*/
#define WM831X_ON_PIN_SECACT_MASK 0x0300 /* ON_PIN_SECACT - [9:8] */
#define WM831X_ON_PIN_SECACT_SHIFT 8 /* ON_PIN_SECACT - [9:8] */
#define WM831X_ON_PIN_SECACT_WIDTH 2 /* ON_PIN_SECACT - [9:8] */
#define WM831X_ON_PIN_PRIMACT_MASK 0x0030 /* ON_PIN_PRIMACT - [5:4] */
#define WM831X_ON_PIN_PRIMACT_SHIFT 4 /* ON_PIN_PRIMACT - [5:4] */
#define WM831X_ON_PIN_PRIMACT_WIDTH 2 /* ON_PIN_PRIMACT - [5:4] */
#define WM831X_ON_PIN_STS 0x0008 /* ON_PIN_STS */
#define WM831X_ON_PIN_STS_MASK 0x0008 /* ON_PIN_STS */
#define WM831X_ON_PIN_STS_SHIFT 3 /* ON_PIN_STS */
#define WM831X_ON_PIN_STS_WIDTH 1 /* ON_PIN_STS */
#define WM831X_ON_PIN_TO_MASK 0x0003 /* ON_PIN_TO - [1:0] */
#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */
#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */
struct regulator_dev;
struct wm831x {
struct mutex io_lock;
struct device *dev;
int (*read_dev)(struct wm831x *wm831x, unsigned short reg,
int bytes, void *dest);
int (*write_dev)(struct wm831x *wm831x, unsigned short reg,
int bytes, void *src);
void *control_data;
int irq; /* Our chip IRQ */
struct mutex irq_lock;
struct workqueue_struct *irq_wq;
struct work_struct irq_work;
unsigned int irq_base;
int irq_masks[5];
struct mutex auxadc_lock;
/* The WM831x has a security key blocking access to certain
* registers. The mutex is taken by the accessors for locking
* and unlocking the security key, locked is used to fail
* writes if the lock is held.
*/
struct mutex key_lock;
unsigned int locked:1;
};
/* Device I/O API */
int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg);
int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
unsigned short val);
void wm831x_reg_lock(struct wm831x *wm831x);
int wm831x_reg_unlock(struct wm831x *wm831x);
int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
unsigned short mask, unsigned short val);
int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
int count, u16 *buf);
int wm831x_irq_init(struct wm831x *wm831x, int irq);
void wm831x_irq_exit(struct wm831x *wm831x);
int __must_check wm831x_request_irq(struct wm831x *wm831x,
unsigned int irq, irq_handler_t handler,
unsigned long flags, const char *name,
void *dev);
void wm831x_free_irq(struct wm831x *wm831x, unsigned int, void *);
void wm831x_disable_irq(struct wm831x *wm831x, int irq);
void wm831x_enable_irq(struct wm831x *wm831x, int irq);
#endif

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kernel/include/linux/mfd/wm831x/gpio.h Normal file
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/*
* include/linux/mfd/wm831x/gpio.h -- GPIO for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_GPIO_H__
#define __MFD_WM831X_GPIO_H__
/*
* R16440-16455 (0x4038-0x4047) - GPIOx Control
*/
#define WM831X_GPN_DIR 0x8000 /* GPN_DIR */
#define WM831X_GPN_DIR_MASK 0x8000 /* GPN_DIR */
#define WM831X_GPN_DIR_SHIFT 15 /* GPN_DIR */
#define WM831X_GPN_DIR_WIDTH 1 /* GPN_DIR */
#define WM831X_GPN_PULL_MASK 0x6000 /* GPN_PULL - [14:13] */
#define WM831X_GPN_PULL_SHIFT 13 /* GPN_PULL - [14:13] */
#define WM831X_GPN_PULL_WIDTH 2 /* GPN_PULL - [14:13] */
#define WM831X_GPN_INT_MODE 0x1000 /* GPN_INT_MODE */
#define WM831X_GPN_INT_MODE_MASK 0x1000 /* GPN_INT_MODE */
#define WM831X_GPN_INT_MODE_SHIFT 12 /* GPN_INT_MODE */
#define WM831X_GPN_INT_MODE_WIDTH 1 /* GPN_INT_MODE */
#define WM831X_GPN_PWR_DOM 0x0800 /* GPN_PWR_DOM */
#define WM831X_GPN_PWR_DOM_MASK 0x0800 /* GPN_PWR_DOM */
#define WM831X_GPN_PWR_DOM_SHIFT 11 /* GPN_PWR_DOM */
#define WM831X_GPN_PWR_DOM_WIDTH 1 /* GPN_PWR_DOM */
#define WM831X_GPN_POL 0x0400 /* GPN_POL */
#define WM831X_GPN_POL_MASK 0x0400 /* GPN_POL */
#define WM831X_GPN_POL_SHIFT 10 /* GPN_POL */
#define WM831X_GPN_POL_WIDTH 1 /* GPN_POL */
#define WM831X_GPN_OD 0x0200 /* GPN_OD */
#define WM831X_GPN_OD_MASK 0x0200 /* GPN_OD */
#define WM831X_GPN_OD_SHIFT 9 /* GPN_OD */
#define WM831X_GPN_OD_WIDTH 1 /* GPN_OD */
#define WM831X_GPN_TRI 0x0080 /* GPN_TRI */
#define WM831X_GPN_TRI_MASK 0x0080 /* GPN_TRI */
#define WM831X_GPN_TRI_SHIFT 7 /* GPN_TRI */
#define WM831X_GPN_TRI_WIDTH 1 /* GPN_TRI */
#define WM831X_GPN_FN_MASK 0x000F /* GPN_FN - [3:0] */
#define WM831X_GPN_FN_SHIFT 0 /* GPN_FN - [3:0] */
#define WM831X_GPN_FN_WIDTH 4 /* GPN_FN - [3:0] */
#define WM831X_GPIO_PULL_NONE (0 << WM831X_GPN_PULL_SHIFT)
#define WM831X_GPIO_PULL_DOWN (1 << WM831X_GPN_PULL_SHIFT)
#define WM831X_GPIO_PULL_UP (2 << WM831X_GPN_PULL_SHIFT)
#endif

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/*
* include/linux/mfd/wm831x/irq.h -- Interrupt controller for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_IRQ_H__
#define __MFD_WM831X_IRQ_H__
/* Interrupt number assignments within Linux */
#define WM831X_IRQ_TEMP_THW 0
#define WM831X_IRQ_GPIO_1 1
#define WM831X_IRQ_GPIO_2 2
#define WM831X_IRQ_GPIO_3 3
#define WM831X_IRQ_GPIO_4 4
#define WM831X_IRQ_GPIO_5 5
#define WM831X_IRQ_GPIO_6 6
#define WM831X_IRQ_GPIO_7 7
#define WM831X_IRQ_GPIO_8 8
#define WM831X_IRQ_GPIO_9 9
#define WM831X_IRQ_GPIO_10 10
#define WM831X_IRQ_GPIO_11 11
#define WM831X_IRQ_GPIO_12 12
#define WM831X_IRQ_GPIO_13 13
#define WM831X_IRQ_GPIO_14 14
#define WM831X_IRQ_GPIO_15 15
#define WM831X_IRQ_GPIO_16 16
#define WM831X_IRQ_ON 17
#define WM831X_IRQ_PPM_SYSLO 18
#define WM831X_IRQ_PPM_PWR_SRC 19
#define WM831X_IRQ_PPM_USB_CURR 20
#define WM831X_IRQ_WDOG_TO 21
#define WM831X_IRQ_RTC_PER 22
#define WM831X_IRQ_RTC_ALM 23
#define WM831X_IRQ_CHG_BATT_HOT 24
#define WM831X_IRQ_CHG_BATT_COLD 25
#define WM831X_IRQ_CHG_BATT_FAIL 26
#define WM831X_IRQ_CHG_OV 27
#define WM831X_IRQ_CHG_END 29
#define WM831X_IRQ_CHG_TO 30
#define WM831X_IRQ_CHG_MODE 31
#define WM831X_IRQ_CHG_START 32
#define WM831X_IRQ_TCHDATA 33
#define WM831X_IRQ_TCHPD 34
#define WM831X_IRQ_AUXADC_DATA 35
#define WM831X_IRQ_AUXADC_DCOMP1 36
#define WM831X_IRQ_AUXADC_DCOMP2 37
#define WM831X_IRQ_AUXADC_DCOMP3 38
#define WM831X_IRQ_AUXADC_DCOMP4 39
#define WM831X_IRQ_CS1 40
#define WM831X_IRQ_CS2 41
#define WM831X_IRQ_HC_DC1 42
#define WM831X_IRQ_HC_DC2 43
#define WM831X_IRQ_UV_LDO1 44
#define WM831X_IRQ_UV_LDO2 45
#define WM831X_IRQ_UV_LDO3 46
#define WM831X_IRQ_UV_LDO4 47
#define WM831X_IRQ_UV_LDO5 48
#define WM831X_IRQ_UV_LDO6 49
#define WM831X_IRQ_UV_LDO7 50
#define WM831X_IRQ_UV_LDO8 51
#define WM831X_IRQ_UV_LDO9 52
#define WM831X_IRQ_UV_LDO10 53
#define WM831X_IRQ_UV_DC1 54
#define WM831X_IRQ_UV_DC2 55
#define WM831X_IRQ_UV_DC3 56
#define WM831X_IRQ_UV_DC4 57
#define WM831X_NUM_IRQS 58
/*
* R16400 (0x4010) - System Interrupts
*/
#define WM831X_PS_INT 0x8000 /* PS_INT */
#define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
#define WM831X_PS_INT_SHIFT 15 /* PS_INT */
#define WM831X_PS_INT_WIDTH 1 /* PS_INT */
#define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
#define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
#define WM831X_TEMP_INT_SHIFT 14 /* TEMP_INT */
#define WM831X_TEMP_INT_WIDTH 1 /* TEMP_INT */
#define WM831X_GP_INT 0x2000 /* GP_INT */
#define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
#define WM831X_GP_INT_SHIFT 13 /* GP_INT */
#define WM831X_GP_INT_WIDTH 1 /* GP_INT */
#define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
#define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
#define WM831X_ON_PIN_INT_SHIFT 12 /* ON_PIN_INT */
#define WM831X_ON_PIN_INT_WIDTH 1 /* ON_PIN_INT */
#define WM831X_WDOG_INT 0x0800 /* WDOG_INT */
#define WM831X_WDOG_INT_MASK 0x0800 /* WDOG_INT */
#define WM831X_WDOG_INT_SHIFT 11 /* WDOG_INT */
#define WM831X_WDOG_INT_WIDTH 1 /* WDOG_INT */
#define WM831X_TCHDATA_INT 0x0400 /* TCHDATA_INT */
#define WM831X_TCHDATA_INT_MASK 0x0400 /* TCHDATA_INT */
#define WM831X_TCHDATA_INT_SHIFT 10 /* TCHDATA_INT */
#define WM831X_TCHDATA_INT_WIDTH 1 /* TCHDATA_INT */
#define WM831X_TCHPD_INT 0x0200 /* TCHPD_INT */
#define WM831X_TCHPD_INT_MASK 0x0200 /* TCHPD_INT */
#define WM831X_TCHPD_INT_SHIFT 9 /* TCHPD_INT */
#define WM831X_TCHPD_INT_WIDTH 1 /* TCHPD_INT */
#define WM831X_AUXADC_INT 0x0100 /* AUXADC_INT */
#define WM831X_AUXADC_INT_MASK 0x0100 /* AUXADC_INT */
#define WM831X_AUXADC_INT_SHIFT 8 /* AUXADC_INT */
#define WM831X_AUXADC_INT_WIDTH 1 /* AUXADC_INT */
#define WM831X_PPM_INT 0x0080 /* PPM_INT */
#define WM831X_PPM_INT_MASK 0x0080 /* PPM_INT */
#define WM831X_PPM_INT_SHIFT 7 /* PPM_INT */
#define WM831X_PPM_INT_WIDTH 1 /* PPM_INT */
#define WM831X_CS_INT 0x0040 /* CS_INT */
#define WM831X_CS_INT_MASK 0x0040 /* CS_INT */
#define WM831X_CS_INT_SHIFT 6 /* CS_INT */
#define WM831X_CS_INT_WIDTH 1 /* CS_INT */
#define WM831X_RTC_INT 0x0020 /* RTC_INT */
#define WM831X_RTC_INT_MASK 0x0020 /* RTC_INT */
#define WM831X_RTC_INT_SHIFT 5 /* RTC_INT */
#define WM831X_RTC_INT_WIDTH 1 /* RTC_INT */
#define WM831X_OTP_INT 0x0010 /* OTP_INT */
#define WM831X_OTP_INT_MASK 0x0010 /* OTP_INT */
#define WM831X_OTP_INT_SHIFT 4 /* OTP_INT */
#define WM831X_OTP_INT_WIDTH 1 /* OTP_INT */
#define WM831X_CHILD_INT 0x0008 /* CHILD_INT */
#define WM831X_CHILD_INT_MASK 0x0008 /* CHILD_INT */
#define WM831X_CHILD_INT_SHIFT 3 /* CHILD_INT */
#define WM831X_CHILD_INT_WIDTH 1 /* CHILD_INT */
#define WM831X_CHG_INT 0x0004 /* CHG_INT */
#define WM831X_CHG_INT_MASK 0x0004 /* CHG_INT */
#define WM831X_CHG_INT_SHIFT 2 /* CHG_INT */
#define WM831X_CHG_INT_WIDTH 1 /* CHG_INT */
#define WM831X_HC_INT 0x0002 /* HC_INT */
#define WM831X_HC_INT_MASK 0x0002 /* HC_INT */
#define WM831X_HC_INT_SHIFT 1 /* HC_INT */
#define WM831X_HC_INT_WIDTH 1 /* HC_INT */
#define WM831X_UV_INT 0x0001 /* UV_INT */
#define WM831X_UV_INT_MASK 0x0001 /* UV_INT */
#define WM831X_UV_INT_SHIFT 0 /* UV_INT */
#define WM831X_UV_INT_WIDTH 1 /* UV_INT */
/*
* R16401 (0x4011) - Interrupt Status 1
*/
#define WM831X_PPM_SYSLO_EINT 0x8000 /* PPM_SYSLO_EINT */
#define WM831X_PPM_SYSLO_EINT_MASK 0x8000 /* PPM_SYSLO_EINT */
#define WM831X_PPM_SYSLO_EINT_SHIFT 15 /* PPM_SYSLO_EINT */
#define WM831X_PPM_SYSLO_EINT_WIDTH 1 /* PPM_SYSLO_EINT */
#define WM831X_PPM_PWR_SRC_EINT 0x4000 /* PPM_PWR_SRC_EINT */
#define WM831X_PPM_PWR_SRC_EINT_MASK 0x4000 /* PPM_PWR_SRC_EINT */
#define WM831X_PPM_PWR_SRC_EINT_SHIFT 14 /* PPM_PWR_SRC_EINT */
#define WM831X_PPM_PWR_SRC_EINT_WIDTH 1 /* PPM_PWR_SRC_EINT */
#define WM831X_PPM_USB_CURR_EINT 0x2000 /* PPM_USB_CURR_EINT */
#define WM831X_PPM_USB_CURR_EINT_MASK 0x2000 /* PPM_USB_CURR_EINT */
#define WM831X_PPM_USB_CURR_EINT_SHIFT 13 /* PPM_USB_CURR_EINT */
#define WM831X_PPM_USB_CURR_EINT_WIDTH 1 /* PPM_USB_CURR_EINT */
#define WM831X_ON_PIN_EINT 0x1000 /* ON_PIN_EINT */
#define WM831X_ON_PIN_EINT_MASK 0x1000 /* ON_PIN_EINT */
#define WM831X_ON_PIN_EINT_SHIFT 12 /* ON_PIN_EINT */
#define WM831X_ON_PIN_EINT_WIDTH 1 /* ON_PIN_EINT */
#define WM831X_WDOG_TO_EINT 0x0800 /* WDOG_TO_EINT */
#define WM831X_WDOG_TO_EINT_MASK 0x0800 /* WDOG_TO_EINT */
#define WM831X_WDOG_TO_EINT_SHIFT 11 /* WDOG_TO_EINT */
#define WM831X_WDOG_TO_EINT_WIDTH 1 /* WDOG_TO_EINT */
#define WM831X_TCHDATA_EINT 0x0400 /* TCHDATA_EINT */
#define WM831X_TCHDATA_EINT_MASK 0x0400 /* TCHDATA_EINT */
#define WM831X_TCHDATA_EINT_SHIFT 10 /* TCHDATA_EINT */
#define WM831X_TCHDATA_EINT_WIDTH 1 /* TCHDATA_EINT */
#define WM831X_TCHPD_EINT 0x0200 /* TCHPD_EINT */
#define WM831X_TCHPD_EINT_MASK 0x0200 /* TCHPD_EINT */
#define WM831X_TCHPD_EINT_SHIFT 9 /* TCHPD_EINT */
#define WM831X_TCHPD_EINT_WIDTH 1 /* TCHPD_EINT */
#define WM831X_AUXADC_DATA_EINT 0x0100 /* AUXADC_DATA_EINT */
#define WM831X_AUXADC_DATA_EINT_MASK 0x0100 /* AUXADC_DATA_EINT */
#define WM831X_AUXADC_DATA_EINT_SHIFT 8 /* AUXADC_DATA_EINT */
#define WM831X_AUXADC_DATA_EINT_WIDTH 1 /* AUXADC_DATA_EINT */
#define WM831X_AUXADC_DCOMP4_EINT 0x0080 /* AUXADC_DCOMP4_EINT */
#define WM831X_AUXADC_DCOMP4_EINT_MASK 0x0080 /* AUXADC_DCOMP4_EINT */
#define WM831X_AUXADC_DCOMP4_EINT_SHIFT 7 /* AUXADC_DCOMP4_EINT */
#define WM831X_AUXADC_DCOMP4_EINT_WIDTH 1 /* AUXADC_DCOMP4_EINT */
#define WM831X_AUXADC_DCOMP3_EINT 0x0040 /* AUXADC_DCOMP3_EINT */
#define WM831X_AUXADC_DCOMP3_EINT_MASK 0x0040 /* AUXADC_DCOMP3_EINT */
#define WM831X_AUXADC_DCOMP3_EINT_SHIFT 6 /* AUXADC_DCOMP3_EINT */
#define WM831X_AUXADC_DCOMP3_EINT_WIDTH 1 /* AUXADC_DCOMP3_EINT */
#define WM831X_AUXADC_DCOMP2_EINT 0x0020 /* AUXADC_DCOMP2_EINT */
#define WM831X_AUXADC_DCOMP2_EINT_MASK 0x0020 /* AUXADC_DCOMP2_EINT */
#define WM831X_AUXADC_DCOMP2_EINT_SHIFT 5 /* AUXADC_DCOMP2_EINT */
#define WM831X_AUXADC_DCOMP2_EINT_WIDTH 1 /* AUXADC_DCOMP2_EINT */
#define WM831X_AUXADC_DCOMP1_EINT 0x0010 /* AUXADC_DCOMP1_EINT */
#define WM831X_AUXADC_DCOMP1_EINT_MASK 0x0010 /* AUXADC_DCOMP1_EINT */
#define WM831X_AUXADC_DCOMP1_EINT_SHIFT 4 /* AUXADC_DCOMP1_EINT */
#define WM831X_AUXADC_DCOMP1_EINT_WIDTH 1 /* AUXADC_DCOMP1_EINT */
#define WM831X_RTC_PER_EINT 0x0008 /* RTC_PER_EINT */
#define WM831X_RTC_PER_EINT_MASK 0x0008 /* RTC_PER_EINT */
#define WM831X_RTC_PER_EINT_SHIFT 3 /* RTC_PER_EINT */
#define WM831X_RTC_PER_EINT_WIDTH 1 /* RTC_PER_EINT */
#define WM831X_RTC_ALM_EINT 0x0004 /* RTC_ALM_EINT */
#define WM831X_RTC_ALM_EINT_MASK 0x0004 /* RTC_ALM_EINT */
#define WM831X_RTC_ALM_EINT_SHIFT 2 /* RTC_ALM_EINT */
#define WM831X_RTC_ALM_EINT_WIDTH 1 /* RTC_ALM_EINT */
#define WM831X_TEMP_THW_EINT 0x0002 /* TEMP_THW_EINT */
#define WM831X_TEMP_THW_EINT_MASK 0x0002 /* TEMP_THW_EINT */
#define WM831X_TEMP_THW_EINT_SHIFT 1 /* TEMP_THW_EINT */
#define WM831X_TEMP_THW_EINT_WIDTH 1 /* TEMP_THW_EINT */
/*
* R16402 (0x4012) - Interrupt Status 2
*/
#define WM831X_CHG_BATT_HOT_EINT 0x8000 /* CHG_BATT_HOT_EINT */
#define WM831X_CHG_BATT_HOT_EINT_MASK 0x8000 /* CHG_BATT_HOT_EINT */
#define WM831X_CHG_BATT_HOT_EINT_SHIFT 15 /* CHG_BATT_HOT_EINT */
#define WM831X_CHG_BATT_HOT_EINT_WIDTH 1 /* CHG_BATT_HOT_EINT */
#define WM831X_CHG_BATT_COLD_EINT 0x4000 /* CHG_BATT_COLD_EINT */
#define WM831X_CHG_BATT_COLD_EINT_MASK 0x4000 /* CHG_BATT_COLD_EINT */
#define WM831X_CHG_BATT_COLD_EINT_SHIFT 14 /* CHG_BATT_COLD_EINT */
#define WM831X_CHG_BATT_COLD_EINT_WIDTH 1 /* CHG_BATT_COLD_EINT */
#define WM831X_CHG_BATT_FAIL_EINT 0x2000 /* CHG_BATT_FAIL_EINT */
#define WM831X_CHG_BATT_FAIL_EINT_MASK 0x2000 /* CHG_BATT_FAIL_EINT */
#define WM831X_CHG_BATT_FAIL_EINT_SHIFT 13 /* CHG_BATT_FAIL_EINT */
#define WM831X_CHG_BATT_FAIL_EINT_WIDTH 1 /* CHG_BATT_FAIL_EINT */
#define WM831X_CHG_OV_EINT 0x1000 /* CHG_OV_EINT */
#define WM831X_CHG_OV_EINT_MASK 0x1000 /* CHG_OV_EINT */
#define WM831X_CHG_OV_EINT_SHIFT 12 /* CHG_OV_EINT */
#define WM831X_CHG_OV_EINT_WIDTH 1 /* CHG_OV_EINT */
#define WM831X_CHG_END_EINT 0x0800 /* CHG_END_EINT */
#define WM831X_CHG_END_EINT_MASK 0x0800 /* CHG_END_EINT */
#define WM831X_CHG_END_EINT_SHIFT 11 /* CHG_END_EINT */
#define WM831X_CHG_END_EINT_WIDTH 1 /* CHG_END_EINT */
#define WM831X_CHG_TO_EINT 0x0400 /* CHG_TO_EINT */
#define WM831X_CHG_TO_EINT_MASK 0x0400 /* CHG_TO_EINT */
#define WM831X_CHG_TO_EINT_SHIFT 10 /* CHG_TO_EINT */
#define WM831X_CHG_TO_EINT_WIDTH 1 /* CHG_TO_EINT */
#define WM831X_CHG_MODE_EINT 0x0200 /* CHG_MODE_EINT */
#define WM831X_CHG_MODE_EINT_MASK 0x0200 /* CHG_MODE_EINT */
#define WM831X_CHG_MODE_EINT_SHIFT 9 /* CHG_MODE_EINT */
#define WM831X_CHG_MODE_EINT_WIDTH 1 /* CHG_MODE_EINT */
#define WM831X_CHG_START_EINT 0x0100 /* CHG_START_EINT */
#define WM831X_CHG_START_EINT_MASK 0x0100 /* CHG_START_EINT */
#define WM831X_CHG_START_EINT_SHIFT 8 /* CHG_START_EINT */
#define WM831X_CHG_START_EINT_WIDTH 1 /* CHG_START_EINT */
#define WM831X_CS2_EINT 0x0080 /* CS2_EINT */
#define WM831X_CS2_EINT_MASK 0x0080 /* CS2_EINT */
#define WM831X_CS2_EINT_SHIFT 7 /* CS2_EINT */
#define WM831X_CS2_EINT_WIDTH 1 /* CS2_EINT */
#define WM831X_CS1_EINT 0x0040 /* CS1_EINT */
#define WM831X_CS1_EINT_MASK 0x0040 /* CS1_EINT */
#define WM831X_CS1_EINT_SHIFT 6 /* CS1_EINT */
#define WM831X_CS1_EINT_WIDTH 1 /* CS1_EINT */
#define WM831X_OTP_CMD_END_EINT 0x0020 /* OTP_CMD_END_EINT */
#define WM831X_OTP_CMD_END_EINT_MASK 0x0020 /* OTP_CMD_END_EINT */
#define WM831X_OTP_CMD_END_EINT_SHIFT 5 /* OTP_CMD_END_EINT */
#define WM831X_OTP_CMD_END_EINT_WIDTH 1 /* OTP_CMD_END_EINT */
#define WM831X_OTP_ERR_EINT 0x0010 /* OTP_ERR_EINT */
#define WM831X_OTP_ERR_EINT_MASK 0x0010 /* OTP_ERR_EINT */
#define WM831X_OTP_ERR_EINT_SHIFT 4 /* OTP_ERR_EINT */
#define WM831X_OTP_ERR_EINT_WIDTH 1 /* OTP_ERR_EINT */
#define WM831X_PS_POR_EINT 0x0004 /* PS_POR_EINT */
#define WM831X_PS_POR_EINT_MASK 0x0004 /* PS_POR_EINT */
#define WM831X_PS_POR_EINT_SHIFT 2 /* PS_POR_EINT */
#define WM831X_PS_POR_EINT_WIDTH 1 /* PS_POR_EINT */
#define WM831X_PS_SLEEP_OFF_EINT 0x0002 /* PS_SLEEP_OFF_EINT */
#define WM831X_PS_SLEEP_OFF_EINT_MASK 0x0002 /* PS_SLEEP_OFF_EINT */
#define WM831X_PS_SLEEP_OFF_EINT_SHIFT 1 /* PS_SLEEP_OFF_EINT */
#define WM831X_PS_SLEEP_OFF_EINT_WIDTH 1 /* PS_SLEEP_OFF_EINT */
#define WM831X_PS_ON_WAKE_EINT 0x0001 /* PS_ON_WAKE_EINT */
#define WM831X_PS_ON_WAKE_EINT_MASK 0x0001 /* PS_ON_WAKE_EINT */
#define WM831X_PS_ON_WAKE_EINT_SHIFT 0 /* PS_ON_WAKE_EINT */
#define WM831X_PS_ON_WAKE_EINT_WIDTH 1 /* PS_ON_WAKE_EINT */
/*
* R16403 (0x4013) - Interrupt Status 3
*/
#define WM831X_UV_LDO10_EINT 0x0200 /* UV_LDO10_EINT */
#define WM831X_UV_LDO10_EINT_MASK 0x0200 /* UV_LDO10_EINT */
#define WM831X_UV_LDO10_EINT_SHIFT 9 /* UV_LDO10_EINT */
#define WM831X_UV_LDO10_EINT_WIDTH 1 /* UV_LDO10_EINT */
#define WM831X_UV_LDO9_EINT 0x0100 /* UV_LDO9_EINT */
#define WM831X_UV_LDO9_EINT_MASK 0x0100 /* UV_LDO9_EINT */
#define WM831X_UV_LDO9_EINT_SHIFT 8 /* UV_LDO9_EINT */
#define WM831X_UV_LDO9_EINT_WIDTH 1 /* UV_LDO9_EINT */
#define WM831X_UV_LDO8_EINT 0x0080 /* UV_LDO8_EINT */
#define WM831X_UV_LDO8_EINT_MASK 0x0080 /* UV_LDO8_EINT */
#define WM831X_UV_LDO8_EINT_SHIFT 7 /* UV_LDO8_EINT */
#define WM831X_UV_LDO8_EINT_WIDTH 1 /* UV_LDO8_EINT */
#define WM831X_UV_LDO7_EINT 0x0040 /* UV_LDO7_EINT */
#define WM831X_UV_LDO7_EINT_MASK 0x0040 /* UV_LDO7_EINT */
#define WM831X_UV_LDO7_EINT_SHIFT 6 /* UV_LDO7_EINT */
#define WM831X_UV_LDO7_EINT_WIDTH 1 /* UV_LDO7_EINT */
#define WM831X_UV_LDO6_EINT 0x0020 /* UV_LDO6_EINT */
#define WM831X_UV_LDO6_EINT_MASK 0x0020 /* UV_LDO6_EINT */
#define WM831X_UV_LDO6_EINT_SHIFT 5 /* UV_LDO6_EINT */
#define WM831X_UV_LDO6_EINT_WIDTH 1 /* UV_LDO6_EINT */
#define WM831X_UV_LDO5_EINT 0x0010 /* UV_LDO5_EINT */
#define WM831X_UV_LDO5_EINT_MASK 0x0010 /* UV_LDO5_EINT */
#define WM831X_UV_LDO5_EINT_SHIFT 4 /* UV_LDO5_EINT */
#define WM831X_UV_LDO5_EINT_WIDTH 1 /* UV_LDO5_EINT */
#define WM831X_UV_LDO4_EINT 0x0008 /* UV_LDO4_EINT */
#define WM831X_UV_LDO4_EINT_MASK 0x0008 /* UV_LDO4_EINT */
#define WM831X_UV_LDO4_EINT_SHIFT 3 /* UV_LDO4_EINT */
#define WM831X_UV_LDO4_EINT_WIDTH 1 /* UV_LDO4_EINT */
#define WM831X_UV_LDO3_EINT 0x0004 /* UV_LDO3_EINT */
#define WM831X_UV_LDO3_EINT_MASK 0x0004 /* UV_LDO3_EINT */
#define WM831X_UV_LDO3_EINT_SHIFT 2 /* UV_LDO3_EINT */
#define WM831X_UV_LDO3_EINT_WIDTH 1 /* UV_LDO3_EINT */
#define WM831X_UV_LDO2_EINT 0x0002 /* UV_LDO2_EINT */
#define WM831X_UV_LDO2_EINT_MASK 0x0002 /* UV_LDO2_EINT */
#define WM831X_UV_LDO2_EINT_SHIFT 1 /* UV_LDO2_EINT */
#define WM831X_UV_LDO2_EINT_WIDTH 1 /* UV_LDO2_EINT */
#define WM831X_UV_LDO1_EINT 0x0001 /* UV_LDO1_EINT */
#define WM831X_UV_LDO1_EINT_MASK 0x0001 /* UV_LDO1_EINT */
#define WM831X_UV_LDO1_EINT_SHIFT 0 /* UV_LDO1_EINT */
#define WM831X_UV_LDO1_EINT_WIDTH 1 /* UV_LDO1_EINT */
/*
* R16404 (0x4014) - Interrupt Status 4
*/
#define WM831X_HC_DC2_EINT 0x0200 /* HC_DC2_EINT */
#define WM831X_HC_DC2_EINT_MASK 0x0200 /* HC_DC2_EINT */
#define WM831X_HC_DC2_EINT_SHIFT 9 /* HC_DC2_EINT */
#define WM831X_HC_DC2_EINT_WIDTH 1 /* HC_DC2_EINT */
#define WM831X_HC_DC1_EINT 0x0100 /* HC_DC1_EINT */
#define WM831X_HC_DC1_EINT_MASK 0x0100 /* HC_DC1_EINT */
#define WM831X_HC_DC1_EINT_SHIFT 8 /* HC_DC1_EINT */
#define WM831X_HC_DC1_EINT_WIDTH 1 /* HC_DC1_EINT */
#define WM831X_UV_DC4_EINT 0x0008 /* UV_DC4_EINT */
#define WM831X_UV_DC4_EINT_MASK 0x0008 /* UV_DC4_EINT */
#define WM831X_UV_DC4_EINT_SHIFT 3 /* UV_DC4_EINT */
#define WM831X_UV_DC4_EINT_WIDTH 1 /* UV_DC4_EINT */
#define WM831X_UV_DC3_EINT 0x0004 /* UV_DC3_EINT */
#define WM831X_UV_DC3_EINT_MASK 0x0004 /* UV_DC3_EINT */
#define WM831X_UV_DC3_EINT_SHIFT 2 /* UV_DC3_EINT */
#define WM831X_UV_DC3_EINT_WIDTH 1 /* UV_DC3_EINT */
#define WM831X_UV_DC2_EINT 0x0002 /* UV_DC2_EINT */
#define WM831X_UV_DC2_EINT_MASK 0x0002 /* UV_DC2_EINT */
#define WM831X_UV_DC2_EINT_SHIFT 1 /* UV_DC2_EINT */
#define WM831X_UV_DC2_EINT_WIDTH 1 /* UV_DC2_EINT */
#define WM831X_UV_DC1_EINT 0x0001 /* UV_DC1_EINT */
#define WM831X_UV_DC1_EINT_MASK 0x0001 /* UV_DC1_EINT */
#define WM831X_UV_DC1_EINT_SHIFT 0 /* UV_DC1_EINT */
#define WM831X_UV_DC1_EINT_WIDTH 1 /* UV_DC1_EINT */
/*
* R16405 (0x4015) - Interrupt Status 5
*/
#define WM831X_GP16_EINT 0x8000 /* GP16_EINT */
#define WM831X_GP16_EINT_MASK 0x8000 /* GP16_EINT */
#define WM831X_GP16_EINT_SHIFT 15 /* GP16_EINT */
#define WM831X_GP16_EINT_WIDTH 1 /* GP16_EINT */
#define WM831X_GP15_EINT 0x4000 /* GP15_EINT */
#define WM831X_GP15_EINT_MASK 0x4000 /* GP15_EINT */
#define WM831X_GP15_EINT_SHIFT 14 /* GP15_EINT */
#define WM831X_GP15_EINT_WIDTH 1 /* GP15_EINT */
#define WM831X_GP14_EINT 0x2000 /* GP14_EINT */
#define WM831X_GP14_EINT_MASK 0x2000 /* GP14_EINT */
#define WM831X_GP14_EINT_SHIFT 13 /* GP14_EINT */
#define WM831X_GP14_EINT_WIDTH 1 /* GP14_EINT */
#define WM831X_GP13_EINT 0x1000 /* GP13_EINT */
#define WM831X_GP13_EINT_MASK 0x1000 /* GP13_EINT */
#define WM831X_GP13_EINT_SHIFT 12 /* GP13_EINT */
#define WM831X_GP13_EINT_WIDTH 1 /* GP13_EINT */
#define WM831X_GP12_EINT 0x0800 /* GP12_EINT */
#define WM831X_GP12_EINT_MASK 0x0800 /* GP12_EINT */
#define WM831X_GP12_EINT_SHIFT 11 /* GP12_EINT */
#define WM831X_GP12_EINT_WIDTH 1 /* GP12_EINT */
#define WM831X_GP11_EINT 0x0400 /* GP11_EINT */
#define WM831X_GP11_EINT_MASK 0x0400 /* GP11_EINT */
#define WM831X_GP11_EINT_SHIFT 10 /* GP11_EINT */
#define WM831X_GP11_EINT_WIDTH 1 /* GP11_EINT */
#define WM831X_GP10_EINT 0x0200 /* GP10_EINT */
#define WM831X_GP10_EINT_MASK 0x0200 /* GP10_EINT */
#define WM831X_GP10_EINT_SHIFT 9 /* GP10_EINT */
#define WM831X_GP10_EINT_WIDTH 1 /* GP10_EINT */
#define WM831X_GP9_EINT 0x0100 /* GP9_EINT */
#define WM831X_GP9_EINT_MASK 0x0100 /* GP9_EINT */
#define WM831X_GP9_EINT_SHIFT 8 /* GP9_EINT */
#define WM831X_GP9_EINT_WIDTH 1 /* GP9_EINT */
#define WM831X_GP8_EINT 0x0080 /* GP8_EINT */
#define WM831X_GP8_EINT_MASK 0x0080 /* GP8_EINT */
#define WM831X_GP8_EINT_SHIFT 7 /* GP8_EINT */
#define WM831X_GP8_EINT_WIDTH 1 /* GP8_EINT */
#define WM831X_GP7_EINT 0x0040 /* GP7_EINT */
#define WM831X_GP7_EINT_MASK 0x0040 /* GP7_EINT */
#define WM831X_GP7_EINT_SHIFT 6 /* GP7_EINT */
#define WM831X_GP7_EINT_WIDTH 1 /* GP7_EINT */
#define WM831X_GP6_EINT 0x0020 /* GP6_EINT */
#define WM831X_GP6_EINT_MASK 0x0020 /* GP6_EINT */
#define WM831X_GP6_EINT_SHIFT 5 /* GP6_EINT */
#define WM831X_GP6_EINT_WIDTH 1 /* GP6_EINT */
#define WM831X_GP5_EINT 0x0010 /* GP5_EINT */
#define WM831X_GP5_EINT_MASK 0x0010 /* GP5_EINT */
#define WM831X_GP5_EINT_SHIFT 4 /* GP5_EINT */
#define WM831X_GP5_EINT_WIDTH 1 /* GP5_EINT */
#define WM831X_GP4_EINT 0x0008 /* GP4_EINT */
#define WM831X_GP4_EINT_MASK 0x0008 /* GP4_EINT */
#define WM831X_GP4_EINT_SHIFT 3 /* GP4_EINT */
#define WM831X_GP4_EINT_WIDTH 1 /* GP4_EINT */
#define WM831X_GP3_EINT 0x0004 /* GP3_EINT */
#define WM831X_GP3_EINT_MASK 0x0004 /* GP3_EINT */
#define WM831X_GP3_EINT_SHIFT 2 /* GP3_EINT */
#define WM831X_GP3_EINT_WIDTH 1 /* GP3_EINT */
#define WM831X_GP2_EINT 0x0002 /* GP2_EINT */
#define WM831X_GP2_EINT_MASK 0x0002 /* GP2_EINT */
#define WM831X_GP2_EINT_SHIFT 1 /* GP2_EINT */
#define WM831X_GP2_EINT_WIDTH 1 /* GP2_EINT */
#define WM831X_GP1_EINT 0x0001 /* GP1_EINT */
#define WM831X_GP1_EINT_MASK 0x0001 /* GP1_EINT */
#define WM831X_GP1_EINT_SHIFT 0 /* GP1_EINT */
#define WM831X_GP1_EINT_WIDTH 1 /* GP1_EINT */
/*
* R16407 (0x4017) - IRQ Config
*/
#define WM831X_IRQ_OD 0x0002 /* IRQ_OD */
#define WM831X_IRQ_OD_MASK 0x0002 /* IRQ_OD */
#define WM831X_IRQ_OD_SHIFT 1 /* IRQ_OD */
#define WM831X_IRQ_OD_WIDTH 1 /* IRQ_OD */
#define WM831X_IM_IRQ 0x0001 /* IM_IRQ */
#define WM831X_IM_IRQ_MASK 0x0001 /* IM_IRQ */
#define WM831X_IM_IRQ_SHIFT 0 /* IM_IRQ */
#define WM831X_IM_IRQ_WIDTH 1 /* IM_IRQ */
/*
* R16408 (0x4018) - System Interrupts Mask
*/
#define WM831X_IM_PS_INT 0x8000 /* IM_PS_INT */
#define WM831X_IM_PS_INT_MASK 0x8000 /* IM_PS_INT */
#define WM831X_IM_PS_INT_SHIFT 15 /* IM_PS_INT */
#define WM831X_IM_PS_INT_WIDTH 1 /* IM_PS_INT */
#define WM831X_IM_TEMP_INT 0x4000 /* IM_TEMP_INT */
#define WM831X_IM_TEMP_INT_MASK 0x4000 /* IM_TEMP_INT */
#define WM831X_IM_TEMP_INT_SHIFT 14 /* IM_TEMP_INT */
#define WM831X_IM_TEMP_INT_WIDTH 1 /* IM_TEMP_INT */
#define WM831X_IM_GP_INT 0x2000 /* IM_GP_INT */
#define WM831X_IM_GP_INT_MASK 0x2000 /* IM_GP_INT */
#define WM831X_IM_GP_INT_SHIFT 13 /* IM_GP_INT */
#define WM831X_IM_GP_INT_WIDTH 1 /* IM_GP_INT */
#define WM831X_IM_ON_PIN_INT 0x1000 /* IM_ON_PIN_INT */
#define WM831X_IM_ON_PIN_INT_MASK 0x1000 /* IM_ON_PIN_INT */
#define WM831X_IM_ON_PIN_INT_SHIFT 12 /* IM_ON_PIN_INT */
#define WM831X_IM_ON_PIN_INT_WIDTH 1 /* IM_ON_PIN_INT */
#define WM831X_IM_WDOG_INT 0x0800 /* IM_WDOG_INT */
#define WM831X_IM_WDOG_INT_MASK 0x0800 /* IM_WDOG_INT */
#define WM831X_IM_WDOG_INT_SHIFT 11 /* IM_WDOG_INT */
#define WM831X_IM_WDOG_INT_WIDTH 1 /* IM_WDOG_INT */
#define WM831X_IM_TCHDATA_INT 0x0400 /* IM_TCHDATA_INT */
#define WM831X_IM_TCHDATA_INT_MASK 0x0400 /* IM_TCHDATA_INT */
#define WM831X_IM_TCHDATA_INT_SHIFT 10 /* IM_TCHDATA_INT */
#define WM831X_IM_TCHDATA_INT_WIDTH 1 /* IM_TCHDATA_INT */
#define WM831X_IM_TCHPD_INT 0x0200 /* IM_TCHPD_INT */
#define WM831X_IM_TCHPD_INT_MASK 0x0200 /* IM_TCHPD_INT */
#define WM831X_IM_TCHPD_INT_SHIFT 9 /* IM_TCHPD_INT */
#define WM831X_IM_TCHPD_INT_WIDTH 1 /* IM_TCHPD_INT */
#define WM831X_IM_AUXADC_INT 0x0100 /* IM_AUXADC_INT */
#define WM831X_IM_AUXADC_INT_MASK 0x0100 /* IM_AUXADC_INT */
#define WM831X_IM_AUXADC_INT_SHIFT 8 /* IM_AUXADC_INT */
#define WM831X_IM_AUXADC_INT_WIDTH 1 /* IM_AUXADC_INT */
#define WM831X_IM_PPM_INT 0x0080 /* IM_PPM_INT */
#define WM831X_IM_PPM_INT_MASK 0x0080 /* IM_PPM_INT */
#define WM831X_IM_PPM_INT_SHIFT 7 /* IM_PPM_INT */
#define WM831X_IM_PPM_INT_WIDTH 1 /* IM_PPM_INT */
#define WM831X_IM_CS_INT 0x0040 /* IM_CS_INT */
#define WM831X_IM_CS_INT_MASK 0x0040 /* IM_CS_INT */
#define WM831X_IM_CS_INT_SHIFT 6 /* IM_CS_INT */
#define WM831X_IM_CS_INT_WIDTH 1 /* IM_CS_INT */
#define WM831X_IM_RTC_INT 0x0020 /* IM_RTC_INT */
#define WM831X_IM_RTC_INT_MASK 0x0020 /* IM_RTC_INT */
#define WM831X_IM_RTC_INT_SHIFT 5 /* IM_RTC_INT */
#define WM831X_IM_RTC_INT_WIDTH 1 /* IM_RTC_INT */
#define WM831X_IM_OTP_INT 0x0010 /* IM_OTP_INT */
#define WM831X_IM_OTP_INT_MASK 0x0010 /* IM_OTP_INT */
#define WM831X_IM_OTP_INT_SHIFT 4 /* IM_OTP_INT */
#define WM831X_IM_OTP_INT_WIDTH 1 /* IM_OTP_INT */
#define WM831X_IM_CHILD_INT 0x0008 /* IM_CHILD_INT */
#define WM831X_IM_CHILD_INT_MASK 0x0008 /* IM_CHILD_INT */
#define WM831X_IM_CHILD_INT_SHIFT 3 /* IM_CHILD_INT */
#define WM831X_IM_CHILD_INT_WIDTH 1 /* IM_CHILD_INT */
#define WM831X_IM_CHG_INT 0x0004 /* IM_CHG_INT */
#define WM831X_IM_CHG_INT_MASK 0x0004 /* IM_CHG_INT */
#define WM831X_IM_CHG_INT_SHIFT 2 /* IM_CHG_INT */
#define WM831X_IM_CHG_INT_WIDTH 1 /* IM_CHG_INT */
#define WM831X_IM_HC_INT 0x0002 /* IM_HC_INT */
#define WM831X_IM_HC_INT_MASK 0x0002 /* IM_HC_INT */
#define WM831X_IM_HC_INT_SHIFT 1 /* IM_HC_INT */
#define WM831X_IM_HC_INT_WIDTH 1 /* IM_HC_INT */
#define WM831X_IM_UV_INT 0x0001 /* IM_UV_INT */
#define WM831X_IM_UV_INT_MASK 0x0001 /* IM_UV_INT */
#define WM831X_IM_UV_INT_SHIFT 0 /* IM_UV_INT */
#define WM831X_IM_UV_INT_WIDTH 1 /* IM_UV_INT */
/*
* R16409 (0x4019) - Interrupt Status 1 Mask
*/
#define WM831X_IM_PPM_SYSLO_EINT 0x8000 /* IM_PPM_SYSLO_EINT */
#define WM831X_IM_PPM_SYSLO_EINT_MASK 0x8000 /* IM_PPM_SYSLO_EINT */
#define WM831X_IM_PPM_SYSLO_EINT_SHIFT 15 /* IM_PPM_SYSLO_EINT */
#define WM831X_IM_PPM_SYSLO_EINT_WIDTH 1 /* IM_PPM_SYSLO_EINT */
#define WM831X_IM_PPM_PWR_SRC_EINT 0x4000 /* IM_PPM_PWR_SRC_EINT */
#define WM831X_IM_PPM_PWR_SRC_EINT_MASK 0x4000 /* IM_PPM_PWR_SRC_EINT */
#define WM831X_IM_PPM_PWR_SRC_EINT_SHIFT 14 /* IM_PPM_PWR_SRC_EINT */
#define WM831X_IM_PPM_PWR_SRC_EINT_WIDTH 1 /* IM_PPM_PWR_SRC_EINT */
#define WM831X_IM_PPM_USB_CURR_EINT 0x2000 /* IM_PPM_USB_CURR_EINT */
#define WM831X_IM_PPM_USB_CURR_EINT_MASK 0x2000 /* IM_PPM_USB_CURR_EINT */
#define WM831X_IM_PPM_USB_CURR_EINT_SHIFT 13 /* IM_PPM_USB_CURR_EINT */
#define WM831X_IM_PPM_USB_CURR_EINT_WIDTH 1 /* IM_PPM_USB_CURR_EINT */
#define WM831X_IM_ON_PIN_EINT 0x1000 /* IM_ON_PIN_EINT */
#define WM831X_IM_ON_PIN_EINT_MASK 0x1000 /* IM_ON_PIN_EINT */
#define WM831X_IM_ON_PIN_EINT_SHIFT 12 /* IM_ON_PIN_EINT */
#define WM831X_IM_ON_PIN_EINT_WIDTH 1 /* IM_ON_PIN_EINT */
#define WM831X_IM_WDOG_TO_EINT 0x0800 /* IM_WDOG_TO_EINT */
#define WM831X_IM_WDOG_TO_EINT_MASK 0x0800 /* IM_WDOG_TO_EINT */
#define WM831X_IM_WDOG_TO_EINT_SHIFT 11 /* IM_WDOG_TO_EINT */
#define WM831X_IM_WDOG_TO_EINT_WIDTH 1 /* IM_WDOG_TO_EINT */
#define WM831X_IM_TCHDATA_EINT 0x0400 /* IM_TCHDATA_EINT */
#define WM831X_IM_TCHDATA_EINT_MASK 0x0400 /* IM_TCHDATA_EINT */
#define WM831X_IM_TCHDATA_EINT_SHIFT 10 /* IM_TCHDATA_EINT */
#define WM831X_IM_TCHDATA_EINT_WIDTH 1 /* IM_TCHDATA_EINT */
#define WM831X_IM_TCHPD_EINT 0x0200 /* IM_TCHPD_EINT */
#define WM831X_IM_TCHPD_EINT_MASK 0x0200 /* IM_TCHPD_EINT */
#define WM831X_IM_TCHPD_EINT_SHIFT 9 /* IM_TCHPD_EINT */
#define WM831X_IM_TCHPD_EINT_WIDTH 1 /* IM_TCHPD_EINT */
#define WM831X_IM_AUXADC_DATA_EINT 0x0100 /* IM_AUXADC_DATA_EINT */
#define WM831X_IM_AUXADC_DATA_EINT_MASK 0x0100 /* IM_AUXADC_DATA_EINT */
#define WM831X_IM_AUXADC_DATA_EINT_SHIFT 8 /* IM_AUXADC_DATA_EINT */
#define WM831X_IM_AUXADC_DATA_EINT_WIDTH 1 /* IM_AUXADC_DATA_EINT */
#define WM831X_IM_AUXADC_DCOMP4_EINT 0x0080 /* IM_AUXADC_DCOMP4_EINT */
#define WM831X_IM_AUXADC_DCOMP4_EINT_MASK 0x0080 /* IM_AUXADC_DCOMP4_EINT */
#define WM831X_IM_AUXADC_DCOMP4_EINT_SHIFT 7 /* IM_AUXADC_DCOMP4_EINT */
#define WM831X_IM_AUXADC_DCOMP4_EINT_WIDTH 1 /* IM_AUXADC_DCOMP4_EINT */
#define WM831X_IM_AUXADC_DCOMP3_EINT 0x0040 /* IM_AUXADC_DCOMP3_EINT */
#define WM831X_IM_AUXADC_DCOMP3_EINT_MASK 0x0040 /* IM_AUXADC_DCOMP3_EINT */
#define WM831X_IM_AUXADC_DCOMP3_EINT_SHIFT 6 /* IM_AUXADC_DCOMP3_EINT */
#define WM831X_IM_AUXADC_DCOMP3_EINT_WIDTH 1 /* IM_AUXADC_DCOMP3_EINT */
#define WM831X_IM_AUXADC_DCOMP2_EINT 0x0020 /* IM_AUXADC_DCOMP2_EINT */
#define WM831X_IM_AUXADC_DCOMP2_EINT_MASK 0x0020 /* IM_AUXADC_DCOMP2_EINT */
#define WM831X_IM_AUXADC_DCOMP2_EINT_SHIFT 5 /* IM_AUXADC_DCOMP2_EINT */
#define WM831X_IM_AUXADC_DCOMP2_EINT_WIDTH 1 /* IM_AUXADC_DCOMP2_EINT */
#define WM831X_IM_AUXADC_DCOMP1_EINT 0x0010 /* IM_AUXADC_DCOMP1_EINT */
#define WM831X_IM_AUXADC_DCOMP1_EINT_MASK 0x0010 /* IM_AUXADC_DCOMP1_EINT */
#define WM831X_IM_AUXADC_DCOMP1_EINT_SHIFT 4 /* IM_AUXADC_DCOMP1_EINT */
#define WM831X_IM_AUXADC_DCOMP1_EINT_WIDTH 1 /* IM_AUXADC_DCOMP1_EINT */
#define WM831X_IM_RTC_PER_EINT 0x0008 /* IM_RTC_PER_EINT */
#define WM831X_IM_RTC_PER_EINT_MASK 0x0008 /* IM_RTC_PER_EINT */
#define WM831X_IM_RTC_PER_EINT_SHIFT 3 /* IM_RTC_PER_EINT */
#define WM831X_IM_RTC_PER_EINT_WIDTH 1 /* IM_RTC_PER_EINT */
#define WM831X_IM_RTC_ALM_EINT 0x0004 /* IM_RTC_ALM_EINT */
#define WM831X_IM_RTC_ALM_EINT_MASK 0x0004 /* IM_RTC_ALM_EINT */
#define WM831X_IM_RTC_ALM_EINT_SHIFT 2 /* IM_RTC_ALM_EINT */
#define WM831X_IM_RTC_ALM_EINT_WIDTH 1 /* IM_RTC_ALM_EINT */
#define WM831X_IM_TEMP_THW_EINT 0x0002 /* IM_TEMP_THW_EINT */
#define WM831X_IM_TEMP_THW_EINT_MASK 0x0002 /* IM_TEMP_THW_EINT */
#define WM831X_IM_TEMP_THW_EINT_SHIFT 1 /* IM_TEMP_THW_EINT */
#define WM831X_IM_TEMP_THW_EINT_WIDTH 1 /* IM_TEMP_THW_EINT */
/*
* R16410 (0x401A) - Interrupt Status 2 Mask
*/
#define WM831X_IM_CHG_BATT_HOT_EINT 0x8000 /* IM_CHG_BATT_HOT_EINT */
#define WM831X_IM_CHG_BATT_HOT_EINT_MASK 0x8000 /* IM_CHG_BATT_HOT_EINT */
#define WM831X_IM_CHG_BATT_HOT_EINT_SHIFT 15 /* IM_CHG_BATT_HOT_EINT */
#define WM831X_IM_CHG_BATT_HOT_EINT_WIDTH 1 /* IM_CHG_BATT_HOT_EINT */
#define WM831X_IM_CHG_BATT_COLD_EINT 0x4000 /* IM_CHG_BATT_COLD_EINT */
#define WM831X_IM_CHG_BATT_COLD_EINT_MASK 0x4000 /* IM_CHG_BATT_COLD_EINT */
#define WM831X_IM_CHG_BATT_COLD_EINT_SHIFT 14 /* IM_CHG_BATT_COLD_EINT */
#define WM831X_IM_CHG_BATT_COLD_EINT_WIDTH 1 /* IM_CHG_BATT_COLD_EINT */
#define WM831X_IM_CHG_BATT_FAIL_EINT 0x2000 /* IM_CHG_BATT_FAIL_EINT */
#define WM831X_IM_CHG_BATT_FAIL_EINT_MASK 0x2000 /* IM_CHG_BATT_FAIL_EINT */
#define WM831X_IM_CHG_BATT_FAIL_EINT_SHIFT 13 /* IM_CHG_BATT_FAIL_EINT */
#define WM831X_IM_CHG_BATT_FAIL_EINT_WIDTH 1 /* IM_CHG_BATT_FAIL_EINT */
#define WM831X_IM_CHG_OV_EINT 0x1000 /* IM_CHG_OV_EINT */
#define WM831X_IM_CHG_OV_EINT_MASK 0x1000 /* IM_CHG_OV_EINT */
#define WM831X_IM_CHG_OV_EINT_SHIFT 12 /* IM_CHG_OV_EINT */
#define WM831X_IM_CHG_OV_EINT_WIDTH 1 /* IM_CHG_OV_EINT */
#define WM831X_IM_CHG_END_EINT 0x0800 /* IM_CHG_END_EINT */
#define WM831X_IM_CHG_END_EINT_MASK 0x0800 /* IM_CHG_END_EINT */
#define WM831X_IM_CHG_END_EINT_SHIFT 11 /* IM_CHG_END_EINT */
#define WM831X_IM_CHG_END_EINT_WIDTH 1 /* IM_CHG_END_EINT */
#define WM831X_IM_CHG_TO_EINT 0x0400 /* IM_CHG_TO_EINT */
#define WM831X_IM_CHG_TO_EINT_MASK 0x0400 /* IM_CHG_TO_EINT */
#define WM831X_IM_CHG_TO_EINT_SHIFT 10 /* IM_CHG_TO_EINT */
#define WM831X_IM_CHG_TO_EINT_WIDTH 1 /* IM_CHG_TO_EINT */
#define WM831X_IM_CHG_MODE_EINT 0x0200 /* IM_CHG_MODE_EINT */
#define WM831X_IM_CHG_MODE_EINT_MASK 0x0200 /* IM_CHG_MODE_EINT */
#define WM831X_IM_CHG_MODE_EINT_SHIFT 9 /* IM_CHG_MODE_EINT */
#define WM831X_IM_CHG_MODE_EINT_WIDTH 1 /* IM_CHG_MODE_EINT */
#define WM831X_IM_CHG_START_EINT 0x0100 /* IM_CHG_START_EINT */
#define WM831X_IM_CHG_START_EINT_MASK 0x0100 /* IM_CHG_START_EINT */
#define WM831X_IM_CHG_START_EINT_SHIFT 8 /* IM_CHG_START_EINT */
#define WM831X_IM_CHG_START_EINT_WIDTH 1 /* IM_CHG_START_EINT */
#define WM831X_IM_CS2_EINT 0x0080 /* IM_CS2_EINT */
#define WM831X_IM_CS2_EINT_MASK 0x0080 /* IM_CS2_EINT */
#define WM831X_IM_CS2_EINT_SHIFT 7 /* IM_CS2_EINT */
#define WM831X_IM_CS2_EINT_WIDTH 1 /* IM_CS2_EINT */
#define WM831X_IM_CS1_EINT 0x0040 /* IM_CS1_EINT */
#define WM831X_IM_CS1_EINT_MASK 0x0040 /* IM_CS1_EINT */
#define WM831X_IM_CS1_EINT_SHIFT 6 /* IM_CS1_EINT */
#define WM831X_IM_CS1_EINT_WIDTH 1 /* IM_CS1_EINT */
#define WM831X_IM_OTP_CMD_END_EINT 0x0020 /* IM_OTP_CMD_END_EINT */
#define WM831X_IM_OTP_CMD_END_EINT_MASK 0x0020 /* IM_OTP_CMD_END_EINT */
#define WM831X_IM_OTP_CMD_END_EINT_SHIFT 5 /* IM_OTP_CMD_END_EINT */
#define WM831X_IM_OTP_CMD_END_EINT_WIDTH 1 /* IM_OTP_CMD_END_EINT */
#define WM831X_IM_OTP_ERR_EINT 0x0010 /* IM_OTP_ERR_EINT */
#define WM831X_IM_OTP_ERR_EINT_MASK 0x0010 /* IM_OTP_ERR_EINT */
#define WM831X_IM_OTP_ERR_EINT_SHIFT 4 /* IM_OTP_ERR_EINT */
#define WM831X_IM_OTP_ERR_EINT_WIDTH 1 /* IM_OTP_ERR_EINT */
#define WM831X_IM_PS_POR_EINT 0x0004 /* IM_PS_POR_EINT */
#define WM831X_IM_PS_POR_EINT_MASK 0x0004 /* IM_PS_POR_EINT */
#define WM831X_IM_PS_POR_EINT_SHIFT 2 /* IM_PS_POR_EINT */
#define WM831X_IM_PS_POR_EINT_WIDTH 1 /* IM_PS_POR_EINT */
#define WM831X_IM_PS_SLEEP_OFF_EINT 0x0002 /* IM_PS_SLEEP_OFF_EINT */
#define WM831X_IM_PS_SLEEP_OFF_EINT_MASK 0x0002 /* IM_PS_SLEEP_OFF_EINT */
#define WM831X_IM_PS_SLEEP_OFF_EINT_SHIFT 1 /* IM_PS_SLEEP_OFF_EINT */
#define WM831X_IM_PS_SLEEP_OFF_EINT_WIDTH 1 /* IM_PS_SLEEP_OFF_EINT */
#define WM831X_IM_PS_ON_WAKE_EINT 0x0001 /* IM_PS_ON_WAKE_EINT */
#define WM831X_IM_PS_ON_WAKE_EINT_MASK 0x0001 /* IM_PS_ON_WAKE_EINT */
#define WM831X_IM_PS_ON_WAKE_EINT_SHIFT 0 /* IM_PS_ON_WAKE_EINT */
#define WM831X_IM_PS_ON_WAKE_EINT_WIDTH 1 /* IM_PS_ON_WAKE_EINT */
/*
* R16411 (0x401B) - Interrupt Status 3 Mask
*/
#define WM831X_IM_UV_LDO10_EINT 0x0200 /* IM_UV_LDO10_EINT */
#define WM831X_IM_UV_LDO10_EINT_MASK 0x0200 /* IM_UV_LDO10_EINT */
#define WM831X_IM_UV_LDO10_EINT_SHIFT 9 /* IM_UV_LDO10_EINT */
#define WM831X_IM_UV_LDO10_EINT_WIDTH 1 /* IM_UV_LDO10_EINT */
#define WM831X_IM_UV_LDO9_EINT 0x0100 /* IM_UV_LDO9_EINT */
#define WM831X_IM_UV_LDO9_EINT_MASK 0x0100 /* IM_UV_LDO9_EINT */
#define WM831X_IM_UV_LDO9_EINT_SHIFT 8 /* IM_UV_LDO9_EINT */
#define WM831X_IM_UV_LDO9_EINT_WIDTH 1 /* IM_UV_LDO9_EINT */
#define WM831X_IM_UV_LDO8_EINT 0x0080 /* IM_UV_LDO8_EINT */
#define WM831X_IM_UV_LDO8_EINT_MASK 0x0080 /* IM_UV_LDO8_EINT */
#define WM831X_IM_UV_LDO8_EINT_SHIFT 7 /* IM_UV_LDO8_EINT */
#define WM831X_IM_UV_LDO8_EINT_WIDTH 1 /* IM_UV_LDO8_EINT */
#define WM831X_IM_UV_LDO7_EINT 0x0040 /* IM_UV_LDO7_EINT */
#define WM831X_IM_UV_LDO7_EINT_MASK 0x0040 /* IM_UV_LDO7_EINT */
#define WM831X_IM_UV_LDO7_EINT_SHIFT 6 /* IM_UV_LDO7_EINT */
#define WM831X_IM_UV_LDO7_EINT_WIDTH 1 /* IM_UV_LDO7_EINT */
#define WM831X_IM_UV_LDO6_EINT 0x0020 /* IM_UV_LDO6_EINT */
#define WM831X_IM_UV_LDO6_EINT_MASK 0x0020 /* IM_UV_LDO6_EINT */
#define WM831X_IM_UV_LDO6_EINT_SHIFT 5 /* IM_UV_LDO6_EINT */
#define WM831X_IM_UV_LDO6_EINT_WIDTH 1 /* IM_UV_LDO6_EINT */
#define WM831X_IM_UV_LDO5_EINT 0x0010 /* IM_UV_LDO5_EINT */
#define WM831X_IM_UV_LDO5_EINT_MASK 0x0010 /* IM_UV_LDO5_EINT */
#define WM831X_IM_UV_LDO5_EINT_SHIFT 4 /* IM_UV_LDO5_EINT */
#define WM831X_IM_UV_LDO5_EINT_WIDTH 1 /* IM_UV_LDO5_EINT */
#define WM831X_IM_UV_LDO4_EINT 0x0008 /* IM_UV_LDO4_EINT */
#define WM831X_IM_UV_LDO4_EINT_MASK 0x0008 /* IM_UV_LDO4_EINT */
#define WM831X_IM_UV_LDO4_EINT_SHIFT 3 /* IM_UV_LDO4_EINT */
#define WM831X_IM_UV_LDO4_EINT_WIDTH 1 /* IM_UV_LDO4_EINT */
#define WM831X_IM_UV_LDO3_EINT 0x0004 /* IM_UV_LDO3_EINT */
#define WM831X_IM_UV_LDO3_EINT_MASK 0x0004 /* IM_UV_LDO3_EINT */
#define WM831X_IM_UV_LDO3_EINT_SHIFT 2 /* IM_UV_LDO3_EINT */
#define WM831X_IM_UV_LDO3_EINT_WIDTH 1 /* IM_UV_LDO3_EINT */
#define WM831X_IM_UV_LDO2_EINT 0x0002 /* IM_UV_LDO2_EINT */
#define WM831X_IM_UV_LDO2_EINT_MASK 0x0002 /* IM_UV_LDO2_EINT */
#define WM831X_IM_UV_LDO2_EINT_SHIFT 1 /* IM_UV_LDO2_EINT */
#define WM831X_IM_UV_LDO2_EINT_WIDTH 1 /* IM_UV_LDO2_EINT */
#define WM831X_IM_UV_LDO1_EINT 0x0001 /* IM_UV_LDO1_EINT */
#define WM831X_IM_UV_LDO1_EINT_MASK 0x0001 /* IM_UV_LDO1_EINT */
#define WM831X_IM_UV_LDO1_EINT_SHIFT 0 /* IM_UV_LDO1_EINT */
#define WM831X_IM_UV_LDO1_EINT_WIDTH 1 /* IM_UV_LDO1_EINT */
/*
* R16412 (0x401C) - Interrupt Status 4 Mask
*/
#define WM831X_IM_HC_DC2_EINT 0x0200 /* IM_HC_DC2_EINT */
#define WM831X_IM_HC_DC2_EINT_MASK 0x0200 /* IM_HC_DC2_EINT */
#define WM831X_IM_HC_DC2_EINT_SHIFT 9 /* IM_HC_DC2_EINT */
#define WM831X_IM_HC_DC2_EINT_WIDTH 1 /* IM_HC_DC2_EINT */
#define WM831X_IM_HC_DC1_EINT 0x0100 /* IM_HC_DC1_EINT */
#define WM831X_IM_HC_DC1_EINT_MASK 0x0100 /* IM_HC_DC1_EINT */
#define WM831X_IM_HC_DC1_EINT_SHIFT 8 /* IM_HC_DC1_EINT */
#define WM831X_IM_HC_DC1_EINT_WIDTH 1 /* IM_HC_DC1_EINT */
#define WM831X_IM_UV_DC4_EINT 0x0008 /* IM_UV_DC4_EINT */
#define WM831X_IM_UV_DC4_EINT_MASK 0x0008 /* IM_UV_DC4_EINT */
#define WM831X_IM_UV_DC4_EINT_SHIFT 3 /* IM_UV_DC4_EINT */
#define WM831X_IM_UV_DC4_EINT_WIDTH 1 /* IM_UV_DC4_EINT */
#define WM831X_IM_UV_DC3_EINT 0x0004 /* IM_UV_DC3_EINT */
#define WM831X_IM_UV_DC3_EINT_MASK 0x0004 /* IM_UV_DC3_EINT */
#define WM831X_IM_UV_DC3_EINT_SHIFT 2 /* IM_UV_DC3_EINT */
#define WM831X_IM_UV_DC3_EINT_WIDTH 1 /* IM_UV_DC3_EINT */
#define WM831X_IM_UV_DC2_EINT 0x0002 /* IM_UV_DC2_EINT */
#define WM831X_IM_UV_DC2_EINT_MASK 0x0002 /* IM_UV_DC2_EINT */
#define WM831X_IM_UV_DC2_EINT_SHIFT 1 /* IM_UV_DC2_EINT */
#define WM831X_IM_UV_DC2_EINT_WIDTH 1 /* IM_UV_DC2_EINT */
#define WM831X_IM_UV_DC1_EINT 0x0001 /* IM_UV_DC1_EINT */
#define WM831X_IM_UV_DC1_EINT_MASK 0x0001 /* IM_UV_DC1_EINT */
#define WM831X_IM_UV_DC1_EINT_SHIFT 0 /* IM_UV_DC1_EINT */
#define WM831X_IM_UV_DC1_EINT_WIDTH 1 /* IM_UV_DC1_EINT */
/*
* R16413 (0x401D) - Interrupt Status 5 Mask
*/
#define WM831X_IM_GP16_EINT 0x8000 /* IM_GP16_EINT */
#define WM831X_IM_GP16_EINT_MASK 0x8000 /* IM_GP16_EINT */
#define WM831X_IM_GP16_EINT_SHIFT 15 /* IM_GP16_EINT */
#define WM831X_IM_GP16_EINT_WIDTH 1 /* IM_GP16_EINT */
#define WM831X_IM_GP15_EINT 0x4000 /* IM_GP15_EINT */
#define WM831X_IM_GP15_EINT_MASK 0x4000 /* IM_GP15_EINT */
#define WM831X_IM_GP15_EINT_SHIFT 14 /* IM_GP15_EINT */
#define WM831X_IM_GP15_EINT_WIDTH 1 /* IM_GP15_EINT */
#define WM831X_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */
#define WM831X_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */
#define WM831X_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */
#define WM831X_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */
#define WM831X_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */
#define WM831X_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */
#define WM831X_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */
#define WM831X_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */
#define WM831X_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */
#define WM831X_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */
#define WM831X_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */
#define WM831X_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */
#define WM831X_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */
#define WM831X_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */
#define WM831X_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */
#define WM831X_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */
#define WM831X_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */
#define WM831X_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */
#define WM831X_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */
#define WM831X_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */
#define WM831X_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */
#define WM831X_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */
#define WM831X_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */
#define WM831X_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */
#define WM831X_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */
#define WM831X_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */
#define WM831X_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */
#define WM831X_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */
#define WM831X_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */
#define WM831X_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */
#define WM831X_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */
#define WM831X_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */
#define WM831X_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
#define WM831X_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
#define WM831X_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
#define WM831X_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
#define WM831X_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
#define WM831X_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
#define WM831X_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
#define WM831X_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
#define WM831X_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
#define WM831X_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
#define WM831X_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
#define WM831X_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
#define WM831X_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
#define WM831X_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
#define WM831X_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
#define WM831X_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
#define WM831X_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
#define WM831X_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
#define WM831X_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
#define WM831X_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
#define WM831X_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
#define WM831X_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
#define WM831X_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
#define WM831X_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
#endif

162
kernel/include/linux/mfd/wm831x/otp.h Normal file
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/*
* include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_OTP_H__
#define __MFD_WM831X_OTP_H__
int wm831x_otp_init(struct wm831x *wm831x);
void wm831x_otp_exit(struct wm831x *wm831x);
/*
* R30720 (0x7800) - Unique ID 1
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30721 (0x7801) - Unique ID 2
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30722 (0x7802) - Unique ID 3
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30723 (0x7803) - Unique ID 4
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30724 (0x7804) - Unique ID 5
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30725 (0x7805) - Unique ID 6
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30726 (0x7806) - Unique ID 7
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30727 (0x7807) - Unique ID 8
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30728 (0x7808) - Factory OTP ID
*/
#define WM831X_OTP_FACT_ID_MASK 0xFFFE /* OTP_FACT_ID - [15:1] */
#define WM831X_OTP_FACT_ID_SHIFT 1 /* OTP_FACT_ID - [15:1] */
#define WM831X_OTP_FACT_ID_WIDTH 15 /* OTP_FACT_ID - [15:1] */
#define WM831X_OTP_FACT_FINAL 0x0001 /* OTP_FACT_FINAL */
#define WM831X_OTP_FACT_FINAL_MASK 0x0001 /* OTP_FACT_FINAL */
#define WM831X_OTP_FACT_FINAL_SHIFT 0 /* OTP_FACT_FINAL */
#define WM831X_OTP_FACT_FINAL_WIDTH 1 /* OTP_FACT_FINAL */
/*
* R30729 (0x7809) - Factory OTP 1
*/
#define WM831X_DC3_TRIM_MASK 0xF000 /* DC3_TRIM - [15:12] */
#define WM831X_DC3_TRIM_SHIFT 12 /* DC3_TRIM - [15:12] */
#define WM831X_DC3_TRIM_WIDTH 4 /* DC3_TRIM - [15:12] */
#define WM831X_DC2_TRIM_MASK 0x0FC0 /* DC2_TRIM - [11:6] */
#define WM831X_DC2_TRIM_SHIFT 6 /* DC2_TRIM - [11:6] */
#define WM831X_DC2_TRIM_WIDTH 6 /* DC2_TRIM - [11:6] */
#define WM831X_DC1_TRIM_MASK 0x003F /* DC1_TRIM - [5:0] */
#define WM831X_DC1_TRIM_SHIFT 0 /* DC1_TRIM - [5:0] */
#define WM831X_DC1_TRIM_WIDTH 6 /* DC1_TRIM - [5:0] */
/*
* R30730 (0x780A) - Factory OTP 2
*/
#define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
#define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
#define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
/*
* R30731 (0x780B) - Factory OTP 3
*/
#define WM831X_OSC_TRIM_MASK 0x0780 /* OSC_TRIM - [10:7] */
#define WM831X_OSC_TRIM_SHIFT 7 /* OSC_TRIM - [10:7] */
#define WM831X_OSC_TRIM_WIDTH 4 /* OSC_TRIM - [10:7] */
#define WM831X_BG_TRIM_MASK 0x0078 /* BG_TRIM - [6:3] */
#define WM831X_BG_TRIM_SHIFT 3 /* BG_TRIM - [6:3] */
#define WM831X_BG_TRIM_WIDTH 4 /* BG_TRIM - [6:3] */
#define WM831X_LPBG_TRIM_MASK 0x0007 /* LPBG_TRIM - [2:0] */
#define WM831X_LPBG_TRIM_SHIFT 0 /* LPBG_TRIM - [2:0] */
#define WM831X_LPBG_TRIM_WIDTH 3 /* LPBG_TRIM - [2:0] */
/*
* R30732 (0x780C) - Factory OTP 4
*/
#define WM831X_CHILD_I2C_ADDR_MASK 0x00FE /* CHILD_I2C_ADDR - [7:1] */
#define WM831X_CHILD_I2C_ADDR_SHIFT 1 /* CHILD_I2C_ADDR - [7:1] */
#define WM831X_CHILD_I2C_ADDR_WIDTH 7 /* CHILD_I2C_ADDR - [7:1] */
#define WM831X_CH_AW 0x0001 /* CH_AW */
#define WM831X_CH_AW_MASK 0x0001 /* CH_AW */
#define WM831X_CH_AW_SHIFT 0 /* CH_AW */
#define WM831X_CH_AW_WIDTH 1 /* CH_AW */
/*
* R30733 (0x780D) - Factory OTP 5
*/
#define WM831X_CHARGE_TRIM_MASK 0x003F /* CHARGE_TRIM - [5:0] */
#define WM831X_CHARGE_TRIM_SHIFT 0 /* CHARGE_TRIM - [5:0] */
#define WM831X_CHARGE_TRIM_WIDTH 6 /* CHARGE_TRIM - [5:0] */
/*
* R30736 (0x7810) - Customer OTP ID
*/
#define WM831X_OTP_AUTO_PROG 0x8000 /* OTP_AUTO_PROG */
#define WM831X_OTP_AUTO_PROG_MASK 0x8000 /* OTP_AUTO_PROG */
#define WM831X_OTP_AUTO_PROG_SHIFT 15 /* OTP_AUTO_PROG */
#define WM831X_OTP_AUTO_PROG_WIDTH 1 /* OTP_AUTO_PROG */
#define WM831X_OTP_CUST_ID_MASK 0x7FFE /* OTP_CUST_ID - [14:1] */
#define WM831X_OTP_CUST_ID_SHIFT 1 /* OTP_CUST_ID - [14:1] */
#define WM831X_OTP_CUST_ID_WIDTH 14 /* OTP_CUST_ID - [14:1] */
#define WM831X_OTP_CUST_FINAL 0x0001 /* OTP_CUST_FINAL */
#define WM831X_OTP_CUST_FINAL_MASK 0x0001 /* OTP_CUST_FINAL */
#define WM831X_OTP_CUST_FINAL_SHIFT 0 /* OTP_CUST_FINAL */
#define WM831X_OTP_CUST_FINAL_WIDTH 1 /* OTP_CUST_FINAL */
/*
* R30759 (0x7827) - DBE CHECK DATA
*/
#define WM831X_DBE_VALID_DATA_MASK 0xFFFF /* DBE_VALID_DATA - [15:0] */
#define WM831X_DBE_VALID_DATA_SHIFT 0 /* DBE_VALID_DATA - [15:0] */
#define WM831X_DBE_VALID_DATA_WIDTH 16 /* DBE_VALID_DATA - [15:0] */
#endif

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/*
* include/linux/mfd/wm831x/pdata.h -- Platform data for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_PDATA_H__
#define __MFD_WM831X_PDATA_H__
struct wm831x;
struct regulator_init_data;
struct wm831x_backlight_pdata {
int isink; /** ISINK to use, 1 or 2 */
int max_uA; /** Maximum current to allow */
};
struct wm831x_backup_pdata {
int charger_enable;
int no_constant_voltage; /** Disable constant voltage charging */
int vlim; /** Voltage limit in milivolts */
int ilim; /** Current limit in microamps */
};
struct wm831x_battery_pdata {
int enable; /** Enable charging */
int fast_enable; /** Enable fast charging */
int off_mask; /** Mask OFF while charging */
int trickle_ilim; /** Trickle charge current limit, in mA */
int vsel; /** Target voltage, in mV */
int eoc_iterm; /** End of trickle charge current, in mA */
int fast_ilim; /** Fast charge current limit, in mA */
int timeout; /** Charge cycle timeout, in minutes */
};
/* Sources for status LED configuration. Values are register values
* plus 1 to allow for a zero default for preserve.
*/
enum wm831x_status_src {
WM831X_STATUS_PRESERVE = 0, /* Keep the current hardware setting */
WM831X_STATUS_OTP = 1,
WM831X_STATUS_POWER = 2,
WM831X_STATUS_CHARGER = 3,
WM831X_STATUS_MANUAL = 4,
};
struct wm831x_status_pdata {
enum wm831x_status_src default_src;
const char *name;
const char *default_trigger;
};
struct wm831x_touch_pdata {
int fivewire; /** 1 for five wire mode, 0 for 4 wire */
int isel; /** Current for pen down (uA) */
int rpu; /** Pen down sensitivity resistor divider */
int pressure; /** Report pressure (boolean) */
int data_irq; /** Touch data ready IRQ */
};
enum wm831x_watchdog_action {
WM831X_WDOG_NONE = 0,
WM831X_WDOG_INTERRUPT = 1,
WM831X_WDOG_RESET = 2,
WM831X_WDOG_WAKE = 3,
};
struct wm831x_watchdog_pdata {
enum wm831x_watchdog_action primary, secondary;
int update_gpio;
unsigned int software:1;
};
#define WM831X_MAX_STATUS 2
#define WM831X_MAX_DCDC 4
#define WM831X_MAX_EPE 2
#define WM831X_MAX_LDO 11
#define WM831X_MAX_ISINK 2
struct wm831x_pdata {
/** Called before subdevices are set up */
int (*pre_init)(struct wm831x *wm831x);
/** Called after subdevices are set up */
int (*post_init)(struct wm831x *wm831x);
int gpio_base;
struct wm831x_backlight_pdata *backlight;
struct wm831x_backup_pdata *backup;
struct wm831x_battery_pdata *battery;
struct wm831x_touch_pdata *touch;
struct wm831x_watchdog_pdata *watchdog;
/** LED1 = 0 and so on */
struct wm831x_status_pdata *status[WM831X_MAX_STATUS];
/** DCDC1 = 0 and so on */
struct regulator_init_data *dcdc[WM831X_MAX_DCDC];
/** EPE1 = 0 and so on */
struct regulator_init_data *epe[WM831X_MAX_EPE];
/** LDO1 = 0 and so on */
struct regulator_init_data *ldo[WM831X_MAX_LDO];
/** ISINK1 = 0 and so on*/
struct regulator_init_data *isink[WM831X_MAX_ISINK];
};
#endif

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/*
* include/linux/mfd/wm831x/pmu.h -- PMU for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_PMU_H__
#define __MFD_WM831X_PMU_H__
/*
* R16387 (0x4003) - Power State
*/
#define WM831X_CHIP_ON 0x8000 /* CHIP_ON */
#define WM831X_CHIP_ON_MASK 0x8000 /* CHIP_ON */
#define WM831X_CHIP_ON_SHIFT 15 /* CHIP_ON */
#define WM831X_CHIP_ON_WIDTH 1 /* CHIP_ON */
#define WM831X_CHIP_SLP 0x4000 /* CHIP_SLP */
#define WM831X_CHIP_SLP_MASK 0x4000 /* CHIP_SLP */
#define WM831X_CHIP_SLP_SHIFT 14 /* CHIP_SLP */
#define WM831X_CHIP_SLP_WIDTH 1 /* CHIP_SLP */
#define WM831X_REF_LP 0x1000 /* REF_LP */
#define WM831X_REF_LP_MASK 0x1000 /* REF_LP */
#define WM831X_REF_LP_SHIFT 12 /* REF_LP */
#define WM831X_REF_LP_WIDTH 1 /* REF_LP */
#define WM831X_PWRSTATE_DLY_MASK 0x0C00 /* PWRSTATE_DLY - [11:10] */
#define WM831X_PWRSTATE_DLY_SHIFT 10 /* PWRSTATE_DLY - [11:10] */
#define WM831X_PWRSTATE_DLY_WIDTH 2 /* PWRSTATE_DLY - [11:10] */
#define WM831X_SWRST_DLY 0x0200 /* SWRST_DLY */
#define WM831X_SWRST_DLY_MASK 0x0200 /* SWRST_DLY */
#define WM831X_SWRST_DLY_SHIFT 9 /* SWRST_DLY */
#define WM831X_SWRST_DLY_WIDTH 1 /* SWRST_DLY */
#define WM831X_USB100MA_STARTUP_MASK 0x0030 /* USB100MA_STARTUP - [5:4] */
#define WM831X_USB100MA_STARTUP_SHIFT 4 /* USB100MA_STARTUP - [5:4] */
#define WM831X_USB100MA_STARTUP_WIDTH 2 /* USB100MA_STARTUP - [5:4] */
#define WM831X_USB_CURR_STS 0x0008 /* USB_CURR_STS */
#define WM831X_USB_CURR_STS_MASK 0x0008 /* USB_CURR_STS */
#define WM831X_USB_CURR_STS_SHIFT 3 /* USB_CURR_STS */
#define WM831X_USB_CURR_STS_WIDTH 1 /* USB_CURR_STS */
#define WM831X_USB_ILIM_MASK 0x0007 /* USB_ILIM - [2:0] */
#define WM831X_USB_ILIM_SHIFT 0 /* USB_ILIM - [2:0] */
#define WM831X_USB_ILIM_WIDTH 3 /* USB_ILIM - [2:0] */
/*
* R16397 (0x400D) - System Status
*/
#define WM831X_THW_STS 0x8000 /* THW_STS */
#define WM831X_THW_STS_MASK 0x8000 /* THW_STS */
#define WM831X_THW_STS_SHIFT 15 /* THW_STS */
#define WM831X_THW_STS_WIDTH 1 /* THW_STS */
#define WM831X_PWR_SRC_BATT 0x0400 /* PWR_SRC_BATT */
#define WM831X_PWR_SRC_BATT_MASK 0x0400 /* PWR_SRC_BATT */
#define WM831X_PWR_SRC_BATT_SHIFT 10 /* PWR_SRC_BATT */
#define WM831X_PWR_SRC_BATT_WIDTH 1 /* PWR_SRC_BATT */
#define WM831X_PWR_WALL 0x0200 /* PWR_WALL */
#define WM831X_PWR_WALL_MASK 0x0200 /* PWR_WALL */
#define WM831X_PWR_WALL_SHIFT 9 /* PWR_WALL */
#define WM831X_PWR_WALL_WIDTH 1 /* PWR_WALL */
#define WM831X_PWR_USB 0x0100 /* PWR_USB */
#define WM831X_PWR_USB_MASK 0x0100 /* PWR_USB */
#define WM831X_PWR_USB_SHIFT 8 /* PWR_USB */
#define WM831X_PWR_USB_WIDTH 1 /* PWR_USB */
#define WM831X_MAIN_STATE_MASK 0x001F /* MAIN_STATE - [4:0] */
#define WM831X_MAIN_STATE_SHIFT 0 /* MAIN_STATE - [4:0] */
#define WM831X_MAIN_STATE_WIDTH 5 /* MAIN_STATE - [4:0] */
/*
* R16456 (0x4048) - Charger Control 1
*/
#define WM831X_CHG_ENA 0x8000 /* CHG_ENA */
#define WM831X_CHG_ENA_MASK 0x8000 /* CHG_ENA */
#define WM831X_CHG_ENA_SHIFT 15 /* CHG_ENA */
#define WM831X_CHG_ENA_WIDTH 1 /* CHG_ENA */
#define WM831X_CHG_FRC 0x4000 /* CHG_FRC */
#define WM831X_CHG_FRC_MASK 0x4000 /* CHG_FRC */
#define WM831X_CHG_FRC_SHIFT 14 /* CHG_FRC */
#define WM831X_CHG_FRC_WIDTH 1 /* CHG_FRC */
#define WM831X_CHG_ITERM_MASK 0x1C00 /* CHG_ITERM - [12:10] */
#define WM831X_CHG_ITERM_SHIFT 10 /* CHG_ITERM - [12:10] */
#define WM831X_CHG_ITERM_WIDTH 3 /* CHG_ITERM - [12:10] */
#define WM831X_CHG_FAST 0x0020 /* CHG_FAST */
#define WM831X_CHG_FAST_MASK 0x0020 /* CHG_FAST */
#define WM831X_CHG_FAST_SHIFT 5 /* CHG_FAST */
#define WM831X_CHG_FAST_WIDTH 1 /* CHG_FAST */
#define WM831X_CHG_IMON_ENA 0x0002 /* CHG_IMON_ENA */
#define WM831X_CHG_IMON_ENA_MASK 0x0002 /* CHG_IMON_ENA */
#define WM831X_CHG_IMON_ENA_SHIFT 1 /* CHG_IMON_ENA */
#define WM831X_CHG_IMON_ENA_WIDTH 1 /* CHG_IMON_ENA */
#define WM831X_CHG_CHIP_TEMP_MON 0x0001 /* CHG_CHIP_TEMP_MON */
#define WM831X_CHG_CHIP_TEMP_MON_MASK 0x0001 /* CHG_CHIP_TEMP_MON */
#define WM831X_CHG_CHIP_TEMP_MON_SHIFT 0 /* CHG_CHIP_TEMP_MON */
#define WM831X_CHG_CHIP_TEMP_MON_WIDTH 1 /* CHG_CHIP_TEMP_MON */
/*
* R16457 (0x4049) - Charger Control 2
*/
#define WM831X_CHG_OFF_MSK 0x4000 /* CHG_OFF_MSK */
#define WM831X_CHG_OFF_MSK_MASK 0x4000 /* CHG_OFF_MSK */
#define WM831X_CHG_OFF_MSK_SHIFT 14 /* CHG_OFF_MSK */
#define WM831X_CHG_OFF_MSK_WIDTH 1 /* CHG_OFF_MSK */
#define WM831X_CHG_TIME_MASK 0x0F00 /* CHG_TIME - [11:8] */
#define WM831X_CHG_TIME_SHIFT 8 /* CHG_TIME - [11:8] */
#define WM831X_CHG_TIME_WIDTH 4 /* CHG_TIME - [11:8] */
#define WM831X_CHG_TRKL_ILIM_MASK 0x00C0 /* CHG_TRKL_ILIM - [7:6] */
#define WM831X_CHG_TRKL_ILIM_SHIFT 6 /* CHG_TRKL_ILIM - [7:6] */
#define WM831X_CHG_TRKL_ILIM_WIDTH 2 /* CHG_TRKL_ILIM - [7:6] */
#define WM831X_CHG_VSEL_MASK 0x0030 /* CHG_VSEL - [5:4] */
#define WM831X_CHG_VSEL_SHIFT 4 /* CHG_VSEL - [5:4] */
#define WM831X_CHG_VSEL_WIDTH 2 /* CHG_VSEL - [5:4] */
#define WM831X_CHG_FAST_ILIM_MASK 0x000F /* CHG_FAST_ILIM - [3:0] */
#define WM831X_CHG_FAST_ILIM_SHIFT 0 /* CHG_FAST_ILIM - [3:0] */
#define WM831X_CHG_FAST_ILIM_WIDTH 4 /* CHG_FAST_ILIM - [3:0] */
/*
* R16458 (0x404A) - Charger Status
*/
#define WM831X_BATT_OV_STS 0x8000 /* BATT_OV_STS */
#define WM831X_BATT_OV_STS_MASK 0x8000 /* BATT_OV_STS */
#define WM831X_BATT_OV_STS_SHIFT 15 /* BATT_OV_STS */
#define WM831X_BATT_OV_STS_WIDTH 1 /* BATT_OV_STS */
#define WM831X_CHG_STATE_MASK 0x7000 /* CHG_STATE - [14:12] */
#define WM831X_CHG_STATE_SHIFT 12 /* CHG_STATE - [14:12] */
#define WM831X_CHG_STATE_WIDTH 3 /* CHG_STATE - [14:12] */
#define WM831X_BATT_HOT_STS 0x0800 /* BATT_HOT_STS */
#define WM831X_BATT_HOT_STS_MASK 0x0800 /* BATT_HOT_STS */
#define WM831X_BATT_HOT_STS_SHIFT 11 /* BATT_HOT_STS */
#define WM831X_BATT_HOT_STS_WIDTH 1 /* BATT_HOT_STS */
#define WM831X_BATT_COLD_STS 0x0400 /* BATT_COLD_STS */
#define WM831X_BATT_COLD_STS_MASK 0x0400 /* BATT_COLD_STS */
#define WM831X_BATT_COLD_STS_SHIFT 10 /* BATT_COLD_STS */
#define WM831X_BATT_COLD_STS_WIDTH 1 /* BATT_COLD_STS */
#define WM831X_CHG_TOPOFF 0x0200 /* CHG_TOPOFF */
#define WM831X_CHG_TOPOFF_MASK 0x0200 /* CHG_TOPOFF */
#define WM831X_CHG_TOPOFF_SHIFT 9 /* CHG_TOPOFF */
#define WM831X_CHG_TOPOFF_WIDTH 1 /* CHG_TOPOFF */
#define WM831X_CHG_ACTIVE 0x0100 /* CHG_ACTIVE */
#define WM831X_CHG_ACTIVE_MASK 0x0100 /* CHG_ACTIVE */
#define WM831X_CHG_ACTIVE_SHIFT 8 /* CHG_ACTIVE */
#define WM831X_CHG_ACTIVE_WIDTH 1 /* CHG_ACTIVE */
#define WM831X_CHG_TIME_ELAPSED_MASK 0x00FF /* CHG_TIME_ELAPSED - [7:0] */
#define WM831X_CHG_TIME_ELAPSED_SHIFT 0 /* CHG_TIME_ELAPSED - [7:0] */
#define WM831X_CHG_TIME_ELAPSED_WIDTH 8 /* CHG_TIME_ELAPSED - [7:0] */
#define WM831X_CHG_STATE_OFF (0 << WM831X_CHG_STATE_SHIFT)
#define WM831X_CHG_STATE_TRICKLE (1 << WM831X_CHG_STATE_SHIFT)
#define WM831X_CHG_STATE_FAST (2 << WM831X_CHG_STATE_SHIFT)
#define WM831X_CHG_STATE_TRICKLE_OT (3 << WM831X_CHG_STATE_SHIFT)
#define WM831X_CHG_STATE_FAST_OT (4 << WM831X_CHG_STATE_SHIFT)
#define WM831X_CHG_STATE_DEFECTIVE (5 << WM831X_CHG_STATE_SHIFT)
/*
* R16459 (0x404B) - Backup Charger Control
*/
#define WM831X_BKUP_CHG_ENA 0x8000 /* BKUP_CHG_ENA */
#define WM831X_BKUP_CHG_ENA_MASK 0x8000 /* BKUP_CHG_ENA */
#define WM831X_BKUP_CHG_ENA_SHIFT 15 /* BKUP_CHG_ENA */
#define WM831X_BKUP_CHG_ENA_WIDTH 1 /* BKUP_CHG_ENA */
#define WM831X_BKUP_CHG_STS 0x4000 /* BKUP_CHG_STS */
#define WM831X_BKUP_CHG_STS_MASK 0x4000 /* BKUP_CHG_STS */
#define WM831X_BKUP_CHG_STS_SHIFT 14 /* BKUP_CHG_STS */
#define WM831X_BKUP_CHG_STS_WIDTH 1 /* BKUP_CHG_STS */
#define WM831X_BKUP_CHG_MODE 0x1000 /* BKUP_CHG_MODE */
#define WM831X_BKUP_CHG_MODE_MASK 0x1000 /* BKUP_CHG_MODE */
#define WM831X_BKUP_CHG_MODE_SHIFT 12 /* BKUP_CHG_MODE */
#define WM831X_BKUP_CHG_MODE_WIDTH 1 /* BKUP_CHG_MODE */
#define WM831X_BKUP_BATT_DET_ENA 0x0800 /* BKUP_BATT_DET_ENA */
#define WM831X_BKUP_BATT_DET_ENA_MASK 0x0800 /* BKUP_BATT_DET_ENA */
#define WM831X_BKUP_BATT_DET_ENA_SHIFT 11 /* BKUP_BATT_DET_ENA */
#define WM831X_BKUP_BATT_DET_ENA_WIDTH 1 /* BKUP_BATT_DET_ENA */
#define WM831X_BKUP_BATT_STS 0x0400 /* BKUP_BATT_STS */
#define WM831X_BKUP_BATT_STS_MASK 0x0400 /* BKUP_BATT_STS */
#define WM831X_BKUP_BATT_STS_SHIFT 10 /* BKUP_BATT_STS */
#define WM831X_BKUP_BATT_STS_WIDTH 1 /* BKUP_BATT_STS */
#define WM831X_BKUP_CHG_VLIM 0x0010 /* BKUP_CHG_VLIM */
#define WM831X_BKUP_CHG_VLIM_MASK 0x0010 /* BKUP_CHG_VLIM */
#define WM831X_BKUP_CHG_VLIM_SHIFT 4 /* BKUP_CHG_VLIM */
#define WM831X_BKUP_CHG_VLIM_WIDTH 1 /* BKUP_CHG_VLIM */
#define WM831X_BKUP_CHG_ILIM_MASK 0x0003 /* BKUP_CHG_ILIM - [1:0] */
#define WM831X_BKUP_CHG_ILIM_SHIFT 0 /* BKUP_CHG_ILIM - [1:0] */
#define WM831X_BKUP_CHG_ILIM_WIDTH 2 /* BKUP_CHG_ILIM - [1:0] */
#endif

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kernel/include/linux/mfd/wm831x/regulator.h Normal file
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kernel/include/linux/mfd/wm831x/status.h Normal file
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/*
* include/linux/mfd/wm831x/status.h -- Status LEDs for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_STATUS_H__
#define __MFD_WM831X_STATUS_H__
#define WM831X_LED_SRC_MASK 0xC000 /* LED_SRC - [15:14] */
#define WM831X_LED_SRC_SHIFT 14 /* LED_SRC - [15:14] */
#define WM831X_LED_SRC_WIDTH 2 /* LED_SRC - [15:14] */
#define WM831X_LED_MODE_MASK 0x0300 /* LED_MODE - [9:8] */
#define WM831X_LED_MODE_SHIFT 8 /* LED_MODE - [9:8] */
#define WM831X_LED_MODE_WIDTH 2 /* LED_MODE - [9:8] */
#define WM831X_LED_SEQ_LEN_MASK 0x0030 /* LED_SEQ_LEN - [5:4] */
#define WM831X_LED_SEQ_LEN_SHIFT 4 /* LED_SEQ_LEN - [5:4] */
#define WM831X_LED_SEQ_LEN_WIDTH 2 /* LED_SEQ_LEN - [5:4] */
#define WM831X_LED_DUR_MASK 0x000C /* LED_DUR - [3:2] */
#define WM831X_LED_DUR_SHIFT 2 /* LED_DUR - [3:2] */
#define WM831X_LED_DUR_WIDTH 2 /* LED_DUR - [3:2] */
#define WM831X_LED_DUTY_CYC_MASK 0x0003 /* LED_DUTY_CYC - [1:0] */
#define WM831X_LED_DUTY_CYC_SHIFT 0 /* LED_DUTY_CYC - [1:0] */
#define WM831X_LED_DUTY_CYC_WIDTH 2 /* LED_DUTY_CYC - [1:0] */
#endif

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/*
* include/linux/mfd/wm831x/watchdog.h -- Watchdog for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_WATCHDOG_H__
#define __MFD_WM831X_WATCHDOG_H__
/*
* R16388 (0x4004) - Watchdog
*/
#define WM831X_WDOG_ENA 0x8000 /* WDOG_ENA */
#define WM831X_WDOG_ENA_MASK 0x8000 /* WDOG_ENA */
#define WM831X_WDOG_ENA_SHIFT 15 /* WDOG_ENA */
#define WM831X_WDOG_ENA_WIDTH 1 /* WDOG_ENA */
#define WM831X_WDOG_DEBUG 0x4000 /* WDOG_DEBUG */
#define WM831X_WDOG_DEBUG_MASK 0x4000 /* WDOG_DEBUG */
#define WM831X_WDOG_DEBUG_SHIFT 14 /* WDOG_DEBUG */
#define WM831X_WDOG_DEBUG_WIDTH 1 /* WDOG_DEBUG */
#define WM831X_WDOG_RST_SRC 0x2000 /* WDOG_RST_SRC */
#define WM831X_WDOG_RST_SRC_MASK 0x2000 /* WDOG_RST_SRC */
#define WM831X_WDOG_RST_SRC_SHIFT 13 /* WDOG_RST_SRC */
#define WM831X_WDOG_RST_SRC_WIDTH 1 /* WDOG_RST_SRC */
#define WM831X_WDOG_SLPENA 0x1000 /* WDOG_SLPENA */
#define WM831X_WDOG_SLPENA_MASK 0x1000 /* WDOG_SLPENA */
#define WM831X_WDOG_SLPENA_SHIFT 12 /* WDOG_SLPENA */
#define WM831X_WDOG_SLPENA_WIDTH 1 /* WDOG_SLPENA */
#define WM831X_WDOG_RESET 0x0800 /* WDOG_RESET */
#define WM831X_WDOG_RESET_MASK 0x0800 /* WDOG_RESET */
#define WM831X_WDOG_RESET_SHIFT 11 /* WDOG_RESET */
#define WM831X_WDOG_RESET_WIDTH 1 /* WDOG_RESET */
#define WM831X_WDOG_SECACT_MASK 0x0300 /* WDOG_SECACT - [9:8] */
#define WM831X_WDOG_SECACT_SHIFT 8 /* WDOG_SECACT - [9:8] */
#define WM831X_WDOG_SECACT_WIDTH 2 /* WDOG_SECACT - [9:8] */
#define WM831X_WDOG_PRIMACT_MASK 0x0030 /* WDOG_PRIMACT - [5:4] */
#define WM831X_WDOG_PRIMACT_SHIFT 4 /* WDOG_PRIMACT - [5:4] */
#define WM831X_WDOG_PRIMACT_WIDTH 2 /* WDOG_PRIMACT - [5:4] */
#define WM831X_WDOG_TO_MASK 0x0007 /* WDOG_TO - [2:0] */
#define WM831X_WDOG_TO_SHIFT 0 /* WDOG_TO - [2:0] */
#define WM831X_WDOG_TO_WIDTH 3 /* WDOG_TO - [2:0] */
#endif

629
kernel/include/linux/mfd/wm8350/audio.h Normal file
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/*
* audio.h -- Audio Driver for Wolfson WM8350 PMIC
*
* Copyright 2007, 2008 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_WM8350_AUDIO_H_
#define __LINUX_MFD_WM8350_AUDIO_H_
#include <linux/platform_device.h>
#define WM8350_CLOCK_CONTROL_1 0x28
#define WM8350_CLOCK_CONTROL_2 0x29
#define WM8350_FLL_CONTROL_1 0x2A
#define WM8350_FLL_CONTROL_2 0x2B
#define WM8350_FLL_CONTROL_3 0x2C
#define WM8350_FLL_CONTROL_4 0x2D
#define WM8350_DAC_CONTROL 0x30
#define WM8350_DAC_DIGITAL_VOLUME_L 0x32
#define WM8350_DAC_DIGITAL_VOLUME_R 0x33
#define WM8350_DAC_LR_RATE 0x35
#define WM8350_DAC_CLOCK_CONTROL 0x36
#define WM8350_DAC_MUTE 0x3A
#define WM8350_DAC_MUTE_VOLUME 0x3B
#define WM8350_DAC_SIDE 0x3C
#define WM8350_ADC_CONTROL 0x40
#define WM8350_ADC_DIGITAL_VOLUME_L 0x42
#define WM8350_ADC_DIGITAL_VOLUME_R 0x43
#define WM8350_ADC_DIVIDER 0x44
#define WM8350_ADC_LR_RATE 0x46
#define WM8350_INPUT_CONTROL 0x48
#define WM8350_IN3_INPUT_CONTROL 0x49
#define WM8350_MIC_BIAS_CONTROL 0x4A
#define WM8350_OUTPUT_CONTROL 0x4C
#define WM8350_JACK_DETECT 0x4D
#define WM8350_ANTI_POP_CONTROL 0x4E
#define WM8350_LEFT_INPUT_VOLUME 0x50
#define WM8350_RIGHT_INPUT_VOLUME 0x51
#define WM8350_LEFT_MIXER_CONTROL 0x58
#define WM8350_RIGHT_MIXER_CONTROL 0x59
#define WM8350_OUT3_MIXER_CONTROL 0x5C
#define WM8350_OUT4_MIXER_CONTROL 0x5D
#define WM8350_OUTPUT_LEFT_MIXER_VOLUME 0x60
#define WM8350_OUTPUT_RIGHT_MIXER_VOLUME 0x61
#define WM8350_INPUT_MIXER_VOLUME_L 0x62
#define WM8350_INPUT_MIXER_VOLUME_R 0x63
#define WM8350_INPUT_MIXER_VOLUME 0x64
#define WM8350_LOUT1_VOLUME 0x68
#define WM8350_ROUT1_VOLUME 0x69
#define WM8350_LOUT2_VOLUME 0x6A
#define WM8350_ROUT2_VOLUME 0x6B
#define WM8350_BEEP_VOLUME 0x6F
#define WM8350_AI_FORMATING 0x70
#define WM8350_ADC_DAC_COMP 0x71
#define WM8350_AI_ADC_CONTROL 0x72
#define WM8350_AI_DAC_CONTROL 0x73
#define WM8350_AIF_TEST 0x74
#define WM8350_JACK_PIN_STATUS 0xE7
/* Bit values for R08 (0x08) */
#define WM8350_CODEC_ISEL_1_5 0 /* x1.5 */
#define WM8350_CODEC_ISEL_1_0 1 /* x1.0 */
#define WM8350_CODEC_ISEL_0_75 2 /* x0.75 */
#define WM8350_CODEC_ISEL_0_5 3 /* x0.5 */
#define WM8350_VMID_OFF 0
#define WM8350_VMID_300K 1
#define WM8350_VMID_50K 2
#define WM8350_VMID_5K 3
/*
* R40 (0x28) - Clock Control 1
*/
#define WM8350_TOCLK_RATE 0x4000
#define WM8350_MCLK_SEL 0x0800
#define WM8350_MCLK_DIV_MASK 0x0100
#define WM8350_BCLK_DIV_MASK 0x00F0
#define WM8350_OPCLK_DIV_MASK 0x0007
/*
* R41 (0x29) - Clock Control 2
*/
#define WM8350_LRC_ADC_SEL 0x8000
#define WM8350_MCLK_DIR 0x0001
/*
* R42 (0x2A) - FLL Control 1
*/
#define WM8350_FLL_DITHER_WIDTH_MASK 0x3000
#define WM8350_FLL_DITHER_HP 0x0800
#define WM8350_FLL_OUTDIV_MASK 0x0700
#define WM8350_FLL_RSP_RATE_MASK 0x00F0
#define WM8350_FLL_RATE_MASK 0x0007
/*
* R43 (0x2B) - FLL Control 2
*/
#define WM8350_FLL_RATIO_MASK 0xF800
#define WM8350_FLL_N_MASK 0x03FF
/*
* R44 (0x2C) - FLL Control 3
*/
#define WM8350_FLL_K_MASK 0xFFFF
/*
* R45 (0x2D) - FLL Control 4
*/
#define WM8350_FLL_FRAC 0x0020
#define WM8350_FLL_SLOW_LOCK_REF 0x0010
#define WM8350_FLL_CLK_SRC_MASK 0x0003
/*
* R48 (0x30) - DAC Control
*/
#define WM8350_DAC_MONO 0x2000
#define WM8350_AIF_LRCLKRATE 0x1000
#define WM8350_DEEMP_MASK 0x0030
#define WM8350_DACL_DATINV 0x0002
#define WM8350_DACR_DATINV 0x0001
/*
* R50 (0x32) - DAC Digital Volume L
*/
#define WM8350_DAC_VU 0x0100
#define WM8350_DACL_VOL_MASK 0x00FF
/*
* R51 (0x33) - DAC Digital Volume R
*/
#define WM8350_DAC_VU 0x0100
#define WM8350_DACR_VOL_MASK 0x00FF
/*
* R53 (0x35) - DAC LR Rate
*/
#define WM8350_DACLRC_ENA 0x0800
#define WM8350_DACLRC_RATE_MASK 0x07FF
/*
* R54 (0x36) - DAC Clock Control
*/
#define WM8350_DACCLK_POL 0x0010
#define WM8350_DAC_CLKDIV_MASK 0x0007
/*
* R58 (0x3A) - DAC Mute
*/
#define WM8350_DAC_MUTE_ENA 0x4000
/*
* R59 (0x3B) - DAC Mute Volume
*/
#define WM8350_DAC_MUTEMODE 0x4000
#define WM8350_DAC_MUTERATE 0x2000
#define WM8350_DAC_SB_FILT 0x1000
/*
* R60 (0x3C) - DAC Side
*/
#define WM8350_ADC_TO_DACL_MASK 0x3000
#define WM8350_ADC_TO_DACR_MASK 0x0C00
/*
* R64 (0x40) - ADC Control
*/
#define WM8350_ADC_HPF_CUT_MASK 0x0300
#define WM8350_ADCL_DATINV 0x0002
#define WM8350_ADCR_DATINV 0x0001
/*
* R66 (0x42) - ADC Digital Volume L
*/
#define WM8350_ADC_VU 0x0100
#define WM8350_ADCL_VOL_MASK 0x00FF
/*
* R67 (0x43) - ADC Digital Volume R
*/
#define WM8350_ADC_VU 0x0100
#define WM8350_ADCR_VOL_MASK 0x00FF
/*
* R68 (0x44) - ADC Divider
*/
#define WM8350_ADCL_DAC_SVOL_MASK 0x0F00
#define WM8350_ADCR_DAC_SVOL_MASK 0x00F0
#define WM8350_ADCCLK_POL 0x0008
#define WM8350_ADC_CLKDIV_MASK 0x0007
/*
* R70 (0x46) - ADC LR Rate
*/
#define WM8350_ADCLRC_ENA 0x0800
#define WM8350_ADCLRC_RATE_MASK 0x07FF
/*
* R72 (0x48) - Input Control
*/
#define WM8350_IN2R_ENA 0x0400
#define WM8350_IN1RN_ENA 0x0200
#define WM8350_IN1RP_ENA 0x0100
#define WM8350_IN2L_ENA 0x0004
#define WM8350_IN1LN_ENA 0x0002
#define WM8350_IN1LP_ENA 0x0001
/*
* R73 (0x49) - IN3 Input Control
*/
#define WM8350_IN3R_SHORT 0x4000
#define WM8350_IN3L_SHORT 0x0040
/*
* R74 (0x4A) - Mic Bias Control
*/
#define WM8350_MICBSEL 0x4000
#define WM8350_MCDTHR_MASK 0x001C
#define WM8350_MCDSCTHR_MASK 0x0003
/*
* R76 (0x4C) - Output Control
*/
#define WM8350_OUT4_VROI 0x0800
#define WM8350_OUT3_VROI 0x0400
#define WM8350_OUT2_VROI 0x0200
#define WM8350_OUT1_VROI 0x0100
#define WM8350_OUT2_FB 0x0004
#define WM8350_OUT1_FB 0x0001
/*
* R77 (0x4D) - Jack Detect
*/
#define WM8350_JDL_ENA 0x8000
#define WM8350_JDR_ENA 0x4000
/*
* R78 (0x4E) - Anti Pop Control
*/
#define WM8350_ANTI_POP_MASK 0x0300
#define WM8350_DIS_OP_LN4_MASK 0x00C0
#define WM8350_DIS_OP_LN3_MASK 0x0030
#define WM8350_DIS_OP_OUT2_MASK 0x000C
#define WM8350_DIS_OP_OUT1_MASK 0x0003
/*
* R80 (0x50) - Left Input Volume
*/
#define WM8350_INL_MUTE 0x4000
#define WM8350_INL_ZC 0x2000
#define WM8350_IN_VU 0x0100
#define WM8350_INL_VOL_MASK 0x00FC
/*
* R81 (0x51) - Right Input Volume
*/
#define WM8350_INR_MUTE 0x4000
#define WM8350_INR_ZC 0x2000
#define WM8350_IN_VU 0x0100
#define WM8350_INR_VOL_MASK 0x00FC
/*
* R88 (0x58) - Left Mixer Control
*/
#define WM8350_DACR_TO_MIXOUTL 0x1000
#define WM8350_DACL_TO_MIXOUTL 0x0800
#define WM8350_IN3L_TO_MIXOUTL 0x0004
#define WM8350_INR_TO_MIXOUTL 0x0002
#define WM8350_INL_TO_MIXOUTL 0x0001
/*
* R89 (0x59) - Right Mixer Control
*/
#define WM8350_DACR_TO_MIXOUTR 0x1000
#define WM8350_DACL_TO_MIXOUTR 0x0800
#define WM8350_IN3R_TO_MIXOUTR 0x0008
#define WM8350_INR_TO_MIXOUTR 0x0002
#define WM8350_INL_TO_MIXOUTR 0x0001
/*
* R92 (0x5C) - OUT3 Mixer Control
*/
#define WM8350_DACL_TO_OUT3 0x0800
#define WM8350_MIXINL_TO_OUT3 0x0100
#define WM8350_OUT4_TO_OUT3 0x0008
#define WM8350_MIXOUTL_TO_OUT3 0x0001
/*
* R93 (0x5D) - OUT4 Mixer Control
*/
#define WM8350_DACR_TO_OUT4 0x1000
#define WM8350_DACL_TO_OUT4 0x0800
#define WM8350_OUT4_ATTN 0x0400
#define WM8350_MIXINR_TO_OUT4 0x0200
#define WM8350_OUT3_TO_OUT4 0x0004
#define WM8350_MIXOUTR_TO_OUT4 0x0002
#define WM8350_MIXOUTL_TO_OUT4 0x0001
/*
* R96 (0x60) - Output Left Mixer Volume
*/
#define WM8350_IN3L_MIXOUTL_VOL_MASK 0x0E00
#define WM8350_IN3L_MIXOUTL_VOL_SHIFT 9
#define WM8350_INR_MIXOUTL_VOL_MASK 0x00E0
#define WM8350_INR_MIXOUTL_VOL_SHIFT 5
#define WM8350_INL_MIXOUTL_VOL_MASK 0x000E
#define WM8350_INL_MIXOUTL_VOL_SHIFT 1
/* Bit values for R96 (0x60) */
#define WM8350_IN3L_MIXOUTL_VOL_OFF 0
#define WM8350_IN3L_MIXOUTL_VOL_M12DB 1
#define WM8350_IN3L_MIXOUTL_VOL_M9DB 2
#define WM8350_IN3L_MIXOUTL_VOL_M6DB 3
#define WM8350_IN3L_MIXOUTL_VOL_M3DB 4
#define WM8350_IN3L_MIXOUTL_VOL_0DB 5
#define WM8350_IN3L_MIXOUTL_VOL_3DB 6
#define WM8350_IN3L_MIXOUTL_VOL_6DB 7
#define WM8350_INR_MIXOUTL_VOL_OFF 0
#define WM8350_INR_MIXOUTL_VOL_M12DB 1
#define WM8350_INR_MIXOUTL_VOL_M9DB 2
#define WM8350_INR_MIXOUTL_VOL_M6DB 3
#define WM8350_INR_MIXOUTL_VOL_M3DB 4
#define WM8350_INR_MIXOUTL_VOL_0DB 5
#define WM8350_INR_MIXOUTL_VOL_3DB 6
#define WM8350_INR_MIXOUTL_VOL_6DB 7
#define WM8350_INL_MIXOUTL_VOL_OFF 0
#define WM8350_INL_MIXOUTL_VOL_M12DB 1
#define WM8350_INL_MIXOUTL_VOL_M9DB 2
#define WM8350_INL_MIXOUTL_VOL_M6DB 3
#define WM8350_INL_MIXOUTL_VOL_M3DB 4
#define WM8350_INL_MIXOUTL_VOL_0DB 5
#define WM8350_INL_MIXOUTL_VOL_3DB 6
#define WM8350_INL_MIXOUTL_VOL_6DB 7
/*
* R97 (0x61) - Output Right Mixer Volume
*/
#define WM8350_IN3R_MIXOUTR_VOL_MASK 0xE000
#define WM8350_IN3R_MIXOUTR_VOL_SHIFT 13
#define WM8350_INR_MIXOUTR_VOL_MASK 0x00E0
#define WM8350_INR_MIXOUTR_VOL_SHIFT 5
#define WM8350_INL_MIXOUTR_VOL_MASK 0x000E
#define WM8350_INL_MIXOUTR_VOL_SHIFT 1
/* Bit values for R96 (0x60) */
#define WM8350_IN3R_MIXOUTR_VOL_OFF 0
#define WM8350_IN3R_MIXOUTR_VOL_M12DB 1
#define WM8350_IN3R_MIXOUTR_VOL_M9DB 2
#define WM8350_IN3R_MIXOUTR_VOL_M6DB 3
#define WM8350_IN3R_MIXOUTR_VOL_M3DB 4
#define WM8350_IN3R_MIXOUTR_VOL_0DB 5
#define WM8350_IN3R_MIXOUTR_VOL_3DB 6
#define WM8350_IN3R_MIXOUTR_VOL_6DB 7
#define WM8350_INR_MIXOUTR_VOL_OFF 0
#define WM8350_INR_MIXOUTR_VOL_M12DB 1
#define WM8350_INR_MIXOUTR_VOL_M9DB 2
#define WM8350_INR_MIXOUTR_VOL_M6DB 3
#define WM8350_INR_MIXOUTR_VOL_M3DB 4
#define WM8350_INR_MIXOUTR_VOL_0DB 5
#define WM8350_INR_MIXOUTR_VOL_3DB 6
#define WM8350_INR_MIXOUTR_VOL_6DB 7
#define WM8350_INL_MIXOUTR_VOL_OFF 0
#define WM8350_INL_MIXOUTR_VOL_M12DB 1
#define WM8350_INL_MIXOUTR_VOL_M9DB 2
#define WM8350_INL_MIXOUTR_VOL_M6DB 3
#define WM8350_INL_MIXOUTR_VOL_M3DB 4
#define WM8350_INL_MIXOUTR_VOL_0DB 5
#define WM8350_INL_MIXOUTR_VOL_3DB 6
#define WM8350_INL_MIXOUTR_VOL_6DB 7
/*
* R98 (0x62) - Input Mixer Volume L
*/
#define WM8350_IN3L_MIXINL_VOL_MASK 0x0E00
#define WM8350_IN2L_MIXINL_VOL_MASK 0x000E
#define WM8350_INL_MIXINL_VOL 0x0001
/*
* R99 (0x63) - Input Mixer Volume R
*/
#define WM8350_IN3R_MIXINR_VOL_MASK 0xE000
#define WM8350_IN2R_MIXINR_VOL_MASK 0x00E0
#define WM8350_INR_MIXINR_VOL 0x0001
/*
* R100 (0x64) - Input Mixer Volume
*/
#define WM8350_OUT4_MIXIN_DST 0x8000
#define WM8350_OUT4_MIXIN_VOL_MASK 0x000E
/*
* R104 (0x68) - LOUT1 Volume
*/
#define WM8350_OUT1L_MUTE 0x4000
#define WM8350_OUT1L_ZC 0x2000
#define WM8350_OUT1_VU 0x0100
#define WM8350_OUT1L_VOL_MASK 0x00FC
#define WM8350_OUT1L_VOL_SHIFT 2
/*
* R105 (0x69) - ROUT1 Volume
*/
#define WM8350_OUT1R_MUTE 0x4000
#define WM8350_OUT1R_ZC 0x2000
#define WM8350_OUT1_VU 0x0100
#define WM8350_OUT1R_VOL_MASK 0x00FC
#define WM8350_OUT1R_VOL_SHIFT 2
/*
* R106 (0x6A) - LOUT2 Volume
*/
#define WM8350_OUT2L_MUTE 0x4000
#define WM8350_OUT2L_ZC 0x2000
#define WM8350_OUT2_VU 0x0100
#define WM8350_OUT2L_VOL_MASK 0x00FC
/*
* R107 (0x6B) - ROUT2 Volume
*/
#define WM8350_OUT2R_MUTE 0x4000
#define WM8350_OUT2R_ZC 0x2000
#define WM8350_OUT2R_INV 0x0400
#define WM8350_OUT2R_INV_MUTE 0x0200
#define WM8350_OUT2_VU 0x0100
#define WM8350_OUT2R_VOL_MASK 0x00FC
/*
* R111 (0x6F) - BEEP Volume
*/
#define WM8350_IN3R_OUT2R_VOL_MASK 0x00E0
/*
* R112 (0x70) - AI Formating
*/
#define WM8350_AIF_BCLK_INV 0x8000
#define WM8350_AIF_TRI 0x2000
#define WM8350_AIF_LRCLK_INV 0x1000
#define WM8350_AIF_WL_MASK 0x0C00
#define WM8350_AIF_FMT_MASK 0x0300
/*
* R113 (0x71) - ADC DAC COMP
*/
#define WM8350_DAC_COMP 0x0080
#define WM8350_DAC_COMPMODE 0x0040
#define WM8350_ADC_COMP 0x0020
#define WM8350_ADC_COMPMODE 0x0010
#define WM8350_LOOPBACK 0x0001
/*
* R114 (0x72) - AI ADC Control
*/
#define WM8350_AIFADC_PD 0x0080
#define WM8350_AIFADCL_SRC 0x0040
#define WM8350_AIFADCR_SRC 0x0020
#define WM8350_AIFADC_TDM_CHAN 0x0010
#define WM8350_AIFADC_TDM 0x0008
/*
* R115 (0x73) - AI DAC Control
*/
#define WM8350_BCLK_MSTR 0x4000
#define WM8350_AIFDAC_PD 0x0080
#define WM8350_DACL_SRC 0x0040
#define WM8350_DACR_SRC 0x0020
#define WM8350_AIFDAC_TDM_CHAN 0x0010
#define WM8350_AIFDAC_TDM 0x0008
#define WM8350_DAC_BOOST_MASK 0x0003
/*
* R116 (0x74) - AIF Test
*/
#define WM8350_CODEC_BYP 0x4000
#define WM8350_AIFADC_WR_TST 0x2000
#define WM8350_AIFADC_RD_TST 0x1000
#define WM8350_AIFDAC_WR_TST 0x0800
#define WM8350_AIFDAC_RD_TST 0x0400
#define WM8350_AIFADC_ASYN 0x0020
#define WM8350_AIFDAC_ASYN 0x0010
/*
* R231 (0xE7) - Jack Status
*/
#define WM8350_JACK_L_LVL 0x0800
#define WM8350_JACK_R_LVL 0x0400
/*
* WM8350 Platform setup
*/
#define WM8350_S_CURVE_NONE 0x0
#define WM8350_S_CURVE_FAST 0x1
#define WM8350_S_CURVE_MEDIUM 0x2
#define WM8350_S_CURVE_SLOW 0x3
#define WM8350_DISCHARGE_OFF 0x0
#define WM8350_DISCHARGE_FAST 0x1
#define WM8350_DISCHARGE_MEDIUM 0x2
#define WM8350_DISCHARGE_SLOW 0x3
#define WM8350_TIE_OFF_500R 0x0
#define WM8350_TIE_OFF_30K 0x1
/*
* Clock sources & directions
*/
#define WM8350_SYSCLK 0
#define WM8350_MCLK_SEL_PLL_MCLK 0
#define WM8350_MCLK_SEL_PLL_DAC 1
#define WM8350_MCLK_SEL_PLL_ADC 2
#define WM8350_MCLK_SEL_PLL_32K 3
#define WM8350_MCLK_SEL_MCLK 5
#define WM8350_MCLK_DIR_OUT 0
#define WM8350_MCLK_DIR_IN 1
/* clock divider id's */
#define WM8350_ADC_CLKDIV 0
#define WM8350_DAC_CLKDIV 1
#define WM8350_BCLK_CLKDIV 2
#define WM8350_OPCLK_CLKDIV 3
#define WM8350_TO_CLKDIV 4
#define WM8350_SYS_CLKDIV 5
#define WM8350_DACLR_CLKDIV 6
#define WM8350_ADCLR_CLKDIV 7
/* ADC clock dividers */
#define WM8350_ADCDIV_1 0x0
#define WM8350_ADCDIV_1_5 0x1
#define WM8350_ADCDIV_2 0x2
#define WM8350_ADCDIV_3 0x3
#define WM8350_ADCDIV_4 0x4
#define WM8350_ADCDIV_5_5 0x5
#define WM8350_ADCDIV_6 0x6
/* ADC clock dividers */
#define WM8350_DACDIV_1 0x0
#define WM8350_DACDIV_1_5 0x1
#define WM8350_DACDIV_2 0x2
#define WM8350_DACDIV_3 0x3
#define WM8350_DACDIV_4 0x4
#define WM8350_DACDIV_5_5 0x5
#define WM8350_DACDIV_6 0x6
/* BCLK clock dividers */
#define WM8350_BCLK_DIV_1 (0x0 << 4)
#define WM8350_BCLK_DIV_1_5 (0x1 << 4)
#define WM8350_BCLK_DIV_2 (0x2 << 4)
#define WM8350_BCLK_DIV_3 (0x3 << 4)
#define WM8350_BCLK_DIV_4 (0x4 << 4)
#define WM8350_BCLK_DIV_5_5 (0x5 << 4)
#define WM8350_BCLK_DIV_6 (0x6 << 4)
#define WM8350_BCLK_DIV_8 (0x7 << 4)
#define WM8350_BCLK_DIV_11 (0x8 << 4)
#define WM8350_BCLK_DIV_12 (0x9 << 4)
#define WM8350_BCLK_DIV_16 (0xa << 4)
#define WM8350_BCLK_DIV_22 (0xb << 4)
#define WM8350_BCLK_DIV_24 (0xc << 4)
#define WM8350_BCLK_DIV_32 (0xd << 4)
#define WM8350_BCLK_DIV_44 (0xe << 4)
#define WM8350_BCLK_DIV_48 (0xf << 4)
/* Sys (MCLK) clock dividers */
#define WM8350_MCLK_DIV_1 (0x0 << 8)
#define WM8350_MCLK_DIV_2 (0x1 << 8)
/* OP clock dividers */
#define WM8350_OPCLK_DIV_1 0x0
#define WM8350_OPCLK_DIV_2 0x1
#define WM8350_OPCLK_DIV_3 0x2
#define WM8350_OPCLK_DIV_4 0x3
#define WM8350_OPCLK_DIV_5_5 0x4
#define WM8350_OPCLK_DIV_6 0x5
/* DAI ID */
#define WM8350_HIFI_DAI 0
/*
* Audio interrupts.
*/
#define WM8350_IRQ_CODEC_JCK_DET_L 39
#define WM8350_IRQ_CODEC_JCK_DET_R 40
#define WM8350_IRQ_CODEC_MICSCD 41
#define WM8350_IRQ_CODEC_MICD 42
/*
* WM8350 Platform data.
*
* This must be initialised per platform for best audio performance.
* Please see WM8350 datasheet for information.
*/
struct wm8350_audio_platform_data {
int vmid_discharge_msecs; /* VMID --> OFF discharge time */
int drain_msecs; /* OFF drain time */
int cap_discharge_msecs; /* Cap ON (from OFF) discharge time */
int vmid_charge_msecs; /* vmid power up time */
u32 vmid_s_curve:2; /* vmid enable s curve speed */
u32 dis_out4:2; /* out4 discharge speed */
u32 dis_out3:2; /* out3 discharge speed */
u32 dis_out2:2; /* out2 discharge speed */
u32 dis_out1:2; /* out1 discharge speed */
u32 vroi_out4:1; /* out4 tie off */
u32 vroi_out3:1; /* out3 tie off */
u32 vroi_out2:1; /* out2 tie off */
u32 vroi_out1:1; /* out1 tie off */
u32 vroi_enable:1; /* enable tie off */
u32 codec_current_on:2; /* current level ON */
u32 codec_current_standby:2; /* current level STANDBY */
u32 codec_current_charge:2; /* codec current @ vmid charge */
};
struct snd_soc_codec;
struct wm8350_codec {
struct platform_device *pdev;
struct snd_soc_codec *codec;
struct wm8350_audio_platform_data *platform_data;
};
#endif

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/*
* comparator.h -- Comparator Aux ADC for Wolfson WM8350 PMIC
*
* Copyright 2007 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_WM8350_COMPARATOR_H_
#define __LINUX_MFD_WM8350_COMPARATOR_H_
/*
* Registers
*/
#define WM8350_DIGITISER_CONTROL_1 0x90
#define WM8350_DIGITISER_CONTROL_2 0x91
#define WM8350_AUX1_READBACK 0x98
#define WM8350_AUX2_READBACK 0x99
#define WM8350_AUX3_READBACK 0x9A
#define WM8350_AUX4_READBACK 0x9B
#define WM8350_CHIP_TEMP_READBACK 0x9F
#define WM8350_GENERIC_COMPARATOR_CONTROL 0xA3
#define WM8350_GENERIC_COMPARATOR_1 0xA4
#define WM8350_GENERIC_COMPARATOR_2 0xA5
#define WM8350_GENERIC_COMPARATOR_3 0xA6
#define WM8350_GENERIC_COMPARATOR_4 0xA7
/*
* R144 (0x90) - Digitiser Control (1)
*/
#define WM8350_AUXADC_CTC 0x4000
#define WM8350_AUXADC_POLL 0x2000
#define WM8350_AUXADC_HIB_MODE 0x1000
#define WM8350_AUXADC_SEL8 0x0080
#define WM8350_AUXADC_SEL7 0x0040
#define WM8350_AUXADC_SEL6 0x0020
#define WM8350_AUXADC_SEL5 0x0010
#define WM8350_AUXADC_SEL4 0x0008
#define WM8350_AUXADC_SEL3 0x0004
#define WM8350_AUXADC_SEL2 0x0002
#define WM8350_AUXADC_SEL1 0x0001
/*
* R145 (0x91) - Digitiser Control (2)
*/
#define WM8350_AUXADC_MASKMODE_MASK 0x3000
#define WM8350_AUXADC_CRATE_MASK 0x0700
#define WM8350_AUXADC_CAL 0x0004
#define WM8350_AUX_RBMODE 0x0002
#define WM8350_AUXADC_WAIT 0x0001
/*
* R152 (0x98) - AUX1 Readback
*/
#define WM8350_AUXADC_SCALE1_MASK 0x6000
#define WM8350_AUXADC_REF1 0x1000
#define WM8350_AUXADC_DATA1_MASK 0x0FFF
/*
* R153 (0x99) - AUX2 Readback
*/
#define WM8350_AUXADC_SCALE2_MASK 0x6000
#define WM8350_AUXADC_REF2 0x1000
#define WM8350_AUXADC_DATA2_MASK 0x0FFF
/*
* R154 (0x9A) - AUX3 Readback
*/
#define WM8350_AUXADC_SCALE3_MASK 0x6000
#define WM8350_AUXADC_REF3 0x1000
#define WM8350_AUXADC_DATA3_MASK 0x0FFF
/*
* R155 (0x9B) - AUX4 Readback
*/
#define WM8350_AUXADC_SCALE4_MASK 0x6000
#define WM8350_AUXADC_REF4 0x1000
#define WM8350_AUXADC_DATA4_MASK 0x0FFF
/*
* R156 (0x9C) - USB Voltage Readback
*/
#define WM8350_AUXADC_DATA_USB_MASK 0x0FFF
/*
* R157 (0x9D) - LINE Voltage Readback
*/
#define WM8350_AUXADC_DATA_LINE_MASK 0x0FFF
/*
* R158 (0x9E) - BATT Voltage Readback
*/
#define WM8350_AUXADC_DATA_BATT_MASK 0x0FFF
/*
* R159 (0x9F) - Chip Temp Readback
*/
#define WM8350_AUXADC_DATA_CHIPTEMP_MASK 0x0FFF
/*
* R163 (0xA3) - Generic Comparator Control
*/
#define WM8350_DCMP4_ENA 0x0008
#define WM8350_DCMP3_ENA 0x0004
#define WM8350_DCMP2_ENA 0x0002
#define WM8350_DCMP1_ENA 0x0001
/*
* R164 (0xA4) - Generic comparator 1
*/
#define WM8350_DCMP1_SRCSEL_MASK 0xE000
#define WM8350_DCMP1_GT 0x1000
#define WM8350_DCMP1_THR_MASK 0x0FFF
/*
* R165 (0xA5) - Generic comparator 2
*/
#define WM8350_DCMP2_SRCSEL_MASK 0xE000
#define WM8350_DCMP2_GT 0x1000
#define WM8350_DCMP2_THR_MASK 0x0FFF
/*
* R166 (0xA6) - Generic comparator 3
*/
#define WM8350_DCMP3_SRCSEL_MASK 0xE000
#define WM8350_DCMP3_GT 0x1000
#define WM8350_DCMP3_THR_MASK 0x0FFF
/*
* R167 (0xA7) - Generic comparator 4
*/
#define WM8350_DCMP4_SRCSEL_MASK 0xE000
#define WM8350_DCMP4_GT 0x1000
#define WM8350_DCMP4_THR_MASK 0x0FFF
/*
* Interrupts.
*/
#define WM8350_IRQ_AUXADC_DATARDY 16
#define WM8350_IRQ_AUXADC_DCOMP4 17
#define WM8350_IRQ_AUXADC_DCOMP3 18
#define WM8350_IRQ_AUXADC_DCOMP2 19
#define WM8350_IRQ_AUXADC_DCOMP1 20
#define WM8350_IRQ_SYS_HYST_COMP_FAIL 21
#define WM8350_IRQ_SYS_CHIP_GT115 22
#define WM8350_IRQ_SYS_CHIP_GT140 23
/*
* USB/2, LINE & BATT = ((VRTC * 2) / 4095)) * 10e6 uV
* Where VRTC = 2.7 V
*/
#define WM8350_AUX_COEFF 1319
#define WM8350_AUXADC_AUX1 0
#define WM8350_AUXADC_AUX2 1
#define WM8350_AUXADC_AUX3 2
#define WM8350_AUXADC_AUX4 3
#define WM8350_AUXADC_USB 4
#define WM8350_AUXADC_LINE 5
#define WM8350_AUXADC_BATT 6
#define WM8350_AUXADC_TEMP 7
struct wm8350;
/*
* AUX ADC Readback
*/
int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale,
int vref);
#endif

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kernel/include/linux/mfd/wm8350/core.h Normal file
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/*
* core.h -- Core Driver for Wolfson WM8350 PMIC
*
* Copyright 2007 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_WM8350_CORE_H_
#define __LINUX_MFD_WM8350_CORE_H_
#include <linux/kernel.h>
#include <linux/mutex.h>
#include <linux/workqueue.h>
#include <linux/mfd/wm8350/audio.h>
#include <linux/mfd/wm8350/gpio.h>
#include <linux/mfd/wm8350/pmic.h>
#include <linux/mfd/wm8350/rtc.h>
#include <linux/mfd/wm8350/supply.h>
#include <linux/mfd/wm8350/wdt.h>
/*
* Register values.
*/
#define WM8350_RESET_ID 0x00
#define WM8350_ID 0x01
#define WM8350_REVISION 0x02
#define WM8350_SYSTEM_CONTROL_1 0x03
#define WM8350_SYSTEM_CONTROL_2 0x04
#define WM8350_SYSTEM_HIBERNATE 0x05
#define WM8350_INTERFACE_CONTROL 0x06
#define WM8350_POWER_MGMT_1 0x08
#define WM8350_POWER_MGMT_2 0x09
#define WM8350_POWER_MGMT_3 0x0A
#define WM8350_POWER_MGMT_4 0x0B
#define WM8350_POWER_MGMT_5 0x0C
#define WM8350_POWER_MGMT_6 0x0D
#define WM8350_POWER_MGMT_7 0x0E
#define WM8350_SYSTEM_INTERRUPTS 0x18
#define WM8350_INT_STATUS_1 0x19
#define WM8350_INT_STATUS_2 0x1A
#define WM8350_POWER_UP_INT_STATUS 0x1B
#define WM8350_UNDER_VOLTAGE_INT_STATUS 0x1C
#define WM8350_OVER_CURRENT_INT_STATUS 0x1D
#define WM8350_GPIO_INT_STATUS 0x1E
#define WM8350_COMPARATOR_INT_STATUS 0x1F
#define WM8350_SYSTEM_INTERRUPTS_MASK 0x20
#define WM8350_INT_STATUS_1_MASK 0x21
#define WM8350_INT_STATUS_2_MASK 0x22
#define WM8350_POWER_UP_INT_STATUS_MASK 0x23
#define WM8350_UNDER_VOLTAGE_INT_STATUS_MASK 0x24
#define WM8350_OVER_CURRENT_INT_STATUS_MASK 0x25
#define WM8350_GPIO_INT_STATUS_MASK 0x26
#define WM8350_COMPARATOR_INT_STATUS_MASK 0x27
#define WM8350_CHARGER_OVERRIDES 0xE2
#define WM8350_MISC_OVERRIDES 0xE3
#define WM8350_COMPARATOR_OVERRIDES 0xE7
#define WM8350_STATE_MACHINE_STATUS 0xE9
#define WM8350_MAX_REGISTER 0xFF
/*
* Field Definitions.
*/
/*
* R0 (0x00) - Reset/ID
*/
#define WM8350_SW_RESET_CHIP_ID_MASK 0xFFFF
/*
* R1 (0x01) - ID
*/
#define WM8350_CHIP_REV_MASK 0x7000
#define WM8350_CONF_STS_MASK 0x0C00
#define WM8350_CUST_ID_MASK 0x00FF
/*
* R2 (0x02) - Revision
*/
#define WM8350_MASK_REV_MASK 0x00FF
/*
* R3 (0x03) - System Control 1
*/
#define WM8350_CHIP_ON 0x8000
#define WM8350_POWERCYCLE 0x2000
#define WM8350_VCC_FAULT_OV 0x1000
#define WM8350_REG_RSTB_TIME_MASK 0x0C00
#define WM8350_BG_SLEEP 0x0200
#define WM8350_MEM_VALID 0x0020
#define WM8350_CHIP_SET_UP 0x0010
#define WM8350_ON_DEB_T 0x0008
#define WM8350_ON_POL 0x0002
#define WM8350_IRQ_POL 0x0001
/*
* R4 (0x04) - System Control 2
*/
#define WM8350_USB_SUSPEND_8MA 0x8000
#define WM8350_USB_SUSPEND 0x4000
#define WM8350_USB_MSTR 0x2000
#define WM8350_USB_MSTR_SRC 0x1000
#define WM8350_USB_500MA 0x0800
#define WM8350_USB_NOLIM 0x0400
/*
* R5 (0x05) - System Hibernate
*/
#define WM8350_HIBERNATE 0x8000
#define WM8350_WDOG_HIB_MODE 0x0080
#define WM8350_REG_HIB_STARTUP_SEQ 0x0040
#define WM8350_REG_RESET_HIB_MODE 0x0020
#define WM8350_RST_HIB_MODE 0x0010
#define WM8350_IRQ_HIB_MODE 0x0008
#define WM8350_MEMRST_HIB_MODE 0x0004
#define WM8350_PCCOMP_HIB_MODE 0x0002
#define WM8350_TEMPMON_HIB_MODE 0x0001
/*
* R6 (0x06) - Interface Control
*/
#define WM8350_USE_DEV_PINS 0x8000
#define WM8350_USE_DEV_PINS_MASK 0x8000
#define WM8350_USE_DEV_PINS_SHIFT 15
#define WM8350_DEV_ADDR_MASK 0x6000
#define WM8350_DEV_ADDR_SHIFT 13
#define WM8350_CONFIG_DONE 0x1000
#define WM8350_CONFIG_DONE_MASK 0x1000
#define WM8350_CONFIG_DONE_SHIFT 12
#define WM8350_RECONFIG_AT_ON 0x0800
#define WM8350_RECONFIG_AT_ON_MASK 0x0800
#define WM8350_RECONFIG_AT_ON_SHIFT 11
#define WM8350_AUTOINC 0x0200
#define WM8350_AUTOINC_MASK 0x0200
#define WM8350_AUTOINC_SHIFT 9
#define WM8350_ARA 0x0100
#define WM8350_ARA_MASK 0x0100
#define WM8350_ARA_SHIFT 8
#define WM8350_SPI_CFG 0x0008
#define WM8350_SPI_CFG_MASK 0x0008
#define WM8350_SPI_CFG_SHIFT 3
#define WM8350_SPI_4WIRE 0x0004
#define WM8350_SPI_4WIRE_MASK 0x0004
#define WM8350_SPI_4WIRE_SHIFT 2
#define WM8350_SPI_3WIRE 0x0002
#define WM8350_SPI_3WIRE_MASK 0x0002
#define WM8350_SPI_3WIRE_SHIFT 1
/* Bit values for R06 (0x06) */
#define WM8350_USE_DEV_PINS_PRIMARY 0
#define WM8350_USE_DEV_PINS_DEV 1
#define WM8350_DEV_ADDR_34 0
#define WM8350_DEV_ADDR_36 1
#define WM8350_DEV_ADDR_3C 2
#define WM8350_DEV_ADDR_3E 3
#define WM8350_CONFIG_DONE_OFF 0
#define WM8350_CONFIG_DONE_DONE 1
#define WM8350_RECONFIG_AT_ON_OFF 0
#define WM8350_RECONFIG_AT_ON_ON 1
#define WM8350_AUTOINC_OFF 0
#define WM8350_AUTOINC_ON 1
#define WM8350_ARA_OFF 0
#define WM8350_ARA_ON 1
#define WM8350_SPI_CFG_CMOS 0
#define WM8350_SPI_CFG_OD 1
#define WM8350_SPI_4WIRE_3WIRE 0
#define WM8350_SPI_4WIRE_4WIRE 1
#define WM8350_SPI_3WIRE_I2C 0
#define WM8350_SPI_3WIRE_SPI 1
/*
* R8 (0x08) - Power mgmt (1)
*/
#define WM8350_CODEC_ISEL_MASK 0xC000
#define WM8350_VBUFEN 0x2000
#define WM8350_OUTPUT_DRAIN_EN 0x0400
#define WM8350_MIC_DET_ENA 0x0100
#define WM8350_BIASEN 0x0020
#define WM8350_MICBEN 0x0010
#define WM8350_VMIDEN 0x0004
#define WM8350_VMID_MASK 0x0003
#define WM8350_VMID_SHIFT 0
/*
* R9 (0x09) - Power mgmt (2)
*/
#define WM8350_IN3R_ENA 0x0800
#define WM8350_IN3L_ENA 0x0400
#define WM8350_INR_ENA 0x0200
#define WM8350_INL_ENA 0x0100
#define WM8350_MIXINR_ENA 0x0080
#define WM8350_MIXINL_ENA 0x0040
#define WM8350_OUT4_ENA 0x0020
#define WM8350_OUT3_ENA 0x0010
#define WM8350_MIXOUTR_ENA 0x0002
#define WM8350_MIXOUTL_ENA 0x0001
/*
* R10 (0x0A) - Power mgmt (3)
*/
#define WM8350_IN3R_TO_OUT2R 0x0080
#define WM8350_OUT2R_ENA 0x0008
#define WM8350_OUT2L_ENA 0x0004
#define WM8350_OUT1R_ENA 0x0002
#define WM8350_OUT1L_ENA 0x0001
/*
* R11 (0x0B) - Power mgmt (4)
*/
#define WM8350_SYSCLK_ENA 0x4000
#define WM8350_ADC_HPF_ENA 0x2000
#define WM8350_FLL_ENA 0x0800
#define WM8350_FLL_OSC_ENA 0x0400
#define WM8350_TOCLK_ENA 0x0100
#define WM8350_DACR_ENA 0x0020
#define WM8350_DACL_ENA 0x0010
#define WM8350_ADCR_ENA 0x0008
#define WM8350_ADCL_ENA 0x0004
/*
* R12 (0x0C) - Power mgmt (5)
*/
#define WM8350_CODEC_ENA 0x1000
#define WM8350_RTC_TICK_ENA 0x0800
#define WM8350_OSC32K_ENA 0x0400
#define WM8350_CHG_ENA 0x0200
#define WM8350_ACC_DET_ENA 0x0100
#define WM8350_AUXADC_ENA 0x0080
#define WM8350_DCMP4_ENA 0x0008
#define WM8350_DCMP3_ENA 0x0004
#define WM8350_DCMP2_ENA 0x0002
#define WM8350_DCMP1_ENA 0x0001
/*
* R13 (0x0D) - Power mgmt (6)
*/
#define WM8350_LS_ENA 0x8000
#define WM8350_LDO4_ENA 0x0800
#define WM8350_LDO3_ENA 0x0400
#define WM8350_LDO2_ENA 0x0200
#define WM8350_LDO1_ENA 0x0100
#define WM8350_DC6_ENA 0x0020
#define WM8350_DC5_ENA 0x0010
#define WM8350_DC4_ENA 0x0008
#define WM8350_DC3_ENA 0x0004
#define WM8350_DC2_ENA 0x0002
#define WM8350_DC1_ENA 0x0001
/*
* R14 (0x0E) - Power mgmt (7)
*/
#define WM8350_CS2_ENA 0x0002
#define WM8350_CS1_ENA 0x0001
/*
* R24 (0x18) - System Interrupts
*/
#define WM8350_OC_INT 0x2000
#define WM8350_UV_INT 0x1000
#define WM8350_PUTO_INT 0x0800
#define WM8350_CS_INT 0x0200
#define WM8350_EXT_INT 0x0100
#define WM8350_CODEC_INT 0x0080
#define WM8350_GP_INT 0x0040
#define WM8350_AUXADC_INT 0x0020
#define WM8350_RTC_INT 0x0010
#define WM8350_SYS_INT 0x0008
#define WM8350_CHG_INT 0x0004
#define WM8350_USB_INT 0x0002
#define WM8350_WKUP_INT 0x0001
/*
* R25 (0x19) - Interrupt Status 1
*/
#define WM8350_CHG_BAT_HOT_EINT 0x8000
#define WM8350_CHG_BAT_COLD_EINT 0x4000
#define WM8350_CHG_BAT_FAIL_EINT 0x2000
#define WM8350_CHG_TO_EINT 0x1000
#define WM8350_CHG_END_EINT 0x0800
#define WM8350_CHG_START_EINT 0x0400
#define WM8350_CHG_FAST_RDY_EINT 0x0200
#define WM8350_RTC_PER_EINT 0x0080
#define WM8350_RTC_SEC_EINT 0x0040
#define WM8350_RTC_ALM_EINT 0x0020
#define WM8350_CHG_VBATT_LT_3P9_EINT 0x0004
#define WM8350_CHG_VBATT_LT_3P1_EINT 0x0002
#define WM8350_CHG_VBATT_LT_2P85_EINT 0x0001
/*
* R26 (0x1A) - Interrupt Status 2
*/
#define WM8350_CS1_EINT 0x2000
#define WM8350_CS2_EINT 0x1000
#define WM8350_USB_LIMIT_EINT 0x0400
#define WM8350_AUXADC_DATARDY_EINT 0x0100
#define WM8350_AUXADC_DCOMP4_EINT 0x0080
#define WM8350_AUXADC_DCOMP3_EINT 0x0040
#define WM8350_AUXADC_DCOMP2_EINT 0x0020
#define WM8350_AUXADC_DCOMP1_EINT 0x0010
#define WM8350_SYS_HYST_COMP_FAIL_EINT 0x0008
#define WM8350_SYS_CHIP_GT115_EINT 0x0004
#define WM8350_SYS_CHIP_GT140_EINT 0x0002
#define WM8350_SYS_WDOG_TO_EINT 0x0001
/*
* R27 (0x1B) - Power Up Interrupt Status
*/
#define WM8350_PUTO_LDO4_EINT 0x0800
#define WM8350_PUTO_LDO3_EINT 0x0400
#define WM8350_PUTO_LDO2_EINT 0x0200
#define WM8350_PUTO_LDO1_EINT 0x0100
#define WM8350_PUTO_DC6_EINT 0x0020
#define WM8350_PUTO_DC5_EINT 0x0010
#define WM8350_PUTO_DC4_EINT 0x0008
#define WM8350_PUTO_DC3_EINT 0x0004
#define WM8350_PUTO_DC2_EINT 0x0002
#define WM8350_PUTO_DC1_EINT 0x0001
/*
* R28 (0x1C) - Under Voltage Interrupt status
*/
#define WM8350_UV_LDO4_EINT 0x0800
#define WM8350_UV_LDO3_EINT 0x0400
#define WM8350_UV_LDO2_EINT 0x0200
#define WM8350_UV_LDO1_EINT 0x0100
#define WM8350_UV_DC6_EINT 0x0020
#define WM8350_UV_DC5_EINT 0x0010
#define WM8350_UV_DC4_EINT 0x0008
#define WM8350_UV_DC3_EINT 0x0004
#define WM8350_UV_DC2_EINT 0x0002
#define WM8350_UV_DC1_EINT 0x0001
/*
* R29 (0x1D) - Over Current Interrupt status
*/
#define WM8350_OC_LS_EINT 0x8000
/*
* R30 (0x1E) - GPIO Interrupt Status
*/
#define WM8350_GP12_EINT 0x1000
#define WM8350_GP11_EINT 0x0800
#define WM8350_GP10_EINT 0x0400
#define WM8350_GP9_EINT 0x0200
#define WM8350_GP8_EINT 0x0100
#define WM8350_GP7_EINT 0x0080
#define WM8350_GP6_EINT 0x0040
#define WM8350_GP5_EINT 0x0020
#define WM8350_GP4_EINT 0x0010
#define WM8350_GP3_EINT 0x0008
#define WM8350_GP2_EINT 0x0004
#define WM8350_GP1_EINT 0x0002
#define WM8350_GP0_EINT 0x0001
/*
* R31 (0x1F) - Comparator Interrupt Status
*/
#define WM8350_EXT_USB_FB_EINT 0x8000
#define WM8350_EXT_WALL_FB_EINT 0x4000
#define WM8350_EXT_BAT_FB_EINT 0x2000
#define WM8350_CODEC_JCK_DET_L_EINT 0x0800
#define WM8350_CODEC_JCK_DET_R_EINT 0x0400
#define WM8350_CODEC_MICSCD_EINT 0x0200
#define WM8350_CODEC_MICD_EINT 0x0100
#define WM8350_WKUP_OFF_STATE_EINT 0x0040
#define WM8350_WKUP_HIB_STATE_EINT 0x0020
#define WM8350_WKUP_CONV_FAULT_EINT 0x0010
#define WM8350_WKUP_WDOG_RST_EINT 0x0008
#define WM8350_WKUP_GP_PWR_ON_EINT 0x0004
#define WM8350_WKUP_ONKEY_EINT 0x0002
#define WM8350_WKUP_GP_WAKEUP_EINT 0x0001
/*
* R32 (0x20) - System Interrupts Mask
*/
#define WM8350_IM_OC_INT 0x2000
#define WM8350_IM_UV_INT 0x1000
#define WM8350_IM_PUTO_INT 0x0800
#define WM8350_IM_SPARE_INT 0x0400
#define WM8350_IM_CS_INT 0x0200
#define WM8350_IM_EXT_INT 0x0100
#define WM8350_IM_CODEC_INT 0x0080
#define WM8350_IM_GP_INT 0x0040
#define WM8350_IM_AUXADC_INT 0x0020
#define WM8350_IM_RTC_INT 0x0010
#define WM8350_IM_SYS_INT 0x0008
#define WM8350_IM_CHG_INT 0x0004
#define WM8350_IM_USB_INT 0x0002
#define WM8350_IM_WKUP_INT 0x0001
/*
* R33 (0x21) - Interrupt Status 1 Mask
*/
#define WM8350_IM_CHG_BAT_HOT_EINT 0x8000
#define WM8350_IM_CHG_BAT_COLD_EINT 0x4000
#define WM8350_IM_CHG_BAT_FAIL_EINT 0x2000
#define WM8350_IM_CHG_TO_EINT 0x1000
#define WM8350_IM_CHG_END_EINT 0x0800
#define WM8350_IM_CHG_START_EINT 0x0400
#define WM8350_IM_CHG_FAST_RDY_EINT 0x0200
#define WM8350_IM_RTC_PER_EINT 0x0080
#define WM8350_IM_RTC_SEC_EINT 0x0040
#define WM8350_IM_RTC_ALM_EINT 0x0020
#define WM8350_IM_CHG_VBATT_LT_3P9_EINT 0x0004
#define WM8350_IM_CHG_VBATT_LT_3P1_EINT 0x0002
#define WM8350_IM_CHG_VBATT_LT_2P85_EINT 0x0001
/*
* R34 (0x22) - Interrupt Status 2 Mask
*/
#define WM8350_IM_SPARE2_EINT 0x8000
#define WM8350_IM_SPARE1_EINT 0x4000
#define WM8350_IM_CS1_EINT 0x2000
#define WM8350_IM_CS2_EINT 0x1000
#define WM8350_IM_USB_LIMIT_EINT 0x0400
#define WM8350_IM_AUXADC_DATARDY_EINT 0x0100
#define WM8350_IM_AUXADC_DCOMP4_EINT 0x0080
#define WM8350_IM_AUXADC_DCOMP3_EINT 0x0040
#define WM8350_IM_AUXADC_DCOMP2_EINT 0x0020
#define WM8350_IM_AUXADC_DCOMP1_EINT 0x0010
#define WM8350_IM_SYS_HYST_COMP_FAIL_EINT 0x0008
#define WM8350_IM_SYS_CHIP_GT115_EINT 0x0004
#define WM8350_IM_SYS_CHIP_GT140_EINT 0x0002
#define WM8350_IM_SYS_WDOG_TO_EINT 0x0001
/*
* R35 (0x23) - Power Up Interrupt Status Mask
*/
#define WM8350_IM_PUTO_LDO4_EINT 0x0800
#define WM8350_IM_PUTO_LDO3_EINT 0x0400
#define WM8350_IM_PUTO_LDO2_EINT 0x0200
#define WM8350_IM_PUTO_LDO1_EINT 0x0100
#define WM8350_IM_PUTO_DC6_EINT 0x0020
#define WM8350_IM_PUTO_DC5_EINT 0x0010
#define WM8350_IM_PUTO_DC4_EINT 0x0008
#define WM8350_IM_PUTO_DC3_EINT 0x0004
#define WM8350_IM_PUTO_DC2_EINT 0x0002
#define WM8350_IM_PUTO_DC1_EINT 0x0001
/*
* R36 (0x24) - Under Voltage Interrupt status Mask
*/
#define WM8350_IM_UV_LDO4_EINT 0x0800
#define WM8350_IM_UV_LDO3_EINT 0x0400
#define WM8350_IM_UV_LDO2_EINT 0x0200
#define WM8350_IM_UV_LDO1_EINT 0x0100
#define WM8350_IM_UV_DC6_EINT 0x0020
#define WM8350_IM_UV_DC5_EINT 0x0010
#define WM8350_IM_UV_DC4_EINT 0x0008
#define WM8350_IM_UV_DC3_EINT 0x0004
#define WM8350_IM_UV_DC2_EINT 0x0002
#define WM8350_IM_UV_DC1_EINT 0x0001
/*
* R37 (0x25) - Over Current Interrupt status Mask
*/
#define WM8350_IM_OC_LS_EINT 0x8000
/*
* R38 (0x26) - GPIO Interrupt Status Mask
*/
#define WM8350_IM_GP12_EINT 0x1000
#define WM8350_IM_GP11_EINT 0x0800
#define WM8350_IM_GP10_EINT 0x0400
#define WM8350_IM_GP9_EINT 0x0200
#define WM8350_IM_GP8_EINT 0x0100
#define WM8350_IM_GP7_EINT 0x0080
#define WM8350_IM_GP6_EINT 0x0040
#define WM8350_IM_GP5_EINT 0x0020
#define WM8350_IM_GP4_EINT 0x0010
#define WM8350_IM_GP3_EINT 0x0008
#define WM8350_IM_GP2_EINT 0x0004
#define WM8350_IM_GP1_EINT 0x0002
#define WM8350_IM_GP0_EINT 0x0001
/*
* R39 (0x27) - Comparator Interrupt Status Mask
*/
#define WM8350_IM_EXT_USB_FB_EINT 0x8000
#define WM8350_IM_EXT_WALL_FB_EINT 0x4000
#define WM8350_IM_EXT_BAT_FB_EINT 0x2000
#define WM8350_IM_CODEC_JCK_DET_L_EINT 0x0800
#define WM8350_IM_CODEC_JCK_DET_R_EINT 0x0400
#define WM8350_IM_CODEC_MICSCD_EINT 0x0200
#define WM8350_IM_CODEC_MICD_EINT 0x0100
#define WM8350_IM_WKUP_OFF_STATE_EINT 0x0040
#define WM8350_IM_WKUP_HIB_STATE_EINT 0x0020
#define WM8350_IM_WKUP_CONV_FAULT_EINT 0x0010
#define WM8350_IM_WKUP_WDOG_RST_EINT 0x0008
#define WM8350_IM_WKUP_GP_PWR_ON_EINT 0x0004
#define WM8350_IM_WKUP_ONKEY_EINT 0x0002
#define WM8350_IM_WKUP_GP_WAKEUP_EINT 0x0001
/*
* R220 (0xDC) - RAM BIST 1
*/
#define WM8350_READ_STATUS 0x0800
#define WM8350_TSTRAM_CLK 0x0100
#define WM8350_TSTRAM_CLK_ENA 0x0080
#define WM8350_STARTSEQ 0x0040
#define WM8350_READ_SRC 0x0020
#define WM8350_COUNT_DIR 0x0010
#define WM8350_TSTRAM_MODE_MASK 0x000E
#define WM8350_TSTRAM_ENA 0x0001
/*
* R225 (0xE1) - DCDC/LDO status
*/
#define WM8350_LS_STS 0x8000
#define WM8350_LDO4_STS 0x0800
#define WM8350_LDO3_STS 0x0400
#define WM8350_LDO2_STS 0x0200
#define WM8350_LDO1_STS 0x0100
#define WM8350_DC6_STS 0x0020
#define WM8350_DC5_STS 0x0010
#define WM8350_DC4_STS 0x0008
#define WM8350_DC3_STS 0x0004
#define WM8350_DC2_STS 0x0002
#define WM8350_DC1_STS 0x0001
/*
* R226 (0xE2) - Charger status
*/
#define WM8350_CHG_BATT_HOT_OVRDE 0x8000
#define WM8350_CHG_BATT_COLD_OVRDE 0x4000
/*
* R227 (0xE3) - Misc Overrides
*/
#define WM8350_USB_LIMIT_OVRDE 0x0400
/*
* R227 (0xE7) - Comparator Overrides
*/
#define WM8350_USB_FB_OVRDE 0x8000
#define WM8350_WALL_FB_OVRDE 0x4000
#define WM8350_BATT_FB_OVRDE 0x2000
/*
* R233 (0xE9) - State Machinine Status
*/
#define WM8350_USB_SM_MASK 0x0700
#define WM8350_USB_SM_SHIFT 8
#define WM8350_USB_SM_100_SLV 1
#define WM8350_USB_SM_500_SLV 5
#define WM8350_USB_SM_STDBY_SLV 7
/* WM8350 wake up conditions */
#define WM8350_IRQ_WKUP_OFF_STATE 43
#define WM8350_IRQ_WKUP_HIB_STATE 44
#define WM8350_IRQ_WKUP_CONV_FAULT 45
#define WM8350_IRQ_WKUP_WDOG_RST 46
#define WM8350_IRQ_WKUP_GP_PWR_ON 47
#define WM8350_IRQ_WKUP_ONKEY 48
#define WM8350_IRQ_WKUP_GP_WAKEUP 49
/* wm8350 chip revisions */
#define WM8350_REV_E 0x4
#define WM8350_REV_F 0x5
#define WM8350_REV_G 0x6
#define WM8350_REV_H 0x7
#define WM8350_NUM_IRQ 63
struct wm8350_reg_access {
u16 readable; /* Mask of readable bits */
u16 writable; /* Mask of writable bits */
u16 vol; /* Mask of volatile bits */
};
extern const struct wm8350_reg_access wm8350_reg_io_map[];
extern const u16 wm8350_mode0_defaults[];
extern const u16 wm8350_mode1_defaults[];
extern const u16 wm8350_mode2_defaults[];
extern const u16 wm8350_mode3_defaults[];
extern const u16 wm8351_mode0_defaults[];
extern const u16 wm8351_mode1_defaults[];
extern const u16 wm8351_mode2_defaults[];
extern const u16 wm8351_mode3_defaults[];
extern const u16 wm8352_mode0_defaults[];
extern const u16 wm8352_mode1_defaults[];
extern const u16 wm8352_mode2_defaults[];
extern const u16 wm8352_mode3_defaults[];
struct wm8350;
struct wm8350_irq {
void (*handler) (struct wm8350 *, int, void *);
void *data;
};
struct wm8350_hwmon {
struct platform_device *pdev;
struct device *classdev;
};
struct wm8350 {
struct device *dev;
/* device IO */
union {
struct i2c_client *i2c_client;
struct spi_device *spi_device;
};
int (*read_dev)(struct wm8350 *wm8350, char reg, int size, void *dest);
int (*write_dev)(struct wm8350 *wm8350, char reg, int size,
void *src);
u16 *reg_cache;
struct mutex auxadc_mutex;
/* Interrupt handling */
struct mutex irq_mutex; /* IRQ table mutex */
struct wm8350_irq irq[WM8350_NUM_IRQ];
int chip_irq;
/* Client devices */
struct wm8350_codec codec;
struct wm8350_gpio gpio;
struct wm8350_hwmon hwmon;
struct wm8350_pmic pmic;
struct wm8350_power power;
struct wm8350_rtc rtc;
struct wm8350_wdt wdt;
};
/**
* Data to be supplied by the platform to initialise the WM8350.
*
* @init: Function called during driver initialisation. Should be
* used by the platform to configure GPIO functions and similar.
* @irq_high: Set if WM8350 IRQ is active high.
*/
struct wm8350_platform_data {
int (*init)(struct wm8350 *wm8350);
int irq_high;
};
/*
* WM8350 device initialisation and exit.
*/
int wm8350_device_init(struct wm8350 *wm8350, int irq,
struct wm8350_platform_data *pdata);
void wm8350_device_exit(struct wm8350 *wm8350);
/*
* WM8350 device IO
*/
int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
u16 wm8350_reg_read(struct wm8350 *wm8350, int reg);
int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val);
int wm8350_reg_lock(struct wm8350 *wm8350);
int wm8350_reg_unlock(struct wm8350 *wm8350);
int wm8350_block_read(struct wm8350 *wm8350, int reg, int size, u16 *dest);
int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src);
/*
* WM8350 internal interrupts
*/
int wm8350_register_irq(struct wm8350 *wm8350, int irq,
void (*handler) (struct wm8350 *, int, void *),
void *data);
int wm8350_free_irq(struct wm8350 *wm8350, int irq);
int wm8350_mask_irq(struct wm8350 *wm8350, int irq);
int wm8350_unmask_irq(struct wm8350 *wm8350, int irq);
#endif

342
kernel/include/linux/mfd/wm8350/gpio.h Normal file
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/*
* gpio.h -- GPIO Driver for Wolfson WM8350 PMIC
*
* Copyright 2007 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_WM8350_GPIO_H_
#define __LINUX_MFD_WM8350_GPIO_H_
#include <linux/platform_device.h>
/*
* GPIO Registers.
*/
#define WM8350_GPIO_DEBOUNCE 0x80
#define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
#define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
#define WM8350_GPIO_INT_MODE 0x83
#define WM8350_GPIO_CONTROL 0x85
#define WM8350_GPIO_CONFIGURATION_I_O 0x86
#define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
#define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
#define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
#define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
#define WM8350_GPIO_FUNCTION_SELECT_4 0x8F
/*
* GPIO Functions
*/
#define WM8350_GPIO0_GPIO_IN 0x0
#define WM8350_GPIO0_GPIO_OUT 0x0
#define WM8350_GPIO0_PWR_ON_IN 0x1
#define WM8350_GPIO0_PWR_ON_OUT 0x1
#define WM8350_GPIO0_LDO_EN_IN 0x2
#define WM8350_GPIO0_VRTC_OUT 0x2
#define WM8350_GPIO0_LPWR1_IN 0x3
#define WM8350_GPIO0_POR_B_OUT 0x3
#define WM8350_GPIO1_GPIO_IN 0x0
#define WM8350_GPIO1_GPIO_OUT 0x0
#define WM8350_GPIO1_PWR_ON_IN 0x1
#define WM8350_GPIO1_DO_CONF_OUT 0x1
#define WM8350_GPIO1_LDO_EN_IN 0x2
#define WM8350_GPIO1_RESET_OUT 0x2
#define WM8350_GPIO1_LPWR2_IN 0x3
#define WM8350_GPIO1_MEMRST_OUT 0x3
#define WM8350_GPIO2_GPIO_IN 0x0
#define WM8350_GPIO2_GPIO_OUT 0x0
#define WM8350_GPIO2_PWR_ON_IN 0x1
#define WM8350_GPIO2_PWR_ON_OUT 0x1
#define WM8350_GPIO2_WAKE_UP_IN 0x2
#define WM8350_GPIO2_VRTC_OUT 0x2
#define WM8350_GPIO2_32KHZ_IN 0x3
#define WM8350_GPIO2_32KHZ_OUT 0x3
#define WM8350_GPIO3_GPIO_IN 0x0
#define WM8350_GPIO3_GPIO_OUT 0x0
#define WM8350_GPIO3_PWR_ON_IN 0x1
#define WM8350_GPIO3_P_CLK_OUT 0x1
#define WM8350_GPIO3_LDO_EN_IN 0x2
#define WM8350_GPIO3_VRTC_OUT 0x2
#define WM8350_GPIO3_PWR_OFF_IN 0x3
#define WM8350_GPIO3_32KHZ_OUT 0x3
#define WM8350_GPIO4_GPIO_IN 0x0
#define WM8350_GPIO4_GPIO_OUT 0x0
#define WM8350_GPIO4_MR_IN 0x1
#define WM8350_GPIO4_MEM_RST_OUT 0x1
#define WM8350_GPIO4_FLASH_IN 0x2
#define WM8350_GPIO4_ADA_OUT 0x2
#define WM8350_GPIO4_HIBERNATE_IN 0x3
#define WM8350_GPIO4_FLASH_OUT 0x3
#define WM8350_GPIO4_MICDET_OUT 0x4
#define WM8350_GPIO4_MICSHT_OUT 0x5
#define WM8350_GPIO5_GPIO_IN 0x0
#define WM8350_GPIO5_GPIO_OUT 0x0
#define WM8350_GPIO5_LPWR1_IN 0x1
#define WM8350_GPIO5_P_CLK_OUT 0x1
#define WM8350_GPIO5_ADCLRCLK_IN 0x2
#define WM8350_GPIO5_ADCLRCLK_OUT 0x2
#define WM8350_GPIO5_HIBERNATE_IN 0x3
#define WM8350_GPIO5_32KHZ_OUT 0x3
#define WM8350_GPIO5_MICDET_OUT 0x4
#define WM8350_GPIO5_MICSHT_OUT 0x5
#define WM8350_GPIO5_ADA_OUT 0x6
#define WM8350_GPIO5_OPCLK_OUT 0x7
#define WM8350_GPIO6_GPIO_IN 0x0
#define WM8350_GPIO6_GPIO_OUT 0x0
#define WM8350_GPIO6_LPWR2_IN 0x1
#define WM8350_GPIO6_MEMRST_OUT 0x1
#define WM8350_GPIO6_FLASH_IN 0x2
#define WM8350_GPIO6_ADA_OUT 0x2
#define WM8350_GPIO6_HIBERNATE_IN 0x3
#define WM8350_GPIO6_RTC_OUT 0x3
#define WM8350_GPIO6_MICDET_OUT 0x4
#define WM8350_GPIO6_MICSHT_OUT 0x5
#define WM8350_GPIO6_ADCLRCLKB_OUT 0x6
#define WM8350_GPIO6_SDOUT_OUT 0x7
#define WM8350_GPIO7_GPIO_IN 0x0
#define WM8350_GPIO7_GPIO_OUT 0x0
#define WM8350_GPIO7_LPWR3_IN 0x1
#define WM8350_GPIO7_P_CLK_OUT 0x1
#define WM8350_GPIO7_MASK_IN 0x2
#define WM8350_GPIO7_VCC_FAULT_OUT 0x2
#define WM8350_GPIO7_HIBERNATE_IN 0x3
#define WM8350_GPIO7_BATT_FAULT_OUT 0x3
#define WM8350_GPIO7_MICDET_OUT 0x4
#define WM8350_GPIO7_MICSHT_OUT 0x5
#define WM8350_GPIO7_ADA_OUT 0x6
#define WM8350_GPIO7_CSB_IN 0x7
#define WM8350_GPIO8_GPIO_IN 0x0
#define WM8350_GPIO8_GPIO_OUT 0x0
#define WM8350_GPIO8_MR_IN 0x1
#define WM8350_GPIO8_VCC_FAULT_OUT 0x1
#define WM8350_GPIO8_ADCBCLK_IN 0x2
#define WM8350_GPIO8_ADCBCLK_OUT 0x2
#define WM8350_GPIO8_PWR_OFF_IN 0x3
#define WM8350_GPIO8_BATT_FAULT_OUT 0x3
#define WM8350_GPIO8_ALTSCL_IN 0xf
#define WM8350_GPIO9_GPIO_IN 0x0
#define WM8350_GPIO9_GPIO_OUT 0x0
#define WM8350_GPIO9_HEARTBEAT_IN 0x1
#define WM8350_GPIO9_VCC_FAULT_OUT 0x1
#define WM8350_GPIO9_MASK_IN 0x2
#define WM8350_GPIO9_LINE_GT_BATT_OUT 0x2
#define WM8350_GPIO9_PWR_OFF_IN 0x3
#define WM8350_GPIO9_BATT_FAULT_OUT 0x3
#define WM8350_GPIO9_ALTSDA_OUT 0xf
#define WM8350_GPIO10_GPIO_IN 0x0
#define WM8350_GPIO10_GPIO_OUT 0x0
#define WM8350_GPIO10_ISINKC_OUT 0x1
#define WM8350_GPIO10_PWR_OFF_IN 0x2
#define WM8350_GPIO10_LINE_GT_BATT_OUT 0x2
#define WM8350_GPIO10_CHD_IND_IN 0x3
#define WM8350_GPIO11_GPIO_IN 0x0
#define WM8350_GPIO11_GPIO_OUT 0x0
#define WM8350_GPIO11_ISINKD_OUT 0x1
#define WM8350_GPIO11_WAKEUP_IN 0x2
#define WM8350_GPIO11_LINE_GT_BATT_OUT 0x2
#define WM8350_GPIO11_CHD_IND_IN 0x3
#define WM8350_GPIO12_GPIO_IN 0x0
#define WM8350_GPIO12_GPIO_OUT 0x0
#define WM8350_GPIO12_ISINKE_OUT 0x1
#define WM8350_GPIO12_LINE_GT_BATT_OUT 0x2
#define WM8350_GPIO12_LINE_EN_OUT 0x3
#define WM8350_GPIO12_32KHZ_OUT 0x4
#define WM8350_GPIO_DIR_IN 0
#define WM8350_GPIO_DIR_OUT 1
#define WM8350_GPIO_ACTIVE_LOW 0
#define WM8350_GPIO_ACTIVE_HIGH 1
#define WM8350_GPIO_PULL_NONE 0
#define WM8350_GPIO_PULL_UP 1
#define WM8350_GPIO_PULL_DOWN 2
#define WM8350_GPIO_INVERT_OFF 0
#define WM8350_GPIO_INVERT_ON 1
#define WM8350_GPIO_DEBOUNCE_OFF 0
#define WM8350_GPIO_DEBOUNCE_ON 1
/*
* R128 (0x80) - GPIO Debounce
*/
#define WM8350_GP12_DB 0x1000
#define WM8350_GP11_DB 0x0800
#define WM8350_GP10_DB 0x0400
#define WM8350_GP9_DB 0x0200
#define WM8350_GP8_DB 0x0100
#define WM8350_GP7_DB 0x0080
#define WM8350_GP6_DB 0x0040
#define WM8350_GP5_DB 0x0020
#define WM8350_GP4_DB 0x0010
#define WM8350_GP3_DB 0x0008
#define WM8350_GP2_DB 0x0004
#define WM8350_GP1_DB 0x0002
#define WM8350_GP0_DB 0x0001
/*
* R129 (0x81) - GPIO Pin pull up Control
*/
#define WM8350_GP12_PU 0x1000
#define WM8350_GP11_PU 0x0800
#define WM8350_GP10_PU 0x0400
#define WM8350_GP9_PU 0x0200
#define WM8350_GP8_PU 0x0100
#define WM8350_GP7_PU 0x0080
#define WM8350_GP6_PU 0x0040
#define WM8350_GP5_PU 0x0020
#define WM8350_GP4_PU 0x0010
#define WM8350_GP3_PU 0x0008
#define WM8350_GP2_PU 0x0004
#define WM8350_GP1_PU 0x0002
#define WM8350_GP0_PU 0x0001
/*
* R130 (0x82) - GPIO Pull down Control
*/
#define WM8350_GP12_PD 0x1000
#define WM8350_GP11_PD 0x0800
#define WM8350_GP10_PD 0x0400
#define WM8350_GP9_PD 0x0200
#define WM8350_GP8_PD 0x0100
#define WM8350_GP7_PD 0x0080
#define WM8350_GP6_PD 0x0040
#define WM8350_GP5_PD 0x0020
#define WM8350_GP4_PD 0x0010
#define WM8350_GP3_PD 0x0008
#define WM8350_GP2_PD 0x0004
#define WM8350_GP1_PD 0x0002
#define WM8350_GP0_PD 0x0001
/*
* R131 (0x83) - GPIO Interrupt Mode
*/
#define WM8350_GP12_INTMODE 0x1000
#define WM8350_GP11_INTMODE 0x0800
#define WM8350_GP10_INTMODE 0x0400
#define WM8350_GP9_INTMODE 0x0200
#define WM8350_GP8_INTMODE 0x0100
#define WM8350_GP7_INTMODE 0x0080
#define WM8350_GP6_INTMODE 0x0040
#define WM8350_GP5_INTMODE 0x0020
#define WM8350_GP4_INTMODE 0x0010
#define WM8350_GP3_INTMODE 0x0008
#define WM8350_GP2_INTMODE 0x0004
#define WM8350_GP1_INTMODE 0x0002
#define WM8350_GP0_INTMODE 0x0001
/*
* R133 (0x85) - GPIO Control
*/
#define WM8350_GP_DBTIME_MASK 0x00C0
/*
* R134 (0x86) - GPIO Configuration (i/o)
*/
#define WM8350_GP12_DIR 0x1000
#define WM8350_GP11_DIR 0x0800
#define WM8350_GP10_DIR 0x0400
#define WM8350_GP9_DIR 0x0200
#define WM8350_GP8_DIR 0x0100
#define WM8350_GP7_DIR 0x0080
#define WM8350_GP6_DIR 0x0040
#define WM8350_GP5_DIR 0x0020
#define WM8350_GP4_DIR 0x0010
#define WM8350_GP3_DIR 0x0008
#define WM8350_GP2_DIR 0x0004
#define WM8350_GP1_DIR 0x0002
#define WM8350_GP0_DIR 0x0001
/*
* R135 (0x87) - GPIO Pin Polarity / Type
*/
#define WM8350_GP12_CFG 0x1000
#define WM8350_GP11_CFG 0x0800
#define WM8350_GP10_CFG 0x0400
#define WM8350_GP9_CFG 0x0200
#define WM8350_GP8_CFG 0x0100
#define WM8350_GP7_CFG 0x0080
#define WM8350_GP6_CFG 0x0040
#define WM8350_GP5_CFG 0x0020
#define WM8350_GP4_CFG 0x0010
#define WM8350_GP3_CFG 0x0008
#define WM8350_GP2_CFG 0x0004
#define WM8350_GP1_CFG 0x0002
#define WM8350_GP0_CFG 0x0001
/*
* R140 (0x8C) - GPIO Function Select 1
*/
#define WM8350_GP3_FN_MASK 0xF000
#define WM8350_GP2_FN_MASK 0x0F00
#define WM8350_GP1_FN_MASK 0x00F0
#define WM8350_GP0_FN_MASK 0x000F
/*
* R141 (0x8D) - GPIO Function Select 2
*/
#define WM8350_GP7_FN_MASK 0xF000
#define WM8350_GP6_FN_MASK 0x0F00
#define WM8350_GP5_FN_MASK 0x00F0
#define WM8350_GP4_FN_MASK 0x000F
/*
* R142 (0x8E) - GPIO Function Select 3
*/
#define WM8350_GP11_FN_MASK 0xF000
#define WM8350_GP10_FN_MASK 0x0F00
#define WM8350_GP9_FN_MASK 0x00F0
#define WM8350_GP8_FN_MASK 0x000F
/*
* R143 (0x8F) - GPIO Function Select 4
*/
#define WM8350_GP12_FN_MASK 0x000F
/*
* R230 (0xE6) - GPIO Pin Status
*/
#define WM8350_GP12_LVL 0x1000
#define WM8350_GP11_LVL 0x0800
#define WM8350_GP10_LVL 0x0400
#define WM8350_GP9_LVL 0x0200
#define WM8350_GP8_LVL 0x0100
#define WM8350_GP7_LVL 0x0080
#define WM8350_GP6_LVL 0x0040
#define WM8350_GP5_LVL 0x0020
#define WM8350_GP4_LVL 0x0010
#define WM8350_GP3_LVL 0x0008
#define WM8350_GP2_LVL 0x0004
#define WM8350_GP1_LVL 0x0002
#define WM8350_GP0_LVL 0x0001
struct wm8350;
int wm8350_gpio_config(struct wm8350 *wm8350, int gpio, int dir, int func,
int pol, int pull, int invert, int debounce);
struct wm8350_gpio {
struct platform_device *pdev;
};
/*
* GPIO Interrupts
*/
#define WM8350_IRQ_GPIO(x) (50 + x)
#endif

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kernel/include/linux/mfd/wm8350/pmic.h Normal file
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/*
* pmic.h -- Power Managment Driver for Wolfson WM8350 PMIC
*
* Copyright 2007 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_WM8350_PMIC_H
#define __LINUX_MFD_WM8350_PMIC_H
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/regulator/machine.h>
/*
* Register values.
*/
#define WM8350_CURRENT_SINK_DRIVER_A 0xAC
#define WM8350_CSA_FLASH_CONTROL 0xAD
#define WM8350_CURRENT_SINK_DRIVER_B 0xAE
#define WM8350_CSB_FLASH_CONTROL 0xAF
#define WM8350_DCDC_LDO_REQUESTED 0xB0
#define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
#define WM8350_DCDC_SLEEP_OPTIONS 0xB2
#define WM8350_POWER_CHECK_COMPARATOR 0xB3
#define WM8350_DCDC1_CONTROL 0xB4
#define WM8350_DCDC1_TIMEOUTS 0xB5
#define WM8350_DCDC1_LOW_POWER 0xB6
#define WM8350_DCDC2_CONTROL 0xB7
#define WM8350_DCDC2_TIMEOUTS 0xB8
#define WM8350_DCDC3_CONTROL 0xBA
#define WM8350_DCDC3_TIMEOUTS 0xBB
#define WM8350_DCDC3_LOW_POWER 0xBC
#define WM8350_DCDC4_CONTROL 0xBD
#define WM8350_DCDC4_TIMEOUTS 0xBE
#define WM8350_DCDC4_LOW_POWER 0xBF
#define WM8350_DCDC5_CONTROL 0xC0
#define WM8350_DCDC5_TIMEOUTS 0xC1
#define WM8350_DCDC6_CONTROL 0xC3
#define WM8350_DCDC6_TIMEOUTS 0xC4
#define WM8350_DCDC6_LOW_POWER 0xC5
#define WM8350_LIMIT_SWITCH_CONTROL 0xC7
#define WM8350_LDO1_CONTROL 0xC8
#define WM8350_LDO1_TIMEOUTS 0xC9
#define WM8350_LDO1_LOW_POWER 0xCA
#define WM8350_LDO2_CONTROL 0xCB
#define WM8350_LDO2_TIMEOUTS 0xCC
#define WM8350_LDO2_LOW_POWER 0xCD
#define WM8350_LDO3_CONTROL 0xCE
#define WM8350_LDO3_TIMEOUTS 0xCF
#define WM8350_LDO3_LOW_POWER 0xD0
#define WM8350_LDO4_CONTROL 0xD1
#define WM8350_LDO4_TIMEOUTS 0xD2
#define WM8350_LDO4_LOW_POWER 0xD3
#define WM8350_VCC_FAULT_MASKS 0xD7
#define WM8350_MAIN_BANDGAP_CONTROL 0xD8
#define WM8350_OSC_CONTROL 0xD9
#define WM8350_RTC_TICK_CONTROL 0xDA
#define WM8350_SECURITY 0xDB
#define WM8350_RAM_BIST_1 0xDC
#define WM8350_DCDC_LDO_STATUS 0xE1
#define WM8350_GPIO_PIN_STATUS 0xE6
#define WM8350_DCDC1_FORCE_PWM 0xF8
#define WM8350_DCDC3_FORCE_PWM 0xFA
#define WM8350_DCDC4_FORCE_PWM 0xFB
#define WM8350_DCDC6_FORCE_PWM 0xFD
/*
* R172 (0xAC) - Current Sink Driver A
*/
#define WM8350_CS1_HIB_MODE 0x1000
#define WM8350_CS1_HIB_MODE_MASK 0x1000
#define WM8350_CS1_HIB_MODE_SHIFT 12
#define WM8350_CS1_ISEL_MASK 0x003F
#define WM8350_CS1_ISEL_SHIFT 0
/* Bit values for R172 (0xAC) */
#define WM8350_CS1_HIB_MODE_DISABLE 0
#define WM8350_CS1_HIB_MODE_LEAVE 1
#define WM8350_CS1_ISEL_220M 0x3F
/*
* R173 (0xAD) - CSA Flash control
*/
#define WM8350_CS1_FLASH_MODE 0x8000
#define WM8350_CS1_TRIGSRC 0x4000
#define WM8350_CS1_DRIVE 0x2000
#define WM8350_CS1_FLASH_DUR_MASK 0x0300
#define WM8350_CS1_OFF_RAMP_MASK 0x0030
#define WM8350_CS1_ON_RAMP_MASK 0x0003
/*
* R174 (0xAE) - Current Sink Driver B
*/
#define WM8350_CS2_HIB_MODE 0x1000
#define WM8350_CS2_ISEL_MASK 0x003F
/*
* R175 (0xAF) - CSB Flash control
*/
#define WM8350_CS2_FLASH_MODE 0x8000
#define WM8350_CS2_TRIGSRC 0x4000
#define WM8350_CS2_DRIVE 0x2000
#define WM8350_CS2_FLASH_DUR_MASK 0x0300
#define WM8350_CS2_OFF_RAMP_MASK 0x0030
#define WM8350_CS2_ON_RAMP_MASK 0x0003
/*
* R176 (0xB0) - DCDC/LDO requested
*/
#define WM8350_LS_ENA 0x8000
#define WM8350_LDO4_ENA 0x0800
#define WM8350_LDO3_ENA 0x0400
#define WM8350_LDO2_ENA 0x0200
#define WM8350_LDO1_ENA 0x0100
#define WM8350_DC6_ENA 0x0020
#define WM8350_DC5_ENA 0x0010
#define WM8350_DC4_ENA 0x0008
#define WM8350_DC3_ENA 0x0004
#define WM8350_DC2_ENA 0x0002
#define WM8350_DC1_ENA 0x0001
/*
* R177 (0xB1) - DCDC Active options
*/
#define WM8350_PUTO_MASK 0x3000
#define WM8350_PWRUP_DELAY_MASK 0x0300
#define WM8350_DC6_ACTIVE 0x0020
#define WM8350_DC4_ACTIVE 0x0008
#define WM8350_DC3_ACTIVE 0x0004
#define WM8350_DC1_ACTIVE 0x0001
/*
* R178 (0xB2) - DCDC Sleep options
*/
#define WM8350_DC6_SLEEP 0x0020
#define WM8350_DC4_SLEEP 0x0008
#define WM8350_DC3_SLEEP 0x0004
#define WM8350_DC1_SLEEP 0x0001
/*
* R179 (0xB3) - Power-check comparator
*/
#define WM8350_PCCMP_ERRACT 0x4000
#define WM8350_PCCMP_RAIL 0x0100
#define WM8350_PCCMP_OFF_THR_MASK 0x0070
#define WM8350_PCCMP_ON_THR_MASK 0x0007
/*
* R180 (0xB4) - DCDC1 Control
*/
#define WM8350_DC1_OPFLT 0x0400
#define WM8350_DC1_VSEL_MASK 0x007F
#define WM8350_DC1_VSEL_SHIFT 0
/*
* R181 (0xB5) - DCDC1 Timeouts
*/
#define WM8350_DC1_ERRACT_MASK 0xC000
#define WM8350_DC1_ERRACT_SHIFT 14
#define WM8350_DC1_ENSLOT_MASK 0x3C00
#define WM8350_DC1_ENSLOT_SHIFT 10
#define WM8350_DC1_SDSLOT_MASK 0x03C0
#define WM8350_DC1_UVTO_MASK 0x0030
#define WM8350_DC1_SDSLOT_SHIFT 6
/* Bit values for R181 (0xB5) */
#define WM8350_DC1_ERRACT_NONE 0
#define WM8350_DC1_ERRACT_SHUTDOWN_CONV 1
#define WM8350_DC1_ERRACT_SHUTDOWN_SYS 2
/*
* R182 (0xB6) - DCDC1 Low Power
*/
#define WM8350_DC1_HIB_MODE_MASK 0x7000
#define WM8350_DC1_HIB_TRIG_MASK 0x0300
#define WM8350_DC1_VIMG_MASK 0x007F
/*
* R183 (0xB7) - DCDC2 Control
*/
#define WM8350_DC2_MODE 0x4000
#define WM8350_DC2_MODE_MASK 0x4000
#define WM8350_DC2_MODE_SHIFT 14
#define WM8350_DC2_HIB_MODE 0x1000
#define WM8350_DC2_HIB_MODE_MASK 0x1000
#define WM8350_DC2_HIB_MODE_SHIFT 12
#define WM8350_DC2_HIB_TRIG_MASK 0x0300
#define WM8350_DC2_HIB_TRIG_SHIFT 8
#define WM8350_DC2_ILIM 0x0040
#define WM8350_DC2_ILIM_MASK 0x0040
#define WM8350_DC2_ILIM_SHIFT 6
#define WM8350_DC2_RMP_MASK 0x0018
#define WM8350_DC2_RMP_SHIFT 3
#define WM8350_DC2_FBSRC_MASK 0x0003
#define WM8350_DC2_FBSRC_SHIFT 0
/* Bit values for R183 (0xB7) */
#define WM8350_DC2_MODE_BOOST 0
#define WM8350_DC2_MODE_SWITCH 1
#define WM8350_DC2_HIB_MODE_ACTIVE 1
#define WM8350_DC2_HIB_MODE_DISABLE 0
#define WM8350_DC2_HIB_TRIG_NONE 0
#define WM8350_DC2_HIB_TRIG_LPWR1 1
#define WM8350_DC2_HIB_TRIG_LPWR2 2
#define WM8350_DC2_HIB_TRIG_LPWR3 3
#define WM8350_DC2_ILIM_HIGH 0
#define WM8350_DC2_ILIM_LOW 1
#define WM8350_DC2_RMP_30V 0
#define WM8350_DC2_RMP_20V 1
#define WM8350_DC2_RMP_10V 2
#define WM8350_DC2_RMP_5V 3
#define WM8350_DC2_FBSRC_FB2 0
#define WM8350_DC2_FBSRC_ISINKA 1
#define WM8350_DC2_FBSRC_ISINKB 2
#define WM8350_DC2_FBSRC_USB 3
/*
* R184 (0xB8) - DCDC2 Timeouts
*/
#define WM8350_DC2_ERRACT_MASK 0xC000
#define WM8350_DC2_ERRACT_SHIFT 14
#define WM8350_DC2_ENSLOT_MASK 0x3C00
#define WM8350_DC2_ENSLOT_SHIFT 10
#define WM8350_DC2_SDSLOT_MASK 0x03C0
#define WM8350_DC2_UVTO_MASK 0x0030
/* Bit values for R184 (0xB8) */
#define WM8350_DC2_ERRACT_NONE 0
#define WM8350_DC2_ERRACT_SHUTDOWN_CONV 1
#define WM8350_DC2_ERRACT_SHUTDOWN_SYS 2
/*
* R186 (0xBA) - DCDC3 Control
*/
#define WM8350_DC3_OPFLT 0x0400
#define WM8350_DC3_VSEL_MASK 0x007F
#define WM8350_DC3_VSEL_SHIFT 0
/*
* R187 (0xBB) - DCDC3 Timeouts
*/
#define WM8350_DC3_ERRACT_MASK 0xC000
#define WM8350_DC3_ERRACT_SHIFT 14
#define WM8350_DC3_ENSLOT_MASK 0x3C00
#define WM8350_DC3_ENSLOT_SHIFT 10
#define WM8350_DC3_SDSLOT_MASK 0x03C0
#define WM8350_DC3_UVTO_MASK 0x0030
#define WM8350_DC3_SDSLOT_SHIFT 6
/* Bit values for R187 (0xBB) */
#define WM8350_DC3_ERRACT_NONE 0
#define WM8350_DC3_ERRACT_SHUTDOWN_CONV 1
#define WM8350_DC3_ERRACT_SHUTDOWN_SYS 2
/*
* R188 (0xBC) - DCDC3 Low Power
*/
#define WM8350_DC3_HIB_MODE_MASK 0x7000
#define WM8350_DC3_HIB_TRIG_MASK 0x0300
#define WM8350_DC3_VIMG_MASK 0x007F
/*
* R189 (0xBD) - DCDC4 Control
*/
#define WM8350_DC4_OPFLT 0x0400
#define WM8350_DC4_VSEL_MASK 0x007F
#define WM8350_DC4_VSEL_SHIFT 0
/*
* R190 (0xBE) - DCDC4 Timeouts
*/
#define WM8350_DC4_ERRACT_MASK 0xC000
#define WM8350_DC4_ERRACT_SHIFT 14
#define WM8350_DC4_ENSLOT_MASK 0x3C00
#define WM8350_DC4_ENSLOT_SHIFT 10
#define WM8350_DC4_SDSLOT_MASK 0x03C0
#define WM8350_DC4_UVTO_MASK 0x0030
#define WM8350_DC4_SDSLOT_SHIFT 6
/* Bit values for R190 (0xBE) */
#define WM8350_DC4_ERRACT_NONE 0
#define WM8350_DC4_ERRACT_SHUTDOWN_CONV 1
#define WM8350_DC4_ERRACT_SHUTDOWN_SYS 2
/*
* R191 (0xBF) - DCDC4 Low Power
*/
#define WM8350_DC4_HIB_MODE_MASK 0x7000
#define WM8350_DC4_HIB_TRIG_MASK 0x0300
#define WM8350_DC4_VIMG_MASK 0x007F
/*
* R192 (0xC0) - DCDC5 Control
*/
#define WM8350_DC5_MODE 0x4000
#define WM8350_DC5_MODE_MASK 0x4000
#define WM8350_DC5_MODE_SHIFT 14
#define WM8350_DC5_HIB_MODE 0x1000
#define WM8350_DC5_HIB_MODE_MASK 0x1000
#define WM8350_DC5_HIB_MODE_SHIFT 12
#define WM8350_DC5_HIB_TRIG_MASK 0x0300
#define WM8350_DC5_HIB_TRIG_SHIFT 8
#define WM8350_DC5_ILIM 0x0040
#define WM8350_DC5_ILIM_MASK 0x0040
#define WM8350_DC5_ILIM_SHIFT 6
#define WM8350_DC5_RMP_MASK 0x0018
#define WM8350_DC5_RMP_SHIFT 3
#define WM8350_DC5_FBSRC_MASK 0x0003
#define WM8350_DC5_FBSRC_SHIFT 0
/* Bit values for R192 (0xC0) */
#define WM8350_DC5_MODE_BOOST 0
#define WM8350_DC5_MODE_SWITCH 1
#define WM8350_DC5_HIB_MODE_ACTIVE 1
#define WM8350_DC5_HIB_MODE_DISABLE 0
#define WM8350_DC5_HIB_TRIG_NONE 0
#define WM8350_DC5_HIB_TRIG_LPWR1 1
#define WM8350_DC5_HIB_TRIG_LPWR2 2
#define WM8350_DC5_HIB_TRIG_LPWR3 3
#define WM8350_DC5_ILIM_HIGH 0
#define WM8350_DC5_ILIM_LOW 1
#define WM8350_DC5_RMP_30V 0
#define WM8350_DC5_RMP_20V 1
#define WM8350_DC5_RMP_10V 2
#define WM8350_DC5_RMP_5V 3
#define WM8350_DC5_FBSRC_FB2 0
#define WM8350_DC5_FBSRC_ISINKA 1
#define WM8350_DC5_FBSRC_ISINKB 2
#define WM8350_DC5_FBSRC_USB 3
/*
* R193 (0xC1) - DCDC5 Timeouts
*/
#define WM8350_DC5_ERRACT_MASK 0xC000
#define WM8350_DC5_ERRACT_SHIFT 14
#define WM8350_DC5_ENSLOT_MASK 0x3C00
#define WM8350_DC5_ENSLOT_SHIFT 10
#define WM8350_DC5_SDSLOT_MASK 0x03C0
#define WM8350_DC5_UVTO_MASK 0x0030
#define WM8350_DC5_SDSLOT_SHIFT 6
/* Bit values for R193 (0xC1) */
#define WM8350_DC5_ERRACT_NONE 0
#define WM8350_DC5_ERRACT_SHUTDOWN_CONV 1
#define WM8350_DC5_ERRACT_SHUTDOWN_SYS 2
/*
* R195 (0xC3) - DCDC6 Control
*/
#define WM8350_DC6_OPFLT 0x0400
#define WM8350_DC6_VSEL_MASK 0x007F
#define WM8350_DC6_VSEL_SHIFT 0
/*
* R196 (0xC4) - DCDC6 Timeouts
*/
#define WM8350_DC6_ERRACT_MASK 0xC000
#define WM8350_DC6_ERRACT_SHIFT 14
#define WM8350_DC6_ENSLOT_MASK 0x3C00
#define WM8350_DC6_ENSLOT_SHIFT 10
#define WM8350_DC6_SDSLOT_MASK 0x03C0
#define WM8350_DC6_UVTO_MASK 0x0030
#define WM8350_DC6_SDSLOT_SHIFT 6
/* Bit values for R196 (0xC4) */
#define WM8350_DC6_ERRACT_NONE 0
#define WM8350_DC6_ERRACT_SHUTDOWN_CONV 1
#define WM8350_DC6_ERRACT_SHUTDOWN_SYS 2
/*
* R197 (0xC5) - DCDC6 Low Power
*/
#define WM8350_DC6_HIB_MODE_MASK 0x7000
#define WM8350_DC6_HIB_TRIG_MASK 0x0300
#define WM8350_DC6_VIMG_MASK 0x007F
/*
* R199 (0xC7) - Limit Switch Control
*/
#define WM8350_LS_ERRACT_MASK 0xC000
#define WM8350_LS_ERRACT_SHIFT 14
#define WM8350_LS_ENSLOT_MASK 0x3C00
#define WM8350_LS_ENSLOT_SHIFT 10
#define WM8350_LS_SDSLOT_MASK 0x03C0
#define WM8350_LS_SDSLOT_SHIFT 6
#define WM8350_LS_HIB_MODE 0x0010
#define WM8350_LS_HIB_MODE_MASK 0x0010
#define WM8350_LS_HIB_MODE_SHIFT 4
#define WM8350_LS_HIB_PROT 0x0002
#define WM8350_LS_HIB_PROT_MASK 0x0002
#define WM8350_LS_HIB_PROT_SHIFT 1
#define WM8350_LS_PROT 0x0001
#define WM8350_LS_PROT_MASK 0x0001
#define WM8350_LS_PROT_SHIFT 0
/* Bit values for R199 (0xC7) */
#define WM8350_LS_ERRACT_NONE 0
#define WM8350_LS_ERRACT_SHUTDOWN_CONV 1
#define WM8350_LS_ERRACT_SHUTDOWN_SYS 2
/*
* R200 (0xC8) - LDO1 Control
*/
#define WM8350_LDO1_SWI 0x4000
#define WM8350_LDO1_OPFLT 0x0400
#define WM8350_LDO1_VSEL_MASK 0x001F
#define WM8350_LDO1_VSEL_SHIFT 0
/*
* R201 (0xC9) - LDO1 Timeouts
*/
#define WM8350_LDO1_ERRACT_MASK 0xC000
#define WM8350_LDO1_ERRACT_SHIFT 14
#define WM8350_LDO1_ENSLOT_MASK 0x3C00
#define WM8350_LDO1_ENSLOT_SHIFT 10
#define WM8350_LDO1_SDSLOT_MASK 0x03C0
#define WM8350_LDO1_UVTO_MASK 0x0030
#define WM8350_LDO1_SDSLOT_SHIFT 6
/* Bit values for R201 (0xC9) */
#define WM8350_LDO1_ERRACT_NONE 0
#define WM8350_LDO1_ERRACT_SHUTDOWN_CONV 1
#define WM8350_LDO1_ERRACT_SHUTDOWN_SYS 2
/*
* R202 (0xCA) - LDO1 Low Power
*/
#define WM8350_LDO1_HIB_MODE_MASK 0x3000
#define WM8350_LDO1_HIB_TRIG_MASK 0x0300
#define WM8350_LDO1_VIMG_MASK 0x001F
#define WM8350_LDO1_HIB_MODE_DIS (0x1 << 12)
/*
* R203 (0xCB) - LDO2 Control
*/
#define WM8350_LDO2_SWI 0x4000
#define WM8350_LDO2_OPFLT 0x0400
#define WM8350_LDO2_VSEL_MASK 0x001F
#define WM8350_LDO2_VSEL_SHIFT 0
/*
* R204 (0xCC) - LDO2 Timeouts
*/
#define WM8350_LDO2_ERRACT_MASK 0xC000
#define WM8350_LDO2_ERRACT_SHIFT 14
#define WM8350_LDO2_ENSLOT_MASK 0x3C00
#define WM8350_LDO2_ENSLOT_SHIFT 10
#define WM8350_LDO2_SDSLOT_MASK 0x03C0
#define WM8350_LDO2_SDSLOT_SHIFT 6
/* Bit values for R204 (0xCC) */
#define WM8350_LDO2_ERRACT_NONE 0
#define WM8350_LDO2_ERRACT_SHUTDOWN_CONV 1
#define WM8350_LDO2_ERRACT_SHUTDOWN_SYS 2
/*
* R205 (0xCD) - LDO2 Low Power
*/
#define WM8350_LDO2_HIB_MODE_MASK 0x3000
#define WM8350_LDO2_HIB_TRIG_MASK 0x0300
#define WM8350_LDO2_VIMG_MASK 0x001F
/*
* R206 (0xCE) - LDO3 Control
*/
#define WM8350_LDO3_SWI 0x4000
#define WM8350_LDO3_OPFLT 0x0400
#define WM8350_LDO3_VSEL_MASK 0x001F
#define WM8350_LDO3_VSEL_SHIFT 0
/*
* R207 (0xCF) - LDO3 Timeouts
*/
#define WM8350_LDO3_ERRACT_MASK 0xC000
#define WM8350_LDO3_ERRACT_SHIFT 14
#define WM8350_LDO3_ENSLOT_MASK 0x3C00
#define WM8350_LDO3_ENSLOT_SHIFT 10
#define WM8350_LDO3_SDSLOT_MASK 0x03C0
#define WM8350_LDO3_UVTO_MASK 0x0030
#define WM8350_LDO3_SDSLOT_SHIFT 6
/* Bit values for R207 (0xCF) */
#define WM8350_LDO3_ERRACT_NONE 0
#define WM8350_LDO3_ERRACT_SHUTDOWN_CONV 1
#define WM8350_LDO3_ERRACT_SHUTDOWN_SYS 2
/*
* R208 (0xD0) - LDO3 Low Power
*/
#define WM8350_LDO3_HIB_MODE_MASK 0x3000
#define WM8350_LDO3_HIB_TRIG_MASK 0x0300
#define WM8350_LDO3_VIMG_MASK 0x001F
/*
* R209 (0xD1) - LDO4 Control
*/
#define WM8350_LDO4_SWI 0x4000
#define WM8350_LDO4_OPFLT 0x0400
#define WM8350_LDO4_VSEL_MASK 0x001F
#define WM8350_LDO4_VSEL_SHIFT 0
/*
* R210 (0xD2) - LDO4 Timeouts
*/
#define WM8350_LDO4_ERRACT_MASK 0xC000
#define WM8350_LDO4_ERRACT_SHIFT 14
#define WM8350_LDO4_ENSLOT_MASK 0x3C00
#define WM8350_LDO4_ENSLOT_SHIFT 10
#define WM8350_LDO4_SDSLOT_MASK 0x03C0
#define WM8350_LDO4_UVTO_MASK 0x0030
#define WM8350_LDO4_SDSLOT_SHIFT 6
/* Bit values for R210 (0xD2) */
#define WM8350_LDO4_ERRACT_NONE 0
#define WM8350_LDO4_ERRACT_SHUTDOWN_CONV 1
#define WM8350_LDO4_ERRACT_SHUTDOWN_SYS 2
/*
* R211 (0xD3) - LDO4 Low Power
*/
#define WM8350_LDO4_HIB_MODE_MASK 0x3000
#define WM8350_LDO4_HIB_TRIG_MASK 0x0300
#define WM8350_LDO4_VIMG_MASK 0x001F
/*
* R215 (0xD7) - VCC_FAULT Masks
*/
#define WM8350_LS_FAULT 0x8000
#define WM8350_LDO4_FAULT 0x0800
#define WM8350_LDO3_FAULT 0x0400
#define WM8350_LDO2_FAULT 0x0200
#define WM8350_LDO1_FAULT 0x0100
#define WM8350_DC6_FAULT 0x0020
#define WM8350_DC5_FAULT 0x0010
#define WM8350_DC4_FAULT 0x0008
#define WM8350_DC3_FAULT 0x0004
#define WM8350_DC2_FAULT 0x0002
#define WM8350_DC1_FAULT 0x0001
/*
* R216 (0xD8) - Main Bandgap Control
*/
#define WM8350_MBG_LOAD_FUSES 0x8000
#define WM8350_MBG_FUSE_WPREP 0x4000
#define WM8350_MBG_FUSE_WRITE 0x2000
#define WM8350_MBG_FUSE_TRIM_MASK 0x1F00
#define WM8350_MBG_TRIM_SRC 0x0020
#define WM8350_MBG_USER_TRIM_MASK 0x001F
/*
* R217 (0xD9) - OSC Control
*/
#define WM8350_OSC_LOAD_FUSES 0x8000
#define WM8350_OSC_FUSE_WPREP 0x4000
#define WM8350_OSC_FUSE_WRITE 0x2000
#define WM8350_OSC_FUSE_TRIM_MASK 0x0F00
#define WM8350_OSC_TRIM_SRC 0x0020
#define WM8350_OSC_USER_TRIM_MASK 0x000F
/*
* R248 (0xF8) - DCDC1 Force PWM
*/
#define WM8350_DCDC1_FORCE_PWM_ENA 0x0010
/*
* R250 (0xFA) - DCDC3 Force PWM
*/
#define WM8350_DCDC3_FORCE_PWM_ENA 0x0010
/*
* R251 (0xFB) - DCDC4 Force PWM
*/
#define WM8350_DCDC4_FORCE_PWM_ENA 0x0010
/*
* R253 (0xFD) - DCDC1 Force PWM
*/
#define WM8350_DCDC6_FORCE_PWM_ENA 0x0010
/*
* DCDC's
*/
#define WM8350_DCDC_1 0
#define WM8350_DCDC_2 1
#define WM8350_DCDC_3 2
#define WM8350_DCDC_4 3
#define WM8350_DCDC_5 4
#define WM8350_DCDC_6 5
/* DCDC modes */
#define WM8350_DCDC_ACTIVE_STANDBY 0
#define WM8350_DCDC_ACTIVE_PULSE 1
#define WM8350_DCDC_SLEEP_NORMAL 0
#define WM8350_DCDC_SLEEP_LOW 1
/* DCDC Low power (Hibernate) mode */
#define WM8350_DCDC_HIB_MODE_CUR (0 << 12)
#define WM8350_DCDC_HIB_MODE_IMAGE (1 << 12)
#define WM8350_DCDC_HIB_MODE_STANDBY (2 << 12)
#define WM8350_DCDC_HIB_MODE_LDO (4 << 12)
#define WM8350_DCDC_HIB_MODE_LDO_IM (5 << 12)
#define WM8350_DCDC_HIB_MODE_DIS (7 << 12)
#define WM8350_DCDC_HIB_MODE_MASK (7 << 12)
/* DCDC Low Power (Hibernate) signal */
#define WM8350_DCDC_HIB_SIG_REG (0 << 8)
#define WM8350_DCDC_HIB_SIG_LPWR1 (1 << 8)
#define WM8350_DCDC_HIB_SIG_LPWR2 (2 << 8)
#define WM8350_DCDC_HIB_SIG_LPWR3 (3 << 8)
/* LDO Low power (Hibernate) mode */
#define WM8350_LDO_HIB_MODE_IMAGE (0 << 0)
#define WM8350_LDO_HIB_MODE_DIS (1 << 0)
/* LDO Low Power (Hibernate) signal */
#define WM8350_LDO_HIB_SIG_REG (0 << 8)
#define WM8350_LDO_HIB_SIG_LPWR1 (1 << 8)
#define WM8350_LDO_HIB_SIG_LPWR2 (2 << 8)
#define WM8350_LDO_HIB_SIG_LPWR3 (3 << 8)
/*
* LDOs
*/
#define WM8350_LDO_1 6
#define WM8350_LDO_2 7
#define WM8350_LDO_3 8
#define WM8350_LDO_4 9
/*
* ISINKs
*/
#define WM8350_ISINK_A 10
#define WM8350_ISINK_B 11
#define WM8350_ISINK_MODE_BOOST 0
#define WM8350_ISINK_MODE_SWITCH 1
#define WM8350_ISINK_ILIM_NORMAL 0
#define WM8350_ISINK_ILIM_LOW 1
#define WM8350_ISINK_FLASH_DISABLE 0
#define WM8350_ISINK_FLASH_ENABLE 1
#define WM8350_ISINK_FLASH_TRIG_BIT 0
#define WM8350_ISINK_FLASH_TRIG_GPIO 1
#define WM8350_ISINK_FLASH_MODE_EN (1 << 13)
#define WM8350_ISINK_FLASH_MODE_DIS (0 << 13)
#define WM8350_ISINK_FLASH_DUR_32MS (0 << 8)
#define WM8350_ISINK_FLASH_DUR_64MS (1 << 8)
#define WM8350_ISINK_FLASH_DUR_96MS (2 << 8)
#define WM8350_ISINK_FLASH_DUR_1024MS (3 << 8)
#define WM8350_ISINK_FLASH_ON_INSTANT (0 << 0)
#define WM8350_ISINK_FLASH_ON_0_25S (1 << 0)
#define WM8350_ISINK_FLASH_ON_0_50S (2 << 0)
#define WM8350_ISINK_FLASH_ON_1_00S (3 << 0)
#define WM8350_ISINK_FLASH_ON_1_95S (1 << 0)
#define WM8350_ISINK_FLASH_ON_3_91S (2 << 0)
#define WM8350_ISINK_FLASH_ON_7_80S (3 << 0)
#define WM8350_ISINK_FLASH_OFF_INSTANT (0 << 4)
#define WM8350_ISINK_FLASH_OFF_0_25S (1 << 4)
#define WM8350_ISINK_FLASH_OFF_0_50S (2 << 4)
#define WM8350_ISINK_FLASH_OFF_1_00S (3 << 4)
#define WM8350_ISINK_FLASH_OFF_1_95S (1 << 4)
#define WM8350_ISINK_FLASH_OFF_3_91S (2 << 4)
#define WM8350_ISINK_FLASH_OFF_7_80S (3 << 4)
/*
* Regulator Interrupts.
*/
#define WM8350_IRQ_CS1 13
#define WM8350_IRQ_CS2 14
#define WM8350_IRQ_UV_LDO4 25
#define WM8350_IRQ_UV_LDO3 26
#define WM8350_IRQ_UV_LDO2 27
#define WM8350_IRQ_UV_LDO1 28
#define WM8350_IRQ_UV_DC6 29
#define WM8350_IRQ_UV_DC5 30
#define WM8350_IRQ_UV_DC4 31
#define WM8350_IRQ_UV_DC3 32
#define WM8350_IRQ_UV_DC2 33
#define WM8350_IRQ_UV_DC1 34
#define WM8350_IRQ_OC_LS 35
#define NUM_WM8350_REGULATORS 12
struct wm8350;
struct platform_device;
struct regulator_init_data;
/*
* WM8350 LED platform data
*/
struct wm8350_led_platform_data {
const char *name;
const char *default_trigger;
int max_uA;
};
struct wm8350_led {
struct platform_device *pdev;
struct mutex mutex;
struct work_struct work;
spinlock_t value_lock;
enum led_brightness value;
struct led_classdev cdev;
int max_uA_index;
int enabled;
struct regulator *isink;
struct regulator_consumer_supply isink_consumer;
struct regulator_init_data isink_init;
struct regulator *dcdc;
struct regulator_consumer_supply dcdc_consumer;
struct regulator_init_data dcdc_init;
};
struct wm8350_pmic {
/* Number of regulators of each type on this device */
int max_dcdc;
int max_isink;
/* ISINK to DCDC mapping */
int isink_A_dcdc;
int isink_B_dcdc;
/* hibernate configs */
u16 dcdc1_hib_mode;
u16 dcdc3_hib_mode;
u16 dcdc4_hib_mode;
u16 dcdc6_hib_mode;
/* regulator devices */
struct platform_device *pdev[NUM_WM8350_REGULATORS];
/* LED devices */
struct wm8350_led led[2];
};
int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
struct regulator_init_data *initdata);
int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink,
struct wm8350_led_platform_data *pdata);
/*
* Additional DCDC control not supported via regulator API
*/
int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
u16 stop, u16 fault);
int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
u16 ilim, u16 ramp, u16 feedback);
/*
* Additional LDO control not supported via regulator API
*/
int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop);
/*
* Additional ISINK control not supported via regulator API
*/
int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
u16 trigger, u16 duration, u16 on_ramp,
u16 off_ramp, u16 drive);
#endif

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kernel/include/linux/mfd/wm8350/rtc.h Normal file
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/*
* rtc.h -- RTC driver for Wolfson WM8350 PMIC
*
* Copyright 2007 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_WM8350_RTC_H
#define __LINUX_MFD_WM8350_RTC_H
#include <linux/platform_device.h>
/*
* Register values.
*/
#define WM8350_RTC_SECONDS_MINUTES 0x10
#define WM8350_RTC_HOURS_DAY 0x11
#define WM8350_RTC_DATE_MONTH 0x12
#define WM8350_RTC_YEAR 0x13
#define WM8350_ALARM_SECONDS_MINUTES 0x14
#define WM8350_ALARM_HOURS_DAY 0x15
#define WM8350_ALARM_DATE_MONTH 0x16
#define WM8350_RTC_TIME_CONTROL 0x17
/*
* R16 (0x10) - RTC Seconds/Minutes
*/
#define WM8350_RTC_MINS_MASK 0x7F00
#define WM8350_RTC_MINS_SHIFT 8
#define WM8350_RTC_SECS_MASK 0x007F
#define WM8350_RTC_SECS_SHIFT 0
/*
* R17 (0x11) - RTC Hours/Day
*/
#define WM8350_RTC_DAY_MASK 0x0700
#define WM8350_RTC_DAY_SHIFT 8
#define WM8350_RTC_HPM_MASK 0x0020
#define WM8350_RTC_HPM_SHIFT 5
#define WM8350_RTC_HRS_MASK 0x001F
#define WM8350_RTC_HRS_SHIFT 0
/* Bit values for R21 (0x15) */
#define WM8350_RTC_DAY_SUN 1
#define WM8350_RTC_DAY_MON 2
#define WM8350_RTC_DAY_TUE 3
#define WM8350_RTC_DAY_WED 4
#define WM8350_RTC_DAY_THU 5
#define WM8350_RTC_DAY_FRI 6
#define WM8350_RTC_DAY_SAT 7
#define WM8350_RTC_HPM_AM 0
#define WM8350_RTC_HPM_PM 1
/*
* R18 (0x12) - RTC Date/Month
*/
#define WM8350_RTC_MTH_MASK 0x1F00
#define WM8350_RTC_MTH_SHIFT 8
#define WM8350_RTC_DATE_MASK 0x003F
#define WM8350_RTC_DATE_SHIFT 0
/* Bit values for R22 (0x16) */
#define WM8350_RTC_MTH_JAN 1
#define WM8350_RTC_MTH_FEB 2
#define WM8350_RTC_MTH_MAR 3
#define WM8350_RTC_MTH_APR 4
#define WM8350_RTC_MTH_MAY 5
#define WM8350_RTC_MTH_JUN 6
#define WM8350_RTC_MTH_JUL 7
#define WM8350_RTC_MTH_AUG 8
#define WM8350_RTC_MTH_SEP 9
#define WM8350_RTC_MTH_OCT 10
#define WM8350_RTC_MTH_NOV 11
#define WM8350_RTC_MTH_DEC 12
#define WM8350_RTC_MTH_JAN_BCD 0x01
#define WM8350_RTC_MTH_FEB_BCD 0x02
#define WM8350_RTC_MTH_MAR_BCD 0x03
#define WM8350_RTC_MTH_APR_BCD 0x04
#define WM8350_RTC_MTH_MAY_BCD 0x05
#define WM8350_RTC_MTH_JUN_BCD 0x06
#define WM8350_RTC_MTH_JUL_BCD 0x07
#define WM8350_RTC_MTH_AUG_BCD 0x08
#define WM8350_RTC_MTH_SEP_BCD 0x09
#define WM8350_RTC_MTH_OCT_BCD 0x10
#define WM8350_RTC_MTH_NOV_BCD 0x11
#define WM8350_RTC_MTH_DEC_BCD 0x12
/*
* R19 (0x13) - RTC Year
*/
#define WM8350_RTC_YHUNDREDS_MASK 0x3F00
#define WM8350_RTC_YHUNDREDS_SHIFT 8
#define WM8350_RTC_YUNITS_MASK 0x00FF
#define WM8350_RTC_YUNITS_SHIFT 0
/*
* R20 (0x14) - Alarm Seconds/Minutes
*/
#define WM8350_RTC_ALMMINS_MASK 0x7F00
#define WM8350_RTC_ALMMINS_SHIFT 8
#define WM8350_RTC_ALMSECS_MASK 0x007F
#define WM8350_RTC_ALMSECS_SHIFT 0
/* Bit values for R20 (0x14) */
#define WM8350_RTC_ALMMINS_DONT_CARE -1
#define WM8350_RTC_ALMSECS_DONT_CARE -1
/*
* R21 (0x15) - Alarm Hours/Day
*/
#define WM8350_RTC_ALMDAY_MASK 0x0F00
#define WM8350_RTC_ALMDAY_SHIFT 8
#define WM8350_RTC_ALMHPM_MASK 0x0020
#define WM8350_RTC_ALMHPM_SHIFT 5
#define WM8350_RTC_ALMHRS_MASK 0x001F
#define WM8350_RTC_ALMHRS_SHIFT 0
/* Bit values for R21 (0x15) */
#define WM8350_RTC_ALMDAY_DONT_CARE -1
#define WM8350_RTC_ALMDAY_SUN 1
#define WM8350_RTC_ALMDAY_MON 2
#define WM8350_RTC_ALMDAY_TUE 3
#define WM8350_RTC_ALMDAY_WED 4
#define WM8350_RTC_ALMDAY_THU 5
#define WM8350_RTC_ALMDAY_FRI 6
#define WM8350_RTC_ALMDAY_SAT 7
#define WM8350_RTC_ALMHPM_AM 0
#define WM8350_RTC_ALMHPM_PM 1
#define WM8350_RTC_ALMHRS_DONT_CARE -1
/*
* R22 (0x16) - Alarm Date/Month
*/
#define WM8350_RTC_ALMMTH_MASK 0x1F00
#define WM8350_RTC_ALMMTH_SHIFT 8
#define WM8350_RTC_ALMDATE_MASK 0x003F
#define WM8350_RTC_ALMDATE_SHIFT 0
/* Bit values for R22 (0x16) */
#define WM8350_RTC_ALMDATE_DONT_CARE -1
#define WM8350_RTC_ALMMTH_DONT_CARE -1
#define WM8350_RTC_ALMMTH_JAN 1
#define WM8350_RTC_ALMMTH_FEB 2
#define WM8350_RTC_ALMMTH_MAR 3
#define WM8350_RTC_ALMMTH_APR 4
#define WM8350_RTC_ALMMTH_MAY 5
#define WM8350_RTC_ALMMTH_JUN 6
#define WM8350_RTC_ALMMTH_JUL 7
#define WM8350_RTC_ALMMTH_AUG 8
#define WM8350_RTC_ALMMTH_SEP 9
#define WM8350_RTC_ALMMTH_OCT 10
#define WM8350_RTC_ALMMTH_NOV 11
#define WM8350_RTC_ALMMTH_DEC 12
#define WM8350_RTC_ALMMTH_JAN_BCD 0x01
#define WM8350_RTC_ALMMTH_FEB_BCD 0x02
#define WM8350_RTC_ALMMTH_MAR_BCD 0x03
#define WM8350_RTC_ALMMTH_APR_BCD 0x04
#define WM8350_RTC_ALMMTH_MAY_BCD 0x05
#define WM8350_RTC_ALMMTH_JUN_BCD 0x06
#define WM8350_RTC_ALMMTH_JUL_BCD 0x07
#define WM8350_RTC_ALMMTH_AUG_BCD 0x08
#define WM8350_RTC_ALMMTH_SEP_BCD 0x09
#define WM8350_RTC_ALMMTH_OCT_BCD 0x10
#define WM8350_RTC_ALMMTH_NOV_BCD 0x11
#define WM8350_RTC_ALMMTH_DEC_BCD 0x12
/*
* R23 (0x17) - RTC Time Control
*/
#define WM8350_RTC_BCD 0x8000
#define WM8350_RTC_BCD_MASK 0x8000
#define WM8350_RTC_BCD_SHIFT 15
#define WM8350_RTC_12HR 0x4000
#define WM8350_RTC_12HR_MASK 0x4000
#define WM8350_RTC_12HR_SHIFT 14
#define WM8350_RTC_DST 0x2000
#define WM8350_RTC_DST_MASK 0x2000
#define WM8350_RTC_DST_SHIFT 13
#define WM8350_RTC_SET 0x0800
#define WM8350_RTC_SET_MASK 0x0800
#define WM8350_RTC_SET_SHIFT 11
#define WM8350_RTC_STS 0x0400
#define WM8350_RTC_STS_MASK 0x0400
#define WM8350_RTC_STS_SHIFT 10
#define WM8350_RTC_ALMSET 0x0200
#define WM8350_RTC_ALMSET_MASK 0x0200
#define WM8350_RTC_ALMSET_SHIFT 9
#define WM8350_RTC_ALMSTS 0x0100
#define WM8350_RTC_ALMSTS_MASK 0x0100
#define WM8350_RTC_ALMSTS_SHIFT 8
#define WM8350_RTC_PINT 0x0070
#define WM8350_RTC_PINT_MASK 0x0070
#define WM8350_RTC_PINT_SHIFT 4
#define WM8350_RTC_DSW 0x000F
#define WM8350_RTC_DSW_MASK 0x000F
#define WM8350_RTC_DSW_SHIFT 0
/* Bit values for R23 (0x17) */
#define WM8350_RTC_BCD_BINARY 0
#define WM8350_RTC_BCD_BCD 1
#define WM8350_RTC_12HR_24HR 0
#define WM8350_RTC_12HR_12HR 1
#define WM8350_RTC_DST_DISABLED 0
#define WM8350_RTC_DST_ENABLED 1
#define WM8350_RTC_SET_RUN 0
#define WM8350_RTC_SET_SET 1
#define WM8350_RTC_STS_RUNNING 0
#define WM8350_RTC_STS_STOPPED 1
#define WM8350_RTC_ALMSET_RUN 0
#define WM8350_RTC_ALMSET_SET 1
#define WM8350_RTC_ALMSTS_RUNNING 0
#define WM8350_RTC_ALMSTS_STOPPED 1
#define WM8350_RTC_PINT_DISABLED 0
#define WM8350_RTC_PINT_SECS 1
#define WM8350_RTC_PINT_MINS 2
#define WM8350_RTC_PINT_HRS 3
#define WM8350_RTC_PINT_DAYS 4
#define WM8350_RTC_PINT_MTHS 5
#define WM8350_RTC_DSW_DISABLED 0
#define WM8350_RTC_DSW_1HZ 1
#define WM8350_RTC_DSW_2HZ 2
#define WM8350_RTC_DSW_4HZ 3
#define WM8350_RTC_DSW_8HZ 4
#define WM8350_RTC_DSW_16HZ 5
#define WM8350_RTC_DSW_32HZ 6
#define WM8350_RTC_DSW_64HZ 7
#define WM8350_RTC_DSW_128HZ 8
#define WM8350_RTC_DSW_256HZ 9
#define WM8350_RTC_DSW_512HZ 10
#define WM8350_RTC_DSW_1024HZ 11
/*
* R218 (0xDA) - RTC Tick Control
*/
#define WM8350_RTC_TICKSTS 0x4000
#define WM8350_RTC_CLKSRC 0x2000
#define WM8350_RTC_TRIM_MASK 0x03FF
/*
* RTC Interrupts.
*/
#define WM8350_IRQ_RTC_PER 7
#define WM8350_IRQ_RTC_SEC 8
#define WM8350_IRQ_RTC_ALM 9
struct wm8350_rtc {
struct platform_device *pdev;
struct rtc_device *rtc;
int alarm_enabled; /* used over suspend/resume */
};
#endif

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kernel/include/linux/mfd/wm8350/supply.h Normal file
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/*
* supply.h -- Power Supply Driver for Wolfson WM8350 PMIC
*
* Copyright 2007 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_WM8350_SUPPLY_H_
#define __LINUX_MFD_WM8350_SUPPLY_H_
#include <linux/mutex.h>
#include <linux/power_supply.h>
/*
* Charger registers
*/
#define WM8350_BATTERY_CHARGER_CONTROL_1 0xA8
#define WM8350_BATTERY_CHARGER_CONTROL_2 0xA9
#define WM8350_BATTERY_CHARGER_CONTROL_3 0xAA
/*
* R168 (0xA8) - Battery Charger Control 1
*/
#define WM8350_CHG_ENA_R168 0x8000
#define WM8350_CHG_THR 0x2000
#define WM8350_CHG_EOC_SEL_MASK 0x1C00
#define WM8350_CHG_TRICKLE_TEMP_CHOKE 0x0200
#define WM8350_CHG_TRICKLE_USB_CHOKE 0x0100
#define WM8350_CHG_RECOVER_T 0x0080
#define WM8350_CHG_END_ACT 0x0040
#define WM8350_CHG_FAST 0x0020
#define WM8350_CHG_FAST_USB_THROTTLE 0x0010
#define WM8350_CHG_NTC_MON 0x0008
#define WM8350_CHG_BATT_HOT_MON 0x0004
#define WM8350_CHG_BATT_COLD_MON 0x0002
#define WM8350_CHG_CHIP_TEMP_MON 0x0001
/*
* R169 (0xA9) - Battery Charger Control 2
*/
#define WM8350_CHG_ACTIVE 0x8000
#define WM8350_CHG_PAUSE 0x4000
#define WM8350_CHG_STS_MASK 0x3000
#define WM8350_CHG_TIME_MASK 0x0F00
#define WM8350_CHG_MASK_WALL_FB 0x0080
#define WM8350_CHG_TRICKLE_SEL 0x0040
#define WM8350_CHG_VSEL_MASK 0x0030
#define WM8350_CHG_ISEL_MASK 0x000F
#define WM8350_CHG_STS_OFF 0x0000
#define WM8350_CHG_STS_TRICKLE 0x1000
#define WM8350_CHG_STS_FAST 0x2000
/*
* R170 (0xAA) - Battery Charger Control 3
*/
#define WM8350_CHG_THROTTLE_T_MASK 0x0060
#define WM8350_CHG_SMART 0x0010
#define WM8350_CHG_TIMER_ADJT_MASK 0x000F
/*
* Charger Interrupts
*/
#define WM8350_IRQ_CHG_BAT_HOT 0
#define WM8350_IRQ_CHG_BAT_COLD 1
#define WM8350_IRQ_CHG_BAT_FAIL 2
#define WM8350_IRQ_CHG_TO 3
#define WM8350_IRQ_CHG_END 4
#define WM8350_IRQ_CHG_START 5
#define WM8350_IRQ_CHG_FAST_RDY 6
#define WM8350_IRQ_CHG_VBATT_LT_3P9 10
#define WM8350_IRQ_CHG_VBATT_LT_3P1 11
#define WM8350_IRQ_CHG_VBATT_LT_2P85 12
/*
* Charger Policy
*/
#define WM8350_CHG_TRICKLE_50mA (0 << 6)
#define WM8350_CHG_TRICKLE_100mA (1 << 6)
#define WM8350_CHG_4_05V (0 << 4)
#define WM8350_CHG_4_10V (1 << 4)
#define WM8350_CHG_4_15V (2 << 4)
#define WM8350_CHG_4_20V (3 << 4)
#define WM8350_CHG_FAST_LIMIT_mA(x) ((x / 50) & 0xf)
#define WM8350_CHG_EOC_mA(x) (((x - 10) & 0x7) << 10)
#define WM8350_CHG_TRICKLE_3_1V (0 << 13)
#define WM8350_CHG_TRICKLE_3_9V (1 << 13)
/*
* Supply Registers.
*/
#define WM8350_USB_VOLTAGE_READBACK 0x9C
#define WM8350_LINE_VOLTAGE_READBACK 0x9D
#define WM8350_BATT_VOLTAGE_READBACK 0x9E
/*
* Supply Interrupts.
*/
#define WM8350_IRQ_USB_LIMIT 15
#define WM8350_IRQ_EXT_USB_FB 36
#define WM8350_IRQ_EXT_WALL_FB 37
#define WM8350_IRQ_EXT_BAT_FB 38
/*
* Policy to control charger state machine.
*/
struct wm8350_charger_policy {
/* charger state machine policy - set in machine driver */
int eoc_mA; /* end of charge current (mA) */
int charge_mV; /* charge voltage */
int fast_limit_mA; /* fast charge current limit */
int fast_limit_USB_mA; /* USB fast charge current limit */
int charge_timeout; /* charge timeout (mins) */
int trickle_start_mV; /* trickle charge starts at mV */
int trickle_charge_mA; /* trickle charge current */
int trickle_charge_USB_mA; /* USB trickle charge current */
};
struct wm8350_power {
struct platform_device *pdev;
struct power_supply battery;
struct power_supply usb;
struct power_supply ac;
struct wm8350_charger_policy *policy;
int rev_g_coeff;
};
#endif

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kernel/include/linux/mfd/wm8350/wdt.h Normal file
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/*
* wdt.h -- Watchdog Driver for Wolfson WM8350 PMIC
*
* Copyright 2007, 2008 Wolfson Microelectronics PLC
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_WM8350_WDT_H_
#define __LINUX_MFD_WM8350_WDT_H_
#include <linux/platform_device.h>
#define WM8350_WDOG_HIB_MODE 0x0080
#define WM8350_WDOG_DEBUG 0x0040
#define WM8350_WDOG_MODE_MASK 0x0030
#define WM8350_WDOG_TO_MASK 0x0007
#define WM8350_IRQ_SYS_WDOG_TO 24
struct wm8350_wdt {
struct platform_device *pdev;
};
#endif

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/*
* wm8400 private definitions.
*
* Copyright 2008 Wolfson Microelectronics plc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __LINUX_MFD_WM8400_PRIV_H
#define __LINUX_MFD_WM8400_PRIV_H
#include <linux/mfd/wm8400.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#define WM8400_REGISTER_COUNT 0x55
struct wm8400 {
struct device *dev;
int (*read_dev)(void *data, char reg, int count, u16 *dst);
int (*write_dev)(void *data, char reg, int count, const u16 *src);
struct mutex io_lock;
void *io_data;
u16 reg_cache[WM8400_REGISTER_COUNT];
struct platform_device regulators[6];
};
/*
* Register values.
*/
#define WM8400_RESET_ID 0x00
#define WM8400_ID 0x01
#define WM8400_POWER_MANAGEMENT_1 0x02
#define WM8400_POWER_MANAGEMENT_2 0x03
#define WM8400_POWER_MANAGEMENT_3 0x04
#define WM8400_AUDIO_INTERFACE_1 0x05
#define WM8400_AUDIO_INTERFACE_2 0x06
#define WM8400_CLOCKING_1 0x07
#define WM8400_CLOCKING_2 0x08
#define WM8400_AUDIO_INTERFACE_3 0x09
#define WM8400_AUDIO_INTERFACE_4 0x0A
#define WM8400_DAC_CTRL 0x0B
#define WM8400_LEFT_DAC_DIGITAL_VOLUME 0x0C
#define WM8400_RIGHT_DAC_DIGITAL_VOLUME 0x0D
#define WM8400_DIGITAL_SIDE_TONE 0x0E
#define WM8400_ADC_CTRL 0x0F
#define WM8400_LEFT_ADC_DIGITAL_VOLUME 0x10
#define WM8400_RIGHT_ADC_DIGITAL_VOLUME 0x11
#define WM8400_GPIO_CTRL_1 0x12
#define WM8400_GPIO1_GPIO2 0x13
#define WM8400_GPIO3_GPIO4 0x14
#define WM8400_GPIO5_GPIO6 0x15
#define WM8400_GPIOCTRL_2 0x16
#define WM8400_GPIO_POL 0x17
#define WM8400_LEFT_LINE_INPUT_1_2_VOLUME 0x18
#define WM8400_LEFT_LINE_INPUT_3_4_VOLUME 0x19
#define WM8400_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A
#define WM8400_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B
#define WM8400_LEFT_OUTPUT_VOLUME 0x1C
#define WM8400_RIGHT_OUTPUT_VOLUME 0x1D
#define WM8400_LINE_OUTPUTS_VOLUME 0x1E
#define WM8400_OUT3_4_VOLUME 0x1F
#define WM8400_LEFT_OPGA_VOLUME 0x20
#define WM8400_RIGHT_OPGA_VOLUME 0x21
#define WM8400_SPEAKER_VOLUME 0x22
#define WM8400_CLASSD1 0x23
#define WM8400_CLASSD3 0x25
#define WM8400_INPUT_MIXER1 0x27
#define WM8400_INPUT_MIXER2 0x28
#define WM8400_INPUT_MIXER3 0x29
#define WM8400_INPUT_MIXER4 0x2A
#define WM8400_INPUT_MIXER5 0x2B
#define WM8400_INPUT_MIXER6 0x2C
#define WM8400_OUTPUT_MIXER1 0x2D
#define WM8400_OUTPUT_MIXER2 0x2E
#define WM8400_OUTPUT_MIXER3 0x2F
#define WM8400_OUTPUT_MIXER4 0x30
#define WM8400_OUTPUT_MIXER5 0x31
#define WM8400_OUTPUT_MIXER6 0x32
#define WM8400_OUT3_4_MIXER 0x33
#define WM8400_LINE_MIXER1 0x34
#define WM8400_LINE_MIXER2 0x35
#define WM8400_SPEAKER_MIXER 0x36
#define WM8400_ADDITIONAL_CONTROL 0x37
#define WM8400_ANTIPOP1 0x38
#define WM8400_ANTIPOP2 0x39
#define WM8400_MICBIAS 0x3A
#define WM8400_FLL_CONTROL_1 0x3C
#define WM8400_FLL_CONTROL_2 0x3D
#define WM8400_FLL_CONTROL_3 0x3E
#define WM8400_FLL_CONTROL_4 0x3F
#define WM8400_LDO1_CONTROL 0x41
#define WM8400_LDO2_CONTROL 0x42
#define WM8400_LDO3_CONTROL 0x43
#define WM8400_LDO4_CONTROL 0x44
#define WM8400_DCDC1_CONTROL_1 0x46
#define WM8400_DCDC1_CONTROL_2 0x47
#define WM8400_DCDC2_CONTROL_1 0x48
#define WM8400_DCDC2_CONTROL_2 0x49
#define WM8400_INTERFACE 0x4B
#define WM8400_PM_GENERAL 0x4C
#define WM8400_PM_SHUTDOWN_CONTROL 0x4E
#define WM8400_INTERRUPT_STATUS_1 0x4F
#define WM8400_INTERRUPT_STATUS_1_MASK 0x50
#define WM8400_INTERRUPT_LEVELS 0x51
#define WM8400_SHUTDOWN_REASON 0x52
#define WM8400_LINE_CIRCUITS 0x54
/*
* Field Definitions.
*/
/*
* R0 (0x00) - Reset/ID
*/
#define WM8400_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET/CHIP_ID - [15:0] */
#define WM8400_SW_RESET_CHIP_ID_SHIFT 0 /* SW_RESET/CHIP_ID - [15:0] */
#define WM8400_SW_RESET_CHIP_ID_WIDTH 16 /* SW_RESET/CHIP_ID - [15:0] */
/*
* R1 (0x01) - ID
*/
#define WM8400_CHIP_REV_MASK 0x7000 /* CHIP_REV - [14:12] */
#define WM8400_CHIP_REV_SHIFT 12 /* CHIP_REV - [14:12] */
#define WM8400_CHIP_REV_WIDTH 3 /* CHIP_REV - [14:12] */
/*
* R18 (0x12) - GPIO CTRL 1
*/
#define WM8400_IRQ 0x1000 /* IRQ */
#define WM8400_IRQ_MASK 0x1000 /* IRQ */
#define WM8400_IRQ_SHIFT 12 /* IRQ */
#define WM8400_IRQ_WIDTH 1 /* IRQ */
#define WM8400_TEMPOK 0x0800 /* TEMPOK */
#define WM8400_TEMPOK_MASK 0x0800 /* TEMPOK */
#define WM8400_TEMPOK_SHIFT 11 /* TEMPOK */
#define WM8400_TEMPOK_WIDTH 1 /* TEMPOK */
#define WM8400_MIC1SHRT 0x0400 /* MIC1SHRT */
#define WM8400_MIC1SHRT_MASK 0x0400 /* MIC1SHRT */
#define WM8400_MIC1SHRT_SHIFT 10 /* MIC1SHRT */
#define WM8400_MIC1SHRT_WIDTH 1 /* MIC1SHRT */
#define WM8400_MIC1DET 0x0200 /* MIC1DET */
#define WM8400_MIC1DET_MASK 0x0200 /* MIC1DET */
#define WM8400_MIC1DET_SHIFT 9 /* MIC1DET */
#define WM8400_MIC1DET_WIDTH 1 /* MIC1DET */
#define WM8400_FLL_LCK 0x0100 /* FLL_LCK */
#define WM8400_FLL_LCK_MASK 0x0100 /* FLL_LCK */
#define WM8400_FLL_LCK_SHIFT 8 /* FLL_LCK */
#define WM8400_FLL_LCK_WIDTH 1 /* FLL_LCK */
#define WM8400_GPIO_STATUS_MASK 0x00FF /* GPIO_STATUS - [7:0] */
#define WM8400_GPIO_STATUS_SHIFT 0 /* GPIO_STATUS - [7:0] */
#define WM8400_GPIO_STATUS_WIDTH 8 /* GPIO_STATUS - [7:0] */
/*
* R19 (0x13) - GPIO1 & GPIO2
*/
#define WM8400_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */
#define WM8400_GPIO2_DEB_ENA_MASK 0x8000 /* GPIO2_DEB_ENA */
#define WM8400_GPIO2_DEB_ENA_SHIFT 15 /* GPIO2_DEB_ENA */
#define WM8400_GPIO2_DEB_ENA_WIDTH 1 /* GPIO2_DEB_ENA */
#define WM8400_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */
#define WM8400_GPIO2_IRQ_ENA_MASK 0x4000 /* GPIO2_IRQ_ENA */
#define WM8400_GPIO2_IRQ_ENA_SHIFT 14 /* GPIO2_IRQ_ENA */
#define WM8400_GPIO2_IRQ_ENA_WIDTH 1 /* GPIO2_IRQ_ENA */
#define WM8400_GPIO2_PU 0x2000 /* GPIO2_PU */
#define WM8400_GPIO2_PU_MASK 0x2000 /* GPIO2_PU */
#define WM8400_GPIO2_PU_SHIFT 13 /* GPIO2_PU */
#define WM8400_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
#define WM8400_GPIO2_PD 0x1000 /* GPIO2_PD */
#define WM8400_GPIO2_PD_MASK 0x1000 /* GPIO2_PD */
#define WM8400_GPIO2_PD_SHIFT 12 /* GPIO2_PD */
#define WM8400_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
#define WM8400_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */
#define WM8400_GPIO2_SEL_SHIFT 8 /* GPIO2_SEL - [11:8] */
#define WM8400_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [11:8] */
#define WM8400_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */
#define WM8400_GPIO1_DEB_ENA_MASK 0x0080 /* GPIO1_DEB_ENA */
#define WM8400_GPIO1_DEB_ENA_SHIFT 7 /* GPIO1_DEB_ENA */
#define WM8400_GPIO1_DEB_ENA_WIDTH 1 /* GPIO1_DEB_ENA */
#define WM8400_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */
#define WM8400_GPIO1_IRQ_ENA_MASK 0x0040 /* GPIO1_IRQ_ENA */
#define WM8400_GPIO1_IRQ_ENA_SHIFT 6 /* GPIO1_IRQ_ENA */
#define WM8400_GPIO1_IRQ_ENA_WIDTH 1 /* GPIO1_IRQ_ENA */
#define WM8400_GPIO1_PU 0x0020 /* GPIO1_PU */
#define WM8400_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
#define WM8400_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
#define WM8400_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
#define WM8400_GPIO1_PD 0x0010 /* GPIO1_PD */
#define WM8400_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
#define WM8400_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
#define WM8400_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
#define WM8400_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
#define WM8400_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
#define WM8400_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
/*
* R20 (0x14) - GPIO3 & GPIO4
*/
#define WM8400_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */
#define WM8400_GPIO4_DEB_ENA_MASK 0x8000 /* GPIO4_DEB_ENA */
#define WM8400_GPIO4_DEB_ENA_SHIFT 15 /* GPIO4_DEB_ENA */
#define WM8400_GPIO4_DEB_ENA_WIDTH 1 /* GPIO4_DEB_ENA */
#define WM8400_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */
#define WM8400_GPIO4_IRQ_ENA_MASK 0x4000 /* GPIO4_IRQ_ENA */
#define WM8400_GPIO4_IRQ_ENA_SHIFT 14 /* GPIO4_IRQ_ENA */
#define WM8400_GPIO4_IRQ_ENA_WIDTH 1 /* GPIO4_IRQ_ENA */
#define WM8400_GPIO4_PU 0x2000 /* GPIO4_PU */
#define WM8400_GPIO4_PU_MASK 0x2000 /* GPIO4_PU */
#define WM8400_GPIO4_PU_SHIFT 13 /* GPIO4_PU */
#define WM8400_GPIO4_PU_WIDTH 1 /* GPIO4_PU */
#define WM8400_GPIO4_PD 0x1000 /* GPIO4_PD */
#define WM8400_GPIO4_PD_MASK 0x1000 /* GPIO4_PD */
#define WM8400_GPIO4_PD_SHIFT 12 /* GPIO4_PD */
#define WM8400_GPIO4_PD_WIDTH 1 /* GPIO4_PD */
#define WM8400_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */
#define WM8400_GPIO4_SEL_SHIFT 8 /* GPIO4_SEL - [11:8] */
#define WM8400_GPIO4_SEL_WIDTH 4 /* GPIO4_SEL - [11:8] */
#define WM8400_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */
#define WM8400_GPIO3_DEB_ENA_MASK 0x0080 /* GPIO3_DEB_ENA */
#define WM8400_GPIO3_DEB_ENA_SHIFT 7 /* GPIO3_DEB_ENA */
#define WM8400_GPIO3_DEB_ENA_WIDTH 1 /* GPIO3_DEB_ENA */
#define WM8400_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */
#define WM8400_GPIO3_IRQ_ENA_MASK 0x0040 /* GPIO3_IRQ_ENA */
#define WM8400_GPIO3_IRQ_ENA_SHIFT 6 /* GPIO3_IRQ_ENA */
#define WM8400_GPIO3_IRQ_ENA_WIDTH 1 /* GPIO3_IRQ_ENA */
#define WM8400_GPIO3_PU 0x0020 /* GPIO3_PU */
#define WM8400_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
#define WM8400_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
#define WM8400_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
#define WM8400_GPIO3_PD 0x0010 /* GPIO3_PD */
#define WM8400_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
#define WM8400_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
#define WM8400_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
#define WM8400_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
#define WM8400_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
#define WM8400_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
/*
* R21 (0x15) - GPIO5 & GPIO6
*/
#define WM8400_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */
#define WM8400_GPIO6_DEB_ENA_MASK 0x8000 /* GPIO6_DEB_ENA */
#define WM8400_GPIO6_DEB_ENA_SHIFT 15 /* GPIO6_DEB_ENA */
#define WM8400_GPIO6_DEB_ENA_WIDTH 1 /* GPIO6_DEB_ENA */
#define WM8400_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */
#define WM8400_GPIO6_IRQ_ENA_MASK 0x4000 /* GPIO6_IRQ_ENA */
#define WM8400_GPIO6_IRQ_ENA_SHIFT 14 /* GPIO6_IRQ_ENA */
#define WM8400_GPIO6_IRQ_ENA_WIDTH 1 /* GPIO6_IRQ_ENA */
#define WM8400_GPIO6_PU 0x2000 /* GPIO6_PU */
#define WM8400_GPIO6_PU_MASK 0x2000 /* GPIO6_PU */
#define WM8400_GPIO6_PU_SHIFT 13 /* GPIO6_PU */
#define WM8400_GPIO6_PU_WIDTH 1 /* GPIO6_PU */
#define WM8400_GPIO6_PD 0x1000 /* GPIO6_PD */
#define WM8400_GPIO6_PD_MASK 0x1000 /* GPIO6_PD */
#define WM8400_GPIO6_PD_SHIFT 12 /* GPIO6_PD */
#define WM8400_GPIO6_PD_WIDTH 1 /* GPIO6_PD */
#define WM8400_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */
#define WM8400_GPIO6_SEL_SHIFT 8 /* GPIO6_SEL - [11:8] */
#define WM8400_GPIO6_SEL_WIDTH 4 /* GPIO6_SEL - [11:8] */
#define WM8400_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */
#define WM8400_GPIO5_DEB_ENA_MASK 0x0080 /* GPIO5_DEB_ENA */
#define WM8400_GPIO5_DEB_ENA_SHIFT 7 /* GPIO5_DEB_ENA */
#define WM8400_GPIO5_DEB_ENA_WIDTH 1 /* GPIO5_DEB_ENA */
#define WM8400_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */
#define WM8400_GPIO5_IRQ_ENA_MASK 0x0040 /* GPIO5_IRQ_ENA */
#define WM8400_GPIO5_IRQ_ENA_SHIFT 6 /* GPIO5_IRQ_ENA */
#define WM8400_GPIO5_IRQ_ENA_WIDTH 1 /* GPIO5_IRQ_ENA */
#define WM8400_GPIO5_PU 0x0020 /* GPIO5_PU */
#define WM8400_GPIO5_PU_MASK 0x0020 /* GPIO5_PU */
#define WM8400_GPIO5_PU_SHIFT 5 /* GPIO5_PU */
#define WM8400_GPIO5_PU_WIDTH 1 /* GPIO5_PU */
#define WM8400_GPIO5_PD 0x0010 /* GPIO5_PD */
#define WM8400_GPIO5_PD_MASK 0x0010 /* GPIO5_PD */
#define WM8400_GPIO5_PD_SHIFT 4 /* GPIO5_PD */
#define WM8400_GPIO5_PD_WIDTH 1 /* GPIO5_PD */
#define WM8400_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */
#define WM8400_GPIO5_SEL_SHIFT 0 /* GPIO5_SEL - [3:0] */
#define WM8400_GPIO5_SEL_WIDTH 4 /* GPIO5_SEL - [3:0] */
/*
* R22 (0x16) - GPIOCTRL 2
*/
#define WM8400_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */
#define WM8400_TEMPOK_IRQ_ENA_MASK 0x0800 /* TEMPOK_IRQ_ENA */
#define WM8400_TEMPOK_IRQ_ENA_SHIFT 11 /* TEMPOK_IRQ_ENA */
#define WM8400_TEMPOK_IRQ_ENA_WIDTH 1 /* TEMPOK_IRQ_ENA */
#define WM8400_MIC1SHRT_IRQ_ENA 0x0400 /* MIC1SHRT_IRQ_ENA */
#define WM8400_MIC1SHRT_IRQ_ENA_MASK 0x0400 /* MIC1SHRT_IRQ_ENA */
#define WM8400_MIC1SHRT_IRQ_ENA_SHIFT 10 /* MIC1SHRT_IRQ_ENA */
#define WM8400_MIC1SHRT_IRQ_ENA_WIDTH 1 /* MIC1SHRT_IRQ_ENA */
#define WM8400_MIC1DET_IRQ_ENA 0x0200 /* MIC1DET_IRQ_ENA */
#define WM8400_MIC1DET_IRQ_ENA_MASK 0x0200 /* MIC1DET_IRQ_ENA */
#define WM8400_MIC1DET_IRQ_ENA_SHIFT 9 /* MIC1DET_IRQ_ENA */
#define WM8400_MIC1DET_IRQ_ENA_WIDTH 1 /* MIC1DET_IRQ_ENA */
#define WM8400_FLL_LCK_IRQ_ENA 0x0100 /* FLL_LCK_IRQ_ENA */
#define WM8400_FLL_LCK_IRQ_ENA_MASK 0x0100 /* FLL_LCK_IRQ_ENA */
#define WM8400_FLL_LCK_IRQ_ENA_SHIFT 8 /* FLL_LCK_IRQ_ENA */
#define WM8400_FLL_LCK_IRQ_ENA_WIDTH 1 /* FLL_LCK_IRQ_ENA */
#define WM8400_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */
#define WM8400_GPI8_DEB_ENA_MASK 0x0080 /* GPI8_DEB_ENA */
#define WM8400_GPI8_DEB_ENA_SHIFT 7 /* GPI8_DEB_ENA */
#define WM8400_GPI8_DEB_ENA_WIDTH 1 /* GPI8_DEB_ENA */
#define WM8400_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */
#define WM8400_GPI8_IRQ_ENA_MASK 0x0040 /* GPI8_IRQ_ENA */
#define WM8400_GPI8_IRQ_ENA_SHIFT 6 /* GPI8_IRQ_ENA */
#define WM8400_GPI8_IRQ_ENA_WIDTH 1 /* GPI8_IRQ_ENA */
#define WM8400_GPI8_ENA 0x0010 /* GPI8_ENA */
#define WM8400_GPI8_ENA_MASK 0x0010 /* GPI8_ENA */
#define WM8400_GPI8_ENA_SHIFT 4 /* GPI8_ENA */
#define WM8400_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
#define WM8400_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */
#define WM8400_GPI7_DEB_ENA_MASK 0x0008 /* GPI7_DEB_ENA */
#define WM8400_GPI7_DEB_ENA_SHIFT 3 /* GPI7_DEB_ENA */
#define WM8400_GPI7_DEB_ENA_WIDTH 1 /* GPI7_DEB_ENA */
#define WM8400_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */
#define WM8400_GPI7_IRQ_ENA_MASK 0x0004 /* GPI7_IRQ_ENA */
#define WM8400_GPI7_IRQ_ENA_SHIFT 2 /* GPI7_IRQ_ENA */
#define WM8400_GPI7_IRQ_ENA_WIDTH 1 /* GPI7_IRQ_ENA */
#define WM8400_GPI7_ENA 0x0001 /* GPI7_ENA */
#define WM8400_GPI7_ENA_MASK 0x0001 /* GPI7_ENA */
#define WM8400_GPI7_ENA_SHIFT 0 /* GPI7_ENA */
#define WM8400_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
/*
* R23 (0x17) - GPIO_POL
*/
#define WM8400_IRQ_INV 0x1000 /* IRQ_INV */
#define WM8400_IRQ_INV_MASK 0x1000 /* IRQ_INV */
#define WM8400_IRQ_INV_SHIFT 12 /* IRQ_INV */
#define WM8400_IRQ_INV_WIDTH 1 /* IRQ_INV */
#define WM8400_TEMPOK_POL 0x0800 /* TEMPOK_POL */
#define WM8400_TEMPOK_POL_MASK 0x0800 /* TEMPOK_POL */
#define WM8400_TEMPOK_POL_SHIFT 11 /* TEMPOK_POL */
#define WM8400_TEMPOK_POL_WIDTH 1 /* TEMPOK_POL */
#define WM8400_MIC1SHRT_POL 0x0400 /* MIC1SHRT_POL */
#define WM8400_MIC1SHRT_POL_MASK 0x0400 /* MIC1SHRT_POL */
#define WM8400_MIC1SHRT_POL_SHIFT 10 /* MIC1SHRT_POL */
#define WM8400_MIC1SHRT_POL_WIDTH 1 /* MIC1SHRT_POL */
#define WM8400_MIC1DET_POL 0x0200 /* MIC1DET_POL */
#define WM8400_MIC1DET_POL_MASK 0x0200 /* MIC1DET_POL */
#define WM8400_MIC1DET_POL_SHIFT 9 /* MIC1DET_POL */
#define WM8400_MIC1DET_POL_WIDTH 1 /* MIC1DET_POL */
#define WM8400_FLL_LCK_POL 0x0100 /* FLL_LCK_POL */
#define WM8400_FLL_LCK_POL_MASK 0x0100 /* FLL_LCK_POL */
#define WM8400_FLL_LCK_POL_SHIFT 8 /* FLL_LCK_POL */
#define WM8400_FLL_LCK_POL_WIDTH 1 /* FLL_LCK_POL */
#define WM8400_GPIO_POL_MASK 0x00FF /* GPIO_POL - [7:0] */
#define WM8400_GPIO_POL_SHIFT 0 /* GPIO_POL - [7:0] */
#define WM8400_GPIO_POL_WIDTH 8 /* GPIO_POL - [7:0] */
/*
* R65 (0x41) - LDO 1 Control
*/
#define WM8400_LDO1_ENA 0x8000 /* LDO1_ENA */
#define WM8400_LDO1_ENA_MASK 0x8000 /* LDO1_ENA */
#define WM8400_LDO1_ENA_SHIFT 15 /* LDO1_ENA */
#define WM8400_LDO1_ENA_WIDTH 1 /* LDO1_ENA */
#define WM8400_LDO1_SWI 0x4000 /* LDO1_SWI */
#define WM8400_LDO1_SWI_MASK 0x4000 /* LDO1_SWI */
#define WM8400_LDO1_SWI_SHIFT 14 /* LDO1_SWI */
#define WM8400_LDO1_SWI_WIDTH 1 /* LDO1_SWI */
#define WM8400_LDO1_OPFLT 0x1000 /* LDO1_OPFLT */
#define WM8400_LDO1_OPFLT_MASK 0x1000 /* LDO1_OPFLT */
#define WM8400_LDO1_OPFLT_SHIFT 12 /* LDO1_OPFLT */
#define WM8400_LDO1_OPFLT_WIDTH 1 /* LDO1_OPFLT */
#define WM8400_LDO1_ERRACT 0x0800 /* LDO1_ERRACT */
#define WM8400_LDO1_ERRACT_MASK 0x0800 /* LDO1_ERRACT */
#define WM8400_LDO1_ERRACT_SHIFT 11 /* LDO1_ERRACT */
#define WM8400_LDO1_ERRACT_WIDTH 1 /* LDO1_ERRACT */
#define WM8400_LDO1_HIB_MODE 0x0400 /* LDO1_HIB_MODE */
#define WM8400_LDO1_HIB_MODE_MASK 0x0400 /* LDO1_HIB_MODE */
#define WM8400_LDO1_HIB_MODE_SHIFT 10 /* LDO1_HIB_MODE */
#define WM8400_LDO1_HIB_MODE_WIDTH 1 /* LDO1_HIB_MODE */
#define WM8400_LDO1_VIMG_MASK 0x03E0 /* LDO1_VIMG - [9:5] */
#define WM8400_LDO1_VIMG_SHIFT 5 /* LDO1_VIMG - [9:5] */
#define WM8400_LDO1_VIMG_WIDTH 5 /* LDO1_VIMG - [9:5] */
#define WM8400_LDO1_VSEL_MASK 0x001F /* LDO1_VSEL - [4:0] */
#define WM8400_LDO1_VSEL_SHIFT 0 /* LDO1_VSEL - [4:0] */
#define WM8400_LDO1_VSEL_WIDTH 5 /* LDO1_VSEL - [4:0] */
/*
* R66 (0x42) - LDO 2 Control
*/
#define WM8400_LDO2_ENA 0x8000 /* LDO2_ENA */
#define WM8400_LDO2_ENA_MASK 0x8000 /* LDO2_ENA */
#define WM8400_LDO2_ENA_SHIFT 15 /* LDO2_ENA */
#define WM8400_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
#define WM8400_LDO2_SWI 0x4000 /* LDO2_SWI */
#define WM8400_LDO2_SWI_MASK 0x4000 /* LDO2_SWI */
#define WM8400_LDO2_SWI_SHIFT 14 /* LDO2_SWI */
#define WM8400_LDO2_SWI_WIDTH 1 /* LDO2_SWI */
#define WM8400_LDO2_OPFLT 0x1000 /* LDO2_OPFLT */
#define WM8400_LDO2_OPFLT_MASK 0x1000 /* LDO2_OPFLT */
#define WM8400_LDO2_OPFLT_SHIFT 12 /* LDO2_OPFLT */
#define WM8400_LDO2_OPFLT_WIDTH 1 /* LDO2_OPFLT */
#define WM8400_LDO2_ERRACT 0x0800 /* LDO2_ERRACT */
#define WM8400_LDO2_ERRACT_MASK 0x0800 /* LDO2_ERRACT */
#define WM8400_LDO2_ERRACT_SHIFT 11 /* LDO2_ERRACT */
#define WM8400_LDO2_ERRACT_WIDTH 1 /* LDO2_ERRACT */
#define WM8400_LDO2_HIB_MODE 0x0400 /* LDO2_HIB_MODE */
#define WM8400_LDO2_HIB_MODE_MASK 0x0400 /* LDO2_HIB_MODE */
#define WM8400_LDO2_HIB_MODE_SHIFT 10 /* LDO2_HIB_MODE */
#define WM8400_LDO2_HIB_MODE_WIDTH 1 /* LDO2_HIB_MODE */
#define WM8400_LDO2_VIMG_MASK 0x03E0 /* LDO2_VIMG - [9:5] */
#define WM8400_LDO2_VIMG_SHIFT 5 /* LDO2_VIMG - [9:5] */
#define WM8400_LDO2_VIMG_WIDTH 5 /* LDO2_VIMG - [9:5] */
#define WM8400_LDO2_VSEL_MASK 0x001F /* LDO2_VSEL - [4:0] */
#define WM8400_LDO2_VSEL_SHIFT 0 /* LDO2_VSEL - [4:0] */
#define WM8400_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [4:0] */
/*
* R67 (0x43) - LDO 3 Control
*/
#define WM8400_LDO3_ENA 0x8000 /* LDO3_ENA */
#define WM8400_LDO3_ENA_MASK 0x8000 /* LDO3_ENA */
#define WM8400_LDO3_ENA_SHIFT 15 /* LDO3_ENA */
#define WM8400_LDO3_ENA_WIDTH 1 /* LDO3_ENA */
#define WM8400_LDO3_SWI 0x4000 /* LDO3_SWI */
#define WM8400_LDO3_SWI_MASK 0x4000 /* LDO3_SWI */
#define WM8400_LDO3_SWI_SHIFT 14 /* LDO3_SWI */
#define WM8400_LDO3_SWI_WIDTH 1 /* LDO3_SWI */
#define WM8400_LDO3_OPFLT 0x1000 /* LDO3_OPFLT */
#define WM8400_LDO3_OPFLT_MASK 0x1000 /* LDO3_OPFLT */
#define WM8400_LDO3_OPFLT_SHIFT 12 /* LDO3_OPFLT */
#define WM8400_LDO3_OPFLT_WIDTH 1 /* LDO3_OPFLT */
#define WM8400_LDO3_ERRACT 0x0800 /* LDO3_ERRACT */
#define WM8400_LDO3_ERRACT_MASK 0x0800 /* LDO3_ERRACT */
#define WM8400_LDO3_ERRACT_SHIFT 11 /* LDO3_ERRACT */
#define WM8400_LDO3_ERRACT_WIDTH 1 /* LDO3_ERRACT */
#define WM8400_LDO3_HIB_MODE 0x0400 /* LDO3_HIB_MODE */
#define WM8400_LDO3_HIB_MODE_MASK 0x0400 /* LDO3_HIB_MODE */
#define WM8400_LDO3_HIB_MODE_SHIFT 10 /* LDO3_HIB_MODE */
#define WM8400_LDO3_HIB_MODE_WIDTH 1 /* LDO3_HIB_MODE */
#define WM8400_LDO3_VIMG_MASK 0x03E0 /* LDO3_VIMG - [9:5] */
#define WM8400_LDO3_VIMG_SHIFT 5 /* LDO3_VIMG - [9:5] */
#define WM8400_LDO3_VIMG_WIDTH 5 /* LDO3_VIMG - [9:5] */
#define WM8400_LDO3_VSEL_MASK 0x001F /* LDO3_VSEL - [4:0] */
#define WM8400_LDO3_VSEL_SHIFT 0 /* LDO3_VSEL - [4:0] */
#define WM8400_LDO3_VSEL_WIDTH 5 /* LDO3_VSEL - [4:0] */
/*
* R68 (0x44) - LDO 4 Control
*/
#define WM8400_LDO4_ENA 0x8000 /* LDO4_ENA */
#define WM8400_LDO4_ENA_MASK 0x8000 /* LDO4_ENA */
#define WM8400_LDO4_ENA_SHIFT 15 /* LDO4_ENA */
#define WM8400_LDO4_ENA_WIDTH 1 /* LDO4_ENA */
#define WM8400_LDO4_SWI 0x4000 /* LDO4_SWI */
#define WM8400_LDO4_SWI_MASK 0x4000 /* LDO4_SWI */
#define WM8400_LDO4_SWI_SHIFT 14 /* LDO4_SWI */
#define WM8400_LDO4_SWI_WIDTH 1 /* LDO4_SWI */
#define WM8400_LDO4_OPFLT 0x1000 /* LDO4_OPFLT */
#define WM8400_LDO4_OPFLT_MASK 0x1000 /* LDO4_OPFLT */
#define WM8400_LDO4_OPFLT_SHIFT 12 /* LDO4_OPFLT */
#define WM8400_LDO4_OPFLT_WIDTH 1 /* LDO4_OPFLT */
#define WM8400_LDO4_ERRACT 0x0800 /* LDO4_ERRACT */
#define WM8400_LDO4_ERRACT_MASK 0x0800 /* LDO4_ERRACT */
#define WM8400_LDO4_ERRACT_SHIFT 11 /* LDO4_ERRACT */
#define WM8400_LDO4_ERRACT_WIDTH 1 /* LDO4_ERRACT */
#define WM8400_LDO4_HIB_MODE 0x0400 /* LDO4_HIB_MODE */
#define WM8400_LDO4_HIB_MODE_MASK 0x0400 /* LDO4_HIB_MODE */
#define WM8400_LDO4_HIB_MODE_SHIFT 10 /* LDO4_HIB_MODE */
#define WM8400_LDO4_HIB_MODE_WIDTH 1 /* LDO4_HIB_MODE */
#define WM8400_LDO4_VIMG_MASK 0x03E0 /* LDO4_VIMG - [9:5] */
#define WM8400_LDO4_VIMG_SHIFT 5 /* LDO4_VIMG - [9:5] */
#define WM8400_LDO4_VIMG_WIDTH 5 /* LDO4_VIMG - [9:5] */
#define WM8400_LDO4_VSEL_MASK 0x001F /* LDO4_VSEL - [4:0] */
#define WM8400_LDO4_VSEL_SHIFT 0 /* LDO4_VSEL - [4:0] */
#define WM8400_LDO4_VSEL_WIDTH 5 /* LDO4_VSEL - [4:0] */
/*
* R70 (0x46) - DCDC1 Control 1
*/
#define WM8400_DC1_ENA 0x8000 /* DC1_ENA */
#define WM8400_DC1_ENA_MASK 0x8000 /* DC1_ENA */
#define WM8400_DC1_ENA_SHIFT 15 /* DC1_ENA */
#define WM8400_DC1_ENA_WIDTH 1 /* DC1_ENA */
#define WM8400_DC1_ACTIVE 0x4000 /* DC1_ACTIVE */
#define WM8400_DC1_ACTIVE_MASK 0x4000 /* DC1_ACTIVE */
#define WM8400_DC1_ACTIVE_SHIFT 14 /* DC1_ACTIVE */
#define WM8400_DC1_ACTIVE_WIDTH 1 /* DC1_ACTIVE */
#define WM8400_DC1_SLEEP 0x2000 /* DC1_SLEEP */
#define WM8400_DC1_SLEEP_MASK 0x2000 /* DC1_SLEEP */
#define WM8400_DC1_SLEEP_SHIFT 13 /* DC1_SLEEP */
#define WM8400_DC1_SLEEP_WIDTH 1 /* DC1_SLEEP */
#define WM8400_DC1_OPFLT 0x1000 /* DC1_OPFLT */
#define WM8400_DC1_OPFLT_MASK 0x1000 /* DC1_OPFLT */
#define WM8400_DC1_OPFLT_SHIFT 12 /* DC1_OPFLT */
#define WM8400_DC1_OPFLT_WIDTH 1 /* DC1_OPFLT */
#define WM8400_DC1_ERRACT 0x0800 /* DC1_ERRACT */
#define WM8400_DC1_ERRACT_MASK 0x0800 /* DC1_ERRACT */
#define WM8400_DC1_ERRACT_SHIFT 11 /* DC1_ERRACT */
#define WM8400_DC1_ERRACT_WIDTH 1 /* DC1_ERRACT */
#define WM8400_DC1_HIB_MODE 0x0400 /* DC1_HIB_MODE */
#define WM8400_DC1_HIB_MODE_MASK 0x0400 /* DC1_HIB_MODE */
#define WM8400_DC1_HIB_MODE_SHIFT 10 /* DC1_HIB_MODE */
#define WM8400_DC1_HIB_MODE_WIDTH 1 /* DC1_HIB_MODE */
#define WM8400_DC1_SOFTST_MASK 0x0300 /* DC1_SOFTST - [9:8] */
#define WM8400_DC1_SOFTST_SHIFT 8 /* DC1_SOFTST - [9:8] */
#define WM8400_DC1_SOFTST_WIDTH 2 /* DC1_SOFTST - [9:8] */
#define WM8400_DC1_OV_PROT 0x0080 /* DC1_OV_PROT */
#define WM8400_DC1_OV_PROT_MASK 0x0080 /* DC1_OV_PROT */
#define WM8400_DC1_OV_PROT_SHIFT 7 /* DC1_OV_PROT */
#define WM8400_DC1_OV_PROT_WIDTH 1 /* DC1_OV_PROT */
#define WM8400_DC1_VSEL_MASK 0x007F /* DC1_VSEL - [6:0] */
#define WM8400_DC1_VSEL_SHIFT 0 /* DC1_VSEL - [6:0] */
#define WM8400_DC1_VSEL_WIDTH 7 /* DC1_VSEL - [6:0] */
/*
* R71 (0x47) - DCDC1 Control 2
*/
#define WM8400_DC1_FRC_PWM 0x2000 /* DC1_FRC_PWM */
#define WM8400_DC1_FRC_PWM_MASK 0x2000 /* DC1_FRC_PWM */
#define WM8400_DC1_FRC_PWM_SHIFT 13 /* DC1_FRC_PWM */
#define WM8400_DC1_FRC_PWM_WIDTH 1 /* DC1_FRC_PWM */
#define WM8400_DC1_STBY_LIM_MASK 0x0300 /* DC1_STBY_LIM - [9:8] */
#define WM8400_DC1_STBY_LIM_SHIFT 8 /* DC1_STBY_LIM - [9:8] */
#define WM8400_DC1_STBY_LIM_WIDTH 2 /* DC1_STBY_LIM - [9:8] */
#define WM8400_DC1_ACT_LIM 0x0080 /* DC1_ACT_LIM */
#define WM8400_DC1_ACT_LIM_MASK 0x0080 /* DC1_ACT_LIM */
#define WM8400_DC1_ACT_LIM_SHIFT 7 /* DC1_ACT_LIM */
#define WM8400_DC1_ACT_LIM_WIDTH 1 /* DC1_ACT_LIM */
#define WM8400_DC1_VIMG_MASK 0x007F /* DC1_VIMG - [6:0] */
#define WM8400_DC1_VIMG_SHIFT 0 /* DC1_VIMG - [6:0] */
#define WM8400_DC1_VIMG_WIDTH 7 /* DC1_VIMG - [6:0] */
/*
* R72 (0x48) - DCDC2 Control 1
*/
#define WM8400_DC2_ENA 0x8000 /* DC2_ENA */
#define WM8400_DC2_ENA_MASK 0x8000 /* DC2_ENA */
#define WM8400_DC2_ENA_SHIFT 15 /* DC2_ENA */
#define WM8400_DC2_ENA_WIDTH 1 /* DC2_ENA */
#define WM8400_DC2_ACTIVE 0x4000 /* DC2_ACTIVE */
#define WM8400_DC2_ACTIVE_MASK 0x4000 /* DC2_ACTIVE */
#define WM8400_DC2_ACTIVE_SHIFT 14 /* DC2_ACTIVE */
#define WM8400_DC2_ACTIVE_WIDTH 1 /* DC2_ACTIVE */
#define WM8400_DC2_SLEEP 0x2000 /* DC2_SLEEP */
#define WM8400_DC2_SLEEP_MASK 0x2000 /* DC2_SLEEP */
#define WM8400_DC2_SLEEP_SHIFT 13 /* DC2_SLEEP */
#define WM8400_DC2_SLEEP_WIDTH 1 /* DC2_SLEEP */
#define WM8400_DC2_OPFLT 0x1000 /* DC2_OPFLT */
#define WM8400_DC2_OPFLT_MASK 0x1000 /* DC2_OPFLT */
#define WM8400_DC2_OPFLT_SHIFT 12 /* DC2_OPFLT */
#define WM8400_DC2_OPFLT_WIDTH 1 /* DC2_OPFLT */
#define WM8400_DC2_ERRACT 0x0800 /* DC2_ERRACT */
#define WM8400_DC2_ERRACT_MASK 0x0800 /* DC2_ERRACT */
#define WM8400_DC2_ERRACT_SHIFT 11 /* DC2_ERRACT */
#define WM8400_DC2_ERRACT_WIDTH 1 /* DC2_ERRACT */
#define WM8400_DC2_HIB_MODE 0x0400 /* DC2_HIB_MODE */
#define WM8400_DC2_HIB_MODE_MASK 0x0400 /* DC2_HIB_MODE */
#define WM8400_DC2_HIB_MODE_SHIFT 10 /* DC2_HIB_MODE */
#define WM8400_DC2_HIB_MODE_WIDTH 1 /* DC2_HIB_MODE */
#define WM8400_DC2_SOFTST_MASK 0x0300 /* DC2_SOFTST - [9:8] */
#define WM8400_DC2_SOFTST_SHIFT 8 /* DC2_SOFTST - [9:8] */
#define WM8400_DC2_SOFTST_WIDTH 2 /* DC2_SOFTST - [9:8] */
#define WM8400_DC2_OV_PROT 0x0080 /* DC2_OV_PROT */
#define WM8400_DC2_OV_PROT_MASK 0x0080 /* DC2_OV_PROT */
#define WM8400_DC2_OV_PROT_SHIFT 7 /* DC2_OV_PROT */
#define WM8400_DC2_OV_PROT_WIDTH 1 /* DC2_OV_PROT */
#define WM8400_DC2_VSEL_MASK 0x007F /* DC2_VSEL - [6:0] */
#define WM8400_DC2_VSEL_SHIFT 0 /* DC2_VSEL - [6:0] */
#define WM8400_DC2_VSEL_WIDTH 7 /* DC2_VSEL - [6:0] */
/*
* R73 (0x49) - DCDC2 Control 2
*/
#define WM8400_DC2_FRC_PWM 0x2000 /* DC2_FRC_PWM */
#define WM8400_DC2_FRC_PWM_MASK 0x2000 /* DC2_FRC_PWM */
#define WM8400_DC2_FRC_PWM_SHIFT 13 /* DC2_FRC_PWM */
#define WM8400_DC2_FRC_PWM_WIDTH 1 /* DC2_FRC_PWM */
#define WM8400_DC2_STBY_LIM_MASK 0x0300 /* DC2_STBY_LIM - [9:8] */
#define WM8400_DC2_STBY_LIM_SHIFT 8 /* DC2_STBY_LIM - [9:8] */
#define WM8400_DC2_STBY_LIM_WIDTH 2 /* DC2_STBY_LIM - [9:8] */
#define WM8400_DC2_ACT_LIM 0x0080 /* DC2_ACT_LIM */
#define WM8400_DC2_ACT_LIM_MASK 0x0080 /* DC2_ACT_LIM */
#define WM8400_DC2_ACT_LIM_SHIFT 7 /* DC2_ACT_LIM */
#define WM8400_DC2_ACT_LIM_WIDTH 1 /* DC2_ACT_LIM */
#define WM8400_DC2_VIMG_MASK 0x007F /* DC2_VIMG - [6:0] */
#define WM8400_DC2_VIMG_SHIFT 0 /* DC2_VIMG - [6:0] */
#define WM8400_DC2_VIMG_WIDTH 7 /* DC2_VIMG - [6:0] */
/*
* R75 (0x4B) - Interface
*/
#define WM8400_AUTOINC 0x0008 /* AUTOINC */
#define WM8400_AUTOINC_MASK 0x0008 /* AUTOINC */
#define WM8400_AUTOINC_SHIFT 3 /* AUTOINC */
#define WM8400_AUTOINC_WIDTH 1 /* AUTOINC */
#define WM8400_ARA_ENA 0x0004 /* ARA_ENA */
#define WM8400_ARA_ENA_MASK 0x0004 /* ARA_ENA */
#define WM8400_ARA_ENA_SHIFT 2 /* ARA_ENA */
#define WM8400_ARA_ENA_WIDTH 1 /* ARA_ENA */
#define WM8400_SPI_CFG 0x0002 /* SPI_CFG */
#define WM8400_SPI_CFG_MASK 0x0002 /* SPI_CFG */
#define WM8400_SPI_CFG_SHIFT 1 /* SPI_CFG */
#define WM8400_SPI_CFG_WIDTH 1 /* SPI_CFG */
/*
* R76 (0x4C) - PM GENERAL
*/
#define WM8400_CODEC_SOFTST 0x8000 /* CODEC_SOFTST */
#define WM8400_CODEC_SOFTST_MASK 0x8000 /* CODEC_SOFTST */
#define WM8400_CODEC_SOFTST_SHIFT 15 /* CODEC_SOFTST */
#define WM8400_CODEC_SOFTST_WIDTH 1 /* CODEC_SOFTST */
#define WM8400_CODEC_SOFTSD 0x4000 /* CODEC_SOFTSD */
#define WM8400_CODEC_SOFTSD_MASK 0x4000 /* CODEC_SOFTSD */
#define WM8400_CODEC_SOFTSD_SHIFT 14 /* CODEC_SOFTSD */
#define WM8400_CODEC_SOFTSD_WIDTH 1 /* CODEC_SOFTSD */
#define WM8400_CHIP_SOFTSD 0x2000 /* CHIP_SOFTSD */
#define WM8400_CHIP_SOFTSD_MASK 0x2000 /* CHIP_SOFTSD */
#define WM8400_CHIP_SOFTSD_SHIFT 13 /* CHIP_SOFTSD */
#define WM8400_CHIP_SOFTSD_WIDTH 1 /* CHIP_SOFTSD */
#define WM8400_DSLEEP1_POL 0x0008 /* DSLEEP1_POL */
#define WM8400_DSLEEP1_POL_MASK 0x0008 /* DSLEEP1_POL */
#define WM8400_DSLEEP1_POL_SHIFT 3 /* DSLEEP1_POL */
#define WM8400_DSLEEP1_POL_WIDTH 1 /* DSLEEP1_POL */
#define WM8400_DSLEEP2_POL 0x0004 /* DSLEEP2_POL */
#define WM8400_DSLEEP2_POL_MASK 0x0004 /* DSLEEP2_POL */
#define WM8400_DSLEEP2_POL_SHIFT 2 /* DSLEEP2_POL */
#define WM8400_DSLEEP2_POL_WIDTH 1 /* DSLEEP2_POL */
#define WM8400_PWR_STATE_MASK 0x0003 /* PWR_STATE - [1:0] */
#define WM8400_PWR_STATE_SHIFT 0 /* PWR_STATE - [1:0] */
#define WM8400_PWR_STATE_WIDTH 2 /* PWR_STATE - [1:0] */
/*
* R78 (0x4E) - PM Shutdown Control
*/
#define WM8400_CHIP_GT150_ERRACT 0x0200 /* CHIP_GT150_ERRACT */
#define WM8400_CHIP_GT150_ERRACT_MASK 0x0200 /* CHIP_GT150_ERRACT */
#define WM8400_CHIP_GT150_ERRACT_SHIFT 9 /* CHIP_GT150_ERRACT */
#define WM8400_CHIP_GT150_ERRACT_WIDTH 1 /* CHIP_GT150_ERRACT */
#define WM8400_CHIP_GT115_ERRACT 0x0100 /* CHIP_GT115_ERRACT */
#define WM8400_CHIP_GT115_ERRACT_MASK 0x0100 /* CHIP_GT115_ERRACT */
#define WM8400_CHIP_GT115_ERRACT_SHIFT 8 /* CHIP_GT115_ERRACT */
#define WM8400_CHIP_GT115_ERRACT_WIDTH 1 /* CHIP_GT115_ERRACT */
#define WM8400_LINE_CMP_ERRACT 0x0080 /* LINE_CMP_ERRACT */
#define WM8400_LINE_CMP_ERRACT_MASK 0x0080 /* LINE_CMP_ERRACT */
#define WM8400_LINE_CMP_ERRACT_SHIFT 7 /* LINE_CMP_ERRACT */
#define WM8400_LINE_CMP_ERRACT_WIDTH 1 /* LINE_CMP_ERRACT */
#define WM8400_UVLO_ERRACT 0x0040 /* UVLO_ERRACT */
#define WM8400_UVLO_ERRACT_MASK 0x0040 /* UVLO_ERRACT */
#define WM8400_UVLO_ERRACT_SHIFT 6 /* UVLO_ERRACT */
#define WM8400_UVLO_ERRACT_WIDTH 1 /* UVLO_ERRACT */
/*
* R79 (0x4F) - Interrupt Status 1
*/
#define WM8400_MICD_CINT 0x8000 /* MICD_CINT */
#define WM8400_MICD_CINT_MASK 0x8000 /* MICD_CINT */
#define WM8400_MICD_CINT_SHIFT 15 /* MICD_CINT */
#define WM8400_MICD_CINT_WIDTH 1 /* MICD_CINT */
#define WM8400_MICSCD_CINT 0x4000 /* MICSCD_CINT */
#define WM8400_MICSCD_CINT_MASK 0x4000 /* MICSCD_CINT */
#define WM8400_MICSCD_CINT_SHIFT 14 /* MICSCD_CINT */
#define WM8400_MICSCD_CINT_WIDTH 1 /* MICSCD_CINT */
#define WM8400_JDL_CINT 0x2000 /* JDL_CINT */
#define WM8400_JDL_CINT_MASK 0x2000 /* JDL_CINT */
#define WM8400_JDL_CINT_SHIFT 13 /* JDL_CINT */
#define WM8400_JDL_CINT_WIDTH 1 /* JDL_CINT */
#define WM8400_JDR_CINT 0x1000 /* JDR_CINT */
#define WM8400_JDR_CINT_MASK 0x1000 /* JDR_CINT */
#define WM8400_JDR_CINT_SHIFT 12 /* JDR_CINT */
#define WM8400_JDR_CINT_WIDTH 1 /* JDR_CINT */
#define WM8400_CODEC_SEQ_END_EINT 0x0800 /* CODEC_SEQ_END_EINT */
#define WM8400_CODEC_SEQ_END_EINT_MASK 0x0800 /* CODEC_SEQ_END_EINT */
#define WM8400_CODEC_SEQ_END_EINT_SHIFT 11 /* CODEC_SEQ_END_EINT */
#define WM8400_CODEC_SEQ_END_EINT_WIDTH 1 /* CODEC_SEQ_END_EINT */
#define WM8400_CDEL_TO_EINT 0x0400 /* CDEL_TO_EINT */
#define WM8400_CDEL_TO_EINT_MASK 0x0400 /* CDEL_TO_EINT */
#define WM8400_CDEL_TO_EINT_SHIFT 10 /* CDEL_TO_EINT */
#define WM8400_CDEL_TO_EINT_WIDTH 1 /* CDEL_TO_EINT */
#define WM8400_CHIP_GT150_EINT 0x0200 /* CHIP_GT150_EINT */
#define WM8400_CHIP_GT150_EINT_MASK 0x0200 /* CHIP_GT150_EINT */
#define WM8400_CHIP_GT150_EINT_SHIFT 9 /* CHIP_GT150_EINT */
#define WM8400_CHIP_GT150_EINT_WIDTH 1 /* CHIP_GT150_EINT */
#define WM8400_CHIP_GT115_EINT 0x0100 /* CHIP_GT115_EINT */
#define WM8400_CHIP_GT115_EINT_MASK 0x0100 /* CHIP_GT115_EINT */
#define WM8400_CHIP_GT115_EINT_SHIFT 8 /* CHIP_GT115_EINT */
#define WM8400_CHIP_GT115_EINT_WIDTH 1 /* CHIP_GT115_EINT */
#define WM8400_LINE_CMP_EINT 0x0080 /* LINE_CMP_EINT */
#define WM8400_LINE_CMP_EINT_MASK 0x0080 /* LINE_CMP_EINT */
#define WM8400_LINE_CMP_EINT_SHIFT 7 /* LINE_CMP_EINT */
#define WM8400_LINE_CMP_EINT_WIDTH 1 /* LINE_CMP_EINT */
#define WM8400_UVLO_EINT 0x0040 /* UVLO_EINT */
#define WM8400_UVLO_EINT_MASK 0x0040 /* UVLO_EINT */
#define WM8400_UVLO_EINT_SHIFT 6 /* UVLO_EINT */
#define WM8400_UVLO_EINT_WIDTH 1 /* UVLO_EINT */
#define WM8400_DC2_UV_EINT 0x0020 /* DC2_UV_EINT */
#define WM8400_DC2_UV_EINT_MASK 0x0020 /* DC2_UV_EINT */
#define WM8400_DC2_UV_EINT_SHIFT 5 /* DC2_UV_EINT */
#define WM8400_DC2_UV_EINT_WIDTH 1 /* DC2_UV_EINT */
#define WM8400_DC1_UV_EINT 0x0010 /* DC1_UV_EINT */
#define WM8400_DC1_UV_EINT_MASK 0x0010 /* DC1_UV_EINT */
#define WM8400_DC1_UV_EINT_SHIFT 4 /* DC1_UV_EINT */
#define WM8400_DC1_UV_EINT_WIDTH 1 /* DC1_UV_EINT */
#define WM8400_LDO4_UV_EINT 0x0008 /* LDO4_UV_EINT */
#define WM8400_LDO4_UV_EINT_MASK 0x0008 /* LDO4_UV_EINT */
#define WM8400_LDO4_UV_EINT_SHIFT 3 /* LDO4_UV_EINT */
#define WM8400_LDO4_UV_EINT_WIDTH 1 /* LDO4_UV_EINT */
#define WM8400_LDO3_UV_EINT 0x0004 /* LDO3_UV_EINT */
#define WM8400_LDO3_UV_EINT_MASK 0x0004 /* LDO3_UV_EINT */
#define WM8400_LDO3_UV_EINT_SHIFT 2 /* LDO3_UV_EINT */
#define WM8400_LDO3_UV_EINT_WIDTH 1 /* LDO3_UV_EINT */
#define WM8400_LDO2_UV_EINT 0x0002 /* LDO2_UV_EINT */
#define WM8400_LDO2_UV_EINT_MASK 0x0002 /* LDO2_UV_EINT */
#define WM8400_LDO2_UV_EINT_SHIFT 1 /* LDO2_UV_EINT */
#define WM8400_LDO2_UV_EINT_WIDTH 1 /* LDO2_UV_EINT */
#define WM8400_LDO1_UV_EINT 0x0001 /* LDO1_UV_EINT */
#define WM8400_LDO1_UV_EINT_MASK 0x0001 /* LDO1_UV_EINT */
#define WM8400_LDO1_UV_EINT_SHIFT 0 /* LDO1_UV_EINT */
#define WM8400_LDO1_UV_EINT_WIDTH 1 /* LDO1_UV_EINT */
/*
* R80 (0x50) - Interrupt Status 1 Mask
*/
#define WM8400_IM_MICD_CINT 0x8000 /* IM_MICD_CINT */
#define WM8400_IM_MICD_CINT_MASK 0x8000 /* IM_MICD_CINT */
#define WM8400_IM_MICD_CINT_SHIFT 15 /* IM_MICD_CINT */
#define WM8400_IM_MICD_CINT_WIDTH 1 /* IM_MICD_CINT */
#define WM8400_IM_MICSCD_CINT 0x4000 /* IM_MICSCD_CINT */
#define WM8400_IM_MICSCD_CINT_MASK 0x4000 /* IM_MICSCD_CINT */
#define WM8400_IM_MICSCD_CINT_SHIFT 14 /* IM_MICSCD_CINT */
#define WM8400_IM_MICSCD_CINT_WIDTH 1 /* IM_MICSCD_CINT */
#define WM8400_IM_JDL_CINT 0x2000 /* IM_JDL_CINT */
#define WM8400_IM_JDL_CINT_MASK 0x2000 /* IM_JDL_CINT */
#define WM8400_IM_JDL_CINT_SHIFT 13 /* IM_JDL_CINT */
#define WM8400_IM_JDL_CINT_WIDTH 1 /* IM_JDL_CINT */
#define WM8400_IM_JDR_CINT 0x1000 /* IM_JDR_CINT */
#define WM8400_IM_JDR_CINT_MASK 0x1000 /* IM_JDR_CINT */
#define WM8400_IM_JDR_CINT_SHIFT 12 /* IM_JDR_CINT */
#define WM8400_IM_JDR_CINT_WIDTH 1 /* IM_JDR_CINT */
#define WM8400_IM_CODEC_SEQ_END_EINT 0x0800 /* IM_CODEC_SEQ_END_EINT */
#define WM8400_IM_CODEC_SEQ_END_EINT_MASK 0x0800 /* IM_CODEC_SEQ_END_EINT */
#define WM8400_IM_CODEC_SEQ_END_EINT_SHIFT 11 /* IM_CODEC_SEQ_END_EINT */
#define WM8400_IM_CODEC_SEQ_END_EINT_WIDTH 1 /* IM_CODEC_SEQ_END_EINT */
#define WM8400_IM_CDEL_TO_EINT 0x0400 /* IM_CDEL_TO_EINT */
#define WM8400_IM_CDEL_TO_EINT_MASK 0x0400 /* IM_CDEL_TO_EINT */
#define WM8400_IM_CDEL_TO_EINT_SHIFT 10 /* IM_CDEL_TO_EINT */
#define WM8400_IM_CDEL_TO_EINT_WIDTH 1 /* IM_CDEL_TO_EINT */
#define WM8400_IM_CHIP_GT150_EINT 0x0200 /* IM_CHIP_GT150_EINT */
#define WM8400_IM_CHIP_GT150_EINT_MASK 0x0200 /* IM_CHIP_GT150_EINT */
#define WM8400_IM_CHIP_GT150_EINT_SHIFT 9 /* IM_CHIP_GT150_EINT */
#define WM8400_IM_CHIP_GT150_EINT_WIDTH 1 /* IM_CHIP_GT150_EINT */
#define WM8400_IM_CHIP_GT115_EINT 0x0100 /* IM_CHIP_GT115_EINT */
#define WM8400_IM_CHIP_GT115_EINT_MASK 0x0100 /* IM_CHIP_GT115_EINT */
#define WM8400_IM_CHIP_GT115_EINT_SHIFT 8 /* IM_CHIP_GT115_EINT */
#define WM8400_IM_CHIP_GT115_EINT_WIDTH 1 /* IM_CHIP_GT115_EINT */
#define WM8400_IM_LINE_CMP_EINT 0x0080 /* IM_LINE_CMP_EINT */
#define WM8400_IM_LINE_CMP_EINT_MASK 0x0080 /* IM_LINE_CMP_EINT */
#define WM8400_IM_LINE_CMP_EINT_SHIFT 7 /* IM_LINE_CMP_EINT */
#define WM8400_IM_LINE_CMP_EINT_WIDTH 1 /* IM_LINE_CMP_EINT */
#define WM8400_IM_UVLO_EINT 0x0040 /* IM_UVLO_EINT */
#define WM8400_IM_UVLO_EINT_MASK 0x0040 /* IM_UVLO_EINT */
#define WM8400_IM_UVLO_EINT_SHIFT 6 /* IM_UVLO_EINT */
#define WM8400_IM_UVLO_EINT_WIDTH 1 /* IM_UVLO_EINT */
#define WM8400_IM_DC2_UV_EINT 0x0020 /* IM_DC2_UV_EINT */
#define WM8400_IM_DC2_UV_EINT_MASK 0x0020 /* IM_DC2_UV_EINT */
#define WM8400_IM_DC2_UV_EINT_SHIFT 5 /* IM_DC2_UV_EINT */
#define WM8400_IM_DC2_UV_EINT_WIDTH 1 /* IM_DC2_UV_EINT */
#define WM8400_IM_DC1_UV_EINT 0x0010 /* IM_DC1_UV_EINT */
#define WM8400_IM_DC1_UV_EINT_MASK 0x0010 /* IM_DC1_UV_EINT */
#define WM8400_IM_DC1_UV_EINT_SHIFT 4 /* IM_DC1_UV_EINT */
#define WM8400_IM_DC1_UV_EINT_WIDTH 1 /* IM_DC1_UV_EINT */
#define WM8400_IM_LDO4_UV_EINT 0x0008 /* IM_LDO4_UV_EINT */
#define WM8400_IM_LDO4_UV_EINT_MASK 0x0008 /* IM_LDO4_UV_EINT */
#define WM8400_IM_LDO4_UV_EINT_SHIFT 3 /* IM_LDO4_UV_EINT */
#define WM8400_IM_LDO4_UV_EINT_WIDTH 1 /* IM_LDO4_UV_EINT */
#define WM8400_IM_LDO3_UV_EINT 0x0004 /* IM_LDO3_UV_EINT */
#define WM8400_IM_LDO3_UV_EINT_MASK 0x0004 /* IM_LDO3_UV_EINT */
#define WM8400_IM_LDO3_UV_EINT_SHIFT 2 /* IM_LDO3_UV_EINT */
#define WM8400_IM_LDO3_UV_EINT_WIDTH 1 /* IM_LDO3_UV_EINT */
#define WM8400_IM_LDO2_UV_EINT 0x0002 /* IM_LDO2_UV_EINT */
#define WM8400_IM_LDO2_UV_EINT_MASK 0x0002 /* IM_LDO2_UV_EINT */
#define WM8400_IM_LDO2_UV_EINT_SHIFT 1 /* IM_LDO2_UV_EINT */
#define WM8400_IM_LDO2_UV_EINT_WIDTH 1 /* IM_LDO2_UV_EINT */
#define WM8400_IM_LDO1_UV_EINT 0x0001 /* IM_LDO1_UV_EINT */
#define WM8400_IM_LDO1_UV_EINT_MASK 0x0001 /* IM_LDO1_UV_EINT */
#define WM8400_IM_LDO1_UV_EINT_SHIFT 0 /* IM_LDO1_UV_EINT */
#define WM8400_IM_LDO1_UV_EINT_WIDTH 1 /* IM_LDO1_UV_EINT */
/*
* R81 (0x51) - Interrupt Levels
*/
#define WM8400_MICD_LVL 0x8000 /* MICD_LVL */
#define WM8400_MICD_LVL_MASK 0x8000 /* MICD_LVL */
#define WM8400_MICD_LVL_SHIFT 15 /* MICD_LVL */
#define WM8400_MICD_LVL_WIDTH 1 /* MICD_LVL */
#define WM8400_MICSCD_LVL 0x4000 /* MICSCD_LVL */
#define WM8400_MICSCD_LVL_MASK 0x4000 /* MICSCD_LVL */
#define WM8400_MICSCD_LVL_SHIFT 14 /* MICSCD_LVL */
#define WM8400_MICSCD_LVL_WIDTH 1 /* MICSCD_LVL */
#define WM8400_JDL_LVL 0x2000 /* JDL_LVL */
#define WM8400_JDL_LVL_MASK 0x2000 /* JDL_LVL */
#define WM8400_JDL_LVL_SHIFT 13 /* JDL_LVL */
#define WM8400_JDL_LVL_WIDTH 1 /* JDL_LVL */
#define WM8400_JDR_LVL 0x1000 /* JDR_LVL */
#define WM8400_JDR_LVL_MASK 0x1000 /* JDR_LVL */
#define WM8400_JDR_LVL_SHIFT 12 /* JDR_LVL */
#define WM8400_JDR_LVL_WIDTH 1 /* JDR_LVL */
#define WM8400_CODEC_SEQ_END_LVL 0x0800 /* CODEC_SEQ_END_LVL */
#define WM8400_CODEC_SEQ_END_LVL_MASK 0x0800 /* CODEC_SEQ_END_LVL */
#define WM8400_CODEC_SEQ_END_LVL_SHIFT 11 /* CODEC_SEQ_END_LVL */
#define WM8400_CODEC_SEQ_END_LVL_WIDTH 1 /* CODEC_SEQ_END_LVL */
#define WM8400_CDEL_TO_LVL 0x0400 /* CDEL_TO_LVL */
#define WM8400_CDEL_TO_LVL_MASK 0x0400 /* CDEL_TO_LVL */
#define WM8400_CDEL_TO_LVL_SHIFT 10 /* CDEL_TO_LVL */
#define WM8400_CDEL_TO_LVL_WIDTH 1 /* CDEL_TO_LVL */
#define WM8400_CHIP_GT150_LVL 0x0200 /* CHIP_GT150_LVL */
#define WM8400_CHIP_GT150_LVL_MASK 0x0200 /* CHIP_GT150_LVL */
#define WM8400_CHIP_GT150_LVL_SHIFT 9 /* CHIP_GT150_LVL */
#define WM8400_CHIP_GT150_LVL_WIDTH 1 /* CHIP_GT150_LVL */
#define WM8400_CHIP_GT115_LVL 0x0100 /* CHIP_GT115_LVL */
#define WM8400_CHIP_GT115_LVL_MASK 0x0100 /* CHIP_GT115_LVL */
#define WM8400_CHIP_GT115_LVL_SHIFT 8 /* CHIP_GT115_LVL */
#define WM8400_CHIP_GT115_LVL_WIDTH 1 /* CHIP_GT115_LVL */
#define WM8400_LINE_CMP_LVL 0x0080 /* LINE_CMP_LVL */
#define WM8400_LINE_CMP_LVL_MASK 0x0080 /* LINE_CMP_LVL */
#define WM8400_LINE_CMP_LVL_SHIFT 7 /* LINE_CMP_LVL */
#define WM8400_LINE_CMP_LVL_WIDTH 1 /* LINE_CMP_LVL */
#define WM8400_UVLO_LVL 0x0040 /* UVLO_LVL */
#define WM8400_UVLO_LVL_MASK 0x0040 /* UVLO_LVL */
#define WM8400_UVLO_LVL_SHIFT 6 /* UVLO_LVL */
#define WM8400_UVLO_LVL_WIDTH 1 /* UVLO_LVL */
#define WM8400_DC2_UV_LVL 0x0020 /* DC2_UV_LVL */
#define WM8400_DC2_UV_LVL_MASK 0x0020 /* DC2_UV_LVL */
#define WM8400_DC2_UV_LVL_SHIFT 5 /* DC2_UV_LVL */
#define WM8400_DC2_UV_LVL_WIDTH 1 /* DC2_UV_LVL */
#define WM8400_DC1_UV_LVL 0x0010 /* DC1_UV_LVL */
#define WM8400_DC1_UV_LVL_MASK 0x0010 /* DC1_UV_LVL */
#define WM8400_DC1_UV_LVL_SHIFT 4 /* DC1_UV_LVL */
#define WM8400_DC1_UV_LVL_WIDTH 1 /* DC1_UV_LVL */
#define WM8400_LDO4_UV_LVL 0x0008 /* LDO4_UV_LVL */
#define WM8400_LDO4_UV_LVL_MASK 0x0008 /* LDO4_UV_LVL */
#define WM8400_LDO4_UV_LVL_SHIFT 3 /* LDO4_UV_LVL */
#define WM8400_LDO4_UV_LVL_WIDTH 1 /* LDO4_UV_LVL */
#define WM8400_LDO3_UV_LVL 0x0004 /* LDO3_UV_LVL */
#define WM8400_LDO3_UV_LVL_MASK 0x0004 /* LDO3_UV_LVL */
#define WM8400_LDO3_UV_LVL_SHIFT 2 /* LDO3_UV_LVL */
#define WM8400_LDO3_UV_LVL_WIDTH 1 /* LDO3_UV_LVL */
#define WM8400_LDO2_UV_LVL 0x0002 /* LDO2_UV_LVL */
#define WM8400_LDO2_UV_LVL_MASK 0x0002 /* LDO2_UV_LVL */
#define WM8400_LDO2_UV_LVL_SHIFT 1 /* LDO2_UV_LVL */
#define WM8400_LDO2_UV_LVL_WIDTH 1 /* LDO2_UV_LVL */
#define WM8400_LDO1_UV_LVL 0x0001 /* LDO1_UV_LVL */
#define WM8400_LDO1_UV_LVL_MASK 0x0001 /* LDO1_UV_LVL */
#define WM8400_LDO1_UV_LVL_SHIFT 0 /* LDO1_UV_LVL */
#define WM8400_LDO1_UV_LVL_WIDTH 1 /* LDO1_UV_LVL */
/*
* R82 (0x52) - Shutdown Reason
*/
#define WM8400_SDR_CHIP_SOFTSD 0x2000 /* SDR_CHIP_SOFTSD */
#define WM8400_SDR_CHIP_SOFTSD_MASK 0x2000 /* SDR_CHIP_SOFTSD */
#define WM8400_SDR_CHIP_SOFTSD_SHIFT 13 /* SDR_CHIP_SOFTSD */
#define WM8400_SDR_CHIP_SOFTSD_WIDTH 1 /* SDR_CHIP_SOFTSD */
#define WM8400_SDR_NPDN 0x0800 /* SDR_NPDN */
#define WM8400_SDR_NPDN_MASK 0x0800 /* SDR_NPDN */
#define WM8400_SDR_NPDN_SHIFT 11 /* SDR_NPDN */
#define WM8400_SDR_NPDN_WIDTH 1 /* SDR_NPDN */
#define WM8400_SDR_CHIP_GT150 0x0200 /* SDR_CHIP_GT150 */
#define WM8400_SDR_CHIP_GT150_MASK 0x0200 /* SDR_CHIP_GT150 */
#define WM8400_SDR_CHIP_GT150_SHIFT 9 /* SDR_CHIP_GT150 */
#define WM8400_SDR_CHIP_GT150_WIDTH 1 /* SDR_CHIP_GT150 */
#define WM8400_SDR_CHIP_GT115 0x0100 /* SDR_CHIP_GT115 */
#define WM8400_SDR_CHIP_GT115_MASK 0x0100 /* SDR_CHIP_GT115 */
#define WM8400_SDR_CHIP_GT115_SHIFT 8 /* SDR_CHIP_GT115 */
#define WM8400_SDR_CHIP_GT115_WIDTH 1 /* SDR_CHIP_GT115 */
#define WM8400_SDR_LINE_CMP 0x0080 /* SDR_LINE_CMP */
#define WM8400_SDR_LINE_CMP_MASK 0x0080 /* SDR_LINE_CMP */
#define WM8400_SDR_LINE_CMP_SHIFT 7 /* SDR_LINE_CMP */
#define WM8400_SDR_LINE_CMP_WIDTH 1 /* SDR_LINE_CMP */
#define WM8400_SDR_UVLO 0x0040 /* SDR_UVLO */
#define WM8400_SDR_UVLO_MASK 0x0040 /* SDR_UVLO */
#define WM8400_SDR_UVLO_SHIFT 6 /* SDR_UVLO */
#define WM8400_SDR_UVLO_WIDTH 1 /* SDR_UVLO */
#define WM8400_SDR_DC2_UV 0x0020 /* SDR_DC2_UV */
#define WM8400_SDR_DC2_UV_MASK 0x0020 /* SDR_DC2_UV */
#define WM8400_SDR_DC2_UV_SHIFT 5 /* SDR_DC2_UV */
#define WM8400_SDR_DC2_UV_WIDTH 1 /* SDR_DC2_UV */
#define WM8400_SDR_DC1_UV 0x0010 /* SDR_DC1_UV */
#define WM8400_SDR_DC1_UV_MASK 0x0010 /* SDR_DC1_UV */
#define WM8400_SDR_DC1_UV_SHIFT 4 /* SDR_DC1_UV */
#define WM8400_SDR_DC1_UV_WIDTH 1 /* SDR_DC1_UV */
#define WM8400_SDR_LDO4_UV 0x0008 /* SDR_LDO4_UV */
#define WM8400_SDR_LDO4_UV_MASK 0x0008 /* SDR_LDO4_UV */
#define WM8400_SDR_LDO4_UV_SHIFT 3 /* SDR_LDO4_UV */
#define WM8400_SDR_LDO4_UV_WIDTH 1 /* SDR_LDO4_UV */
#define WM8400_SDR_LDO3_UV 0x0004 /* SDR_LDO3_UV */
#define WM8400_SDR_LDO3_UV_MASK 0x0004 /* SDR_LDO3_UV */
#define WM8400_SDR_LDO3_UV_SHIFT 2 /* SDR_LDO3_UV */
#define WM8400_SDR_LDO3_UV_WIDTH 1 /* SDR_LDO3_UV */
#define WM8400_SDR_LDO2_UV 0x0002 /* SDR_LDO2_UV */
#define WM8400_SDR_LDO2_UV_MASK 0x0002 /* SDR_LDO2_UV */
#define WM8400_SDR_LDO2_UV_SHIFT 1 /* SDR_LDO2_UV */
#define WM8400_SDR_LDO2_UV_WIDTH 1 /* SDR_LDO2_UV */
#define WM8400_SDR_LDO1_UV 0x0001 /* SDR_LDO1_UV */
#define WM8400_SDR_LDO1_UV_MASK 0x0001 /* SDR_LDO1_UV */
#define WM8400_SDR_LDO1_UV_SHIFT 0 /* SDR_LDO1_UV */
#define WM8400_SDR_LDO1_UV_WIDTH 1 /* SDR_LDO1_UV */
/*
* R84 (0x54) - Line Circuits
*/
#define WM8400_BG_LINE_COMP 0x8000 /* BG_LINE_COMP */
#define WM8400_BG_LINE_COMP_MASK 0x8000 /* BG_LINE_COMP */
#define WM8400_BG_LINE_COMP_SHIFT 15 /* BG_LINE_COMP */
#define WM8400_BG_LINE_COMP_WIDTH 1 /* BG_LINE_COMP */
#define WM8400_LINE_CMP_VTHI_MASK 0x00F0 /* LINE_CMP_VTHI - [7:4] */
#define WM8400_LINE_CMP_VTHI_SHIFT 4 /* LINE_CMP_VTHI - [7:4] */
#define WM8400_LINE_CMP_VTHI_WIDTH 4 /* LINE_CMP_VTHI - [7:4] */
#define WM8400_LINE_CMP_VTHD_MASK 0x000F /* LINE_CMP_VTHD - [3:0] */
#define WM8400_LINE_CMP_VTHD_SHIFT 0 /* LINE_CMP_VTHD - [3:0] */
#define WM8400_LINE_CMP_VTHD_WIDTH 4 /* LINE_CMP_VTHD - [3:0] */
u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg);
int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data);
int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val);
#endif

40
kernel/include/linux/mfd/wm8400.h Normal file
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/*
* wm8400 client interface
*
* Copyright 2008 Wolfson Microelectronics plc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __LINUX_MFD_WM8400_H
#define __LINUX_MFD_WM8400_H
#include <linux/regulator/machine.h>
#define WM8400_LDO1 0
#define WM8400_LDO2 1
#define WM8400_LDO3 2
#define WM8400_LDO4 3
#define WM8400_DCDC1 4
#define WM8400_DCDC2 5
struct wm8400_platform_data {
int (*platform_init)(struct device *dev);
};
int wm8400_register_regulator(struct device *dev, int reg,
struct regulator_init_data *initdata);
#endif