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add idl4k kernel firmware version 1.13.0.105

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This commit is contained in:
Jaroslav Kysela
2015-03-26 17:22:37 +01:00
parent 5194d2792e
commit e9070cdc77
31064 changed files with 12769984 additions and 0 deletions
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222
kernel/sound/soc/codecs/Kconfig Normal file
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# Helper to resolve issues with configs that have SPI enabled but I2C
# modular, meaning we can't build the codec driver in with I2C support.
# We use an ordered list of conditional defaults to pick the appropriate
# setting - SPI can't be modular so that case doesn't need to be covered.
config SND_SOC_I2C_AND_SPI
tristate
default m if I2C=m
default y if I2C=y
default y if SPI_MASTER=y
config SND_SOC_ALL_CODECS
tristate "Build all ASoC CODEC drivers"
select SND_SOC_L3
select SND_SOC_AC97_CODEC if SND_SOC_AC97_BUS
select SND_SOC_AD1836 if SPI_MASTER
select SND_SOC_AD1938 if SPI_MASTER
select SND_SOC_AD1980 if SND_SOC_AC97_BUS
select SND_SOC_AD73311 if I2C
select SND_SOC_AK4104 if SPI_MASTER
select SND_SOC_AK4535 if I2C
select SND_SOC_AK4642 if I2C
select SND_SOC_CS4270 if I2C
select SND_SOC_MAX9877 if I2C
select SND_SOC_PCM3008
select SND_SOC_SPDIF
select SND_SOC_SSM2602 if I2C
select SND_SOC_STAC9766 if SND_SOC_AC97_BUS
select SND_SOC_TLV320AIC23 if I2C
select SND_SOC_TLV320AIC26 if SPI_MASTER
select SND_SOC_TLV320AIC3X if I2C
select SND_SOC_TWL4030 if TWL4030_CORE
select SND_SOC_UDA134X
select SND_SOC_UDA1380 if I2C
select SND_SOC_WM8350 if MFD_WM8350
select SND_SOC_WM8400 if MFD_WM8400
select SND_SOC_WM8510 if SND_SOC_I2C_AND_SPI
select SND_SOC_WM8523 if I2C
select SND_SOC_WM8580 if I2C
select SND_SOC_WM8728 if SND_SOC_I2C_AND_SPI
select SND_SOC_WM8731 if SND_SOC_I2C_AND_SPI
select SND_SOC_WM8750 if SND_SOC_I2C_AND_SPI
select SND_SOC_WM8753 if SND_SOC_I2C_AND_SPI
select SND_SOC_WM8776 if SND_SOC_I2C_AND_SPI
select SND_SOC_WM8900 if I2C
select SND_SOC_WM8903 if I2C
select SND_SOC_WM8940 if I2C
select SND_SOC_WM8960 if I2C
select SND_SOC_WM8961 if I2C
select SND_SOC_WM8971 if I2C
select SND_SOC_WM8974 if I2C
select SND_SOC_WM8988 if SND_SOC_I2C_AND_SPI
select SND_SOC_WM8990 if I2C
select SND_SOC_WM8993 if I2C
select SND_SOC_WM9081 if I2C
select SND_SOC_WM9705 if SND_SOC_AC97_BUS
select SND_SOC_WM9712 if SND_SOC_AC97_BUS
select SND_SOC_WM9713 if SND_SOC_AC97_BUS
help
Normally ASoC codec drivers are only built if a machine driver which
uses them is also built since they are only usable with a machine
driver. Selecting this option will allow these drivers to be built
without an explicit machine driver for test and development purposes.
Support for the bus types used to access the codecs to be built must
be selected separately.
If unsure select "N".
config SND_SOC_WM_HUBS
tristate
default y if SND_SOC_WM8993=y
default m if SND_SOC_WM8993=m
config SND_SOC_AC97_CODEC
tristate
select SND_AC97_CODEC
config SND_SOC_AD1836
tristate
config SND_SOC_AD1938
tristate
config SND_SOC_AD1980
tristate
config SND_SOC_AD73311
tristate
config SND_SOC_AK4104
tristate
config SND_SOC_AK4535
tristate
config SND_SOC_AK4642
tristate
# Cirrus Logic CS4270 Codec
config SND_SOC_CS4270
tristate
# Cirrus Logic CS4270 Codec VD = 3.3V Errata
# Select if you are affected by the errata where the part will not function
# if MCLK divide-by-1.5 is selected and VD is set to 3.3V. The driver will
# not select any sample rates that require MCLK to be divided by 1.5.
config SND_SOC_CS4270_VD33_ERRATA
bool
depends on SND_SOC_CS4270
config SND_SOC_CX20442
tristate
config SND_SOC_L3
tristate
config SND_SOC_PCM3008
tristate
config SND_SOC_SPDIF
tristate
config SND_SOC_SSM2602
tristate
config SND_SOC_STAC9766
tristate
config SND_SOC_TLV320AIC23
tristate
config SND_SOC_TLV320AIC26
tristate "TI TLV320AIC26 Codec support" if SND_SOC_OF_SIMPLE
depends on SPI
config SND_SOC_TLV320AIC3X
tristate
config SND_SOC_TWL4030
tristate
config SND_SOC_UDA134X
tristate
config SND_SOC_UDA1380
tristate
config SND_SOC_WM8350
tristate
config SND_SOC_WM8400
tristate
config SND_SOC_WM8510
tristate
config SND_SOC_WM8523
tristate
config SND_SOC_WM8580
tristate
config SND_SOC_WM8728
tristate
config SND_SOC_WM8731
tristate
config SND_SOC_WM8750
tristate
config SND_SOC_WM8753
tristate
config SND_SOC_WM8776
tristate
config SND_SOC_WM8900
tristate
config SND_SOC_WM8903
tristate
config SND_SOC_WM8940
tristate
config SND_SOC_WM8960
tristate
config SND_SOC_WM8961
tristate
config SND_SOC_WM8971
tristate
config SND_SOC_WM8974
tristate
config SND_SOC_WM8988
tristate
config SND_SOC_WM8990
tristate
config SND_SOC_WM8993
tristate
config SND_SOC_WM9081
tristate
config SND_SOC_WM9705
tristate
config SND_SOC_WM9712
tristate
config SND_SOC_WM9713
tristate
# Amp
config SND_SOC_MAX9877
tristate

99
kernel/sound/soc/codecs/Makefile Normal file
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snd-soc-ac97-objs := ac97.o
snd-soc-ad1836-objs := ad1836.o
snd-soc-ad1938-objs := ad1938.o
snd-soc-ad1980-objs := ad1980.o
snd-soc-ad73311-objs := ad73311.o
snd-soc-ak4104-objs := ak4104.o
snd-soc-ak4535-objs := ak4535.o
snd-soc-ak4642-objs := ak4642.o
snd-soc-cs4270-objs := cs4270.o
snd-soc-cx20442-objs := cx20442.o
snd-soc-l3-objs := l3.o
snd-soc-pcm3008-objs := pcm3008.o
snd-soc-spdif-objs := spdif_transciever.o
snd-soc-ssm2602-objs := ssm2602.o
snd-soc-stac9766-objs := stac9766.o
snd-soc-tlv320aic23-objs := tlv320aic23.o
snd-soc-tlv320aic26-objs := tlv320aic26.o
snd-soc-tlv320aic3x-objs := tlv320aic3x.o
snd-soc-twl4030-objs := twl4030.o
snd-soc-uda134x-objs := uda134x.o
snd-soc-uda1380-objs := uda1380.o
snd-soc-wm8350-objs := wm8350.o
snd-soc-wm8400-objs := wm8400.o
snd-soc-wm8510-objs := wm8510.o
snd-soc-wm8523-objs := wm8523.o
snd-soc-wm8580-objs := wm8580.o
snd-soc-wm8728-objs := wm8728.o
snd-soc-wm8731-objs := wm8731.o
snd-soc-wm8750-objs := wm8750.o
snd-soc-wm8753-objs := wm8753.o
snd-soc-wm8776-objs := wm8776.o
snd-soc-wm8900-objs := wm8900.o
snd-soc-wm8903-objs := wm8903.o
snd-soc-wm8940-objs := wm8940.o
snd-soc-wm8960-objs := wm8960.o
snd-soc-wm8961-objs := wm8961.o
snd-soc-wm8971-objs := wm8971.o
snd-soc-wm8974-objs := wm8974.o
snd-soc-wm8988-objs := wm8988.o
snd-soc-wm8990-objs := wm8990.o
snd-soc-wm8993-objs := wm8993.o
snd-soc-wm9081-objs := wm9081.o
snd-soc-wm9705-objs := wm9705.o
snd-soc-wm9712-objs := wm9712.o
snd-soc-wm9713-objs := wm9713.o
snd-soc-wm-hubs-objs := wm_hubs.o
# Amp
snd-soc-max9877-objs := max9877.o
obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o
obj-$(CONFIG_SND_SOC_AD1836) += snd-soc-ad1836.o
obj-$(CONFIG_SND_SOC_AD1938) += snd-soc-ad1938.o
obj-$(CONFIG_SND_SOC_AD1980) += snd-soc-ad1980.o
obj-$(CONFIG_SND_SOC_AD73311) += snd-soc-ad73311.o
obj-$(CONFIG_SND_SOC_AK4104) += snd-soc-ak4104.o
obj-$(CONFIG_SND_SOC_AK4535) += snd-soc-ak4535.o
obj-$(CONFIG_SND_SOC_AK4642) += snd-soc-ak4642.o
obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o
obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o
obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o
obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o
obj-$(CONFIG_SND_SOC_SPDIF) += snd-soc-spdif.o
obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o
obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o
obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o
obj-$(CONFIG_SND_SOC_TLV320AIC26) += snd-soc-tlv320aic26.o
obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o
obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o
obj-$(CONFIG_SND_SOC_UDA134X) += snd-soc-uda134x.o
obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o
obj-$(CONFIG_SND_SOC_WM8350) += snd-soc-wm8350.o
obj-$(CONFIG_SND_SOC_WM8400) += snd-soc-wm8400.o
obj-$(CONFIG_SND_SOC_WM8510) += snd-soc-wm8510.o
obj-$(CONFIG_SND_SOC_WM8523) += snd-soc-wm8523.o
obj-$(CONFIG_SND_SOC_WM8580) += snd-soc-wm8580.o
obj-$(CONFIG_SND_SOC_WM8728) += snd-soc-wm8728.o
obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o
obj-$(CONFIG_SND_SOC_WM8750) += snd-soc-wm8750.o
obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o
obj-$(CONFIG_SND_SOC_WM8776) += snd-soc-wm8776.o
obj-$(CONFIG_SND_SOC_WM8900) += snd-soc-wm8900.o
obj-$(CONFIG_SND_SOC_WM8903) += snd-soc-wm8903.o
obj-$(CONFIG_SND_SOC_WM8971) += snd-soc-wm8971.o
obj-$(CONFIG_SND_SOC_WM8974) += snd-soc-wm8974.o
obj-$(CONFIG_SND_SOC_WM8940) += snd-soc-wm8940.o
obj-$(CONFIG_SND_SOC_WM8960) += snd-soc-wm8960.o
obj-$(CONFIG_SND_SOC_WM8961) += snd-soc-wm8961.o
obj-$(CONFIG_SND_SOC_WM8988) += snd-soc-wm8988.o
obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o
obj-$(CONFIG_SND_SOC_WM8993) += snd-soc-wm8993.o
obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o
obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o
obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o
obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o
obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o
# Amp
obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o

181
kernel/sound/soc/codecs/ac97.c Normal file
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@@ -0,0 +1,181 @@
/*
* ac97.c -- ALSA Soc AC97 codec support
*
* Copyright 2005 Wolfson Microelectronics PLC.
* Author: Liam Girdwood <lrg@slimlogic.co.uk>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Generic AC97 support.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include "ac97.h"
#define AC97_VERSION "0.6"
static int ac97_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE;
return snd_ac97_set_rate(codec->ac97, reg, runtime->rate);
}
#define STD_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000)
static struct snd_soc_dai_ops ac97_dai_ops = {
.prepare = ac97_prepare,
};
struct snd_soc_dai ac97_dai = {
.name = "AC97 HiFi",
.ac97_control = 1,
.playback = {
.stream_name = "AC97 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = STD_AC97_RATES,
.formats = SND_SOC_STD_AC97_FMTS,},
.capture = {
.stream_name = "AC97 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = STD_AC97_RATES,
.formats = SND_SOC_STD_AC97_FMTS,},
.ops = &ac97_dai_ops,
};
EXPORT_SYMBOL_GPL(ac97_dai);
static unsigned int ac97_read(struct snd_soc_codec *codec,
unsigned int reg)
{
return soc_ac97_ops.read(codec->ac97, reg);
}
static int ac97_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int val)
{
soc_ac97_ops.write(codec->ac97, reg, val);
return 0;
}
static int ac97_soc_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
struct snd_ac97_bus *ac97_bus;
struct snd_ac97_template ac97_template;
int ret = 0;
printk(KERN_INFO "AC97 SoC Audio Codec %s\n", AC97_VERSION);
socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
if (!socdev->card->codec)
return -ENOMEM;
codec = socdev->card->codec;
mutex_init(&codec->mutex);
codec->name = "AC97";
codec->owner = THIS_MODULE;
codec->dai = &ac97_dai;
codec->num_dai = 1;
codec->write = ac97_write;
codec->read = ac97_read;
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0)
goto err;
/* add codec as bus device for standard ac97 */
ret = snd_ac97_bus(codec->card, 0, &soc_ac97_ops, NULL, &ac97_bus);
if (ret < 0)
goto bus_err;
memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
ret = snd_ac97_mixer(ac97_bus, &ac97_template, &codec->ac97);
if (ret < 0)
goto bus_err;
ret = snd_soc_init_card(socdev);
if (ret < 0)
goto bus_err;
return 0;
bus_err:
snd_soc_free_pcms(socdev);
err:
kfree(socdev->card->codec);
socdev->card->codec = NULL;
return ret;
}
static int ac97_soc_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
if (!codec)
return 0;
snd_soc_free_pcms(socdev);
kfree(socdev->card->codec);
return 0;
}
#ifdef CONFIG_PM
static int ac97_soc_suspend(struct platform_device *pdev, pm_message_t msg)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_ac97_suspend(socdev->card->codec->ac97);
return 0;
}
static int ac97_soc_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_ac97_resume(socdev->card->codec->ac97);
return 0;
}
#else
#define ac97_soc_suspend NULL
#define ac97_soc_resume NULL
#endif
struct snd_soc_codec_device soc_codec_dev_ac97 = {
.probe = ac97_soc_probe,
.remove = ac97_soc_remove,
.suspend = ac97_soc_suspend,
.resume = ac97_soc_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_ac97);
MODULE_DESCRIPTION("Soc Generic AC97 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");

19
kernel/sound/soc/codecs/ac97.h Normal file
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@@ -0,0 +1,19 @@
/*
* linux/sound/codecs/ac97.h -- ALSA SoC Layer
*
* Author: Liam Girdwood
* Created: Dec 1st 2005
* Copyright: Wolfson Microelectronics. PLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_SND_SOC_AC97_H
#define __LINUX_SND_SOC_AC97_H
extern struct snd_soc_codec_device soc_codec_dev_ac97;
extern struct snd_soc_dai ac97_dai;
#endif

444
kernel/sound/soc/codecs/ad1836.c Normal file
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@@ -0,0 +1,444 @@
/*
* File: sound/soc/codecs/ad1836.c
* Author: Barry Song <Barry.Song@analog.com>
*
* Created: Aug 04 2009
* Description: Driver for AD1836 sound chip
*
* Modified:
* Copyright 2009 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/soc-dapm.h>
#include <linux/spi/spi.h>
#include "ad1836.h"
/* codec private data */
struct ad1836_priv {
struct snd_soc_codec codec;
u16 reg_cache[AD1836_NUM_REGS];
};
static struct snd_soc_codec *ad1836_codec;
struct snd_soc_codec_device soc_codec_dev_ad1836;
static int ad1836_register(struct ad1836_priv *ad1836);
static void ad1836_unregister(struct ad1836_priv *ad1836);
/*
* AD1836 volume/mute/de-emphasis etc. controls
*/
static const char *ad1836_deemp[] = {"None", "44.1kHz", "32kHz", "48kHz"};
static const struct soc_enum ad1836_deemp_enum =
SOC_ENUM_SINGLE(AD1836_DAC_CTRL1, 8, 4, ad1836_deemp);
static const struct snd_kcontrol_new ad1836_snd_controls[] = {
/* DAC volume control */
SOC_DOUBLE_R("DAC1 Volume", AD1836_DAC_L1_VOL,
AD1836_DAC_R1_VOL, 0, 0x3FF, 0),
SOC_DOUBLE_R("DAC2 Volume", AD1836_DAC_L2_VOL,
AD1836_DAC_R2_VOL, 0, 0x3FF, 0),
SOC_DOUBLE_R("DAC3 Volume", AD1836_DAC_L3_VOL,
AD1836_DAC_R3_VOL, 0, 0x3FF, 0),
/* ADC switch control */
SOC_DOUBLE("ADC1 Switch", AD1836_ADC_CTRL2, AD1836_ADCL1_MUTE,
AD1836_ADCR1_MUTE, 1, 1),
SOC_DOUBLE("ADC2 Switch", AD1836_ADC_CTRL2, AD1836_ADCL2_MUTE,
AD1836_ADCR2_MUTE, 1, 1),
/* DAC switch control */
SOC_DOUBLE("DAC1 Switch", AD1836_DAC_CTRL2, AD1836_DACL1_MUTE,
AD1836_DACR1_MUTE, 1, 1),
SOC_DOUBLE("DAC2 Switch", AD1836_DAC_CTRL2, AD1836_DACL2_MUTE,
AD1836_DACR2_MUTE, 1, 1),
SOC_DOUBLE("DAC3 Switch", AD1836_DAC_CTRL2, AD1836_DACL3_MUTE,
AD1836_DACR3_MUTE, 1, 1),
/* ADC high-pass filter */
SOC_SINGLE("ADC High Pass Filter Switch", AD1836_ADC_CTRL1,
AD1836_ADC_HIGHPASS_FILTER, 1, 0),
/* DAC de-emphasis */
SOC_ENUM("Playback Deemphasis", ad1836_deemp_enum),
};
static const struct snd_soc_dapm_widget ad1836_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", AD1836_DAC_CTRL1,
AD1836_DAC_POWERDOWN, 1),
SND_SOC_DAPM_ADC("ADC", "Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC_PWR", AD1836_ADC_CTRL1,
AD1836_ADC_POWERDOWN, 1, NULL, 0),
SND_SOC_DAPM_OUTPUT("DAC1OUT"),
SND_SOC_DAPM_OUTPUT("DAC2OUT"),
SND_SOC_DAPM_OUTPUT("DAC3OUT"),
SND_SOC_DAPM_INPUT("ADC1IN"),
SND_SOC_DAPM_INPUT("ADC2IN"),
};
static const struct snd_soc_dapm_route audio_paths[] = {
{ "DAC", NULL, "ADC_PWR" },
{ "ADC", NULL, "ADC_PWR" },
{ "DAC1OUT", "DAC1 Switch", "DAC" },
{ "DAC2OUT", "DAC2 Switch", "DAC" },
{ "DAC3OUT", "DAC3 Switch", "DAC" },
{ "ADC", "ADC1 Switch", "ADC1IN" },
{ "ADC", "ADC2 Switch", "ADC2IN" },
};
/*
* DAI ops entries
*/
static int ad1836_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
/* at present, we support adc aux mode to interface with
* blackfin sport tdm mode
*/
case SND_SOC_DAIFMT_DSP_A:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
/* ALCLK,ABCLK are both output, AD1836 can only be master */
case SND_SOC_DAIFMT_CBM_CFM:
break;
default:
return -EINVAL;
}
return 0;
}
static int ad1836_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
int word_len = 0;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
/* bit size */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
word_len = 3;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
word_len = 1;
break;
case SNDRV_PCM_FORMAT_S24_LE:
case SNDRV_PCM_FORMAT_S32_LE:
word_len = 0;
break;
}
snd_soc_update_bits(codec, AD1836_DAC_CTRL1,
AD1836_DAC_WORD_LEN_MASK, word_len);
snd_soc_update_bits(codec, AD1836_ADC_CTRL2,
AD1836_ADC_WORD_LEN_MASK, word_len);
return 0;
}
/*
* interface to read/write ad1836 register
*/
#define AD1836_SPI_REG_SHFT 12
#define AD1836_SPI_READ (1 << 11)
#define AD1836_SPI_VAL_MSK 0x3FF
/*
* write to the ad1836 register space
*/
static int ad1836_write_reg(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
u16 *reg_cache = codec->reg_cache;
int ret = 0;
if (value != reg_cache[reg]) {
unsigned short buf;
struct spi_transfer t = {
.tx_buf = &buf,
.len = 2,
};
struct spi_message m;
buf = (reg << AD1836_SPI_REG_SHFT) |
(value & AD1836_SPI_VAL_MSK);
spi_message_init(&m);
spi_message_add_tail(&t, &m);
ret = spi_sync(codec->control_data, &m);
if (ret == 0)
reg_cache[reg] = value;
}
return ret;
}
/*
* read from the ad1836 register space cache
*/
static unsigned int ad1836_read_reg_cache(struct snd_soc_codec *codec,
unsigned int reg)
{
u16 *reg_cache = codec->reg_cache;
if (reg >= codec->reg_cache_size)
return -EINVAL;
return reg_cache[reg];
}
static int __devinit ad1836_spi_probe(struct spi_device *spi)
{
struct snd_soc_codec *codec;
struct ad1836_priv *ad1836;
ad1836 = kzalloc(sizeof(struct ad1836_priv), GFP_KERNEL);
if (ad1836 == NULL)
return -ENOMEM;
codec = &ad1836->codec;
codec->control_data = spi;
codec->dev = &spi->dev;
dev_set_drvdata(&spi->dev, ad1836);
return ad1836_register(ad1836);
}
static int __devexit ad1836_spi_remove(struct spi_device *spi)
{
struct ad1836_priv *ad1836 = dev_get_drvdata(&spi->dev);
ad1836_unregister(ad1836);
return 0;
}
static struct spi_driver ad1836_spi_driver = {
.driver = {
.name = "ad1836",
.owner = THIS_MODULE,
},
.probe = ad1836_spi_probe,
.remove = __devexit_p(ad1836_spi_remove),
};
static struct snd_soc_dai_ops ad1836_dai_ops = {
.hw_params = ad1836_hw_params,
.set_fmt = ad1836_set_dai_fmt,
};
/* codec DAI instance */
struct snd_soc_dai ad1836_dai = {
.name = "AD1836",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 6,
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 4,
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE,
},
.ops = &ad1836_dai_ops,
};
EXPORT_SYMBOL_GPL(ad1836_dai);
static int ad1836_register(struct ad1836_priv *ad1836)
{
int ret;
struct snd_soc_codec *codec = &ad1836->codec;
if (ad1836_codec) {
dev_err(codec->dev, "Another ad1836 is registered\n");
return -EINVAL;
}
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->private_data = ad1836;
codec->reg_cache = ad1836->reg_cache;
codec->reg_cache_size = AD1836_NUM_REGS;
codec->name = "AD1836";
codec->owner = THIS_MODULE;
codec->dai = &ad1836_dai;
codec->num_dai = 1;
codec->write = ad1836_write_reg;
codec->read = ad1836_read_reg_cache;
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
ad1836_dai.dev = codec->dev;
ad1836_codec = codec;
/* default setting for ad1836 */
/* de-emphasis: 48kHz, power-on dac */
codec->write(codec, AD1836_DAC_CTRL1, 0x300);
/* unmute dac channels */
codec->write(codec, AD1836_DAC_CTRL2, 0x0);
/* high-pass filter enable, power-on adc */
codec->write(codec, AD1836_ADC_CTRL1, 0x100);
/* unmute adc channles, adc aux mode */
codec->write(codec, AD1836_ADC_CTRL2, 0x180);
/* left/right diff:PGA/MUX */
codec->write(codec, AD1836_ADC_CTRL3, 0x3A);
/* volume */
codec->write(codec, AD1836_DAC_L1_VOL, 0x3FF);
codec->write(codec, AD1836_DAC_R1_VOL, 0x3FF);
codec->write(codec, AD1836_DAC_L2_VOL, 0x3FF);
codec->write(codec, AD1836_DAC_R2_VOL, 0x3FF);
codec->write(codec, AD1836_DAC_L3_VOL, 0x3FF);
codec->write(codec, AD1836_DAC_R3_VOL, 0x3FF);
ret = snd_soc_register_codec(codec);
if (ret != 0) {
dev_err(codec->dev, "Failed to register codec: %d\n", ret);
kfree(ad1836);
return ret;
}
ret = snd_soc_register_dai(&ad1836_dai);
if (ret != 0) {
dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
snd_soc_unregister_codec(codec);
kfree(ad1836);
return ret;
}
return 0;
}
static void ad1836_unregister(struct ad1836_priv *ad1836)
{
snd_soc_unregister_dai(&ad1836_dai);
snd_soc_unregister_codec(&ad1836->codec);
kfree(ad1836);
ad1836_codec = NULL;
}
static int ad1836_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
if (ad1836_codec == NULL) {
dev_err(&pdev->dev, "Codec device not registered\n");
return -ENODEV;
}
socdev->card->codec = ad1836_codec;
codec = ad1836_codec;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms: %d\n", ret);
goto pcm_err;
}
snd_soc_add_controls(codec, ad1836_snd_controls,
ARRAY_SIZE(ad1836_snd_controls));
snd_soc_dapm_new_controls(codec, ad1836_dapm_widgets,
ARRAY_SIZE(ad1836_dapm_widgets));
snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
snd_soc_dapm_new_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(codec->dev, "failed to register card: %d\n", ret);
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
return ret;
}
/* power down chip */
static int ad1836_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_ad1836 = {
.probe = ad1836_probe,
.remove = ad1836_remove,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_ad1836);
static int __init ad1836_init(void)
{
int ret;
ret = spi_register_driver(&ad1836_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register ad1836 SPI driver: %d\n",
ret);
}
return ret;
}
module_init(ad1836_init);
static void __exit ad1836_exit(void)
{
spi_unregister_driver(&ad1836_spi_driver);
}
module_exit(ad1836_exit);
MODULE_DESCRIPTION("ASoC ad1836 driver");
MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
MODULE_LICENSE("GPL");

64
kernel/sound/soc/codecs/ad1836.h Normal file
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/*
* File: sound/soc/codecs/ad1836.h
* Based on:
* Author: Barry Song <Barry.Song@analog.com>
*
* Created: Aug 04, 2009
* Description: definitions for AD1836 registers
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __AD1836_H__
#define __AD1836_H__
#define AD1836_DAC_CTRL1 0
#define AD1836_DAC_POWERDOWN 2
#define AD1836_DAC_SERFMT_MASK 0xE0
#define AD1836_DAC_SERFMT_PCK256 (0x4 << 5)
#define AD1836_DAC_SERFMT_PCK128 (0x5 << 5)
#define AD1836_DAC_WORD_LEN_MASK 0x18
#define AD1836_DAC_CTRL2 1
#define AD1836_DACL1_MUTE 0
#define AD1836_DACR1_MUTE 1
#define AD1836_DACL2_MUTE 2
#define AD1836_DACR2_MUTE 3
#define AD1836_DACL3_MUTE 4
#define AD1836_DACR3_MUTE 5
#define AD1836_DAC_L1_VOL 2
#define AD1836_DAC_R1_VOL 3
#define AD1836_DAC_L2_VOL 4
#define AD1836_DAC_R2_VOL 5
#define AD1836_DAC_L3_VOL 6
#define AD1836_DAC_R3_VOL 7
#define AD1836_ADC_CTRL1 12
#define AD1836_ADC_POWERDOWN 7
#define AD1836_ADC_HIGHPASS_FILTER 8
#define AD1836_ADC_CTRL2 13
#define AD1836_ADCL1_MUTE 0
#define AD1836_ADCR1_MUTE 1
#define AD1836_ADCL2_MUTE 2
#define AD1836_ADCR2_MUTE 3
#define AD1836_ADC_WORD_LEN_MASK 0x30
#define AD1836_ADC_SERFMT_MASK (7 << 6)
#define AD1836_ADC_SERFMT_PCK256 (0x4 << 6)
#define AD1836_ADC_SERFMT_PCK128 (0x5 << 6)
#define AD1836_ADC_CTRL3 14
#define AD1836_NUM_REGS 16
extern struct snd_soc_dai ad1836_dai;
extern struct snd_soc_codec_device soc_codec_dev_ad1836;
#endif

681
kernel/sound/soc/codecs/ad1938.c Normal file
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/*
* File: sound/soc/codecs/ad1938.c
* Author: Barry Song <Barry.Song@analog.com>
*
* Created: June 04 2009
* Description: Driver for AD1938 sound chip
*
* Modified:
* Copyright 2009 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/soc-dapm.h>
#include <linux/spi/spi.h>
#include "ad1938.h"
/* codec private data */
struct ad1938_priv {
struct snd_soc_codec codec;
u8 reg_cache[AD1938_NUM_REGS];
};
static struct snd_soc_codec *ad1938_codec;
struct snd_soc_codec_device soc_codec_dev_ad1938;
static int ad1938_register(struct ad1938_priv *ad1938);
static void ad1938_unregister(struct ad1938_priv *ad1938);
/*
* AD1938 volume/mute/de-emphasis etc. controls
*/
static const char *ad1938_deemp[] = {"None", "48kHz", "44.1kHz", "32kHz"};
static const struct soc_enum ad1938_deemp_enum =
SOC_ENUM_SINGLE(AD1938_DAC_CTRL2, 1, 4, ad1938_deemp);
static const struct snd_kcontrol_new ad1938_snd_controls[] = {
/* DAC volume control */
SOC_DOUBLE_R("DAC1 Volume", AD1938_DAC_L1_VOL,
AD1938_DAC_R1_VOL, 0, 0xFF, 1),
SOC_DOUBLE_R("DAC2 Volume", AD1938_DAC_L2_VOL,
AD1938_DAC_R2_VOL, 0, 0xFF, 1),
SOC_DOUBLE_R("DAC3 Volume", AD1938_DAC_L3_VOL,
AD1938_DAC_R3_VOL, 0, 0xFF, 1),
SOC_DOUBLE_R("DAC4 Volume", AD1938_DAC_L4_VOL,
AD1938_DAC_R4_VOL, 0, 0xFF, 1),
/* ADC switch control */
SOC_DOUBLE("ADC1 Switch", AD1938_ADC_CTRL0, AD1938_ADCL1_MUTE,
AD1938_ADCR1_MUTE, 1, 1),
SOC_DOUBLE("ADC2 Switch", AD1938_ADC_CTRL0, AD1938_ADCL2_MUTE,
AD1938_ADCR2_MUTE, 1, 1),
/* DAC switch control */
SOC_DOUBLE("DAC1 Switch", AD1938_DAC_CHNL_MUTE, AD1938_DACL1_MUTE,
AD1938_DACR1_MUTE, 1, 1),
SOC_DOUBLE("DAC2 Switch", AD1938_DAC_CHNL_MUTE, AD1938_DACL2_MUTE,
AD1938_DACR2_MUTE, 1, 1),
SOC_DOUBLE("DAC3 Switch", AD1938_DAC_CHNL_MUTE, AD1938_DACL3_MUTE,
AD1938_DACR3_MUTE, 1, 1),
SOC_DOUBLE("DAC4 Switch", AD1938_DAC_CHNL_MUTE, AD1938_DACL4_MUTE,
AD1938_DACR4_MUTE, 1, 1),
/* ADC high-pass filter */
SOC_SINGLE("ADC High Pass Filter Switch", AD1938_ADC_CTRL0,
AD1938_ADC_HIGHPASS_FILTER, 1, 0),
/* DAC de-emphasis */
SOC_ENUM("Playback Deemphasis", ad1938_deemp_enum),
};
static const struct snd_soc_dapm_widget ad1938_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", AD1938_DAC_CTRL0, 0, 1),
SND_SOC_DAPM_ADC("ADC", "Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC_PWR", AD1938_ADC_CTRL0, 0, 1, NULL, 0),
SND_SOC_DAPM_OUTPUT("DAC1OUT"),
SND_SOC_DAPM_OUTPUT("DAC2OUT"),
SND_SOC_DAPM_OUTPUT("DAC3OUT"),
SND_SOC_DAPM_OUTPUT("DAC4OUT"),
SND_SOC_DAPM_INPUT("ADC1IN"),
SND_SOC_DAPM_INPUT("ADC2IN"),
};
static const struct snd_soc_dapm_route audio_paths[] = {
{ "DAC", NULL, "ADC_PWR" },
{ "ADC", NULL, "ADC_PWR" },
{ "DAC1OUT", "DAC1 Switch", "DAC" },
{ "DAC2OUT", "DAC2 Switch", "DAC" },
{ "DAC3OUT", "DAC3 Switch", "DAC" },
{ "DAC4OUT", "DAC4 Switch", "DAC" },
{ "ADC", "ADC1 Switch", "ADC1IN" },
{ "ADC", "ADC2 Switch", "ADC2IN" },
};
/*
* DAI ops entries
*/
static int ad1938_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
int reg;
reg = codec->read(codec, AD1938_DAC_CTRL2);
reg = (mute > 0) ? reg | AD1938_DAC_MASTER_MUTE : reg &
(~AD1938_DAC_MASTER_MUTE);
codec->write(codec, AD1938_DAC_CTRL2, reg);
return 0;
}
static inline int ad1938_pll_powerctrl(struct snd_soc_codec *codec, int cmd)
{
int reg = codec->read(codec, AD1938_PLL_CLK_CTRL0);
reg = (cmd > 0) ? reg & (~AD1938_PLL_POWERDOWN) : reg |
AD1938_PLL_POWERDOWN;
codec->write(codec, AD1938_PLL_CLK_CTRL0, reg);
return 0;
}
static int ad1938_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int mask, int slots, int width)
{
struct snd_soc_codec *codec = dai->codec;
int dac_reg = codec->read(codec, AD1938_DAC_CTRL1);
int adc_reg = codec->read(codec, AD1938_ADC_CTRL2);
dac_reg &= ~AD1938_DAC_CHAN_MASK;
adc_reg &= ~AD1938_ADC_CHAN_MASK;
switch (slots) {
case 2:
dac_reg |= AD1938_DAC_2_CHANNELS << AD1938_DAC_CHAN_SHFT;
adc_reg |= AD1938_ADC_2_CHANNELS << AD1938_ADC_CHAN_SHFT;
break;
case 4:
dac_reg |= AD1938_DAC_4_CHANNELS << AD1938_DAC_CHAN_SHFT;
adc_reg |= AD1938_ADC_4_CHANNELS << AD1938_ADC_CHAN_SHFT;
break;
case 8:
dac_reg |= AD1938_DAC_8_CHANNELS << AD1938_DAC_CHAN_SHFT;
adc_reg |= AD1938_ADC_8_CHANNELS << AD1938_ADC_CHAN_SHFT;
break;
case 16:
dac_reg |= AD1938_DAC_16_CHANNELS << AD1938_DAC_CHAN_SHFT;
adc_reg |= AD1938_ADC_16_CHANNELS << AD1938_ADC_CHAN_SHFT;
break;
default:
return -EINVAL;
}
codec->write(codec, AD1938_DAC_CTRL1, dac_reg);
codec->write(codec, AD1938_ADC_CTRL2, adc_reg);
return 0;
}
static int ad1938_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
int adc_reg, dac_reg;
adc_reg = codec->read(codec, AD1938_ADC_CTRL2);
dac_reg = codec->read(codec, AD1938_DAC_CTRL1);
/* At present, the driver only support AUX ADC mode(SND_SOC_DAIFMT_I2S
* with TDM) and ADC&DAC TDM mode(SND_SOC_DAIFMT_DSP_A)
*/
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
adc_reg &= ~AD1938_ADC_SERFMT_MASK;
adc_reg |= AD1938_ADC_SERFMT_TDM;
break;
case SND_SOC_DAIFMT_DSP_A:
adc_reg &= ~AD1938_ADC_SERFMT_MASK;
adc_reg |= AD1938_ADC_SERFMT_AUX;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
adc_reg &= ~AD1938_ADC_LEFT_HIGH;
adc_reg &= ~AD1938_ADC_BCLK_INV;
dac_reg &= ~AD1938_DAC_LEFT_HIGH;
dac_reg &= ~AD1938_DAC_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF: /* normal bclk + invert frm */
adc_reg |= AD1938_ADC_LEFT_HIGH;
adc_reg &= ~AD1938_ADC_BCLK_INV;
dac_reg |= AD1938_DAC_LEFT_HIGH;
dac_reg &= ~AD1938_DAC_BCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF: /* invert bclk + normal frm */
adc_reg &= ~AD1938_ADC_LEFT_HIGH;
adc_reg |= AD1938_ADC_BCLK_INV;
dac_reg &= ~AD1938_DAC_LEFT_HIGH;
dac_reg |= AD1938_DAC_BCLK_INV;
break;
case SND_SOC_DAIFMT_IB_IF: /* invert bclk + frm */
adc_reg |= AD1938_ADC_LEFT_HIGH;
adc_reg |= AD1938_ADC_BCLK_INV;
dac_reg |= AD1938_DAC_LEFT_HIGH;
dac_reg |= AD1938_DAC_BCLK_INV;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM: /* codec clk & frm master */
adc_reg |= AD1938_ADC_LCR_MASTER;
adc_reg |= AD1938_ADC_BCLK_MASTER;
dac_reg |= AD1938_DAC_LCR_MASTER;
dac_reg |= AD1938_DAC_BCLK_MASTER;
break;
case SND_SOC_DAIFMT_CBS_CFM: /* codec clk slave & frm master */
adc_reg |= AD1938_ADC_LCR_MASTER;
adc_reg &= ~AD1938_ADC_BCLK_MASTER;
dac_reg |= AD1938_DAC_LCR_MASTER;
dac_reg &= ~AD1938_DAC_BCLK_MASTER;
break;
case SND_SOC_DAIFMT_CBM_CFS: /* codec clk master & frame slave */
adc_reg &= ~AD1938_ADC_LCR_MASTER;
adc_reg |= AD1938_ADC_BCLK_MASTER;
dac_reg &= ~AD1938_DAC_LCR_MASTER;
dac_reg |= AD1938_DAC_BCLK_MASTER;
break;
case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & frm slave */
adc_reg &= ~AD1938_ADC_LCR_MASTER;
adc_reg &= ~AD1938_ADC_BCLK_MASTER;
dac_reg &= ~AD1938_DAC_LCR_MASTER;
dac_reg &= ~AD1938_DAC_BCLK_MASTER;
break;
default:
return -EINVAL;
}
codec->write(codec, AD1938_ADC_CTRL2, adc_reg);
codec->write(codec, AD1938_DAC_CTRL1, dac_reg);
return 0;
}
static int ad1938_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
int word_len = 0, reg = 0;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
/* bit size */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
word_len = 3;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
word_len = 1;
break;
case SNDRV_PCM_FORMAT_S24_LE:
case SNDRV_PCM_FORMAT_S32_LE:
word_len = 0;
break;
}
reg = codec->read(codec, AD1938_DAC_CTRL2);
reg = (reg & (~AD1938_DAC_WORD_LEN_MASK)) | word_len;
codec->write(codec, AD1938_DAC_CTRL2, reg);
reg = codec->read(codec, AD1938_ADC_CTRL1);
reg = (reg & (~AD1938_ADC_WORD_LEN_MASK)) | word_len;
codec->write(codec, AD1938_ADC_CTRL1, reg);
return 0;
}
static int ad1938_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
ad1938_pll_powerctrl(codec, 1);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
case SND_SOC_BIAS_OFF:
ad1938_pll_powerctrl(codec, 0);
break;
}
codec->bias_level = level;
return 0;
}
/*
* interface to read/write ad1938 register
*/
#define AD1938_SPI_ADDR 0x4
#define AD1938_SPI_READ 0x1
#define AD1938_SPI_BUFLEN 3
/*
* write to the ad1938 register space
*/
static int ad1938_write_reg(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
u8 *reg_cache = codec->reg_cache;
int ret = 0;
if (value != reg_cache[reg]) {
uint8_t buf[AD1938_SPI_BUFLEN];
struct spi_transfer t = {
.tx_buf = buf,
.len = AD1938_SPI_BUFLEN,
};
struct spi_message m;
buf[0] = AD1938_SPI_ADDR << 1;
buf[1] = reg;
buf[2] = value;
spi_message_init(&m);
spi_message_add_tail(&t, &m);
ret = spi_sync(codec->control_data, &m);
if (ret == 0)
reg_cache[reg] = value;
}
return ret;
}
/*
* read from the ad1938 register space cache
*/
static unsigned int ad1938_read_reg_cache(struct snd_soc_codec *codec,
unsigned int reg)
{
u8 *reg_cache = codec->reg_cache;
if (reg >= codec->reg_cache_size)
return -EINVAL;
return reg_cache[reg];
}
/*
* read from the ad1938 register space
*/
static unsigned int ad1938_read_reg(struct snd_soc_codec *codec,
unsigned int reg)
{
char w_buf[AD1938_SPI_BUFLEN];
char r_buf[AD1938_SPI_BUFLEN];
int ret;
struct spi_transfer t = {
.tx_buf = w_buf,
.rx_buf = r_buf,
.len = AD1938_SPI_BUFLEN,
};
struct spi_message m;
w_buf[0] = (AD1938_SPI_ADDR << 1) | AD1938_SPI_READ;
w_buf[1] = reg;
w_buf[2] = 0;
spi_message_init(&m);
spi_message_add_tail(&t, &m);
ret = spi_sync(codec->control_data, &m);
if (ret == 0)
return r_buf[2];
else
return -EIO;
}
static int ad1938_fill_cache(struct snd_soc_codec *codec)
{
int i;
u8 *reg_cache = codec->reg_cache;
struct spi_device *spi = codec->control_data;
for (i = 0; i < codec->reg_cache_size; i++) {
int ret = ad1938_read_reg(codec, i);
if (ret == -EIO) {
dev_err(&spi->dev, "AD1938 SPI read failure\n");
return ret;
}
reg_cache[i] = ret;
}
return 0;
}
static int __devinit ad1938_spi_probe(struct spi_device *spi)
{
struct snd_soc_codec *codec;
struct ad1938_priv *ad1938;
ad1938 = kzalloc(sizeof(struct ad1938_priv), GFP_KERNEL);
if (ad1938 == NULL)
return -ENOMEM;
codec = &ad1938->codec;
codec->control_data = spi;
codec->dev = &spi->dev;
dev_set_drvdata(&spi->dev, ad1938);
return ad1938_register(ad1938);
}
static int __devexit ad1938_spi_remove(struct spi_device *spi)
{
struct ad1938_priv *ad1938 = dev_get_drvdata(&spi->dev);
ad1938_unregister(ad1938);
return 0;
}
static struct spi_driver ad1938_spi_driver = {
.driver = {
.name = "ad1938",
.owner = THIS_MODULE,
},
.probe = ad1938_spi_probe,
.remove = __devexit_p(ad1938_spi_remove),
};
static struct snd_soc_dai_ops ad1938_dai_ops = {
.hw_params = ad1938_hw_params,
.digital_mute = ad1938_mute,
.set_tdm_slot = ad1938_set_tdm_slot,
.set_fmt = ad1938_set_dai_fmt,
};
/* codec DAI instance */
struct snd_soc_dai ad1938_dai = {
.name = "AD1938",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 4,
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE,
},
.ops = &ad1938_dai_ops,
};
EXPORT_SYMBOL_GPL(ad1938_dai);
static int ad1938_register(struct ad1938_priv *ad1938)
{
int ret;
struct snd_soc_codec *codec = &ad1938->codec;
if (ad1938_codec) {
dev_err(codec->dev, "Another ad1938 is registered\n");
return -EINVAL;
}
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->private_data = ad1938;
codec->reg_cache = ad1938->reg_cache;
codec->reg_cache_size = AD1938_NUM_REGS;
codec->name = "AD1938";
codec->owner = THIS_MODULE;
codec->dai = &ad1938_dai;
codec->num_dai = 1;
codec->write = ad1938_write_reg;
codec->read = ad1938_read_reg_cache;
codec->set_bias_level = ad1938_set_bias_level;
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
ad1938_dai.dev = codec->dev;
ad1938_codec = codec;
/* default setting for ad1938 */
/* unmute dac channels */
codec->write(codec, AD1938_DAC_CHNL_MUTE, 0x0);
/* de-emphasis: 48kHz, powedown dac */
codec->write(codec, AD1938_DAC_CTRL2, 0x1A);
/* powerdown dac, dac in tdm mode */
codec->write(codec, AD1938_DAC_CTRL0, 0x41);
/* high-pass filter enable */
codec->write(codec, AD1938_ADC_CTRL0, 0x3);
/* sata delay=1, adc aux mode */
codec->write(codec, AD1938_ADC_CTRL1, 0x43);
/* pll input: mclki/xi */
codec->write(codec, AD1938_PLL_CLK_CTRL0, 0x9D);
codec->write(codec, AD1938_PLL_CLK_CTRL1, 0x04);
ad1938_fill_cache(codec);
ret = snd_soc_register_codec(codec);
if (ret != 0) {
dev_err(codec->dev, "Failed to register codec: %d\n", ret);
kfree(ad1938);
return ret;
}
ret = snd_soc_register_dai(&ad1938_dai);
if (ret != 0) {
dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
snd_soc_unregister_codec(codec);
kfree(ad1938);
return ret;
}
return 0;
}
static void ad1938_unregister(struct ad1938_priv *ad1938)
{
ad1938_set_bias_level(&ad1938->codec, SND_SOC_BIAS_OFF);
snd_soc_unregister_dai(&ad1938_dai);
snd_soc_unregister_codec(&ad1938->codec);
kfree(ad1938);
ad1938_codec = NULL;
}
static int ad1938_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
if (ad1938_codec == NULL) {
dev_err(&pdev->dev, "Codec device not registered\n");
return -ENODEV;
}
socdev->card->codec = ad1938_codec;
codec = ad1938_codec;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms: %d\n", ret);
goto pcm_err;
}
snd_soc_add_controls(codec, ad1938_snd_controls,
ARRAY_SIZE(ad1938_snd_controls));
snd_soc_dapm_new_controls(codec, ad1938_dapm_widgets,
ARRAY_SIZE(ad1938_dapm_widgets));
snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
snd_soc_dapm_new_widgets(codec);
ad1938_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(codec->dev, "failed to register card: %d\n", ret);
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
return ret;
}
/* power down chip */
static int ad1938_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
return 0;
}
#ifdef CONFIG_PM
static int ad1938_suspend(struct platform_device *pdev,
pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
ad1938_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int ad1938_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
if (codec->suspend_bias_level == SND_SOC_BIAS_ON)
ad1938_set_bias_level(codec, SND_SOC_BIAS_ON);
return 0;
}
#else
#define ad1938_suspend NULL
#define ad1938_resume NULL
#endif
struct snd_soc_codec_device soc_codec_dev_ad1938 = {
.probe = ad1938_probe,
.remove = ad1938_remove,
.suspend = ad1938_suspend,
.resume = ad1938_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_ad1938);
static int __init ad1938_init(void)
{
int ret;
ret = spi_register_driver(&ad1938_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register ad1938 SPI driver: %d\n",
ret);
}
return ret;
}
module_init(ad1938_init);
static void __exit ad1938_exit(void)
{
spi_unregister_driver(&ad1938_spi_driver);
}
module_exit(ad1938_exit);
MODULE_DESCRIPTION("ASoC ad1938 driver");
MODULE_AUTHOR("Barry Song ");
MODULE_LICENSE("GPL");

100
kernel/sound/soc/codecs/ad1938.h Normal file
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/*
* File: sound/soc/codecs/ad1836.h
* Based on:
* Author: Barry Song <Barry.Song@analog.com>
*
* Created: May 25, 2009
* Description: definitions for AD1938 registers
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __AD1938_H__
#define __AD1938_H__
#define AD1938_PLL_CLK_CTRL0 0
#define AD1938_PLL_POWERDOWN 0x01
#define AD1938_PLL_CLK_CTRL1 1
#define AD1938_DAC_CTRL0 2
#define AD1938_DAC_POWERDOWN 0x01
#define AD1938_DAC_SERFMT_MASK 0xC0
#define AD1938_DAC_SERFMT_STEREO (0 << 6)
#define AD1938_DAC_SERFMT_TDM (1 << 6)
#define AD1938_DAC_CTRL1 3
#define AD1938_DAC_2_CHANNELS 0
#define AD1938_DAC_4_CHANNELS 1
#define AD1938_DAC_8_CHANNELS 2
#define AD1938_DAC_16_CHANNELS 3
#define AD1938_DAC_CHAN_SHFT 1
#define AD1938_DAC_CHAN_MASK (3 << AD1938_DAC_CHAN_SHFT)
#define AD1938_DAC_LCR_MASTER (1 << 4)
#define AD1938_DAC_BCLK_MASTER (1 << 5)
#define AD1938_DAC_LEFT_HIGH (1 << 3)
#define AD1938_DAC_BCLK_INV (1 << 7)
#define AD1938_DAC_CTRL2 4
#define AD1938_DAC_WORD_LEN_MASK 0xC
#define AD1938_DAC_MASTER_MUTE 1
#define AD1938_DAC_CHNL_MUTE 5
#define AD1938_DACL1_MUTE 0
#define AD1938_DACR1_MUTE 1
#define AD1938_DACL2_MUTE 2
#define AD1938_DACR2_MUTE 3
#define AD1938_DACL3_MUTE 4
#define AD1938_DACR3_MUTE 5
#define AD1938_DACL4_MUTE 6
#define AD1938_DACR4_MUTE 7
#define AD1938_DAC_L1_VOL 6
#define AD1938_DAC_R1_VOL 7
#define AD1938_DAC_L2_VOL 8
#define AD1938_DAC_R2_VOL 9
#define AD1938_DAC_L3_VOL 10
#define AD1938_DAC_R3_VOL 11
#define AD1938_DAC_L4_VOL 12
#define AD1938_DAC_R4_VOL 13
#define AD1938_ADC_CTRL0 14
#define AD1938_ADC_POWERDOWN 0x01
#define AD1938_ADC_HIGHPASS_FILTER 1
#define AD1938_ADCL1_MUTE 2
#define AD1938_ADCR1_MUTE 3
#define AD1938_ADCL2_MUTE 4
#define AD1938_ADCR2_MUTE 5
#define AD1938_ADC_CTRL1 15
#define AD1938_ADC_SERFMT_MASK 0x60
#define AD1938_ADC_SERFMT_STEREO (0 << 5)
#define AD1938_ADC_SERFMT_TDM (1 << 2)
#define AD1938_ADC_SERFMT_AUX (2 << 5)
#define AD1938_ADC_WORD_LEN_MASK 0x3
#define AD1938_ADC_CTRL2 16
#define AD1938_ADC_2_CHANNELS 0
#define AD1938_ADC_4_CHANNELS 1
#define AD1938_ADC_8_CHANNELS 2
#define AD1938_ADC_16_CHANNELS 3
#define AD1938_ADC_CHAN_SHFT 4
#define AD1938_ADC_CHAN_MASK (3 << AD1938_ADC_CHAN_SHFT)
#define AD1938_ADC_LCR_MASTER (1 << 3)
#define AD1938_ADC_BCLK_MASTER (1 << 6)
#define AD1938_ADC_LEFT_HIGH (1 << 2)
#define AD1938_ADC_BCLK_INV (1 << 1)
#define AD1938_NUM_REGS 17
extern struct snd_soc_dai ad1938_dai;
extern struct snd_soc_codec_device soc_codec_dev_ad1938;
#endif

307
kernel/sound/soc/codecs/ad1980.c Normal file
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@@ -0,0 +1,307 @@
/*
* ad1980.c -- ALSA Soc AD1980 codec support
*
* Copyright: Analog Device Inc.
* Author: Roy Huang <roy.huang@analog.com>
* Cliff Cai <cliff.cai@analog.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "ad1980.h"
static unsigned int ac97_read(struct snd_soc_codec *codec,
unsigned int reg);
static int ac97_write(struct snd_soc_codec *codec,
unsigned int reg, unsigned int val);
/*
* AD1980 register cache
*/
static const u16 ad1980_reg[] = {
0x0090, 0x8000, 0x8000, 0x8000, /* 0 - 6 */
0x0000, 0x0000, 0x8008, 0x8008, /* 8 - e */
0x8808, 0x8808, 0x0000, 0x8808, /* 10 - 16 */
0x8808, 0x0000, 0x8000, 0x0000, /* 18 - 1e */
0x0000, 0x0000, 0x0000, 0x0000, /* 20 - 26 */
0x03c7, 0x0000, 0xbb80, 0xbb80, /* 28 - 2e */
0xbb80, 0xbb80, 0x0000, 0x8080, /* 30 - 36 */
0x8080, 0x2000, 0x0000, 0x0000, /* 38 - 3e */
0x0000, 0x0000, 0x0000, 0x0000, /* reserved */
0x0000, 0x0000, 0x0000, 0x0000, /* reserved */
0x0000, 0x0000, 0x0000, 0x0000, /* reserved */
0x0000, 0x0000, 0x0000, 0x0000, /* reserved */
0x8080, 0x0000, 0x0000, 0x0000, /* 60 - 66 */
0x0000, 0x0000, 0x0000, 0x0000, /* reserved */
0x0000, 0x0000, 0x1001, 0x0000, /* 70 - 76 */
0x0000, 0x0000, 0x4144, 0x5370 /* 78 - 7e */
};
static const char *ad1980_rec_sel[] = {"Mic", "CD", "NC", "AUX", "Line",
"Stereo Mix", "Mono Mix", "Phone"};
static const struct soc_enum ad1980_cap_src =
SOC_ENUM_DOUBLE(AC97_REC_SEL, 8, 0, 7, ad1980_rec_sel);
static const struct snd_kcontrol_new ad1980_snd_ac97_controls[] = {
SOC_DOUBLE("Master Playback Volume", AC97_MASTER, 8, 0, 31, 1),
SOC_SINGLE("Master Playback Switch", AC97_MASTER, 15, 1, 1),
SOC_DOUBLE("Headphone Playback Volume", AC97_HEADPHONE, 8, 0, 31, 1),
SOC_SINGLE("Headphone Playback Switch", AC97_HEADPHONE, 15, 1, 1),
SOC_DOUBLE("PCM Playback Volume", AC97_PCM, 8, 0, 31, 1),
SOC_SINGLE("PCM Playback Switch", AC97_PCM, 15, 1, 1),
SOC_DOUBLE("PCM Capture Volume", AC97_REC_GAIN, 8, 0, 31, 0),
SOC_SINGLE("PCM Capture Switch", AC97_REC_GAIN, 15, 1, 1),
SOC_SINGLE("Mono Playback Volume", AC97_MASTER_MONO, 0, 31, 1),
SOC_SINGLE("Mono Playback Switch", AC97_MASTER_MONO, 15, 1, 1),
SOC_SINGLE("Phone Capture Volume", AC97_PHONE, 0, 31, 1),
SOC_SINGLE("Phone Capture Switch", AC97_PHONE, 15, 1, 1),
SOC_SINGLE("Mic Volume", AC97_MIC, 0, 31, 1),
SOC_SINGLE("Mic Switch", AC97_MIC, 15, 1, 1),
SOC_SINGLE("Stereo Mic Switch", AC97_AD_MISC, 6, 1, 0),
SOC_DOUBLE("Line HP Swap Switch", AC97_AD_MISC, 10, 5, 1, 0),
SOC_DOUBLE("Surround Playback Volume", AC97_SURROUND_MASTER, 8, 0, 31, 1),
SOC_DOUBLE("Surround Playback Switch", AC97_SURROUND_MASTER, 15, 7, 1, 1),
SOC_DOUBLE("Center/LFE Playback Volume", AC97_CENTER_LFE_MASTER, 8, 0, 31, 1),
SOC_DOUBLE("Center/LFE Playback Switch", AC97_CENTER_LFE_MASTER, 15, 7, 1, 1),
SOC_ENUM("Capture Source", ad1980_cap_src),
SOC_SINGLE("Mic Boost Switch", AC97_MIC, 6, 1, 0),
};
static unsigned int ac97_read(struct snd_soc_codec *codec,
unsigned int reg)
{
u16 *cache = codec->reg_cache;
switch (reg) {
case AC97_RESET:
case AC97_INT_PAGING:
case AC97_POWERDOWN:
case AC97_EXTENDED_STATUS:
case AC97_VENDOR_ID1:
case AC97_VENDOR_ID2:
return soc_ac97_ops.read(codec->ac97, reg);
default:
reg = reg >> 1;
if (reg >= ARRAY_SIZE(ad1980_reg))
return -EINVAL;
return cache[reg];
}
}
static int ac97_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int val)
{
u16 *cache = codec->reg_cache;
soc_ac97_ops.write(codec->ac97, reg, val);
reg = reg >> 1;
if (reg < ARRAY_SIZE(ad1980_reg))
cache[reg] = val;
return 0;
}
struct snd_soc_dai ad1980_dai = {
.name = "AC97",
.ac97_control = 1,
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 6,
.rates = SNDRV_PCM_RATE_48000,
.formats = SND_SOC_STD_AC97_FMTS, },
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.formats = SND_SOC_STD_AC97_FMTS, },
};
EXPORT_SYMBOL_GPL(ad1980_dai);
static int ad1980_reset(struct snd_soc_codec *codec, int try_warm)
{
u16 retry_cnt = 0;
retry:
if (try_warm && soc_ac97_ops.warm_reset) {
soc_ac97_ops.warm_reset(codec->ac97);
if (ac97_read(codec, AC97_RESET) == 0x0090)
return 1;
}
soc_ac97_ops.reset(codec->ac97);
/* Set bit 16slot in register 74h, then every slot will has only 16
* bits. This command is sent out in 20bit mode, in which case the
* first nibble of data is eaten by the addr. (Tag is always 16 bit)*/
ac97_write(codec, AC97_AD_SERIAL_CFG, 0x9900);
if (ac97_read(codec, AC97_RESET) != 0x0090)
goto err;
return 0;
err:
while (retry_cnt++ < 10)
goto retry;
printk(KERN_ERR "AD1980 AC97 reset failed\n");
return -EIO;
}
static int ad1980_soc_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
u16 vendor_id2;
u16 ext_status;
printk(KERN_INFO "AD1980 SoC Audio Codec\n");
socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
if (socdev->card->codec == NULL)
return -ENOMEM;
codec = socdev->card->codec;
mutex_init(&codec->mutex);
codec->reg_cache =
kzalloc(sizeof(u16) * ARRAY_SIZE(ad1980_reg), GFP_KERNEL);
if (codec->reg_cache == NULL) {
ret = -ENOMEM;
goto cache_err;
}
memcpy(codec->reg_cache, ad1980_reg, sizeof(u16) * \
ARRAY_SIZE(ad1980_reg));
codec->reg_cache_size = sizeof(u16) * ARRAY_SIZE(ad1980_reg);
codec->reg_cache_step = 2;
codec->name = "AD1980";
codec->owner = THIS_MODULE;
codec->dai = &ad1980_dai;
codec->num_dai = 1;
codec->write = ac97_write;
codec->read = ac97_read;
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
ret = snd_soc_new_ac97_codec(codec, &soc_ac97_ops, 0);
if (ret < 0) {
printk(KERN_ERR "ad1980: failed to register AC97 codec\n");
goto codec_err;
}
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0)
goto pcm_err;
ret = ad1980_reset(codec, 0);
if (ret < 0) {
printk(KERN_ERR "Failed to reset AD1980: AC97 link error\n");
goto reset_err;
}
/* Read out vendor ID to make sure it is ad1980 */
if (ac97_read(codec, AC97_VENDOR_ID1) != 0x4144)
goto reset_err;
vendor_id2 = ac97_read(codec, AC97_VENDOR_ID2);
if (vendor_id2 != 0x5370) {
if (vendor_id2 != 0x5374)
goto reset_err;
else
printk(KERN_WARNING "ad1980: "
"Found AD1981 - only 2/2 IN/OUT Channels "
"supported\n");
}
/* unmute captures and playbacks volume */
ac97_write(codec, AC97_MASTER, 0x0000);
ac97_write(codec, AC97_PCM, 0x0000);
ac97_write(codec, AC97_REC_GAIN, 0x0000);
ac97_write(codec, AC97_CENTER_LFE_MASTER, 0x0000);
ac97_write(codec, AC97_SURROUND_MASTER, 0x0000);
/*power on LFE/CENTER/Surround DACs*/
ext_status = ac97_read(codec, AC97_EXTENDED_STATUS);
ac97_write(codec, AC97_EXTENDED_STATUS, ext_status&~0x3800);
snd_soc_add_controls(codec, ad1980_snd_ac97_controls,
ARRAY_SIZE(ad1980_snd_ac97_controls));
ret = snd_soc_init_card(socdev);
if (ret < 0) {
printk(KERN_ERR "ad1980: failed to register card\n");
goto reset_err;
}
return 0;
reset_err:
snd_soc_free_pcms(socdev);
pcm_err:
snd_soc_free_ac97_codec(codec);
codec_err:
kfree(codec->reg_cache);
cache_err:
kfree(socdev->card->codec);
socdev->card->codec = NULL;
return ret;
}
static int ad1980_soc_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
if (codec == NULL)
return 0;
snd_soc_dapm_free(socdev);
snd_soc_free_pcms(socdev);
snd_soc_free_ac97_codec(codec);
kfree(codec->reg_cache);
kfree(codec);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_ad1980 = {
.probe = ad1980_soc_probe,
.remove = ad1980_soc_remove,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_ad1980);
MODULE_DESCRIPTION("ASoC ad1980 driver");
MODULE_AUTHOR("Roy Huang, Cliff Cai");
MODULE_LICENSE("GPL");

23
kernel/sound/soc/codecs/ad1980.h Normal file
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/*
* ad1980.h -- ad1980 Soc Audio driver
*/
#ifndef _AD1980_H
#define _AD1980_H
/* Bit definition of Power-Down Control/Status Register */
#define ADC 0x0001
#define DAC 0x0002
#define ANL 0x0004
#define REF 0x0008
#define PR0 0x0100
#define PR1 0x0200
#define PR2 0x0400
#define PR3 0x0800
#define PR4 0x1000
#define PR5 0x2000
#define PR6 0x4000
extern struct snd_soc_dai ad1980_dai;
extern struct snd_soc_codec_device soc_codec_dev_ad1980;
#endif

115
kernel/sound/soc/codecs/ad73311.c Normal file
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/*
* ad73311.c -- ALSA Soc AD73311 codec support
*
* Copyright: Analog Device Inc.
* Author: Cliff Cai <cliff.cai@analog.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include "ad73311.h"
struct snd_soc_dai ad73311_dai = {
.name = "AD73311",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE, },
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE, },
};
EXPORT_SYMBOL_GPL(ad73311_dai);
static int ad73311_soc_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
if (codec == NULL)
return -ENOMEM;
mutex_init(&codec->mutex);
codec->name = "AD73311";
codec->owner = THIS_MODULE;
codec->dai = &ad73311_dai;
codec->num_dai = 1;
socdev->card->codec = codec;
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
printk(KERN_ERR "ad73311: failed to create pcms\n");
goto pcm_err;
}
ret = snd_soc_init_card(socdev);
if (ret < 0) {
printk(KERN_ERR "ad73311: failed to register card\n");
goto register_err;
}
return ret;
register_err:
snd_soc_free_pcms(socdev);
pcm_err:
kfree(socdev->card->codec);
socdev->card->codec = NULL;
return ret;
}
static int ad73311_soc_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
if (codec == NULL)
return 0;
snd_soc_free_pcms(socdev);
kfree(codec);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_ad73311 = {
.probe = ad73311_soc_probe,
.remove = ad73311_soc_remove,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_ad73311);
static int __init ad73311_init(void)
{
return snd_soc_register_dai(&ad73311_dai);
}
module_init(ad73311_init);
static void __exit ad73311_exit(void)
{
snd_soc_unregister_dai(&ad73311_dai);
}
module_exit(ad73311_exit);
MODULE_DESCRIPTION("ASoC ad73311 driver");
MODULE_AUTHOR("Cliff Cai ");
MODULE_LICENSE("GPL");

90
kernel/sound/soc/codecs/ad73311.h Normal file
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/*
* File: sound/soc/codec/ad73311.h
* Based on:
* Author: Cliff Cai <cliff.cai@analog.com>
*
* Created: Thur Sep 25, 2008
* Description: definitions for AD73311 registers
*
*
* Modified:
* Copyright 2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __AD73311_H__
#define __AD73311_H__
#define AD_CONTROL 0x8000
#define AD_DATA 0x0000
#define AD_READ 0x4000
#define AD_WRITE 0x0000
/* Control register A */
#define CTRL_REG_A (0 << 8)
#define REGA_MODE_PRO 0x00
#define REGA_MODE_DATA 0x01
#define REGA_MODE_MIXED 0x03
#define REGA_DLB 0x04
#define REGA_SLB 0x08
#define REGA_DEVC(x) ((x & 0x7) << 4)
#define REGA_RESET 0x80
/* Control register B */
#define CTRL_REG_B (1 << 8)
#define REGB_DIRATE(x) (x & 0x3)
#define REGB_SCDIV(x) ((x & 0x3) << 2)
#define REGB_MCDIV(x) ((x & 0x7) << 4)
#define REGB_CEE (1 << 7)
/* Control register C */
#define CTRL_REG_C (2 << 8)
#define REGC_PUDEV (1 << 0)
#define REGC_PUADC (1 << 3)
#define REGC_PUDAC (1 << 4)
#define REGC_PUREF (1 << 5)
#define REGC_REFUSE (1 << 6)
/* Control register D */
#define CTRL_REG_D (3 << 8)
#define REGD_IGS(x) (x & 0x7)
#define REGD_RMOD (1 << 3)
#define REGD_OGS(x) ((x & 0x7) << 4)
#define REGD_MUTE (1 << 7)
/* Control register E */
#define CTRL_REG_E (4 << 8)
#define REGE_DA(x) (x & 0x1f)
#define REGE_IBYP (1 << 5)
/* Control register F */
#define CTRL_REG_F (5 << 8)
#define REGF_SEEN (1 << 5)
#define REGF_INV (1 << 6)
#define REGF_ALB (1 << 7)
extern struct snd_soc_dai ad73311_dai;
extern struct snd_soc_codec_device soc_codec_dev_ad73311;
#endif

363
kernel/sound/soc/codecs/ak4104.c Normal file
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/*
* AK4104 ALSA SoC (ASoC) driver
*
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <linux/spi/spi.h>
#include <sound/asoundef.h>
#include "ak4104.h"
/* AK4104 registers addresses */
#define AK4104_REG_CONTROL1 0x00
#define AK4104_REG_RESERVED 0x01
#define AK4104_REG_CONTROL2 0x02
#define AK4104_REG_TX 0x03
#define AK4104_REG_CHN_STATUS(x) ((x) + 0x04)
#define AK4104_NUM_REGS 10
#define AK4104_REG_MASK 0x1f
#define AK4104_READ 0xc0
#define AK4104_WRITE 0xe0
#define AK4104_RESERVED_VAL 0x5b
/* Bit masks for AK4104 registers */
#define AK4104_CONTROL1_RSTN (1 << 0)
#define AK4104_CONTROL1_PW (1 << 1)
#define AK4104_CONTROL1_DIF0 (1 << 2)
#define AK4104_CONTROL1_DIF1 (1 << 3)
#define AK4104_CONTROL2_SEL0 (1 << 0)
#define AK4104_CONTROL2_SEL1 (1 << 1)
#define AK4104_CONTROL2_MODE (1 << 2)
#define AK4104_TX_TXE (1 << 0)
#define AK4104_TX_V (1 << 1)
#define DRV_NAME "ak4104"
struct ak4104_private {
struct snd_soc_codec codec;
u8 reg_cache[AK4104_NUM_REGS];
};
static int ak4104_fill_cache(struct snd_soc_codec *codec)
{
int i;
u8 *reg_cache = codec->reg_cache;
struct spi_device *spi = codec->control_data;
for (i = 0; i < codec->reg_cache_size; i++) {
int ret = spi_w8r8(spi, i | AK4104_READ);
if (ret < 0) {
dev_err(&spi->dev, "SPI write failure\n");
return ret;
}
reg_cache[i] = ret;
}
return 0;
}
static unsigned int ak4104_read_reg_cache(struct snd_soc_codec *codec,
unsigned int reg)
{
u8 *reg_cache = codec->reg_cache;
if (reg >= codec->reg_cache_size)
return -EINVAL;
return reg_cache[reg];
}
static int ak4104_spi_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
u8 *cache = codec->reg_cache;
struct spi_device *spi = codec->control_data;
if (reg >= codec->reg_cache_size)
return -EINVAL;
/* only write to the hardware if value has changed */
if (cache[reg] != value) {
u8 tmp[2] = { (reg & AK4104_REG_MASK) | AK4104_WRITE, value };
if (spi_write(spi, tmp, sizeof(tmp))) {
dev_err(&spi->dev, "SPI write failed\n");
return -EIO;
}
cache[reg] = value;
}
return 0;
}
static int ak4104_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_codec *codec = codec_dai->codec;
int val = 0;
val = ak4104_read_reg_cache(codec, AK4104_REG_CONTROL1);
if (val < 0)
return val;
val &= ~(AK4104_CONTROL1_DIF0 | AK4104_CONTROL1_DIF1);
/* set DAI format */
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
val |= AK4104_CONTROL1_DIF0;
break;
case SND_SOC_DAIFMT_I2S:
val |= AK4104_CONTROL1_DIF0 | AK4104_CONTROL1_DIF1;
break;
default:
dev_err(codec->dev, "invalid dai format\n");
return -EINVAL;
}
/* This device can only be slave */
if ((format & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
return -EINVAL;
return ak4104_spi_write(codec, AK4104_REG_CONTROL1, val);
}
static int ak4104_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
int val = 0;
/* set the IEC958 bits: consumer mode, no copyright bit */
val |= IEC958_AES0_CON_NOT_COPYRIGHT;
ak4104_spi_write(codec, AK4104_REG_CHN_STATUS(0), val);
val = 0;
switch (params_rate(params)) {
case 44100:
val |= IEC958_AES3_CON_FS_44100;
break;
case 48000:
val |= IEC958_AES3_CON_FS_48000;
break;
case 32000:
val |= IEC958_AES3_CON_FS_32000;
break;
default:
dev_err(codec->dev, "unsupported sampling rate\n");
return -EINVAL;
}
return ak4104_spi_write(codec, AK4104_REG_CHN_STATUS(3), val);
}
static struct snd_soc_dai_ops ak4101_dai_ops = {
.hw_params = ak4104_hw_params,
.set_fmt = ak4104_set_dai_fmt,
};
struct snd_soc_dai ak4104_dai = {
.name = DRV_NAME,
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_32000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_3LE |
SNDRV_PCM_FMTBIT_S24_LE
},
.ops = &ak4101_dai_ops,
};
static struct snd_soc_codec *ak4104_codec;
static int ak4104_spi_probe(struct spi_device *spi)
{
struct snd_soc_codec *codec;
struct ak4104_private *ak4104;
int ret, val;
spi->bits_per_word = 8;
spi->mode = SPI_MODE_0;
ret = spi_setup(spi);
if (ret < 0)
return ret;
ak4104 = kzalloc(sizeof(struct ak4104_private), GFP_KERNEL);
if (!ak4104) {
dev_err(&spi->dev, "could not allocate codec\n");
return -ENOMEM;
}
codec = &ak4104->codec;
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->dev = &spi->dev;
codec->name = DRV_NAME;
codec->owner = THIS_MODULE;
codec->dai = &ak4104_dai;
codec->num_dai = 1;
codec->private_data = ak4104;
codec->control_data = spi;
codec->reg_cache = ak4104->reg_cache;
codec->reg_cache_size = AK4104_NUM_REGS;
/* read all regs and fill the cache */
ret = ak4104_fill_cache(codec);
if (ret < 0) {
dev_err(&spi->dev, "failed to fill register cache\n");
return ret;
}
/* read the 'reserved' register - according to the datasheet, it
* should contain 0x5b. Not a good way to verify the presence of
* the device, but there is no hardware ID register. */
if (ak4104_read_reg_cache(codec, AK4104_REG_RESERVED) !=
AK4104_RESERVED_VAL) {
ret = -ENODEV;
goto error_free_codec;
}
/* set power-up and non-reset bits */
val = ak4104_read_reg_cache(codec, AK4104_REG_CONTROL1);
val |= AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN;
ret = ak4104_spi_write(codec, AK4104_REG_CONTROL1, val);
if (ret < 0)
goto error_free_codec;
/* enable transmitter */
val = ak4104_read_reg_cache(codec, AK4104_REG_TX);
val |= AK4104_TX_TXE;
ret = ak4104_spi_write(codec, AK4104_REG_TX, val);
if (ret < 0)
goto error_free_codec;
ak4104_codec = codec;
ret = snd_soc_register_dai(&ak4104_dai);
if (ret < 0) {
dev_err(&spi->dev, "failed to register DAI\n");
goto error_free_codec;
}
spi_set_drvdata(spi, ak4104);
dev_info(&spi->dev, "SPI device initialized\n");
return 0;
error_free_codec:
kfree(ak4104);
ak4104_dai.dev = NULL;
return ret;
}
static int __devexit ak4104_spi_remove(struct spi_device *spi)
{
int ret, val;
struct ak4104_private *ak4104 = spi_get_drvdata(spi);
val = ak4104_read_reg_cache(&ak4104->codec, AK4104_REG_CONTROL1);
if (val < 0)
return val;
/* clear power-up and non-reset bits */
val &= ~(AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN);
ret = ak4104_spi_write(&ak4104->codec, AK4104_REG_CONTROL1, val);
if (ret < 0)
return ret;
ak4104_codec = NULL;
kfree(ak4104);
return 0;
}
static int ak4104_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = ak4104_codec;
int ret;
/* Connect the codec to the socdev. snd_soc_new_pcms() needs this. */
socdev->card->codec = codec;
/* Register PCMs */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms\n");
return ret;
}
/* Register the socdev */
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(codec->dev, "failed to register card\n");
snd_soc_free_pcms(socdev);
return ret;
}
return 0;
}
static int ak4104_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
return 0;
};
struct snd_soc_codec_device soc_codec_device_ak4104 = {
.probe = ak4104_probe,
.remove = ak4104_remove
};
EXPORT_SYMBOL_GPL(soc_codec_device_ak4104);
static struct spi_driver ak4104_spi_driver = {
.driver = {
.name = DRV_NAME,
.owner = THIS_MODULE,
},
.probe = ak4104_spi_probe,
.remove = __devexit_p(ak4104_spi_remove),
};
static int __init ak4104_init(void)
{
pr_info("Asahi Kasei AK4104 ALSA SoC Codec Driver\n");
return spi_register_driver(&ak4104_spi_driver);
}
module_init(ak4104_init);
static void __exit ak4104_exit(void)
{
spi_unregister_driver(&ak4104_spi_driver);
}
module_exit(ak4104_exit);
MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
MODULE_DESCRIPTION("Asahi Kasei AK4104 ALSA SoC driver");
MODULE_LICENSE("GPL");

7
kernel/sound/soc/codecs/ak4104.h Normal file
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#ifndef _AK4104_H
#define _AK4104_H
extern struct snd_soc_dai ak4104_dai;
extern struct snd_soc_codec_device soc_codec_device_ak4104;
#endif

678
kernel/sound/soc/codecs/ak4535.c Normal file
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/*
* ak4535.c -- AK4535 ALSA Soc Audio driver
*
* Copyright 2005 Openedhand Ltd.
*
* Author: Richard Purdie <richard@openedhand.com>
*
* Based on wm8753.c by Liam Girdwood
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include "ak4535.h"
#define AK4535_VERSION "0.3"
struct snd_soc_codec_device soc_codec_dev_ak4535;
/* codec private data */
struct ak4535_priv {
unsigned int sysclk;
};
/*
* ak4535 register cache
*/
static const u16 ak4535_reg[AK4535_CACHEREGNUM] = {
0x0000, 0x0080, 0x0000, 0x0003,
0x0002, 0x0000, 0x0011, 0x0001,
0x0000, 0x0040, 0x0036, 0x0010,
0x0000, 0x0000, 0x0057, 0x0000,
};
/*
* read ak4535 register cache
*/
static inline unsigned int ak4535_read_reg_cache(struct snd_soc_codec *codec,
unsigned int reg)
{
u16 *cache = codec->reg_cache;
if (reg >= AK4535_CACHEREGNUM)
return -1;
return cache[reg];
}
/*
* write ak4535 register cache
*/
static inline void ak4535_write_reg_cache(struct snd_soc_codec *codec,
u16 reg, unsigned int value)
{
u16 *cache = codec->reg_cache;
if (reg >= AK4535_CACHEREGNUM)
return;
cache[reg] = value;
}
/*
* write to the AK4535 register space
*/
static int ak4535_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
u8 data[2];
/* data is
* D15..D8 AK4535 register offset
* D7...D0 register data
*/
data[0] = reg & 0xff;
data[1] = value & 0xff;
ak4535_write_reg_cache(codec, reg, value);
if (codec->hw_write(codec->control_data, data, 2) == 2)
return 0;
else
return -EIO;
}
static int ak4535_sync(struct snd_soc_codec *codec)
{
u16 *cache = codec->reg_cache;
int i, r = 0;
for (i = 0; i < AK4535_CACHEREGNUM; i++)
r |= ak4535_write(codec, i, cache[i]);
return r;
};
static const char *ak4535_mono_gain[] = {"+6dB", "-17dB"};
static const char *ak4535_mono_out[] = {"(L + R)/2", "Hi-Z"};
static const char *ak4535_hp_out[] = {"Stereo", "Mono"};
static const char *ak4535_deemp[] = {"44.1kHz", "Off", "48kHz", "32kHz"};
static const char *ak4535_mic_select[] = {"Internal", "External"};
static const struct soc_enum ak4535_enum[] = {
SOC_ENUM_SINGLE(AK4535_SIG1, 7, 2, ak4535_mono_gain),
SOC_ENUM_SINGLE(AK4535_SIG1, 6, 2, ak4535_mono_out),
SOC_ENUM_SINGLE(AK4535_MODE2, 2, 2, ak4535_hp_out),
SOC_ENUM_SINGLE(AK4535_DAC, 0, 4, ak4535_deemp),
SOC_ENUM_SINGLE(AK4535_MIC, 1, 2, ak4535_mic_select),
};
static const struct snd_kcontrol_new ak4535_snd_controls[] = {
SOC_SINGLE("ALC2 Switch", AK4535_SIG1, 1, 1, 0),
SOC_ENUM("Mono 1 Output", ak4535_enum[1]),
SOC_ENUM("Mono 1 Gain", ak4535_enum[0]),
SOC_ENUM("Headphone Output", ak4535_enum[2]),
SOC_ENUM("Playback Deemphasis", ak4535_enum[3]),
SOC_SINGLE("Bass Volume", AK4535_DAC, 2, 3, 0),
SOC_SINGLE("Mic Boost (+20dB) Switch", AK4535_MIC, 0, 1, 0),
SOC_ENUM("Mic Select", ak4535_enum[4]),
SOC_SINGLE("ALC Operation Time", AK4535_TIMER, 0, 3, 0),
SOC_SINGLE("ALC Recovery Time", AK4535_TIMER, 2, 3, 0),
SOC_SINGLE("ALC ZC Time", AK4535_TIMER, 4, 3, 0),
SOC_SINGLE("ALC 1 Switch", AK4535_ALC1, 5, 1, 0),
SOC_SINGLE("ALC 2 Switch", AK4535_ALC1, 6, 1, 0),
SOC_SINGLE("ALC Volume", AK4535_ALC2, 0, 127, 0),
SOC_SINGLE("Capture Volume", AK4535_PGA, 0, 127, 0),
SOC_SINGLE("Left Playback Volume", AK4535_LATT, 0, 127, 1),
SOC_SINGLE("Right Playback Volume", AK4535_RATT, 0, 127, 1),
SOC_SINGLE("AUX Bypass Volume", AK4535_VOL, 0, 15, 0),
SOC_SINGLE("Mic Sidetone Volume", AK4535_VOL, 4, 7, 0),
};
/* Mono 1 Mixer */
static const struct snd_kcontrol_new ak4535_mono1_mixer_controls[] = {
SOC_DAPM_SINGLE("Mic Sidetone Switch", AK4535_SIG1, 4, 1, 0),
SOC_DAPM_SINGLE("Mono Playback Switch", AK4535_SIG1, 5, 1, 0),
};
/* Stereo Mixer */
static const struct snd_kcontrol_new ak4535_stereo_mixer_controls[] = {
SOC_DAPM_SINGLE("Mic Sidetone Switch", AK4535_SIG2, 4, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", AK4535_SIG2, 7, 1, 0),
SOC_DAPM_SINGLE("Aux Bypass Switch", AK4535_SIG2, 5, 1, 0),
};
/* Input Mixer */
static const struct snd_kcontrol_new ak4535_input_mixer_controls[] = {
SOC_DAPM_SINGLE("Mic Capture Switch", AK4535_MIC, 2, 1, 0),
SOC_DAPM_SINGLE("Aux Capture Switch", AK4535_MIC, 5, 1, 0),
};
/* Input mux */
static const struct snd_kcontrol_new ak4535_input_mux_control =
SOC_DAPM_ENUM("Input Select", ak4535_enum[4]);
/* HP L switch */
static const struct snd_kcontrol_new ak4535_hpl_control =
SOC_DAPM_SINGLE("Switch", AK4535_SIG2, 1, 1, 1);
/* HP R switch */
static const struct snd_kcontrol_new ak4535_hpr_control =
SOC_DAPM_SINGLE("Switch", AK4535_SIG2, 0, 1, 1);
/* mono 2 switch */
static const struct snd_kcontrol_new ak4535_mono2_control =
SOC_DAPM_SINGLE("Switch", AK4535_SIG1, 0, 1, 0);
/* Line out switch */
static const struct snd_kcontrol_new ak4535_line_control =
SOC_DAPM_SINGLE("Switch", AK4535_SIG2, 6, 1, 0);
/* ak4535 dapm widgets */
static const struct snd_soc_dapm_widget ak4535_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Stereo Mixer", SND_SOC_NOPM, 0, 0,
&ak4535_stereo_mixer_controls[0],
ARRAY_SIZE(ak4535_stereo_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono1 Mixer", SND_SOC_NOPM, 0, 0,
&ak4535_mono1_mixer_controls[0],
ARRAY_SIZE(ak4535_mono1_mixer_controls)),
SND_SOC_DAPM_MIXER("Input Mixer", SND_SOC_NOPM, 0, 0,
&ak4535_input_mixer_controls[0],
ARRAY_SIZE(ak4535_input_mixer_controls)),
SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
&ak4535_input_mux_control),
SND_SOC_DAPM_DAC("DAC", "Playback", AK4535_PM2, 0, 0),
SND_SOC_DAPM_SWITCH("Mono 2 Enable", SND_SOC_NOPM, 0, 0,
&ak4535_mono2_control),
/* speaker powersave bit */
SND_SOC_DAPM_PGA("Speaker Enable", AK4535_MODE2, 0, 0, NULL, 0),
SND_SOC_DAPM_SWITCH("Line Out Enable", SND_SOC_NOPM, 0, 0,
&ak4535_line_control),
SND_SOC_DAPM_SWITCH("Left HP Enable", SND_SOC_NOPM, 0, 0,
&ak4535_hpl_control),
SND_SOC_DAPM_SWITCH("Right HP Enable", SND_SOC_NOPM, 0, 0,
&ak4535_hpr_control),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("SPP"),
SND_SOC_DAPM_OUTPUT("SPN"),
SND_SOC_DAPM_OUTPUT("MOUT1"),
SND_SOC_DAPM_OUTPUT("MOUT2"),
SND_SOC_DAPM_OUTPUT("MICOUT"),
SND_SOC_DAPM_ADC("ADC", "Capture", AK4535_PM1, 0, 0),
SND_SOC_DAPM_PGA("Spk Amp", AK4535_PM2, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("HP R Amp", AK4535_PM2, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("HP L Amp", AK4535_PM2, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mic", AK4535_PM1, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("Line Out", AK4535_PM1, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out", AK4535_PM1, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("AUX In", AK4535_PM1, 2, 0, NULL, 0),
SND_SOC_DAPM_MICBIAS("Mic Int Bias", AK4535_MIC, 3, 0),
SND_SOC_DAPM_MICBIAS("Mic Ext Bias", AK4535_MIC, 4, 0),
SND_SOC_DAPM_INPUT("MICIN"),
SND_SOC_DAPM_INPUT("MICEXT"),
SND_SOC_DAPM_INPUT("AUX"),
SND_SOC_DAPM_INPUT("MIN"),
SND_SOC_DAPM_INPUT("AIN"),
};
static const struct snd_soc_dapm_route audio_map[] = {
/*stereo mixer */
{"Stereo Mixer", "Playback Switch", "DAC"},
{"Stereo Mixer", "Mic Sidetone Switch", "Mic"},
{"Stereo Mixer", "Aux Bypass Switch", "AUX In"},
/* mono1 mixer */
{"Mono1 Mixer", "Mic Sidetone Switch", "Mic"},
{"Mono1 Mixer", "Mono Playback Switch", "DAC"},
/* Mic */
{"Mic", NULL, "AIN"},
{"Input Mux", "Internal", "Mic Int Bias"},
{"Input Mux", "External", "Mic Ext Bias"},
{"Mic Int Bias", NULL, "MICIN"},
{"Mic Ext Bias", NULL, "MICEXT"},
{"MICOUT", NULL, "Input Mux"},
/* line out */
{"LOUT", NULL, "Line Out Enable"},
{"ROUT", NULL, "Line Out Enable"},
{"Line Out Enable", "Switch", "Line Out"},
{"Line Out", NULL, "Stereo Mixer"},
/* mono1 out */
{"MOUT1", NULL, "Mono Out"},
{"Mono Out", NULL, "Mono1 Mixer"},
/* left HP */
{"HPL", NULL, "Left HP Enable"},
{"Left HP Enable", "Switch", "HP L Amp"},
{"HP L Amp", NULL, "Stereo Mixer"},
/* right HP */
{"HPR", NULL, "Right HP Enable"},
{"Right HP Enable", "Switch", "HP R Amp"},
{"HP R Amp", NULL, "Stereo Mixer"},
/* speaker */
{"SPP", NULL, "Speaker Enable"},
{"SPN", NULL, "Speaker Enable"},
{"Speaker Enable", "Switch", "Spk Amp"},
{"Spk Amp", NULL, "MIN"},
/* mono 2 */
{"MOUT2", NULL, "Mono 2 Enable"},
{"Mono 2 Enable", "Switch", "Stereo Mixer"},
/* Aux In */
{"Aux In", NULL, "AUX"},
/* ADC */
{"ADC", NULL, "Input Mixer"},
{"Input Mixer", "Mic Capture Switch", "Mic"},
{"Input Mixer", "Aux Capture Switch", "Aux In"},
};
static int ak4535_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, ak4535_dapm_widgets,
ARRAY_SIZE(ak4535_dapm_widgets));
snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
snd_soc_dapm_new_widgets(codec);
return 0;
}
static int ak4535_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct ak4535_priv *ak4535 = codec->private_data;
ak4535->sysclk = freq;
return 0;
}
static int ak4535_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct ak4535_priv *ak4535 = codec->private_data;
u8 mode2 = ak4535_read_reg_cache(codec, AK4535_MODE2) & ~(0x3 << 5);
int rate = params_rate(params), fs = 256;
if (rate)
fs = ak4535->sysclk / rate;
/* set fs */
switch (fs) {
case 1024:
mode2 |= (0x2 << 5);
break;
case 512:
mode2 |= (0x1 << 5);
break;
case 256:
break;
}
/* set rate */
ak4535_write(codec, AK4535_MODE2, mode2);
return 0;
}
static int ak4535_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u8 mode1 = 0;
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
mode1 = 0x0002;
break;
case SND_SOC_DAIFMT_LEFT_J:
mode1 = 0x0001;
break;
default:
return -EINVAL;
}
/* use 32 fs for BCLK to save power */
mode1 |= 0x4;
ak4535_write(codec, AK4535_MODE1, mode1);
return 0;
}
static int ak4535_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
u16 mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC) & 0xffdf;
if (!mute)
ak4535_write(codec, AK4535_DAC, mute_reg);
else
ak4535_write(codec, AK4535_DAC, mute_reg | 0x20);
return 0;
}
static int ak4535_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
u16 i;
switch (level) {
case SND_SOC_BIAS_ON:
ak4535_mute(codec->dai, 0);
break;
case SND_SOC_BIAS_PREPARE:
ak4535_mute(codec->dai, 1);
break;
case SND_SOC_BIAS_STANDBY:
i = ak4535_read_reg_cache(codec, AK4535_PM1);
ak4535_write(codec, AK4535_PM1, i | 0x80);
i = ak4535_read_reg_cache(codec, AK4535_PM2);
ak4535_write(codec, AK4535_PM2, i & (~0x80));
break;
case SND_SOC_BIAS_OFF:
i = ak4535_read_reg_cache(codec, AK4535_PM1);
ak4535_write(codec, AK4535_PM1, i & (~0x80));
break;
}
codec->bias_level = level;
return 0;
}
#define AK4535_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
static struct snd_soc_dai_ops ak4535_dai_ops = {
.hw_params = ak4535_hw_params,
.set_fmt = ak4535_set_dai_fmt,
.digital_mute = ak4535_mute,
.set_sysclk = ak4535_set_dai_sysclk,
};
struct snd_soc_dai ak4535_dai = {
.name = "AK4535",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = AK4535_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = AK4535_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.ops = &ak4535_dai_ops,
};
EXPORT_SYMBOL_GPL(ak4535_dai);
static int ak4535_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
ak4535_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int ak4535_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
ak4535_sync(codec);
ak4535_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
ak4535_set_bias_level(codec, codec->suspend_bias_level);
return 0;
}
/*
* initialise the AK4535 driver
* register the mixer and dsp interfaces with the kernel
*/
static int ak4535_init(struct snd_soc_device *socdev)
{
struct snd_soc_codec *codec = socdev->card->codec;
int ret = 0;
codec->name = "AK4535";
codec->owner = THIS_MODULE;
codec->read = ak4535_read_reg_cache;
codec->write = ak4535_write;
codec->set_bias_level = ak4535_set_bias_level;
codec->dai = &ak4535_dai;
codec->num_dai = 1;
codec->reg_cache_size = ARRAY_SIZE(ak4535_reg);
codec->reg_cache = kmemdup(ak4535_reg, sizeof(ak4535_reg), GFP_KERNEL);
if (codec->reg_cache == NULL)
return -ENOMEM;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
printk(KERN_ERR "ak4535: failed to create pcms\n");
goto pcm_err;
}
/* power on device */
ak4535_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
snd_soc_add_controls(codec, ak4535_snd_controls,
ARRAY_SIZE(ak4535_snd_controls));
ak4535_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
printk(KERN_ERR "ak4535: failed to register card\n");
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
kfree(codec->reg_cache);
return ret;
}
static struct snd_soc_device *ak4535_socdev;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
static int ak4535_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct snd_soc_device *socdev = ak4535_socdev;
struct snd_soc_codec *codec = socdev->card->codec;
int ret;
i2c_set_clientdata(i2c, codec);
codec->control_data = i2c;
ret = ak4535_init(socdev);
if (ret < 0)
printk(KERN_ERR "failed to initialise AK4535\n");
return ret;
}
static int ak4535_i2c_remove(struct i2c_client *client)
{
struct snd_soc_codec *codec = i2c_get_clientdata(client);
kfree(codec->reg_cache);
return 0;
}
static const struct i2c_device_id ak4535_i2c_id[] = {
{ "ak4535", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ak4535_i2c_id);
static struct i2c_driver ak4535_i2c_driver = {
.driver = {
.name = "AK4535 I2C Codec",
.owner = THIS_MODULE,
},
.probe = ak4535_i2c_probe,
.remove = ak4535_i2c_remove,
.id_table = ak4535_i2c_id,
};
static int ak4535_add_i2c_device(struct platform_device *pdev,
const struct ak4535_setup_data *setup)
{
struct i2c_board_info info;
struct i2c_adapter *adapter;
struct i2c_client *client;
int ret;
ret = i2c_add_driver(&ak4535_i2c_driver);
if (ret != 0) {
dev_err(&pdev->dev, "can't add i2c driver\n");
return ret;
}
memset(&info, 0, sizeof(struct i2c_board_info));
info.addr = setup->i2c_address;
strlcpy(info.type, "ak4535", I2C_NAME_SIZE);
adapter = i2c_get_adapter(setup->i2c_bus);
if (!adapter) {
dev_err(&pdev->dev, "can't get i2c adapter %d\n",
setup->i2c_bus);
goto err_driver;
}
client = i2c_new_device(adapter, &info);
i2c_put_adapter(adapter);
if (!client) {
dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
(unsigned int)info.addr);
goto err_driver;
}
return 0;
err_driver:
i2c_del_driver(&ak4535_i2c_driver);
return -ENODEV;
}
#endif
static int ak4535_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct ak4535_setup_data *setup;
struct snd_soc_codec *codec;
struct ak4535_priv *ak4535;
int ret;
printk(KERN_INFO "AK4535 Audio Codec %s", AK4535_VERSION);
setup = socdev->codec_data;
codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
if (codec == NULL)
return -ENOMEM;
ak4535 = kzalloc(sizeof(struct ak4535_priv), GFP_KERNEL);
if (ak4535 == NULL) {
kfree(codec);
return -ENOMEM;
}
codec->private_data = ak4535;
socdev->card->codec = codec;
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
ak4535_socdev = socdev;
ret = -ENODEV;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
if (setup->i2c_address) {
codec->hw_write = (hw_write_t)i2c_master_send;
ret = ak4535_add_i2c_device(pdev, setup);
}
#endif
if (ret != 0) {
kfree(codec->private_data);
kfree(codec);
}
return ret;
}
/* power down chip */
static int ak4535_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
if (codec->control_data)
ak4535_set_bias_level(codec, SND_SOC_BIAS_OFF);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
if (codec->control_data)
i2c_unregister_device(codec->control_data);
i2c_del_driver(&ak4535_i2c_driver);
#endif
kfree(codec->private_data);
kfree(codec);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_ak4535 = {
.probe = ak4535_probe,
.remove = ak4535_remove,
.suspend = ak4535_suspend,
.resume = ak4535_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_ak4535);
static int __init ak4535_modinit(void)
{
return snd_soc_register_dai(&ak4535_dai);
}
module_init(ak4535_modinit);
static void __exit ak4535_exit(void)
{
snd_soc_unregister_dai(&ak4535_dai);
}
module_exit(ak4535_exit);
MODULE_DESCRIPTION("Soc AK4535 driver");
MODULE_AUTHOR("Richard Purdie");
MODULE_LICENSE("GPL");

47
kernel/sound/soc/codecs/ak4535.h Normal file
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@@ -0,0 +1,47 @@
/*
* ak4535.h -- AK4535 Soc Audio driver
*
* Copyright 2005 Openedhand Ltd.
*
* Author: Richard Purdie <richard@openedhand.com>
*
* Based on wm8753.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _AK4535_H
#define _AK4535_H
/* AK4535 register space */
#define AK4535_PM1 0x0
#define AK4535_PM2 0x1
#define AK4535_SIG1 0x2
#define AK4535_SIG2 0x3
#define AK4535_MODE1 0x4
#define AK4535_MODE2 0x5
#define AK4535_DAC 0x6
#define AK4535_MIC 0x7
#define AK4535_TIMER 0x8
#define AK4535_ALC1 0x9
#define AK4535_ALC2 0xa
#define AK4535_PGA 0xb
#define AK4535_LATT 0xc
#define AK4535_RATT 0xd
#define AK4535_VOL 0xe
#define AK4535_STATUS 0xf
#define AK4535_CACHEREGNUM 0x10
struct ak4535_setup_data {
int i2c_bus;
unsigned short i2c_address;
};
extern struct snd_soc_dai ak4535_dai;
extern struct snd_soc_codec_device soc_codec_dev_ak4535;
#endif

502
kernel/sound/soc/codecs/ak4642.c Normal file
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@@ -0,0 +1,502 @@
/*
* ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
*
* Copyright (C) 2009 Renesas Solutions Corp.
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
*
* Based on wm8731.c by Richard Purdie
* Based on ak4535.c by Richard Purdie
* Based on wm8753.c by Liam Girdwood
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* ** CAUTION **
*
* This is very simple driver.
* It can use headphone output / stereo input only
*
* AK4642 is not tested.
* AK4643 is tested.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include "ak4642.h"
#define AK4642_VERSION "0.0.1"
#define PW_MGMT1 0x00
#define PW_MGMT2 0x01
#define SG_SL1 0x02
#define SG_SL2 0x03
#define MD_CTL1 0x04
#define MD_CTL2 0x05
#define TIMER 0x06
#define ALC_CTL1 0x07
#define ALC_CTL2 0x08
#define L_IVC 0x09
#define L_DVC 0x0a
#define ALC_CTL3 0x0b
#define R_IVC 0x0c
#define R_DVC 0x0d
#define MD_CTL3 0x0e
#define MD_CTL4 0x0f
#define PW_MGMT3 0x10
#define DF_S 0x11
#define FIL3_0 0x12
#define FIL3_1 0x13
#define FIL3_2 0x14
#define FIL3_3 0x15
#define EQ_0 0x16
#define EQ_1 0x17
#define EQ_2 0x18
#define EQ_3 0x19
#define EQ_4 0x1a
#define EQ_5 0x1b
#define FIL1_0 0x1c
#define FIL1_1 0x1d
#define FIL1_2 0x1e
#define FIL1_3 0x1f
#define PW_MGMT4 0x20
#define MD_CTL5 0x21
#define LO_MS 0x22
#define HP_MS 0x23
#define SPK_MS 0x24
#define AK4642_CACHEREGNUM 0x25
struct snd_soc_codec_device soc_codec_dev_ak4642;
/* codec private data */
struct ak4642_priv {
struct snd_soc_codec codec;
unsigned int sysclk;
};
static struct snd_soc_codec *ak4642_codec;
/*
* ak4642 register cache
*/
static const u16 ak4642_reg[AK4642_CACHEREGNUM] = {
0x0000, 0x0000, 0x0001, 0x0000,
0x0002, 0x0000, 0x0000, 0x0000,
0x00e1, 0x00e1, 0x0018, 0x0000,
0x00e1, 0x0018, 0x0011, 0x0008,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000,
};
/*
* read ak4642 register cache
*/
static inline unsigned int ak4642_read_reg_cache(struct snd_soc_codec *codec,
unsigned int reg)
{
u16 *cache = codec->reg_cache;
if (reg >= AK4642_CACHEREGNUM)
return -1;
return cache[reg];
}
/*
* write ak4642 register cache
*/
static inline void ak4642_write_reg_cache(struct snd_soc_codec *codec,
u16 reg, unsigned int value)
{
u16 *cache = codec->reg_cache;
if (reg >= AK4642_CACHEREGNUM)
return;
cache[reg] = value;
}
/*
* write to the AK4642 register space
*/
static int ak4642_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
u8 data[2];
/* data is
* D15..D8 AK4642 register offset
* D7...D0 register data
*/
data[0] = reg & 0xff;
data[1] = value & 0xff;
if (codec->hw_write(codec->control_data, data, 2) == 2) {
ak4642_write_reg_cache(codec, reg, value);
return 0;
} else
return -EIO;
}
static int ak4642_sync(struct snd_soc_codec *codec)
{
u16 *cache = codec->reg_cache;
int i, r = 0;
for (i = 0; i < AK4642_CACHEREGNUM; i++)
r |= ak4642_write(codec, i, cache[i]);
return r;
};
static int ak4642_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
struct snd_soc_codec *codec = dai->codec;
if (is_play) {
/*
* start headphone output
*
* PLL, Master Mode
* Audio I/F Format :MSB justified (ADC & DAC)
* Sampling Frequency: 44.1kHz
* Digital Volume: −8dB
* Bass Boost Level : Middle
*
* This operation came from example code of
* "ASAHI KASEI AK4642" (japanese) manual p97.
*
* Example code use 0x39, 0x79 value for 0x01 address,
* But we need MCKO (0x02) bit now
*/
ak4642_write(codec, 0x05, 0x27);
ak4642_write(codec, 0x0f, 0x09);
ak4642_write(codec, 0x0e, 0x19);
ak4642_write(codec, 0x09, 0x91);
ak4642_write(codec, 0x0c, 0x91);
ak4642_write(codec, 0x0a, 0x28);
ak4642_write(codec, 0x0d, 0x28);
ak4642_write(codec, 0x00, 0x64);
ak4642_write(codec, 0x01, 0x3b); /* + MCKO bit */
ak4642_write(codec, 0x01, 0x7b); /* + MCKO bit */
} else {
/*
* start stereo input
*
* PLL Master Mode
* Audio I/F Format:MSB justified (ADC & DAC)
* Sampling Frequency:44.1kHz
* Pre MIC AMP:+20dB
* MIC Power On
* ALC setting:Refer to Table 35
* ALC bit=“1”
*
* This operation came from example code of
* "ASAHI KASEI AK4642" (japanese) manual p94.
*/
ak4642_write(codec, 0x05, 0x27);
ak4642_write(codec, 0x02, 0x05);
ak4642_write(codec, 0x06, 0x3c);
ak4642_write(codec, 0x08, 0xe1);
ak4642_write(codec, 0x0b, 0x00);
ak4642_write(codec, 0x07, 0x21);
ak4642_write(codec, 0x00, 0x41);
ak4642_write(codec, 0x10, 0x01);
}
return 0;
}
static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
struct snd_soc_codec *codec = dai->codec;
if (is_play) {
/* stop headphone output */
ak4642_write(codec, 0x01, 0x3b);
ak4642_write(codec, 0x01, 0x0b);
ak4642_write(codec, 0x00, 0x40);
ak4642_write(codec, 0x0e, 0x11);
ak4642_write(codec, 0x0f, 0x08);
} else {
/* stop stereo input */
ak4642_write(codec, 0x00, 0x40);
ak4642_write(codec, 0x10, 0x00);
ak4642_write(codec, 0x07, 0x01);
}
}
static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct ak4642_priv *ak4642 = codec->private_data;
ak4642->sysclk = freq;
return 0;
}
static struct snd_soc_dai_ops ak4642_dai_ops = {
.startup = ak4642_dai_startup,
.shutdown = ak4642_dai_shutdown,
.set_sysclk = ak4642_dai_set_sysclk,
};
struct snd_soc_dai ak4642_dai = {
.name = "AK4642",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE },
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE },
.ops = &ak4642_dai_ops,
};
EXPORT_SYMBOL_GPL(ak4642_dai);
static int ak4642_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
ak4642_sync(codec);
return 0;
}
/*
* initialise the AK4642 driver
* register the mixer and dsp interfaces with the kernel
*/
static int ak4642_init(struct ak4642_priv *ak4642)
{
struct snd_soc_codec *codec = &ak4642->codec;
int ret = 0;
if (ak4642_codec) {
dev_err(codec->dev, "Another ak4642 is registered\n");
return -EINVAL;
}
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->private_data = ak4642;
codec->name = "AK4642";
codec->owner = THIS_MODULE;
codec->read = ak4642_read_reg_cache;
codec->write = ak4642_write;
codec->dai = &ak4642_dai;
codec->num_dai = 1;
codec->hw_write = (hw_write_t)i2c_master_send;
codec->reg_cache_size = ARRAY_SIZE(ak4642_reg);
codec->reg_cache = kmemdup(ak4642_reg,
sizeof(ak4642_reg), GFP_KERNEL);
if (!codec->reg_cache)
return -ENOMEM;
ak4642_dai.dev = codec->dev;
ak4642_codec = codec;
ret = snd_soc_register_codec(codec);
if (ret) {
dev_err(codec->dev, "Failed to register codec: %d\n", ret);
goto reg_cache_err;
}
ret = snd_soc_register_dai(&ak4642_dai);
if (ret) {
dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
snd_soc_unregister_codec(codec);
goto reg_cache_err;
}
/*
* clock setting
*
* Audio I/F Format: MSB justified (ADC & DAC)
* BICK frequency at Master Mode: 64fs
* Input Master Clock Select at PLL Mode: 11.2896MHz
* MCKO: Enable
* Sampling Frequency: 44.1kHz
*
* This operation came from example code of
* "ASAHI KASEI AK4642" (japanese) manual p89.
*
* please fix-me
*/
ak4642_write(codec, 0x01, 0x08);
ak4642_write(codec, 0x04, 0x4a);
ak4642_write(codec, 0x05, 0x27);
ak4642_write(codec, 0x00, 0x40);
ak4642_write(codec, 0x01, 0x0b);
return ret;
reg_cache_err:
kfree(codec->reg_cache);
codec->reg_cache = NULL;
return ret;
}
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
static int ak4642_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct ak4642_priv *ak4642;
struct snd_soc_codec *codec;
int ret;
ak4642 = kzalloc(sizeof(struct ak4642_priv), GFP_KERNEL);
if (!ak4642)
return -ENOMEM;
codec = &ak4642->codec;
codec->dev = &i2c->dev;
i2c_set_clientdata(i2c, ak4642);
codec->control_data = i2c;
ret = ak4642_init(ak4642);
if (ret < 0)
printk(KERN_ERR "failed to initialise AK4642\n");
return ret;
}
static int ak4642_i2c_remove(struct i2c_client *client)
{
struct ak4642_priv *ak4642 = i2c_get_clientdata(client);
snd_soc_unregister_dai(&ak4642_dai);
snd_soc_unregister_codec(&ak4642->codec);
kfree(ak4642->codec.reg_cache);
kfree(ak4642);
ak4642_codec = NULL;
return 0;
}
static const struct i2c_device_id ak4642_i2c_id[] = {
{ "ak4642", 0 },
{ "ak4643", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
static struct i2c_driver ak4642_i2c_driver = {
.driver = {
.name = "AK4642 I2C Codec",
.owner = THIS_MODULE,
},
.probe = ak4642_i2c_probe,
.remove = ak4642_i2c_remove,
.id_table = ak4642_i2c_id,
};
#endif
static int ak4642_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
int ret;
if (!ak4642_codec) {
dev_err(&pdev->dev, "Codec device not registered\n");
return -ENODEV;
}
socdev->card->codec = ak4642_codec;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
printk(KERN_ERR "ak4642: failed to create pcms\n");
goto pcm_err;
}
ret = snd_soc_init_card(socdev);
if (ret < 0) {
printk(KERN_ERR "ak4642: failed to register card\n");
goto card_err;
}
dev_info(&pdev->dev, "AK4642 Audio Codec %s", AK4642_VERSION);
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
return ret;
}
/* power down chip */
static int ak4642_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_ak4642 = {
.probe = ak4642_probe,
.remove = ak4642_remove,
.resume = ak4642_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_ak4642);
static int __init ak4642_modinit(void)
{
int ret;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
ret = i2c_add_driver(&ak4642_i2c_driver);
#endif
return ret;
}
module_init(ak4642_modinit);
static void __exit ak4642_exit(void)
{
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
i2c_del_driver(&ak4642_i2c_driver);
#endif
}
module_exit(ak4642_exit);
MODULE_DESCRIPTION("Soc AK4642 driver");
MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
MODULE_LICENSE("GPL");

20
kernel/sound/soc/codecs/ak4642.h Normal file
View File

@@ -0,0 +1,20 @@
/*
* ak4642.h -- AK4642 Soc Audio driver
*
* Copyright (C) 2009 Renesas Solutions Corp.
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
*
* Based on ak4535.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _AK4642_H
#define _AK4642_H
extern struct snd_soc_dai ak4642_dai;
extern struct snd_soc_codec_device soc_codec_dev_ak4642;
#endif

910
kernel/sound/soc/codecs/cs4270.c Normal file
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@@ -0,0 +1,910 @@
/*
* CS4270 ALSA SoC (ASoC) codec driver
*
* Author: Timur Tabi <timur@freescale.com>
*
* Copyright 2007-2009 Freescale Semiconductor, Inc. This file is licensed
* under the terms of the GNU General Public License version 2. This
* program is licensed "as is" without any warranty of any kind, whether
* express or implied.
*
* This is an ASoC device driver for the Cirrus Logic CS4270 codec.
*
* Current features/limitations:
*
* - Software mode is supported. Stand-alone mode is not supported.
* - Only I2C is supported, not SPI
* - Support for master and slave mode
* - The machine driver's 'startup' function must call
* cs4270_set_dai_sysclk() with the value of MCLK.
* - Only I2S and left-justified modes are supported
* - Power management is supported
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include "cs4270.h"
/*
* The codec isn't really big-endian or little-endian, since the I2S
* interface requires data to be sent serially with the MSbit first.
* However, to support BE and LE I2S devices, we specify both here. That
* way, ALSA will always match the bit patterns.
*/
#define CS4270_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE)
/* CS4270 registers addresses */
#define CS4270_CHIPID 0x01 /* Chip ID */
#define CS4270_PWRCTL 0x02 /* Power Control */
#define CS4270_MODE 0x03 /* Mode Control */
#define CS4270_FORMAT 0x04 /* Serial Format, ADC/DAC Control */
#define CS4270_TRANS 0x05 /* Transition Control */
#define CS4270_MUTE 0x06 /* Mute Control */
#define CS4270_VOLA 0x07 /* DAC Channel A Volume Control */
#define CS4270_VOLB 0x08 /* DAC Channel B Volume Control */
#define CS4270_FIRSTREG 0x01
#define CS4270_LASTREG 0x08
#define CS4270_NUMREGS (CS4270_LASTREG - CS4270_FIRSTREG + 1)
#define CS4270_I2C_INCR 0x80
/* Bit masks for the CS4270 registers */
#define CS4270_CHIPID_ID 0xF0
#define CS4270_CHIPID_REV 0x0F
#define CS4270_PWRCTL_FREEZE 0x80
#define CS4270_PWRCTL_PDN_ADC 0x20
#define CS4270_PWRCTL_PDN_DAC 0x02
#define CS4270_PWRCTL_PDN 0x01
#define CS4270_PWRCTL_PDN_ALL \
(CS4270_PWRCTL_PDN_ADC | CS4270_PWRCTL_PDN_DAC | CS4270_PWRCTL_PDN)
#define CS4270_MODE_SPEED_MASK 0x30
#define CS4270_MODE_1X 0x00
#define CS4270_MODE_2X 0x10
#define CS4270_MODE_4X 0x20
#define CS4270_MODE_SLAVE 0x30
#define CS4270_MODE_DIV_MASK 0x0E
#define CS4270_MODE_DIV1 0x00
#define CS4270_MODE_DIV15 0x02
#define CS4270_MODE_DIV2 0x04
#define CS4270_MODE_DIV3 0x06
#define CS4270_MODE_DIV4 0x08
#define CS4270_MODE_POPGUARD 0x01
#define CS4270_FORMAT_FREEZE_A 0x80
#define CS4270_FORMAT_FREEZE_B 0x40
#define CS4270_FORMAT_LOOPBACK 0x20
#define CS4270_FORMAT_DAC_MASK 0x18
#define CS4270_FORMAT_DAC_LJ 0x00
#define CS4270_FORMAT_DAC_I2S 0x08
#define CS4270_FORMAT_DAC_RJ16 0x18
#define CS4270_FORMAT_DAC_RJ24 0x10
#define CS4270_FORMAT_ADC_MASK 0x01
#define CS4270_FORMAT_ADC_LJ 0x00
#define CS4270_FORMAT_ADC_I2S 0x01
#define CS4270_TRANS_ONE_VOL 0x80
#define CS4270_TRANS_SOFT 0x40
#define CS4270_TRANS_ZERO 0x20
#define CS4270_TRANS_INV_ADC_A 0x08
#define CS4270_TRANS_INV_ADC_B 0x10
#define CS4270_TRANS_INV_DAC_A 0x02
#define CS4270_TRANS_INV_DAC_B 0x04
#define CS4270_TRANS_DEEMPH 0x01
#define CS4270_MUTE_AUTO 0x20
#define CS4270_MUTE_ADC_A 0x08
#define CS4270_MUTE_ADC_B 0x10
#define CS4270_MUTE_POLARITY 0x04
#define CS4270_MUTE_DAC_A 0x01
#define CS4270_MUTE_DAC_B 0x02
/* Private data for the CS4270 */
struct cs4270_private {
struct snd_soc_codec codec;
u8 reg_cache[CS4270_NUMREGS];
unsigned int mclk; /* Input frequency of the MCLK pin */
unsigned int mode; /* The mode (I2S or left-justified) */
unsigned int slave_mode;
unsigned int manual_mute;
};
/**
* struct cs4270_mode_ratios - clock ratio tables
* @ratio: the ratio of MCLK to the sample rate
* @speed_mode: the Speed Mode bits to set in the Mode Control register for
* this ratio
* @mclk: the Ratio Select bits to set in the Mode Control register for this
* ratio
*
* The data for this chart is taken from Table 5 of the CS4270 reference
* manual.
*
* This table is used to determine how to program the Mode Control register.
* It is also used by cs4270_set_dai_sysclk() to tell ALSA which sampling
* rates the CS4270 currently supports.
*
* @speed_mode is the corresponding bit pattern to be written to the
* MODE bits of the Mode Control Register
*
* @mclk is the corresponding bit pattern to be wirten to the MCLK bits of
* the Mode Control Register.
*
* In situations where a single ratio is represented by multiple speed
* modes, we favor the slowest speed. E.g, for a ratio of 128, we pick
* double-speed instead of quad-speed. However, the CS4270 errata states
* that divide-By-1.5 can cause failures, so we avoid that mode where
* possible.
*
* Errata: There is an errata for the CS4270 where divide-by-1.5 does not
* work if Vd is 3.3V. If this effects you, select the
* CONFIG_SND_SOC_CS4270_VD33_ERRATA Kconfig option, and the driver will
* never select any sample rates that require divide-by-1.5.
*/
struct cs4270_mode_ratios {
unsigned int ratio;
u8 speed_mode;
u8 mclk;
};
static struct cs4270_mode_ratios cs4270_mode_ratios[] = {
{64, CS4270_MODE_4X, CS4270_MODE_DIV1},
#ifndef CONFIG_SND_SOC_CS4270_VD33_ERRATA
{96, CS4270_MODE_4X, CS4270_MODE_DIV15},
#endif
{128, CS4270_MODE_2X, CS4270_MODE_DIV1},
{192, CS4270_MODE_4X, CS4270_MODE_DIV3},
{256, CS4270_MODE_1X, CS4270_MODE_DIV1},
{384, CS4270_MODE_2X, CS4270_MODE_DIV3},
{512, CS4270_MODE_1X, CS4270_MODE_DIV2},
{768, CS4270_MODE_1X, CS4270_MODE_DIV3},
{1024, CS4270_MODE_1X, CS4270_MODE_DIV4}
};
/* The number of MCLK/LRCK ratios supported by the CS4270 */
#define NUM_MCLK_RATIOS ARRAY_SIZE(cs4270_mode_ratios)
/**
* cs4270_set_dai_sysclk - determine the CS4270 samples rates.
* @codec_dai: the codec DAI
* @clk_id: the clock ID (ignored)
* @freq: the MCLK input frequency
* @dir: the clock direction (ignored)
*
* This function is used to tell the codec driver what the input MCLK
* frequency is.
*
* The value of MCLK is used to determine which sample rates are supported
* by the CS4270. The ratio of MCLK / Fs must be equal to one of nine
* supported values - 64, 96, 128, 192, 256, 384, 512, 768, and 1024.
*
* This function calculates the nine ratios and determines which ones match
* a standard sample rate. If there's a match, then it is added to the list
* of supported sample rates.
*
* This function must be called by the machine driver's 'startup' function,
* otherwise the list of supported sample rates will not be available in
* time for ALSA.
*/
static int cs4270_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct cs4270_private *cs4270 = codec->private_data;
unsigned int rates = 0;
unsigned int rate_min = -1;
unsigned int rate_max = 0;
unsigned int i;
cs4270->mclk = freq;
for (i = 0; i < NUM_MCLK_RATIOS; i++) {
unsigned int rate = freq / cs4270_mode_ratios[i].ratio;
rates |= snd_pcm_rate_to_rate_bit(rate);
if (rate < rate_min)
rate_min = rate;
if (rate > rate_max)
rate_max = rate;
}
/* FIXME: soc should support a rate list */
rates &= ~SNDRV_PCM_RATE_KNOT;
if (!rates) {
dev_err(codec->dev, "could not find a valid sample rate\n");
return -EINVAL;
}
codec_dai->playback.rates = rates;
codec_dai->playback.rate_min = rate_min;
codec_dai->playback.rate_max = rate_max;
codec_dai->capture.rates = rates;
codec_dai->capture.rate_min = rate_min;
codec_dai->capture.rate_max = rate_max;
return 0;
}
/**
* cs4270_set_dai_fmt - configure the codec for the selected audio format
* @codec_dai: the codec DAI
* @format: a SND_SOC_DAIFMT_x value indicating the data format
*
* This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
* codec accordingly.
*
* Currently, this function only supports SND_SOC_DAIFMT_I2S and
* SND_SOC_DAIFMT_LEFT_J. The CS4270 codec also supports right-justified
* data for playback only, but ASoC currently does not support different
* formats for playback vs. record.
*/
static int cs4270_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct cs4270_private *cs4270 = codec->private_data;
int ret = 0;
/* set DAI format */
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
cs4270->mode = format & SND_SOC_DAIFMT_FORMAT_MASK;
break;
default:
dev_err(codec->dev, "invalid dai format\n");
ret = -EINVAL;
}
/* set master/slave audio interface */
switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
cs4270->slave_mode = 1;
break;
case SND_SOC_DAIFMT_CBM_CFM:
cs4270->slave_mode = 0;
break;
default:
/* all other modes are unsupported by the hardware */
ret = -EINVAL;
}
return ret;
}
/**
* cs4270_fill_cache - pre-fill the CS4270 register cache.
* @codec: the codec for this CS4270
*
* This function fills in the CS4270 register cache by reading the register
* values from the hardware.
*
* This CS4270 registers are cached to avoid excessive I2C I/O operations.
* After the initial read to pre-fill the cache, the CS4270 never updates
* the register values, so we won't have a cache coherency problem.
*
* We use the auto-increment feature of the CS4270 to read all registers in
* one shot.
*/
static int cs4270_fill_cache(struct snd_soc_codec *codec)
{
u8 *cache = codec->reg_cache;
struct i2c_client *i2c_client = codec->control_data;
s32 length;
length = i2c_smbus_read_i2c_block_data(i2c_client,
CS4270_FIRSTREG | CS4270_I2C_INCR, CS4270_NUMREGS, cache);
if (length != CS4270_NUMREGS) {
dev_err(codec->dev, "i2c read failure, addr=0x%x\n",
i2c_client->addr);
return -EIO;
}
return 0;
}
/**
* cs4270_read_reg_cache - read from the CS4270 register cache.
* @codec: the codec for this CS4270
* @reg: the register to read
*
* This function returns the value for a given register. It reads only from
* the register cache, not the hardware itself.
*
* This CS4270 registers are cached to avoid excessive I2C I/O operations.
* After the initial read to pre-fill the cache, the CS4270 never updates
* the register values, so we won't have a cache coherency problem.
*/
static unsigned int cs4270_read_reg_cache(struct snd_soc_codec *codec,
unsigned int reg)
{
u8 *cache = codec->reg_cache;
if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG))
return -EIO;
return cache[reg - CS4270_FIRSTREG];
}
/**
* cs4270_i2c_write - write to a CS4270 register via the I2C bus.
* @codec: the codec for this CS4270
* @reg: the register to write
* @value: the value to write to the register
*
* This function writes the given value to the given CS4270 register, and
* also updates the register cache.
*
* Note that we don't use the hw_write function pointer of snd_soc_codec.
* That's because it's too clunky: the hw_write_t prototype does not match
* i2c_smbus_write_byte_data(), and it's just another layer of overhead.
*/
static int cs4270_i2c_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
u8 *cache = codec->reg_cache;
if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG))
return -EIO;
/* Only perform an I2C operation if the new value is different */
if (cache[reg - CS4270_FIRSTREG] != value) {
struct i2c_client *client = codec->control_data;
if (i2c_smbus_write_byte_data(client, reg, value)) {
dev_err(codec->dev, "i2c write failed\n");
return -EIO;
}
/* We've written to the hardware, so update the cache */
cache[reg - CS4270_FIRSTREG] = value;
}
return 0;
}
/**
* cs4270_hw_params - program the CS4270 with the given hardware parameters.
* @substream: the audio stream
* @params: the hardware parameters to set
* @dai: the SOC DAI (ignored)
*
* This function programs the hardware with the values provided.
* Specifically, the sample rate and the data format.
*
* The .ops functions are used to provide board-specific data, like input
* frequencies, to this driver. This function takes that information,
* combines it with the hardware parameters provided, and programs the
* hardware accordingly.
*/
static int cs4270_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct cs4270_private *cs4270 = codec->private_data;
int ret;
unsigned int i;
unsigned int rate;
unsigned int ratio;
int reg;
/* Figure out which MCLK/LRCK ratio to use */
rate = params_rate(params); /* Sampling rate, in Hz */
ratio = cs4270->mclk / rate; /* MCLK/LRCK ratio */
for (i = 0; i < NUM_MCLK_RATIOS; i++) {
if (cs4270_mode_ratios[i].ratio == ratio)
break;
}
if (i == NUM_MCLK_RATIOS) {
/* We did not find a matching ratio */
dev_err(codec->dev, "could not find matching ratio\n");
return -EINVAL;
}
/* Set the sample rate */
reg = snd_soc_read(codec, CS4270_MODE);
reg &= ~(CS4270_MODE_SPEED_MASK | CS4270_MODE_DIV_MASK);
reg |= cs4270_mode_ratios[i].mclk;
if (cs4270->slave_mode)
reg |= CS4270_MODE_SLAVE;
else
reg |= cs4270_mode_ratios[i].speed_mode;
ret = snd_soc_write(codec, CS4270_MODE, reg);
if (ret < 0) {
dev_err(codec->dev, "i2c write failed\n");
return ret;
}
/* Set the DAI format */
reg = snd_soc_read(codec, CS4270_FORMAT);
reg &= ~(CS4270_FORMAT_DAC_MASK | CS4270_FORMAT_ADC_MASK);
switch (cs4270->mode) {
case SND_SOC_DAIFMT_I2S:
reg |= CS4270_FORMAT_DAC_I2S | CS4270_FORMAT_ADC_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
reg |= CS4270_FORMAT_DAC_LJ | CS4270_FORMAT_ADC_LJ;
break;
default:
dev_err(codec->dev, "unknown dai format\n");
return -EINVAL;
}
ret = snd_soc_write(codec, CS4270_FORMAT, reg);
if (ret < 0) {
dev_err(codec->dev, "i2c write failed\n");
return ret;
}
return ret;
}
/**
* cs4270_dai_mute - enable/disable the CS4270 external mute
* @dai: the SOC DAI
* @mute: 0 = disable mute, 1 = enable mute
*
* This function toggles the mute bits in the MUTE register. The CS4270's
* mute capability is intended for external muting circuitry, so if the
* board does not have the MUTEA or MUTEB pins connected to such circuitry,
* then this function will do nothing.
*/
static int cs4270_dai_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
struct cs4270_private *cs4270 = codec->private_data;
int reg6;
reg6 = snd_soc_read(codec, CS4270_MUTE);
if (mute)
reg6 |= CS4270_MUTE_DAC_A | CS4270_MUTE_DAC_B;
else {
reg6 &= ~(CS4270_MUTE_DAC_A | CS4270_MUTE_DAC_B);
reg6 |= cs4270->manual_mute;
}
return snd_soc_write(codec, CS4270_MUTE, reg6);
}
/**
* cs4270_soc_put_mute - put callback for the 'Master Playback switch'
* alsa control.
* @kcontrol: mixer control
* @ucontrol: control element information
*
* This function basically passes the arguments on to the generic
* snd_soc_put_volsw() function and saves the mute information in
* our private data structure. This is because we want to prevent
* cs4270_dai_mute() neglecting the user's decision to manually
* mute the codec's output.
*
* Returns 0 for success.
*/
static int cs4270_soc_put_mute(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
struct cs4270_private *cs4270 = codec->private_data;
int left = !ucontrol->value.integer.value[0];
int right = !ucontrol->value.integer.value[1];
cs4270->manual_mute = (left ? CS4270_MUTE_DAC_A : 0) |
(right ? CS4270_MUTE_DAC_B : 0);
return snd_soc_put_volsw(kcontrol, ucontrol);
}
/* A list of non-DAPM controls that the CS4270 supports */
static const struct snd_kcontrol_new cs4270_snd_controls[] = {
SOC_DOUBLE_R("Master Playback Volume",
CS4270_VOLA, CS4270_VOLB, 0, 0xFF, 1),
SOC_SINGLE("Digital Sidetone Switch", CS4270_FORMAT, 5, 1, 0),
SOC_SINGLE("Soft Ramp Switch", CS4270_TRANS, 6, 1, 0),
SOC_SINGLE("Zero Cross Switch", CS4270_TRANS, 5, 1, 0),
SOC_SINGLE("Popguard Switch", CS4270_MODE, 0, 1, 1),
SOC_SINGLE("Auto-Mute Switch", CS4270_MUTE, 5, 1, 0),
SOC_DOUBLE("Master Capture Switch", CS4270_MUTE, 3, 4, 1, 1),
SOC_DOUBLE_EXT("Master Playback Switch", CS4270_MUTE, 0, 1, 1, 1,
snd_soc_get_volsw, cs4270_soc_put_mute),
};
/*
* cs4270_codec - global variable to store codec for the ASoC probe function
*
* If struct i2c_driver had a private_data field, we wouldn't need to use
* cs4270_codec. This is the only way to pass the codec structure from
* cs4270_i2c_probe() to cs4270_probe(). Unfortunately, there is no good
* way to synchronize these two functions. cs4270_i2c_probe() can be called
* multiple times before cs4270_probe() is called even once. So for now, we
* also only allow cs4270_i2c_probe() to be run once. That means that we do
* not support more than one cs4270 device in the system, at least for now.
*/
static struct snd_soc_codec *cs4270_codec;
static struct snd_soc_dai_ops cs4270_dai_ops = {
.hw_params = cs4270_hw_params,
.set_sysclk = cs4270_set_dai_sysclk,
.set_fmt = cs4270_set_dai_fmt,
.digital_mute = cs4270_dai_mute,
};
struct snd_soc_dai cs4270_dai = {
.name = "cs4270",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = 0,
.formats = CS4270_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = 0,
.formats = CS4270_FORMATS,
},
.ops = &cs4270_dai_ops,
};
EXPORT_SYMBOL_GPL(cs4270_dai);
/**
* cs4270_probe - ASoC probe function
* @pdev: platform device
*
* This function is called when ASoC has all the pieces it needs to
* instantiate a sound driver.
*/
static int cs4270_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = cs4270_codec;
int ret;
/* Connect the codec to the socdev. snd_soc_new_pcms() needs this. */
socdev->card->codec = codec;
/* Register PCMs */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms\n");
return ret;
}
/* Add the non-DAPM controls */
ret = snd_soc_add_controls(codec, cs4270_snd_controls,
ARRAY_SIZE(cs4270_snd_controls));
if (ret < 0) {
dev_err(codec->dev, "failed to add controls\n");
goto error_free_pcms;
}
/* And finally, register the socdev */
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(codec->dev, "failed to register card\n");
goto error_free_pcms;
}
return 0;
error_free_pcms:
snd_soc_free_pcms(socdev);
return ret;
}
/**
* cs4270_remove - ASoC remove function
* @pdev: platform device
*
* This function is the counterpart to cs4270_probe().
*/
static int cs4270_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
return 0;
};
/**
* cs4270_i2c_probe - initialize the I2C interface of the CS4270
* @i2c_client: the I2C client object
* @id: the I2C device ID (ignored)
*
* This function is called whenever the I2C subsystem finds a device that
* matches the device ID given via a prior call to i2c_add_driver().
*/
static int cs4270_i2c_probe(struct i2c_client *i2c_client,
const struct i2c_device_id *id)
{
struct snd_soc_codec *codec;
struct cs4270_private *cs4270;
unsigned int reg;
int ret;
/* For now, we only support one cs4270 device in the system. See the
* comment for cs4270_codec.
*/
if (cs4270_codec) {
dev_err(&i2c_client->dev, "ignoring CS4270 at addr %X\n",
i2c_client->addr);
dev_err(&i2c_client->dev, "only one per board allowed\n");
/* Should we return something other than ENODEV here? */
return -ENODEV;
}
/* Verify that we have a CS4270 */
ret = i2c_smbus_read_byte_data(i2c_client, CS4270_CHIPID);
if (ret < 0) {
dev_err(&i2c_client->dev, "failed to read i2c at addr %X\n",
i2c_client->addr);
return ret;
}
/* The top four bits of the chip ID should be 1100. */
if ((ret & 0xF0) != 0xC0) {
dev_err(&i2c_client->dev, "device at addr %X is not a CS4270\n",
i2c_client->addr);
return -ENODEV;
}
dev_info(&i2c_client->dev, "found device at i2c address %X\n",
i2c_client->addr);
dev_info(&i2c_client->dev, "hardware revision %X\n", ret & 0xF);
/* Allocate enough space for the snd_soc_codec structure
and our private data together. */
cs4270 = kzalloc(sizeof(struct cs4270_private), GFP_KERNEL);
if (!cs4270) {
dev_err(&i2c_client->dev, "could not allocate codec\n");
return -ENOMEM;
}
codec = &cs4270->codec;
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->dev = &i2c_client->dev;
codec->name = "CS4270";
codec->owner = THIS_MODULE;
codec->dai = &cs4270_dai;
codec->num_dai = 1;
codec->private_data = cs4270;
codec->control_data = i2c_client;
codec->read = cs4270_read_reg_cache;
codec->write = cs4270_i2c_write;
codec->reg_cache = cs4270->reg_cache;
codec->reg_cache_size = CS4270_NUMREGS;
/* The I2C interface is set up, so pre-fill our register cache */
ret = cs4270_fill_cache(codec);
if (ret < 0) {
dev_err(&i2c_client->dev, "failed to fill register cache\n");
goto error_free_codec;
}
/* Disable auto-mute. This feature appears to be buggy. In some
* situations, auto-mute will not deactivate when it should, so we want
* this feature disabled by default. An application (e.g. alsactl) can
* re-enabled it by using the controls.
*/
reg = cs4270_read_reg_cache(codec, CS4270_MUTE);
reg &= ~CS4270_MUTE_AUTO;
ret = cs4270_i2c_write(codec, CS4270_MUTE, reg);
if (ret < 0) {
dev_err(&i2c_client->dev, "i2c write failed\n");
return ret;
}
/* Disable automatic volume control. The hardware enables, and it
* causes volume change commands to be delayed, sometimes until after
* playback has started. An application (e.g. alsactl) can
* re-enabled it by using the controls.
*/
reg = cs4270_read_reg_cache(codec, CS4270_TRANS);
reg &= ~(CS4270_TRANS_SOFT | CS4270_TRANS_ZERO);
ret = cs4270_i2c_write(codec, CS4270_TRANS, reg);
if (ret < 0) {
dev_err(&i2c_client->dev, "i2c write failed\n");
return ret;
}
/* Initialize the DAI. Normally, we'd prefer to have a kmalloc'd DAI
* structure for each CS4270 device, but the machine driver needs to
* have a pointer to the DAI structure, so for now it must be a global
* variable.
*/
cs4270_dai.dev = &i2c_client->dev;
/* Register the DAI. If all the other ASoC driver have already
* registered, then this will call our probe function, so
* cs4270_codec needs to be ready.
*/
cs4270_codec = codec;
ret = snd_soc_register_dai(&cs4270_dai);
if (ret < 0) {
dev_err(&i2c_client->dev, "failed to register DAIe\n");
goto error_free_codec;
}
i2c_set_clientdata(i2c_client, cs4270);
return 0;
error_free_codec:
kfree(cs4270);
cs4270_codec = NULL;
cs4270_dai.dev = NULL;
return ret;
}
/**
* cs4270_i2c_remove - remove an I2C device
* @i2c_client: the I2C client object
*
* This function is the counterpart to cs4270_i2c_probe().
*/
static int cs4270_i2c_remove(struct i2c_client *i2c_client)
{
struct cs4270_private *cs4270 = i2c_get_clientdata(i2c_client);
kfree(cs4270);
cs4270_codec = NULL;
cs4270_dai.dev = NULL;
return 0;
}
/*
* cs4270_id - I2C device IDs supported by this driver
*/
static struct i2c_device_id cs4270_id[] = {
{"cs4270", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cs4270_id);
#ifdef CONFIG_PM
/* This suspend/resume implementation can handle both - a simple standby
* where the codec remains powered, and a full suspend, where the voltage
* domain the codec is connected to is teared down and/or any other hardware
* reset condition is asserted.
*
* The codec's own power saving features are enabled in the suspend callback,
* and all registers are written back to the hardware when resuming.
*/
static int cs4270_i2c_suspend(struct i2c_client *client, pm_message_t mesg)
{
struct cs4270_private *cs4270 = i2c_get_clientdata(client);
struct snd_soc_codec *codec = &cs4270->codec;
return snd_soc_suspend_device(codec->dev);
}
static int cs4270_i2c_resume(struct i2c_client *client)
{
struct cs4270_private *cs4270 = i2c_get_clientdata(client);
struct snd_soc_codec *codec = &cs4270->codec;
return snd_soc_resume_device(codec->dev);
}
static int cs4270_soc_suspend(struct platform_device *pdev, pm_message_t mesg)
{
struct snd_soc_codec *codec = cs4270_codec;
int reg = snd_soc_read(codec, CS4270_PWRCTL) | CS4270_PWRCTL_PDN_ALL;
return snd_soc_write(codec, CS4270_PWRCTL, reg);
}
static int cs4270_soc_resume(struct platform_device *pdev)
{
struct snd_soc_codec *codec = cs4270_codec;
struct i2c_client *i2c_client = codec->control_data;
int reg;
/* In case the device was put to hard reset during sleep, we need to
* wait 500ns here before any I2C communication. */
ndelay(500);
/* first restore the entire register cache ... */
for (reg = CS4270_FIRSTREG; reg <= CS4270_LASTREG; reg++) {
u8 val = snd_soc_read(codec, reg);
if (i2c_smbus_write_byte_data(i2c_client, reg, val)) {
dev_err(codec->dev, "i2c write failed\n");
return -EIO;
}
}
/* ... then disable the power-down bits */
reg = snd_soc_read(codec, CS4270_PWRCTL);
reg &= ~CS4270_PWRCTL_PDN_ALL;
return snd_soc_write(codec, CS4270_PWRCTL, reg);
}
#else
#define cs4270_i2c_suspend NULL
#define cs4270_i2c_resume NULL
#define cs4270_soc_suspend NULL
#define cs4270_soc_resume NULL
#endif /* CONFIG_PM */
/*
* cs4270_i2c_driver - I2C device identification
*
* This structure tells the I2C subsystem how to identify and support a
* given I2C device type.
*/
static struct i2c_driver cs4270_i2c_driver = {
.driver = {
.name = "cs4270",
.owner = THIS_MODULE,
},
.id_table = cs4270_id,
.probe = cs4270_i2c_probe,
.remove = cs4270_i2c_remove,
.suspend = cs4270_i2c_suspend,
.resume = cs4270_i2c_resume,
};
/*
* ASoC codec device structure
*
* Assign this variable to the codec_dev field of the machine driver's
* snd_soc_device structure.
*/
struct snd_soc_codec_device soc_codec_device_cs4270 = {
.probe = cs4270_probe,
.remove = cs4270_remove,
.suspend = cs4270_soc_suspend,
.resume = cs4270_soc_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_device_cs4270);
static int __init cs4270_init(void)
{
pr_info("Cirrus Logic CS4270 ALSA SoC Codec Driver\n");
return i2c_add_driver(&cs4270_i2c_driver);
}
module_init(cs4270_init);
static void __exit cs4270_exit(void)
{
i2c_del_driver(&cs4270_i2c_driver);
}
module_exit(cs4270_exit);
MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
MODULE_DESCRIPTION("Cirrus Logic CS4270 ALSA SoC Codec Driver");
MODULE_LICENSE("GPL");

28
kernel/sound/soc/codecs/cs4270.h Normal file
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@@ -0,0 +1,28 @@
/*
* Cirrus Logic CS4270 ALSA SoC Codec Driver
*
* Author: Timur Tabi <timur@freescale.com>
*
* Copyright 2007 Freescale Semiconductor, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef _CS4270_H
#define _CS4270_H
/*
* The ASoC codec DAI structure for the CS4270. Assign this structure to
* the .codec_dai field of your machine driver's snd_soc_dai_link structure.
*/
extern struct snd_soc_dai cs4270_dai;
/*
* The ASoC codec device structure for the CS4270. Assign this structure
* to the .codec_dev field of your machine driver's snd_soc_device
* structure.
*/
extern struct snd_soc_codec_device soc_codec_device_cs4270;
#endif

501
kernel/sound/soc/codecs/cx20442.c Normal file
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@@ -0,0 +1,501 @@
/*
* cx20442.c -- CX20442 ALSA Soc Audio driver
*
* Copyright 2009 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
*
* Initially based on sound/soc/codecs/wm8400.c
* Copyright 2008, 2009 Wolfson Microelectronics PLC.
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/tty.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/soc-dapm.h>
#include "cx20442.h"
struct cx20442_priv {
struct snd_soc_codec codec;
u8 reg_cache[1];
};
#define CX20442_PM 0x0
#define CX20442_TELIN 0
#define CX20442_TELOUT 1
#define CX20442_MIC 2
#define CX20442_SPKOUT 3
#define CX20442_AGC 4
static const struct snd_soc_dapm_widget cx20442_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("TELOUT"),
SND_SOC_DAPM_OUTPUT("SPKOUT"),
SND_SOC_DAPM_OUTPUT("AGCOUT"),
SND_SOC_DAPM_MIXER("SPKOUT Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("TELOUT Amp", CX20442_PM, CX20442_TELOUT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPKOUT Amp", CX20442_PM, CX20442_SPKOUT, 0, NULL, 0),
SND_SOC_DAPM_PGA("SPKOUT AGC", CX20442_PM, CX20442_AGC, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("ADC", "Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MIXER("Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MICBIAS("TELIN Bias", CX20442_PM, CX20442_TELIN, 0),
SND_SOC_DAPM_MICBIAS("MIC Bias", CX20442_PM, CX20442_MIC, 0),
SND_SOC_DAPM_PGA("MIC AGC", CX20442_PM, CX20442_AGC, 0, NULL, 0),
SND_SOC_DAPM_INPUT("TELIN"),
SND_SOC_DAPM_INPUT("MIC"),
SND_SOC_DAPM_INPUT("AGCIN"),
};
static const struct snd_soc_dapm_route cx20442_audio_map[] = {
{"TELOUT", NULL, "TELOUT Amp"},
{"SPKOUT", NULL, "SPKOUT Mixer"},
{"SPKOUT Mixer", NULL, "SPKOUT Amp"},
{"TELOUT Amp", NULL, "DAC"},
{"SPKOUT Amp", NULL, "DAC"},
{"SPKOUT Mixer", NULL, "SPKOUT AGC"},
{"SPKOUT AGC", NULL, "AGCIN"},
{"AGCOUT", NULL, "MIC AGC"},
{"MIC AGC", NULL, "MIC"},
{"MIC Bias", NULL, "MIC"},
{"Input Mixer", NULL, "MIC Bias"},
{"TELIN Bias", NULL, "TELIN"},
{"Input Mixer", NULL, "TELIN Bias"},
{"ADC", NULL, "Input Mixer"},
};
static int cx20442_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, cx20442_dapm_widgets,
ARRAY_SIZE(cx20442_dapm_widgets));
snd_soc_dapm_add_routes(codec, cx20442_audio_map,
ARRAY_SIZE(cx20442_audio_map));
snd_soc_dapm_new_widgets(codec);
return 0;
}
static unsigned int cx20442_read_reg_cache(struct snd_soc_codec *codec,
unsigned int reg)
{
u8 *reg_cache = codec->reg_cache;
if (reg >= codec->reg_cache_size)
return -EINVAL;
return reg_cache[reg];
}
enum v253_vls {
V253_VLS_NONE = 0,
V253_VLS_T,
V253_VLS_L,
V253_VLS_LT,
V253_VLS_S,
V253_VLS_ST,
V253_VLS_M,
V253_VLS_MST,
V253_VLS_S1,
V253_VLS_S1T,
V253_VLS_MS1T,
V253_VLS_M1,
V253_VLS_M1ST,
V253_VLS_M1S1T,
V253_VLS_H,
V253_VLS_HT,
V253_VLS_MS,
V253_VLS_MS1,
V253_VLS_M1S,
V253_VLS_M1S1,
V253_VLS_TEST,
};
static int cx20442_pm_to_v253_vls(u8 value)
{
switch (value & ~(1 << CX20442_AGC)) {
case 0:
return V253_VLS_T;
case (1 << CX20442_SPKOUT):
case (1 << CX20442_MIC):
case (1 << CX20442_SPKOUT) | (1 << CX20442_MIC):
return V253_VLS_M1S1;
case (1 << CX20442_TELOUT):
case (1 << CX20442_TELIN):
case (1 << CX20442_TELOUT) | (1 << CX20442_TELIN):
return V253_VLS_L;
case (1 << CX20442_TELOUT) | (1 << CX20442_MIC):
return V253_VLS_NONE;
}
return -EINVAL;
}
static int cx20442_pm_to_v253_vsp(u8 value)
{
switch (value & ~(1 << CX20442_AGC)) {
case (1 << CX20442_SPKOUT):
case (1 << CX20442_MIC):
case (1 << CX20442_SPKOUT) | (1 << CX20442_MIC):
return (bool)(value & (1 << CX20442_AGC));
}
return (value & (1 << CX20442_AGC)) ? -EINVAL : 0;
}
static int cx20442_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
u8 *reg_cache = codec->reg_cache;
int vls, vsp, old, len;
char buf[18];
if (reg >= codec->reg_cache_size)
return -EINVAL;
/* hw_write and control_data pointers required for talking to the modem
* are expected to be set by the line discipline initialization code */
if (!codec->hw_write || !codec->control_data)
return -EIO;
old = reg_cache[reg];
reg_cache[reg] = value;
vls = cx20442_pm_to_v253_vls(value);
if (vls < 0)
return vls;
vsp = cx20442_pm_to_v253_vsp(value);
if (vsp < 0)
return vsp;
if ((vls == V253_VLS_T) ||
(vls == cx20442_pm_to_v253_vls(old))) {
if (vsp == cx20442_pm_to_v253_vsp(old))
return 0;
len = snprintf(buf, ARRAY_SIZE(buf), "at+vsp=%d\r", vsp);
} else if (vsp == cx20442_pm_to_v253_vsp(old))
len = snprintf(buf, ARRAY_SIZE(buf), "at+vls=%d\r", vls);
else
len = snprintf(buf, ARRAY_SIZE(buf),
"at+vls=%d;+vsp=%d\r", vls, vsp);
if (unlikely(len > (ARRAY_SIZE(buf) - 1)))
return -ENOMEM;
dev_dbg(codec->dev, "%s: %s\n", __func__, buf);
if (codec->hw_write(codec->control_data, buf, len) != len)
return -EIO;
return 0;
}
/* Moved up here as line discipline referres it during initialization */
static struct snd_soc_codec *cx20442_codec;
/*
* Line discpline related code
*
* Any of the callback functions below can be used in two ways:
* 1) registerd by a machine driver as one of line discipline operations,
* 2) called from a machine's provided line discipline callback function
* in case when extra machine specific code must be run as well.
*/
/* Modem init: echo off, digital speaker off, quiet off, voice mode */
static const char *v253_init = "ate0m0q0+fclass=8\r";
/* Line discipline .open() */
static int v253_open(struct tty_struct *tty)
{
struct snd_soc_codec *codec = cx20442_codec;
int ret, len = strlen(v253_init);
/* Doesn't make sense without write callback */
if (!tty->ops->write)
return -EINVAL;
/* Pass the codec structure address for use by other ldisc callbacks */
tty->disc_data = codec;
if (tty->ops->write(tty, v253_init, len) != len) {
ret = -EIO;
goto err;
}
/* Actual setup will be performed after the modem responds. */
return 0;
err:
tty->disc_data = NULL;
return ret;
}
/* Line discipline .close() */
static void v253_close(struct tty_struct *tty)
{
struct snd_soc_codec *codec = tty->disc_data;
tty->disc_data = NULL;
if (!codec)
return;
/* Prevent the codec driver from further accessing the modem */
codec->hw_write = NULL;
codec->control_data = NULL;
codec->pop_time = 0;
}
/* Line discipline .hangup() */
static int v253_hangup(struct tty_struct *tty)
{
v253_close(tty);
return 0;
}
/* Line discipline .receive_buf() */
static void v253_receive(struct tty_struct *tty,
const unsigned char *cp, char *fp, int count)
{
struct snd_soc_codec *codec = tty->disc_data;
if (!codec)
return;
if (!codec->control_data) {
/* First modem response, complete setup procedure */
/* Set up codec driver access to modem controls */
codec->control_data = tty;
codec->hw_write = (hw_write_t)tty->ops->write;
codec->pop_time = 1;
}
}
/* Line discipline .write_wakeup() */
static void v253_wakeup(struct tty_struct *tty)
{
}
struct tty_ldisc_ops v253_ops = {
.magic = TTY_LDISC_MAGIC,
.name = "cx20442",
.owner = THIS_MODULE,
.open = v253_open,
.close = v253_close,
.hangup = v253_hangup,
.receive_buf = v253_receive,
.write_wakeup = v253_wakeup,
};
EXPORT_SYMBOL_GPL(v253_ops);
/*
* Codec DAI
*/
struct snd_soc_dai cx20442_dai = {
.name = "CX20442",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
};
EXPORT_SYMBOL_GPL(cx20442_dai);
static int cx20442_codec_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret;
if (!cx20442_codec) {
dev_err(&pdev->dev, "cx20442 not yet discovered\n");
return -ENODEV;
}
codec = cx20442_codec;
socdev->card->codec = codec;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(&pdev->dev, "failed to create pcms\n");
goto pcm_err;
}
cx20442_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(&pdev->dev, "failed to register card\n");
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
return ret;
}
/* power down chip */
static int cx20442_codec_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
return 0;
}
struct snd_soc_codec_device cx20442_codec_dev = {
.probe = cx20442_codec_probe,
.remove = cx20442_codec_remove,
};
EXPORT_SYMBOL_GPL(cx20442_codec_dev);
static int cx20442_register(struct cx20442_priv *cx20442)
{
struct snd_soc_codec *codec = &cx20442->codec;
int ret;
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->name = "CX20442";
codec->owner = THIS_MODULE;
codec->private_data = cx20442;
codec->dai = &cx20442_dai;
codec->num_dai = 1;
codec->reg_cache = &cx20442->reg_cache;
codec->reg_cache_size = ARRAY_SIZE(cx20442->reg_cache);
codec->read = cx20442_read_reg_cache;
codec->write = cx20442_write;
codec->bias_level = SND_SOC_BIAS_OFF;
cx20442_dai.dev = codec->dev;
cx20442_codec = codec;
ret = snd_soc_register_codec(codec);
if (ret != 0) {
dev_err(codec->dev, "Failed to register codec: %d\n", ret);
goto err;
}
ret = snd_soc_register_dai(&cx20442_dai);
if (ret != 0) {
dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
goto err_codec;
}
return 0;
err_codec:
snd_soc_unregister_codec(codec);
err:
cx20442_codec = NULL;
kfree(cx20442);
return ret;
}
static void cx20442_unregister(struct cx20442_priv *cx20442)
{
snd_soc_unregister_dai(&cx20442_dai);
snd_soc_unregister_codec(&cx20442->codec);
cx20442_codec = NULL;
kfree(cx20442);
}
static int cx20442_platform_probe(struct platform_device *pdev)
{
struct cx20442_priv *cx20442;
struct snd_soc_codec *codec;
cx20442 = kzalloc(sizeof(struct cx20442_priv), GFP_KERNEL);
if (cx20442 == NULL)
return -ENOMEM;
codec = &cx20442->codec;
codec->control_data = NULL;
codec->hw_write = NULL;
codec->pop_time = 0;
codec->dev = &pdev->dev;
platform_set_drvdata(pdev, cx20442);
return cx20442_register(cx20442);
}
static int __exit cx20442_platform_remove(struct platform_device *pdev)
{
struct cx20442_priv *cx20442 = platform_get_drvdata(pdev);
cx20442_unregister(cx20442);
return 0;
}
static struct platform_driver cx20442_platform_driver = {
.driver = {
.name = "cx20442",
.owner = THIS_MODULE,
},
.probe = cx20442_platform_probe,
.remove = __exit_p(cx20442_platform_remove),
};
static int __init cx20442_init(void)
{
return platform_driver_register(&cx20442_platform_driver);
}
module_init(cx20442_init);
static void __exit cx20442_exit(void)
{
platform_driver_unregister(&cx20442_platform_driver);
}
module_exit(cx20442_exit);
MODULE_DESCRIPTION("ASoC CX20442-11 voice modem codec driver");
MODULE_AUTHOR("Janusz Krzysztofik");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:cx20442");

20
kernel/sound/soc/codecs/cx20442.h Normal file
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/*
* cx20442.h -- audio driver for CX20442
*
* Copyright 2009 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef _CX20442_CODEC_H
#define _CX20442_CODEC_H
extern struct snd_soc_dai cx20442_dai;
extern struct snd_soc_codec_device cx20442_codec_dev;
extern struct tty_ldisc_ops v253_ops;
#endif

91
kernel/sound/soc/codecs/l3.c Normal file
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/*
* L3 code
*
* Copyright (C) 2008, Christian Pellegrin <chripell@evolware.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*
* based on:
*
* L3 bus algorithm module.
*
* Copyright (C) 2001 Russell King, All Rights Reserved.
*
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <sound/l3.h>
/*
* Send one byte of data to the chip. Data is latched into the chip on
* the rising edge of the clock.
*/
static void sendbyte(struct l3_pins *adap, unsigned int byte)
{
int i;
for (i = 0; i < 8; i++) {
adap->setclk(0);
udelay(adap->data_hold);
adap->setdat(byte & 1);
udelay(adap->data_setup);
adap->setclk(1);
udelay(adap->clock_high);
byte >>= 1;
}
}
/*
* Send a set of bytes to the chip. We need to pulse the MODE line
* between each byte, but never at the start nor at the end of the
* transfer.
*/
static void sendbytes(struct l3_pins *adap, const u8 *buf,
int len)
{
int i;
for (i = 0; i < len; i++) {
if (i) {
udelay(adap->mode_hold);
adap->setmode(0);
udelay(adap->mode);
}
adap->setmode(1);
udelay(adap->mode_setup);
sendbyte(adap, buf[i]);
}
}
int l3_write(struct l3_pins *adap, u8 addr, u8 *data, int len)
{
adap->setclk(1);
adap->setdat(1);
adap->setmode(1);
udelay(adap->mode);
adap->setmode(0);
udelay(adap->mode_setup);
sendbyte(adap, addr);
udelay(adap->mode_hold);
sendbytes(adap, data, len);
adap->setclk(1);
adap->setdat(1);
adap->setmode(0);
return len;
}
EXPORT_SYMBOL_GPL(l3_write);
MODULE_DESCRIPTION("L3 bit-banging driver");
MODULE_AUTHOR("Christian Pellegrin <chripell@evolware.org>");
MODULE_LICENSE("GPL");

308
kernel/sound/soc/codecs/max9877.c Normal file
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/*
* max9877.c -- amp driver for max9877
*
* Copyright (C) 2009 Samsung Electronics Co.Ltd
* Author: Joonyoung Shim <jy0922.shim@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "max9877.h"
static struct i2c_client *i2c;
static u8 max9877_regs[5] = { 0x40, 0x00, 0x00, 0x00, 0x49 };
static void max9877_write_regs(void)
{
unsigned int i;
u8 data[6];
data[0] = MAX9877_INPUT_MODE;
for (i = 0; i < ARRAY_SIZE(max9877_regs); i++)
data[i + 1] = max9877_regs[i];
if (i2c_master_send(i2c, data, 6) != 6)
dev_err(&i2c->dev, "i2c write failed\n");
}
static int max9877_get_reg(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int reg = mc->reg;
unsigned int shift = mc->shift;
unsigned int mask = mc->max;
unsigned int invert = mc->invert;
ucontrol->value.integer.value[0] = (max9877_regs[reg] >> shift) & mask;
if (invert)
ucontrol->value.integer.value[0] =
mask - ucontrol->value.integer.value[0];
return 0;
}
static int max9877_set_reg(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int reg = mc->reg;
unsigned int shift = mc->shift;
unsigned int mask = mc->max;
unsigned int invert = mc->invert;
unsigned int val = (ucontrol->value.integer.value[0] & mask);
if (invert)
val = mask - val;
if (((max9877_regs[reg] >> shift) & mask) == val)
return 0;
max9877_regs[reg] &= ~(mask << shift);
max9877_regs[reg] |= val << shift;
max9877_write_regs();
return 1;
}
static int max9877_get_2reg(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int reg = mc->reg;
unsigned int reg2 = mc->rreg;
unsigned int shift = mc->shift;
unsigned int mask = mc->max;
ucontrol->value.integer.value[0] = (max9877_regs[reg] >> shift) & mask;
ucontrol->value.integer.value[1] = (max9877_regs[reg2] >> shift) & mask;
return 0;
}
static int max9877_set_2reg(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
unsigned int reg = mc->reg;
unsigned int reg2 = mc->rreg;
unsigned int shift = mc->shift;
unsigned int mask = mc->max;
unsigned int val = (ucontrol->value.integer.value[0] & mask);
unsigned int val2 = (ucontrol->value.integer.value[1] & mask);
unsigned int change = 1;
if (((max9877_regs[reg] >> shift) & mask) == val)
change = 0;
if (((max9877_regs[reg2] >> shift) & mask) == val2)
change = 0;
if (change) {
max9877_regs[reg] &= ~(mask << shift);
max9877_regs[reg] |= val << shift;
max9877_regs[reg2] &= ~(mask << shift);
max9877_regs[reg2] |= val2 << shift;
max9877_write_regs();
}
return change;
}
static int max9877_get_out_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
u8 value = max9877_regs[MAX9877_OUTPUT_MODE] & MAX9877_OUTMODE_MASK;
if (value)
value -= 1;
ucontrol->value.integer.value[0] = value;
return 0;
}
static int max9877_set_out_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
u8 value = ucontrol->value.integer.value[0];
value += 1;
if ((max9877_regs[MAX9877_OUTPUT_MODE] & MAX9877_OUTMODE_MASK) == value)
return 0;
max9877_regs[MAX9877_OUTPUT_MODE] &= ~MAX9877_OUTMODE_MASK;
max9877_regs[MAX9877_OUTPUT_MODE] |= value;
max9877_write_regs();
return 1;
}
static int max9877_get_osc_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
u8 value = (max9877_regs[MAX9877_OUTPUT_MODE] & MAX9877_OSC_MASK);
value = value >> MAX9877_OSC_OFFSET;
ucontrol->value.integer.value[0] = value;
return 0;
}
static int max9877_set_osc_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
u8 value = ucontrol->value.integer.value[0];
value = value << MAX9877_OSC_OFFSET;
if ((max9877_regs[MAX9877_OUTPUT_MODE] & MAX9877_OSC_MASK) == value)
return 0;
max9877_regs[MAX9877_OUTPUT_MODE] &= ~MAX9877_OSC_MASK;
max9877_regs[MAX9877_OUTPUT_MODE] |= value;
max9877_write_regs();
return 1;
}
static const unsigned int max9877_pgain_tlv[] = {
TLV_DB_RANGE_HEAD(2),
0, 1, TLV_DB_SCALE_ITEM(0, 900, 0),
2, 2, TLV_DB_SCALE_ITEM(2000, 0, 0),
};
static const unsigned int max9877_output_tlv[] = {
TLV_DB_RANGE_HEAD(4),
0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1),
8, 15, TLV_DB_SCALE_ITEM(-4700, 300, 0),
16, 23, TLV_DB_SCALE_ITEM(-2300, 200, 0),
24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0),
};
static const char *max9877_out_mode[] = {
"INA -> SPK",
"INA -> HP",
"INA -> SPK and HP",
"INB -> SPK",
"INB -> HP",
"INB -> SPK and HP",
"INA + INB -> SPK",
"INA + INB -> HP",
"INA + INB -> SPK and HP",
};
static const char *max9877_osc_mode[] = {
"1176KHz",
"1100KHz",
"700KHz",
};
static const struct soc_enum max9877_enum[] = {
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(max9877_out_mode), max9877_out_mode),
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(max9877_osc_mode), max9877_osc_mode),
};
static const struct snd_kcontrol_new max9877_controls[] = {
SOC_SINGLE_EXT_TLV("MAX9877 PGAINA Playback Volume",
MAX9877_INPUT_MODE, 0, 2, 0,
max9877_get_reg, max9877_set_reg, max9877_pgain_tlv),
SOC_SINGLE_EXT_TLV("MAX9877 PGAINB Playback Volume",
MAX9877_INPUT_MODE, 2, 2, 0,
max9877_get_reg, max9877_set_reg, max9877_pgain_tlv),
SOC_SINGLE_EXT_TLV("MAX9877 Amp Speaker Playback Volume",
MAX9877_SPK_VOLUME, 0, 31, 0,
max9877_get_reg, max9877_set_reg, max9877_output_tlv),
SOC_DOUBLE_R_EXT_TLV("MAX9877 Amp HP Playback Volume",
MAX9877_HPL_VOLUME, MAX9877_HPR_VOLUME, 0, 31, 0,
max9877_get_2reg, max9877_set_2reg, max9877_output_tlv),
SOC_SINGLE_EXT("MAX9877 INB Stereo Switch",
MAX9877_INPUT_MODE, 4, 1, 1,
max9877_get_reg, max9877_set_reg),
SOC_SINGLE_EXT("MAX9877 INA Stereo Switch",
MAX9877_INPUT_MODE, 5, 1, 1,
max9877_get_reg, max9877_set_reg),
SOC_SINGLE_EXT("MAX9877 Zero-crossing detection Switch",
MAX9877_INPUT_MODE, 6, 1, 0,
max9877_get_reg, max9877_set_reg),
SOC_SINGLE_EXT("MAX9877 Bypass Mode Switch",
MAX9877_OUTPUT_MODE, 6, 1, 0,
max9877_get_reg, max9877_set_reg),
SOC_SINGLE_EXT("MAX9877 Shutdown Mode Switch",
MAX9877_OUTPUT_MODE, 7, 1, 1,
max9877_get_reg, max9877_set_reg),
SOC_ENUM_EXT("MAX9877 Output Mode", max9877_enum[0],
max9877_get_out_mode, max9877_set_out_mode),
SOC_ENUM_EXT("MAX9877 Oscillator Mode", max9877_enum[1],
max9877_get_osc_mode, max9877_set_osc_mode),
};
/* This function is called from ASoC machine driver */
int max9877_add_controls(struct snd_soc_codec *codec)
{
return snd_soc_add_controls(codec, max9877_controls,
ARRAY_SIZE(max9877_controls));
}
EXPORT_SYMBOL_GPL(max9877_add_controls);
static int __devinit max9877_i2c_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
i2c = client;
max9877_write_regs();
return 0;
}
static __devexit int max9877_i2c_remove(struct i2c_client *client)
{
i2c = NULL;
return 0;
}
static const struct i2c_device_id max9877_i2c_id[] = {
{ "max9877", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max9877_i2c_id);
static struct i2c_driver max9877_i2c_driver = {
.driver = {
.name = "max9877",
.owner = THIS_MODULE,
},
.probe = max9877_i2c_probe,
.remove = __devexit_p(max9877_i2c_remove),
.id_table = max9877_i2c_id,
};
static int __init max9877_init(void)
{
return i2c_add_driver(&max9877_i2c_driver);
}
module_init(max9877_init);
static void __exit max9877_exit(void)
{
i2c_del_driver(&max9877_i2c_driver);
}
module_exit(max9877_exit);
MODULE_DESCRIPTION("ASoC MAX9877 amp driver");
MODULE_AUTHOR("Joonyoung Shim <jy0922.shim@samsung.com>");
MODULE_LICENSE("GPL");

37
kernel/sound/soc/codecs/max9877.h Normal file
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/*
* max9877.h -- amp driver for max9877
*
* Copyright (C) 2009 Samsung Electronics Co.Ltd
* Author: Joonyoung Shim <jy0922.shim@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef _MAX9877_H
#define _MAX9877_H
#define MAX9877_INPUT_MODE 0x00
#define MAX9877_SPK_VOLUME 0x01
#define MAX9877_HPL_VOLUME 0x02
#define MAX9877_HPR_VOLUME 0x03
#define MAX9877_OUTPUT_MODE 0x04
/* MAX9877_INPUT_MODE */
#define MAX9877_INB (1 << 4)
#define MAX9877_INA (1 << 5)
#define MAX9877_ZCD (1 << 6)
/* MAX9877_OUTPUT_MODE */
#define MAX9877_OUTMODE_MASK (15 << 0)
#define MAX9877_OSC_MASK (3 << 4)
#define MAX9877_OSC_OFFSET 4
#define MAX9877_BYPASS (1 << 6)
#define MAX9877_SHDN (1 << 7)
extern int max9877_add_controls(struct snd_soc_codec *codec);
#endif

212
kernel/sound/soc/codecs/pcm3008.c Normal file
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/*
* ALSA Soc PCM3008 codec support
*
* Author: Hugo Villeneuve
* Copyright (C) 2008 Lyrtech inc
*
* Based on AC97 Soc codec, original copyright follow:
* Copyright 2005 Wolfson Microelectronics PLC.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Generic PCM3008 support.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include "pcm3008.h"
#define PCM3008_VERSION "0.2"
#define PCM3008_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000)
struct snd_soc_dai pcm3008_dai = {
.name = "PCM3008 HiFi",
.playback = {
.stream_name = "PCM3008 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = PCM3008_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "PCM3008 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = PCM3008_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
};
EXPORT_SYMBOL_GPL(pcm3008_dai);
static void pcm3008_gpio_free(struct pcm3008_setup_data *setup)
{
gpio_free(setup->dem0_pin);
gpio_free(setup->dem1_pin);
gpio_free(setup->pdad_pin);
gpio_free(setup->pdda_pin);
}
static int pcm3008_soc_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
struct pcm3008_setup_data *setup = socdev->codec_data;
int ret = 0;
printk(KERN_INFO "PCM3008 SoC Audio Codec %s\n", PCM3008_VERSION);
socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
if (!socdev->card->codec)
return -ENOMEM;
codec = socdev->card->codec;
mutex_init(&codec->mutex);
codec->name = "PCM3008";
codec->owner = THIS_MODULE;
codec->dai = &pcm3008_dai;
codec->num_dai = 1;
codec->write = NULL;
codec->read = NULL;
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
/* Register PCMs. */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
printk(KERN_ERR "pcm3008: failed to create pcms\n");
goto pcm_err;
}
/* Register Card. */
ret = snd_soc_init_card(socdev);
if (ret < 0) {
printk(KERN_ERR "pcm3008: failed to register card\n");
goto card_err;
}
/* DEM1 DEM0 DE-EMPHASIS_MODE
* Low Low De-emphasis 44.1 kHz ON
* Low High De-emphasis OFF
* High Low De-emphasis 48 kHz ON
* High High De-emphasis 32 kHz ON
*/
/* Configure DEM0 GPIO (turning OFF DAC De-emphasis). */
ret = gpio_request(setup->dem0_pin, "codec_dem0");
if (ret == 0)
ret = gpio_direction_output(setup->dem0_pin, 1);
if (ret != 0)
goto gpio_err;
/* Configure DEM1 GPIO (turning OFF DAC De-emphasis). */
ret = gpio_request(setup->dem1_pin, "codec_dem1");
if (ret == 0)
ret = gpio_direction_output(setup->dem1_pin, 0);
if (ret != 0)
goto gpio_err;
/* Configure PDAD GPIO. */
ret = gpio_request(setup->pdad_pin, "codec_pdad");
if (ret == 0)
ret = gpio_direction_output(setup->pdad_pin, 1);
if (ret != 0)
goto gpio_err;
/* Configure PDDA GPIO. */
ret = gpio_request(setup->pdda_pin, "codec_pdda");
if (ret == 0)
ret = gpio_direction_output(setup->pdda_pin, 1);
if (ret != 0)
goto gpio_err;
return ret;
gpio_err:
pcm3008_gpio_free(setup);
card_err:
snd_soc_free_pcms(socdev);
pcm_err:
kfree(socdev->card->codec);
return ret;
}
static int pcm3008_soc_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
struct pcm3008_setup_data *setup = socdev->codec_data;
if (!codec)
return 0;
pcm3008_gpio_free(setup);
snd_soc_free_pcms(socdev);
kfree(socdev->card->codec);
return 0;
}
#ifdef CONFIG_PM
static int pcm3008_soc_suspend(struct platform_device *pdev, pm_message_t msg)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct pcm3008_setup_data *setup = socdev->codec_data;
gpio_set_value(setup->pdad_pin, 0);
gpio_set_value(setup->pdda_pin, 0);
return 0;
}
static int pcm3008_soc_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct pcm3008_setup_data *setup = socdev->codec_data;
gpio_set_value(setup->pdad_pin, 1);
gpio_set_value(setup->pdda_pin, 1);
return 0;
}
#else
#define pcm3008_soc_suspend NULL
#define pcm3008_soc_resume NULL
#endif
struct snd_soc_codec_device soc_codec_dev_pcm3008 = {
.probe = pcm3008_soc_probe,
.remove = pcm3008_soc_remove,
.suspend = pcm3008_soc_suspend,
.resume = pcm3008_soc_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_pcm3008);
static int __init pcm3008_init(void)
{
return snd_soc_register_dai(&pcm3008_dai);
}
module_init(pcm3008_init);
static void __exit pcm3008_exit(void)
{
snd_soc_unregister_dai(&pcm3008_dai);
}
module_exit(pcm3008_exit);
MODULE_DESCRIPTION("Soc PCM3008 driver");
MODULE_AUTHOR("Hugo Villeneuve");
MODULE_LICENSE("GPL");

25
kernel/sound/soc/codecs/pcm3008.h Normal file
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/*
* PCM3008 ALSA SoC Layer
*
* Author: Hugo Villeneuve
* Copyright (C) 2008 Lyrtech inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_SND_SOC_PCM3008_H
#define __LINUX_SND_SOC_PCM3008_H
struct pcm3008_setup_data {
unsigned dem0_pin;
unsigned dem1_pin;
unsigned pdad_pin;
unsigned pdda_pin;
};
extern struct snd_soc_codec_device soc_codec_dev_pcm3008;
extern struct snd_soc_dai pcm3008_dai;
#endif

74
kernel/sound/soc/codecs/spdif_transciever.c Normal file
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/*
* ALSA SoC SPDIF DIT driver
*
* This driver is used by controllers which can operate in DIT (SPDI/F) where
* no codec is needed. This file provides stub codec that can be used
* in these configurations. TI DaVinci Audio controller uses this driver.
*
* Author: Steve Chen, <schen@mvista.com>
* Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
* Copyright: (C) 2009 Texas Instruments, India
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include "spdif_transciever.h"
MODULE_LICENSE("GPL");
#define STUB_RATES SNDRV_PCM_RATE_8000_96000
#define STUB_FORMATS SNDRV_PCM_FMTBIT_S16_LE
struct snd_soc_dai dit_stub_dai = {
.name = "DIT",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 384,
.rates = STUB_RATES,
.formats = STUB_FORMATS,
},
};
EXPORT_SYMBOL_GPL(dit_stub_dai);
static int spdif_dit_probe(struct platform_device *pdev)
{
dit_stub_dai.dev = &pdev->dev;
return snd_soc_register_dai(&dit_stub_dai);
}
static int spdif_dit_remove(struct platform_device *pdev)
{
snd_soc_unregister_dai(&dit_stub_dai);
return 0;
}
static struct platform_driver spdif_dit_driver = {
.probe = spdif_dit_probe,
.remove = spdif_dit_remove,
.driver = {
.name = "spdif-dit",
.owner = THIS_MODULE,
},
};
static int __init dit_modinit(void)
{
return platform_driver_register(&spdif_dit_driver);
}
static void __exit dit_exit(void)
{
platform_driver_unregister(&spdif_dit_driver);
}
module_init(dit_modinit);
module_exit(dit_exit);

17
kernel/sound/soc/codecs/spdif_transciever.h Normal file
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/*
* ALSA SoC DIT/DIR driver header
*
* Author: Steve Chen, <schen@mvista.com>
* Copyright: (C) 2008 MontaVista Software, Inc., <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef CODEC_STUBS_H
#define CODEC_STUBS_H
extern struct snd_soc_dai dit_stub_dai;
#endif /* CODEC_STUBS_H */

799
kernel/sound/soc/codecs/ssm2602.c Normal file
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/*
* File: sound/soc/codecs/ssm2602.c
* Author: Cliff Cai <Cliff.Cai@analog.com>
*
* Created: Tue June 06 2008
* Description: Driver for ssm2602 sound chip
*
* Modified:
* Copyright 2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include "ssm2602.h"
#define SSM2602_VERSION "0.1"
struct snd_soc_codec_device soc_codec_dev_ssm2602;
/* codec private data */
struct ssm2602_priv {
unsigned int sysclk;
struct snd_pcm_substream *master_substream;
struct snd_pcm_substream *slave_substream;
};
/*
* ssm2602 register cache
* We can't read the ssm2602 register space when we are
* using 2 wire for device control, so we cache them instead.
* There is no point in caching the reset register
*/
static const u16 ssm2602_reg[SSM2602_CACHEREGNUM] = {
0x0017, 0x0017, 0x0079, 0x0079,
0x0000, 0x0000, 0x0000, 0x000a,
0x0000, 0x0000
};
/*
* read ssm2602 register cache
*/
static inline unsigned int ssm2602_read_reg_cache(struct snd_soc_codec *codec,
unsigned int reg)
{
u16 *cache = codec->reg_cache;
if (reg == SSM2602_RESET)
return 0;
if (reg >= SSM2602_CACHEREGNUM)
return -1;
return cache[reg];
}
/*
* write ssm2602 register cache
*/
static inline void ssm2602_write_reg_cache(struct snd_soc_codec *codec,
u16 reg, unsigned int value)
{
u16 *cache = codec->reg_cache;
if (reg >= SSM2602_CACHEREGNUM)
return;
cache[reg] = value;
}
/*
* write to the ssm2602 register space
*/
static int ssm2602_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
u8 data[2];
/* data is
* D15..D9 ssm2602 register offset
* D8...D0 register data
*/
data[0] = (reg << 1) | ((value >> 8) & 0x0001);
data[1] = value & 0x00ff;
ssm2602_write_reg_cache(codec, reg, value);
if (codec->hw_write(codec->control_data, data, 2) == 2)
return 0;
else
return -EIO;
}
#define ssm2602_reset(c) ssm2602_write(c, SSM2602_RESET, 0)
/*Appending several "None"s just for OSS mixer use*/
static const char *ssm2602_input_select[] = {
"Line", "Mic", "None", "None", "None",
"None", "None", "None",
};
static const char *ssm2602_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static const struct soc_enum ssm2602_enum[] = {
SOC_ENUM_SINGLE(SSM2602_APANA, 2, 2, ssm2602_input_select),
SOC_ENUM_SINGLE(SSM2602_APDIGI, 1, 4, ssm2602_deemph),
};
static const struct snd_kcontrol_new ssm2602_snd_controls[] = {
SOC_DOUBLE_R("Master Playback Volume", SSM2602_LOUT1V, SSM2602_ROUT1V,
0, 127, 0),
SOC_DOUBLE_R("Master Playback ZC Switch", SSM2602_LOUT1V, SSM2602_ROUT1V,
7, 1, 0),
SOC_DOUBLE_R("Capture Volume", SSM2602_LINVOL, SSM2602_RINVOL, 0, 31, 0),
SOC_DOUBLE_R("Capture Switch", SSM2602_LINVOL, SSM2602_RINVOL, 7, 1, 1),
SOC_SINGLE("Mic Boost (+20dB)", SSM2602_APANA, 0, 1, 0),
SOC_SINGLE("Mic Switch", SSM2602_APANA, 1, 1, 1),
SOC_SINGLE("Sidetone Playback Volume", SSM2602_APANA, 6, 3, 1),
SOC_SINGLE("ADC High Pass Filter Switch", SSM2602_APDIGI, 0, 1, 1),
SOC_SINGLE("Store DC Offset Switch", SSM2602_APDIGI, 4, 1, 0),
SOC_ENUM("Capture Source", ssm2602_enum[0]),
SOC_ENUM("Playback De-emphasis", ssm2602_enum[1]),
};
/* Output Mixer */
static const struct snd_kcontrol_new ssm2602_output_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", SSM2602_APANA, 3, 1, 0),
SOC_DAPM_SINGLE("Mic Sidetone Switch", SSM2602_APANA, 5, 1, 0),
SOC_DAPM_SINGLE("HiFi Playback Switch", SSM2602_APANA, 4, 1, 0),
};
/* Input mux */
static const struct snd_kcontrol_new ssm2602_input_mux_controls =
SOC_DAPM_ENUM("Input Select", ssm2602_enum[0]);
static const struct snd_soc_dapm_widget ssm2602_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Output Mixer", SSM2602_PWR, 4, 1,
&ssm2602_output_mixer_controls[0],
ARRAY_SIZE(ssm2602_output_mixer_controls)),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", SSM2602_PWR, 3, 1),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("LHPOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("RHPOUT"),
SND_SOC_DAPM_ADC("ADC", "HiFi Capture", SSM2602_PWR, 2, 1),
SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0, &ssm2602_input_mux_controls),
SND_SOC_DAPM_PGA("Line Input", SSM2602_PWR, 0, 1, NULL, 0),
SND_SOC_DAPM_MICBIAS("Mic Bias", SSM2602_PWR, 1, 1),
SND_SOC_DAPM_INPUT("MICIN"),
SND_SOC_DAPM_INPUT("RLINEIN"),
SND_SOC_DAPM_INPUT("LLINEIN"),
};
static const struct snd_soc_dapm_route audio_conn[] = {
/* output mixer */
{"Output Mixer", "Line Bypass Switch", "Line Input"},
{"Output Mixer", "HiFi Playback Switch", "DAC"},
{"Output Mixer", "Mic Sidetone Switch", "Mic Bias"},
/* outputs */
{"RHPOUT", NULL, "Output Mixer"},
{"ROUT", NULL, "Output Mixer"},
{"LHPOUT", NULL, "Output Mixer"},
{"LOUT", NULL, "Output Mixer"},
/* input mux */
{"Input Mux", "Line", "Line Input"},
{"Input Mux", "Mic", "Mic Bias"},
{"ADC", NULL, "Input Mux"},
/* inputs */
{"Line Input", NULL, "LLINEIN"},
{"Line Input", NULL, "RLINEIN"},
{"Mic Bias", NULL, "MICIN"},
};
static int ssm2602_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, ssm2602_dapm_widgets,
ARRAY_SIZE(ssm2602_dapm_widgets));
snd_soc_dapm_add_routes(codec, audio_conn, ARRAY_SIZE(audio_conn));
snd_soc_dapm_new_widgets(codec);
return 0;
}
struct _coeff_div {
u32 mclk;
u32 rate;
u16 fs;
u8 sr:4;
u8 bosr:1;
u8 usb:1;
};
/* codec mclk clock divider coefficients */
static const struct _coeff_div coeff_div[] = {
/* 48k */
{12288000, 48000, 256, 0x0, 0x0, 0x0},
{18432000, 48000, 384, 0x0, 0x1, 0x0},
{12000000, 48000, 250, 0x0, 0x0, 0x1},
/* 32k */
{12288000, 32000, 384, 0x6, 0x0, 0x0},
{18432000, 32000, 576, 0x6, 0x1, 0x0},
{12000000, 32000, 375, 0x6, 0x0, 0x1},
/* 8k */
{12288000, 8000, 1536, 0x3, 0x0, 0x0},
{18432000, 8000, 2304, 0x3, 0x1, 0x0},
{11289600, 8000, 1408, 0xb, 0x0, 0x0},
{16934400, 8000, 2112, 0xb, 0x1, 0x0},
{12000000, 8000, 1500, 0x3, 0x0, 0x1},
/* 96k */
{12288000, 96000, 128, 0x7, 0x0, 0x0},
{18432000, 96000, 192, 0x7, 0x1, 0x0},
{12000000, 96000, 125, 0x7, 0x0, 0x1},
/* 44.1k */
{11289600, 44100, 256, 0x8, 0x0, 0x0},
{16934400, 44100, 384, 0x8, 0x1, 0x0},
{12000000, 44100, 272, 0x8, 0x1, 0x1},
/* 88.2k */
{11289600, 88200, 128, 0xf, 0x0, 0x0},
{16934400, 88200, 192, 0xf, 0x1, 0x0},
{12000000, 88200, 136, 0xf, 0x1, 0x1},
};
static inline int get_coeff(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
return i;
}
return i;
}
static int ssm2602_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
u16 srate;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct ssm2602_priv *ssm2602 = codec->private_data;
struct i2c_client *i2c = codec->control_data;
u16 iface = ssm2602_read_reg_cache(codec, SSM2602_IFACE) & 0xfff3;
int i = get_coeff(ssm2602->sysclk, params_rate(params));
if (substream == ssm2602->slave_substream) {
dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
return 0;
}
/*no match is found*/
if (i == ARRAY_SIZE(coeff_div))
return -EINVAL;
srate = (coeff_div[i].sr << 2) |
(coeff_div[i].bosr << 1) | coeff_div[i].usb;
ssm2602_write(codec, SSM2602_ACTIVE, 0);
ssm2602_write(codec, SSM2602_SRATE, srate);
/* bit size */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
iface |= 0x0004;
break;
case SNDRV_PCM_FORMAT_S24_LE:
iface |= 0x0008;
break;
case SNDRV_PCM_FORMAT_S32_LE:
iface |= 0x000c;
break;
}
ssm2602_write(codec, SSM2602_IFACE, iface);
ssm2602_write(codec, SSM2602_ACTIVE, ACTIVE_ACTIVATE_CODEC);
return 0;
}
static int ssm2602_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct ssm2602_priv *ssm2602 = codec->private_data;
struct i2c_client *i2c = codec->control_data;
struct snd_pcm_runtime *master_runtime;
/* The DAI has shared clocks so if we already have a playback or
* capture going then constrain this substream to match it.
* TODO: the ssm2602 allows pairs of non-matching PB/REC rates
*/
if (ssm2602->master_substream) {
master_runtime = ssm2602->master_substream->runtime;
dev_dbg(&i2c->dev, "Constraining to %d bits at %dHz\n",
master_runtime->sample_bits,
master_runtime->rate);
if (master_runtime->rate != 0)
snd_pcm_hw_constraint_minmax(substream->runtime,
SNDRV_PCM_HW_PARAM_RATE,
master_runtime->rate,
master_runtime->rate);
if (master_runtime->sample_bits != 0)
snd_pcm_hw_constraint_minmax(substream->runtime,
SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
master_runtime->sample_bits,
master_runtime->sample_bits);
ssm2602->slave_substream = substream;
} else
ssm2602->master_substream = substream;
return 0;
}
static int ssm2602_pcm_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
/* set active */
ssm2602_write(codec, SSM2602_ACTIVE, ACTIVE_ACTIVATE_CODEC);
return 0;
}
static void ssm2602_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct ssm2602_priv *ssm2602 = codec->private_data;
/* deactivate */
if (!codec->active)
ssm2602_write(codec, SSM2602_ACTIVE, 0);
if (ssm2602->master_substream == substream)
ssm2602->master_substream = ssm2602->slave_substream;
ssm2602->slave_substream = NULL;
}
static int ssm2602_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
u16 mute_reg = ssm2602_read_reg_cache(codec, SSM2602_APDIGI) & ~APDIGI_ENABLE_DAC_MUTE;
if (mute)
ssm2602_write(codec, SSM2602_APDIGI,
mute_reg | APDIGI_ENABLE_DAC_MUTE);
else
ssm2602_write(codec, SSM2602_APDIGI, mute_reg);
return 0;
}
static int ssm2602_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct ssm2602_priv *ssm2602 = codec->private_data;
switch (freq) {
case 11289600:
case 12000000:
case 12288000:
case 16934400:
case 18432000:
ssm2602->sysclk = freq;
return 0;
}
return -EINVAL;
}
static int ssm2602_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 iface = 0;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
iface |= 0x0040;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x0013;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= 0x0003;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0090;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0010;
break;
default:
return -EINVAL;
}
/* set iface */
ssm2602_write(codec, SSM2602_IFACE, iface);
return 0;
}
static int ssm2602_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
u16 reg = ssm2602_read_reg_cache(codec, SSM2602_PWR) & 0xff7f;
switch (level) {
case SND_SOC_BIAS_ON:
/* vref/mid, osc on, dac unmute */
ssm2602_write(codec, SSM2602_PWR, reg);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* everything off except vref/vmid, */
ssm2602_write(codec, SSM2602_PWR, reg | PWR_CLK_OUT_PDN);
break;
case SND_SOC_BIAS_OFF:
/* everything off, dac mute, inactive */
ssm2602_write(codec, SSM2602_ACTIVE, 0);
ssm2602_write(codec, SSM2602_PWR, 0xffff);
break;
}
codec->bias_level = level;
return 0;
}
#define SSM2602_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define SSM2602_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_ops ssm2602_dai_ops = {
.startup = ssm2602_startup,
.prepare = ssm2602_pcm_prepare,
.hw_params = ssm2602_hw_params,
.shutdown = ssm2602_shutdown,
.digital_mute = ssm2602_mute,
.set_sysclk = ssm2602_set_dai_sysclk,
.set_fmt = ssm2602_set_dai_fmt,
};
struct snd_soc_dai ssm2602_dai = {
.name = "SSM2602",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SSM2602_RATES,
.formats = SSM2602_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SSM2602_RATES,
.formats = SSM2602_FORMATS,},
.ops = &ssm2602_dai_ops,
};
EXPORT_SYMBOL_GPL(ssm2602_dai);
static int ssm2602_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
ssm2602_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int ssm2602_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
int i;
u8 data[2];
u16 *cache = codec->reg_cache;
/* Sync reg_cache with the hardware */
for (i = 0; i < ARRAY_SIZE(ssm2602_reg); i++) {
data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
data[1] = cache[i] & 0x00ff;
codec->hw_write(codec->control_data, data, 2);
}
ssm2602_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
ssm2602_set_bias_level(codec, codec->suspend_bias_level);
return 0;
}
/*
* initialise the ssm2602 driver
* register the mixer and dsp interfaces with the kernel
*/
static int ssm2602_init(struct snd_soc_device *socdev)
{
struct snd_soc_codec *codec = socdev->card->codec;
int reg, ret = 0;
codec->name = "SSM2602";
codec->owner = THIS_MODULE;
codec->read = ssm2602_read_reg_cache;
codec->write = ssm2602_write;
codec->set_bias_level = ssm2602_set_bias_level;
codec->dai = &ssm2602_dai;
codec->num_dai = 1;
codec->reg_cache_size = sizeof(ssm2602_reg);
codec->reg_cache = kmemdup(ssm2602_reg, sizeof(ssm2602_reg),
GFP_KERNEL);
if (codec->reg_cache == NULL)
return -ENOMEM;
ssm2602_reset(codec);
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
pr_err("ssm2602: failed to create pcms\n");
goto pcm_err;
}
/*power on device*/
ssm2602_write(codec, SSM2602_ACTIVE, 0);
/* set the update bits */
reg = ssm2602_read_reg_cache(codec, SSM2602_LINVOL);
ssm2602_write(codec, SSM2602_LINVOL, reg | LINVOL_LRIN_BOTH);
reg = ssm2602_read_reg_cache(codec, SSM2602_RINVOL);
ssm2602_write(codec, SSM2602_RINVOL, reg | RINVOL_RLIN_BOTH);
reg = ssm2602_read_reg_cache(codec, SSM2602_LOUT1V);
ssm2602_write(codec, SSM2602_LOUT1V, reg | LOUT1V_LRHP_BOTH);
reg = ssm2602_read_reg_cache(codec, SSM2602_ROUT1V);
ssm2602_write(codec, SSM2602_ROUT1V, reg | ROUT1V_RLHP_BOTH);
/*select Line in as default input*/
ssm2602_write(codec, SSM2602_APANA,
APANA_ENABLE_MIC_BOOST2 | APANA_SELECT_DAC |
APANA_ENABLE_MIC_BOOST);
ssm2602_write(codec, SSM2602_PWR, 0);
snd_soc_add_controls(codec, ssm2602_snd_controls,
ARRAY_SIZE(ssm2602_snd_controls));
ssm2602_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
pr_err("ssm2602: failed to register card\n");
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
kfree(codec->reg_cache);
return ret;
}
static struct snd_soc_device *ssm2602_socdev;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
/*
* ssm2602 2 wire address is determined by GPIO5
* state during powerup.
* low = 0x1a
* high = 0x1b
*/
static int ssm2602_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct snd_soc_device *socdev = ssm2602_socdev;
struct snd_soc_codec *codec = socdev->card->codec;
int ret;
i2c_set_clientdata(i2c, codec);
codec->control_data = i2c;
ret = ssm2602_init(socdev);
if (ret < 0)
pr_err("failed to initialise SSM2602\n");
return ret;
}
static int ssm2602_i2c_remove(struct i2c_client *client)
{
struct snd_soc_codec *codec = i2c_get_clientdata(client);
kfree(codec->reg_cache);
return 0;
}
static const struct i2c_device_id ssm2602_i2c_id[] = {
{ "ssm2602", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ssm2602_i2c_id);
/* corgi i2c codec control layer */
static struct i2c_driver ssm2602_i2c_driver = {
.driver = {
.name = "SSM2602 I2C Codec",
.owner = THIS_MODULE,
},
.probe = ssm2602_i2c_probe,
.remove = ssm2602_i2c_remove,
.id_table = ssm2602_i2c_id,
};
static int ssm2602_add_i2c_device(struct platform_device *pdev,
const struct ssm2602_setup_data *setup)
{
struct i2c_board_info info;
struct i2c_adapter *adapter;
struct i2c_client *client;
int ret;
ret = i2c_add_driver(&ssm2602_i2c_driver);
if (ret != 0) {
dev_err(&pdev->dev, "can't add i2c driver\n");
return ret;
}
memset(&info, 0, sizeof(struct i2c_board_info));
info.addr = setup->i2c_address;
strlcpy(info.type, "ssm2602", I2C_NAME_SIZE);
adapter = i2c_get_adapter(setup->i2c_bus);
if (!adapter) {
dev_err(&pdev->dev, "can't get i2c adapter %d\n",
setup->i2c_bus);
goto err_driver;
}
client = i2c_new_device(adapter, &info);
i2c_put_adapter(adapter);
if (!client) {
dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
(unsigned int)info.addr);
goto err_driver;
}
return 0;
err_driver:
i2c_del_driver(&ssm2602_i2c_driver);
return -ENODEV;
}
#endif
static int ssm2602_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct ssm2602_setup_data *setup;
struct snd_soc_codec *codec;
struct ssm2602_priv *ssm2602;
int ret = 0;
pr_info("ssm2602 Audio Codec %s", SSM2602_VERSION);
setup = socdev->codec_data;
codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
if (codec == NULL)
return -ENOMEM;
ssm2602 = kzalloc(sizeof(struct ssm2602_priv), GFP_KERNEL);
if (ssm2602 == NULL) {
kfree(codec);
return -ENOMEM;
}
codec->private_data = ssm2602;
socdev->card->codec = codec;
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
ssm2602_socdev = socdev;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
if (setup->i2c_address) {
codec->hw_write = (hw_write_t)i2c_master_send;
ret = ssm2602_add_i2c_device(pdev, setup);
}
#else
/* other interfaces */
#endif
return ret;
}
/* remove everything here */
static int ssm2602_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
if (codec->control_data)
ssm2602_set_bias_level(codec, SND_SOC_BIAS_OFF);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
i2c_unregister_device(codec->control_data);
i2c_del_driver(&ssm2602_i2c_driver);
#endif
kfree(codec->private_data);
kfree(codec);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_ssm2602 = {
.probe = ssm2602_probe,
.remove = ssm2602_remove,
.suspend = ssm2602_suspend,
.resume = ssm2602_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_ssm2602);
static int __init ssm2602_modinit(void)
{
return snd_soc_register_dai(&ssm2602_dai);
}
module_init(ssm2602_modinit);
static void __exit ssm2602_exit(void)
{
snd_soc_unregister_dai(&ssm2602_dai);
}
module_exit(ssm2602_exit);
MODULE_DESCRIPTION("ASoC ssm2602 driver");
MODULE_AUTHOR("Cliff Cai");
MODULE_LICENSE("GPL");

130
kernel/sound/soc/codecs/ssm2602.h Normal file
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/*
* File: sound/soc/codecs/ssm2602.h
* Author: Cliff Cai <Cliff.Cai@analog.com>
*
* Created: Tue June 06 2008
*
* Modified:
* Copyright 2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _SSM2602_H
#define _SSM2602_H
/* SSM2602 Codec Register definitions */
#define SSM2602_LINVOL 0x00
#define SSM2602_RINVOL 0x01
#define SSM2602_LOUT1V 0x02
#define SSM2602_ROUT1V 0x03
#define SSM2602_APANA 0x04
#define SSM2602_APDIGI 0x05
#define SSM2602_PWR 0x06
#define SSM2602_IFACE 0x07
#define SSM2602_SRATE 0x08
#define SSM2602_ACTIVE 0x09
#define SSM2602_RESET 0x0f
/*SSM2602 Codec Register Field definitions
*(Mask value to extract the corresponding Register field)
*/
/*Left ADC Volume Control (SSM2602_REG_LEFT_ADC_VOL)*/
#define LINVOL_LIN_VOL 0x01F /* Left Channel PGA Volume control */
#define LINVOL_LIN_ENABLE_MUTE 0x080 /* Left Channel Input Mute */
#define LINVOL_LRIN_BOTH 0x100 /* Left Channel Line Input Volume update */
/*Right ADC Volume Control (SSM2602_REG_RIGHT_ADC_VOL)*/
#define RINVOL_RIN_VOL 0x01F /* Right Channel PGA Volume control */
#define RINVOL_RIN_ENABLE_MUTE 0x080 /* Right Channel Input Mute */
#define RINVOL_RLIN_BOTH 0x100 /* Right Channel Line Input Volume update */
/*Left DAC Volume Control (SSM2602_REG_LEFT_DAC_VOL)*/
#define LOUT1V_LHP_VOL 0x07F /* Left Channel Headphone volume control */
#define LOUT1V_ENABLE_LZC 0x080 /* Left Channel Zero cross detect enable */
#define LOUT1V_LRHP_BOTH 0x100 /* Left Channel Headphone volume update */
/*Right DAC Volume Control (SSM2602_REG_RIGHT_DAC_VOL)*/
#define ROUT1V_RHP_VOL 0x07F /* Right Channel Headphone volume control */
#define ROUT1V_ENABLE_RZC 0x080 /* Right Channel Zero cross detect enable */
#define ROUT1V_RLHP_BOTH 0x100 /* Right Channel Headphone volume update */
/*Analogue Audio Path Control (SSM2602_REG_ANALOGUE_PATH)*/
#define APANA_ENABLE_MIC_BOOST 0x001 /* Primary Microphone Amplifier gain booster control */
#define APANA_ENABLE_MIC_MUTE 0x002 /* Microphone Mute Control */
#define APANA_ADC_IN_SELECT 0x004 /* Microphone/Line IN select to ADC (1=MIC, 0=Line In) */
#define APANA_ENABLE_BYPASS 0x008 /* Line input bypass to line output */
#define APANA_SELECT_DAC 0x010 /* Select DAC (1=Select DAC, 0=Don't Select DAC) */
#define APANA_ENABLE_SIDETONE 0x020 /* Enable/Disable Side Tone */
#define APANA_SIDETONE_ATTN 0x0C0 /* Side Tone Attenuation */
#define APANA_ENABLE_MIC_BOOST2 0x100 /* Secondary Microphone Amplifier gain booster control */
/*Digital Audio Path Control (SSM2602_REG_DIGITAL_PATH)*/
#define APDIGI_ENABLE_ADC_HPF 0x001 /* Enable/Disable ADC Highpass Filter */
#define APDIGI_DE_EMPHASIS 0x006 /* De-Emphasis Control */
#define APDIGI_ENABLE_DAC_MUTE 0x008 /* DAC Mute Control */
#define APDIGI_STORE_OFFSET 0x010 /* Store/Clear DC offset when HPF is disabled */
/*Power Down Control (SSM2602_REG_POWER)
*(1=Enable PowerDown, 0=Disable PowerDown)
*/
#define PWR_LINE_IN_PDN 0x001 /* Line Input Power Down */
#define PWR_MIC_PDN 0x002 /* Microphone Input & Bias Power Down */
#define PWR_ADC_PDN 0x004 /* ADC Power Down */
#define PWR_DAC_PDN 0x008 /* DAC Power Down */
#define PWR_OUT_PDN 0x010 /* Outputs Power Down */
#define PWR_OSC_PDN 0x020 /* Oscillator Power Down */
#define PWR_CLK_OUT_PDN 0x040 /* CLKOUT Power Down */
#define PWR_POWER_OFF 0x080 /* POWEROFF Mode */
/*Digital Audio Interface Format (SSM2602_REG_DIGITAL_IFACE)*/
#define IFACE_IFACE_FORMAT 0x003 /* Digital Audio input format control */
#define IFACE_AUDIO_DATA_LEN 0x00C /* Audio Data word length control */
#define IFACE_DAC_LR_POLARITY 0x010 /* Polarity Control for clocks in RJ,LJ and I2S modes */
#define IFACE_DAC_LR_SWAP 0x020 /* Swap DAC data control */
#define IFACE_ENABLE_MASTER 0x040 /* Enable/Disable Master Mode */
#define IFACE_BCLK_INVERT 0x080 /* Bit Clock Inversion control */
/*Sampling Control (SSM2602_REG_SAMPLING_CTRL)*/
#define SRATE_ENABLE_USB_MODE 0x001 /* Enable/Disable USB Mode */
#define SRATE_BOS_RATE 0x002 /* Base Over-Sampling rate */
#define SRATE_SAMPLE_RATE 0x03C /* Clock setting condition (Sampling rate control) */
#define SRATE_CORECLK_DIV2 0x040 /* Core Clock divider select */
#define SRATE_CLKOUT_DIV2 0x080 /* Clock Out divider select */
/*Active Control (SSM2602_REG_ACTIVE_CTRL)*/
#define ACTIVE_ACTIVATE_CODEC 0x001 /* Activate Codec Digital Audio Interface */
/*********************************************************************/
#define SSM2602_CACHEREGNUM 10
#define SSM2602_SYSCLK 0
#define SSM2602_DAI 0
struct ssm2602_setup_data {
int i2c_bus;
unsigned short i2c_address;
};
extern struct snd_soc_dai ssm2602_dai;
extern struct snd_soc_codec_device soc_codec_dev_ssm2602;
#endif

463
kernel/sound/soc/codecs/stac9766.c Normal file
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/*
* stac9766.c -- ALSA SoC STAC9766 codec support
*
* Copyright 2009 Jon Smirl, Digispeaker
* Author: Jon Smirl <jonsmirl@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Features:-
*
* o Support for AC97 Codec, S/PDIF
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/soc-of-simple.h>
#include "stac9766.h"
#define STAC9766_VERSION "0.10"
/*
* STAC9766 register cache
*/
static const u16 stac9766_reg[] = {
0x6A90, 0x8000, 0x8000, 0x8000, /* 6 */
0x0000, 0x0000, 0x8008, 0x8008, /* e */
0x8808, 0x8808, 0x8808, 0x8808, /* 16 */
0x8808, 0x0000, 0x8000, 0x0000, /* 1e */
0x0000, 0x0000, 0x0000, 0x000f, /* 26 */
0x0a05, 0x0400, 0xbb80, 0x0000, /* 2e */
0x0000, 0xbb80, 0x0000, 0x0000, /* 36 */
0x0000, 0x2000, 0x0000, 0x0100, /* 3e */
0x0000, 0x0000, 0x0080, 0x0000, /* 46 */
0x0000, 0x0000, 0x0003, 0xffff, /* 4e */
0x0000, 0x0000, 0x0000, 0x0000, /* 56 */
0x4000, 0x0000, 0x0000, 0x0000, /* 5e */
0x1201, 0xFFFF, 0xFFFF, 0x0000, /* 66 */
0x0000, 0x0000, 0x0000, 0x0000, /* 6e */
0x0000, 0x0000, 0x0000, 0x0006, /* 76 */
0x0000, 0x0000, 0x0000, 0x0000, /* 7e */
};
static const char *stac9766_record_mux[] = {"Mic", "CD", "Video", "AUX",
"Line", "Stereo Mix", "Mono Mix", "Phone"};
static const char *stac9766_mono_mux[] = {"Mix", "Mic"};
static const char *stac9766_mic_mux[] = {"Mic1", "Mic2"};
static const char *stac9766_SPDIF_mux[] = {"PCM", "ADC Record"};
static const char *stac9766_popbypass_mux[] = {"Normal", "Bypass Mixer"};
static const char *stac9766_record_all_mux[] = {"All analog",
"Analog plus DAC"};
static const char *stac9766_boost1[] = {"0dB", "10dB"};
static const char *stac9766_boost2[] = {"0dB", "20dB"};
static const char *stac9766_stereo_mic[] = {"Off", "On"};
static const struct soc_enum stac9766_record_enum =
SOC_ENUM_DOUBLE(AC97_REC_SEL, 8, 0, 8, stac9766_record_mux);
static const struct soc_enum stac9766_mono_enum =
SOC_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 9, 2, stac9766_mono_mux);
static const struct soc_enum stac9766_mic_enum =
SOC_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 8, 2, stac9766_mic_mux);
static const struct soc_enum stac9766_SPDIF_enum =
SOC_ENUM_SINGLE(AC97_STAC_DA_CONTROL, 1, 2, stac9766_SPDIF_mux);
static const struct soc_enum stac9766_popbypass_enum =
SOC_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 15, 2, stac9766_popbypass_mux);
static const struct soc_enum stac9766_record_all_enum =
SOC_ENUM_SINGLE(AC97_STAC_ANALOG_SPECIAL, 12, 2,
stac9766_record_all_mux);
static const struct soc_enum stac9766_boost1_enum =
SOC_ENUM_SINGLE(AC97_MIC, 6, 2, stac9766_boost1); /* 0/10dB */
static const struct soc_enum stac9766_boost2_enum =
SOC_ENUM_SINGLE(AC97_STAC_ANALOG_SPECIAL, 2, 2, stac9766_boost2); /* 0/20dB */
static const struct soc_enum stac9766_stereo_mic_enum =
SOC_ENUM_SINGLE(AC97_STAC_STEREO_MIC, 2, 1, stac9766_stereo_mic);
static const DECLARE_TLV_DB_LINEAR(master_tlv, -4600, 0);
static const DECLARE_TLV_DB_LINEAR(record_tlv, 0, 2250);
static const DECLARE_TLV_DB_LINEAR(beep_tlv, -4500, 0);
static const DECLARE_TLV_DB_LINEAR(mix_tlv, -3450, 1200);
static const struct snd_kcontrol_new stac9766_snd_ac97_controls[] = {
SOC_DOUBLE_TLV("Speaker Volume", AC97_MASTER, 8, 0, 31, 1, master_tlv),
SOC_SINGLE("Speaker Switch", AC97_MASTER, 15, 1, 1),
SOC_DOUBLE_TLV("Headphone Volume", AC97_HEADPHONE, 8, 0, 31, 1,
master_tlv),
SOC_SINGLE("Headphone Switch", AC97_HEADPHONE, 15, 1, 1),
SOC_SINGLE_TLV("Mono Out Volume", AC97_MASTER_MONO, 0, 31, 1,
master_tlv),
SOC_SINGLE("Mono Out Switch", AC97_MASTER_MONO, 15, 1, 1),
SOC_DOUBLE_TLV("Record Volume", AC97_REC_GAIN, 8, 0, 15, 0, record_tlv),
SOC_SINGLE("Record Switch", AC97_REC_GAIN, 15, 1, 1),
SOC_SINGLE_TLV("Beep Volume", AC97_PC_BEEP, 1, 15, 1, beep_tlv),
SOC_SINGLE("Beep Switch", AC97_PC_BEEP, 15, 1, 1),
SOC_SINGLE("Beep Frequency", AC97_PC_BEEP, 5, 127, 1),
SOC_SINGLE_TLV("Phone Volume", AC97_PHONE, 0, 31, 1, mix_tlv),
SOC_SINGLE("Phone Switch", AC97_PHONE, 15, 1, 1),
SOC_ENUM("Mic Boost1", stac9766_boost1_enum),
SOC_ENUM("Mic Boost2", stac9766_boost2_enum),
SOC_SINGLE_TLV("Mic Volume", AC97_MIC, 0, 31, 1, mix_tlv),
SOC_SINGLE("Mic Switch", AC97_MIC, 15, 1, 1),
SOC_ENUM("Stereo Mic", stac9766_stereo_mic_enum),
SOC_DOUBLE_TLV("Line Volume", AC97_LINE, 8, 0, 31, 1, mix_tlv),
SOC_SINGLE("Line Switch", AC97_LINE, 15, 1, 1),
SOC_DOUBLE_TLV("CD Volume", AC97_CD, 8, 0, 31, 1, mix_tlv),
SOC_SINGLE("CD Switch", AC97_CD, 15, 1, 1),
SOC_DOUBLE_TLV("AUX Volume", AC97_AUX, 8, 0, 31, 1, mix_tlv),
SOC_SINGLE("AUX Switch", AC97_AUX, 15, 1, 1),
SOC_DOUBLE_TLV("Video Volume", AC97_VIDEO, 8, 0, 31, 1, mix_tlv),
SOC_SINGLE("Video Switch", AC97_VIDEO, 15, 1, 1),
SOC_DOUBLE_TLV("DAC Volume", AC97_PCM, 8, 0, 31, 1, mix_tlv),
SOC_SINGLE("DAC Switch", AC97_PCM, 15, 1, 1),
SOC_SINGLE("Loopback Test Switch", AC97_GENERAL_PURPOSE, 7, 1, 0),
SOC_SINGLE("3D Volume", AC97_3D_CONTROL, 3, 2, 1),
SOC_SINGLE("3D Switch", AC97_GENERAL_PURPOSE, 13, 1, 0),
SOC_ENUM("SPDIF Mux", stac9766_SPDIF_enum),
SOC_ENUM("Mic1/2 Mux", stac9766_mic_enum),
SOC_ENUM("Record All Mux", stac9766_record_all_enum),
SOC_ENUM("Record Mux", stac9766_record_enum),
SOC_ENUM("Mono Mux", stac9766_mono_enum),
SOC_ENUM("Pop Bypass Mux", stac9766_popbypass_enum),
};
static int stac9766_ac97_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int val)
{
u16 *cache = codec->reg_cache;
if (reg > AC97_STAC_PAGE0) {
stac9766_ac97_write(codec, AC97_INT_PAGING, 0);
soc_ac97_ops.write(codec->ac97, reg, val);
stac9766_ac97_write(codec, AC97_INT_PAGING, 1);
return 0;
}
if (reg / 2 >= ARRAY_SIZE(stac9766_reg))
return -EIO;
soc_ac97_ops.write(codec->ac97, reg, val);
cache[reg / 2] = val;
return 0;
}
static unsigned int stac9766_ac97_read(struct snd_soc_codec *codec,
unsigned int reg)
{
u16 val = 0, *cache = codec->reg_cache;
if (reg > AC97_STAC_PAGE0) {
stac9766_ac97_write(codec, AC97_INT_PAGING, 0);
val = soc_ac97_ops.read(codec->ac97, reg - AC97_STAC_PAGE0);
stac9766_ac97_write(codec, AC97_INT_PAGING, 1);
return val;
}
if (reg / 2 >= ARRAY_SIZE(stac9766_reg))
return -EIO;
if (reg == AC97_RESET || reg == AC97_GPIO_STATUS ||
reg == AC97_INT_PAGING || reg == AC97_VENDOR_ID1 ||
reg == AC97_VENDOR_ID2) {
val = soc_ac97_ops.read(codec->ac97, reg);
return val;
}
return cache[reg / 2];
}
static int ac97_analog_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct snd_pcm_runtime *runtime = substream->runtime;
unsigned short reg, vra;
vra = stac9766_ac97_read(codec, AC97_EXTENDED_STATUS);
vra |= 0x1; /* enable variable rate audio */
stac9766_ac97_write(codec, AC97_EXTENDED_STATUS, vra);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = AC97_PCM_FRONT_DAC_RATE;
else
reg = AC97_PCM_LR_ADC_RATE;
return stac9766_ac97_write(codec, reg, runtime->rate);
}
static int ac97_digital_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct snd_pcm_runtime *runtime = substream->runtime;
unsigned short reg, vra;
stac9766_ac97_write(codec, AC97_SPDIF, 0x2002);
vra = stac9766_ac97_read(codec, AC97_EXTENDED_STATUS);
vra |= 0x5; /* Enable VRA and SPDIF out */
stac9766_ac97_write(codec, AC97_EXTENDED_STATUS, vra);
reg = AC97_PCM_FRONT_DAC_RATE;
return stac9766_ac97_write(codec, reg, runtime->rate);
}
static int ac97_digital_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
unsigned short vra;
switch (cmd) {
case SNDRV_PCM_TRIGGER_STOP:
vra = stac9766_ac97_read(codec, AC97_EXTENDED_STATUS);
vra &= !0x04;
stac9766_ac97_write(codec, AC97_EXTENDED_STATUS, vra);
break;
}
return 0;
}
static int stac9766_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON: /* full On */
case SND_SOC_BIAS_PREPARE: /* partial On */
case SND_SOC_BIAS_STANDBY: /* Off, with power */
stac9766_ac97_write(codec, AC97_POWERDOWN, 0x0000);
break;
case SND_SOC_BIAS_OFF: /* Off, without power */
/* disable everything including AC link */
stac9766_ac97_write(codec, AC97_POWERDOWN, 0xffff);
break;
}
codec->bias_level = level;
return 0;
}
static int stac9766_reset(struct snd_soc_codec *codec, int try_warm)
{
if (try_warm && soc_ac97_ops.warm_reset) {
soc_ac97_ops.warm_reset(codec->ac97);
if (stac9766_ac97_read(codec, 0) == stac9766_reg[0])
return 1;
}
soc_ac97_ops.reset(codec->ac97);
if (soc_ac97_ops.warm_reset)
soc_ac97_ops.warm_reset(codec->ac97);
if (stac9766_ac97_read(codec, 0) != stac9766_reg[0])
return -EIO;
return 0;
}
static int stac9766_codec_suspend(struct platform_device *pdev,
pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
stac9766_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int stac9766_codec_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
u16 id, reset;
reset = 0;
/* give the codec an AC97 warm reset to start the link */
reset:
if (reset > 5) {
printk(KERN_ERR "stac9766 failed to resume");
return -EIO;
}
codec->ac97->bus->ops->warm_reset(codec->ac97);
id = soc_ac97_ops.read(codec->ac97, AC97_VENDOR_ID2);
if (id != 0x4c13) {
stac9766_reset(codec, 0);
reset++;
goto reset;
}
stac9766_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
if (codec->suspend_bias_level == SND_SOC_BIAS_ON)
stac9766_set_bias_level(codec, SND_SOC_BIAS_ON);
return 0;
}
static struct snd_soc_dai_ops stac9766_dai_ops_analog = {
.prepare = ac97_analog_prepare,
};
static struct snd_soc_dai_ops stac9766_dai_ops_digital = {
.prepare = ac97_digital_prepare,
.trigger = ac97_digital_trigger,
};
struct snd_soc_dai stac9766_dai[] = {
{
.name = "stac9766 analog",
.id = 0,
.ac97_control = 1,
/* stream cababilities */
.playback = {
.stream_name = "stac9766 analog",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SND_SOC_STD_AC97_FMTS,
},
.capture = {
.stream_name = "stac9766 analog",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SND_SOC_STD_AC97_FMTS,
},
/* alsa ops */
.ops = &stac9766_dai_ops_analog,
},
{
.name = "stac9766 IEC958",
.id = 1,
.ac97_control = 1,
/* stream cababilities */
.playback = {
.stream_name = "stac9766 IEC958",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE,
},
/* alsa ops */
.ops = &stac9766_dai_ops_digital,
}
};
EXPORT_SYMBOL_GPL(stac9766_dai);
static int stac9766_codec_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
printk(KERN_INFO "STAC9766 SoC Audio Codec %s\n", STAC9766_VERSION);
socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
if (socdev->card->codec == NULL)
return -ENOMEM;
codec = socdev->card->codec;
mutex_init(&codec->mutex);
codec->reg_cache = kmemdup(stac9766_reg, sizeof(stac9766_reg),
GFP_KERNEL);
if (codec->reg_cache == NULL) {
ret = -ENOMEM;
goto cache_err;
}
codec->reg_cache_size = sizeof(stac9766_reg);
codec->reg_cache_step = 2;
codec->name = "STAC9766";
codec->owner = THIS_MODULE;
codec->dai = stac9766_dai;
codec->num_dai = ARRAY_SIZE(stac9766_dai);
codec->write = stac9766_ac97_write;
codec->read = stac9766_ac97_read;
codec->set_bias_level = stac9766_set_bias_level;
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
ret = snd_soc_new_ac97_codec(codec, &soc_ac97_ops, 0);
if (ret < 0)
goto codec_err;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0)
goto pcm_err;
/* do a cold reset for the controller and then try
* a warm reset followed by an optional cold reset for codec */
stac9766_reset(codec, 0);
ret = stac9766_reset(codec, 1);
if (ret < 0) {
printk(KERN_ERR "Failed to reset STAC9766: AC97 link error\n");
goto reset_err;
}
stac9766_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
snd_soc_add_controls(codec, stac9766_snd_ac97_controls,
ARRAY_SIZE(stac9766_snd_ac97_controls));
ret = snd_soc_init_card(socdev);
if (ret < 0)
goto reset_err;
return 0;
reset_err:
snd_soc_free_pcms(socdev);
pcm_err:
snd_soc_free_ac97_codec(codec);
codec_err:
kfree(codec->private_data);
cache_err:
kfree(socdev->card->codec);
socdev->card->codec = NULL;
return ret;
}
static int stac9766_codec_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
if (codec == NULL)
return 0;
snd_soc_free_pcms(socdev);
snd_soc_free_ac97_codec(codec);
kfree(codec->reg_cache);
kfree(codec);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_stac9766 = {
.probe = stac9766_codec_probe,
.remove = stac9766_codec_remove,
.suspend = stac9766_codec_suspend,
.resume = stac9766_codec_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_stac9766);
MODULE_DESCRIPTION("ASoC stac9766 driver");
MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
MODULE_LICENSE("GPL");

21
kernel/sound/soc/codecs/stac9766.h Normal file
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@@ -0,0 +1,21 @@
/*
* stac9766.h -- STAC9766 Soc Audio driver
*/
#ifndef _STAC9766_H
#define _STAC9766_H
#define AC97_STAC_PAGE0 0x1000
#define AC97_STAC_DA_CONTROL (AC97_STAC_PAGE0 | 0x6A)
#define AC97_STAC_ANALOG_SPECIAL (AC97_STAC_PAGE0 | 0x6E)
#define AC97_STAC_STEREO_MIC 0x78
/* STAC9766 DAI ID's */
#define STAC9766_DAI_AC97_ANALOG 0
#define STAC9766_DAI_AC97_DIGITAL 1
extern struct snd_soc_dai stac9766_dai[];
extern struct snd_soc_codec_device soc_codec_dev_stac9766;
#endif

850
kernel/sound/soc/codecs/tlv320aic23.c Normal file
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/*
* ALSA SoC TLV320AIC23 codec driver
*
* Author: Arun KS, <arunks@mistralsolutions.com>
* Copyright: (C) 2008 Mistral Solutions Pvt Ltd.,
*
* Based on sound/soc/codecs/wm8731.c by Richard Purdie
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Notes:
* The AIC23 is a driver for a low power stereo audio
* codec tlv320aic23
*
* The machine layer should disable unsupported inputs/outputs by
* snd_soc_dapm_disable_pin(codec, "LHPOUT"), etc.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include <sound/initval.h>
#include "tlv320aic23.h"
#define AIC23_VERSION "0.1"
/*
* AIC23 register cache
*/
static const u16 tlv320aic23_reg[] = {
0x0097, 0x0097, 0x00F9, 0x00F9, /* 0 */
0x001A, 0x0004, 0x0007, 0x0001, /* 4 */
0x0020, 0x0000, 0x0000, 0x0000, /* 8 */
0x0000, 0x0000, 0x0000, 0x0000, /* 12 */
};
/*
* read tlv320aic23 register cache
*/
static inline unsigned int tlv320aic23_read_reg_cache(struct snd_soc_codec
*codec, unsigned int reg)
{
u16 *cache = codec->reg_cache;
if (reg >= ARRAY_SIZE(tlv320aic23_reg))
return -1;
return cache[reg];
}
/*
* write tlv320aic23 register cache
*/
static inline void tlv320aic23_write_reg_cache(struct snd_soc_codec *codec,
u8 reg, u16 value)
{
u16 *cache = codec->reg_cache;
if (reg >= ARRAY_SIZE(tlv320aic23_reg))
return;
cache[reg] = value;
}
/*
* write to the tlv320aic23 register space
*/
static int tlv320aic23_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
u8 data[2];
/* TLV320AIC23 has 7 bit address and 9 bits of data
* so we need to switch one data bit into reg and rest
* of data into val
*/
if ((reg < 0 || reg > 9) && (reg != 15)) {
printk(KERN_WARNING "%s Invalid register R%u\n", __func__, reg);
return -1;
}
data[0] = (reg << 1) | (value >> 8 & 0x01);
data[1] = value & 0xff;
tlv320aic23_write_reg_cache(codec, reg, value);
if (codec->hw_write(codec->control_data, data, 2) == 2)
return 0;
printk(KERN_ERR "%s cannot write %03x to register R%u\n", __func__,
value, reg);
return -EIO;
}
static const char *rec_src_text[] = { "Line", "Mic" };
static const char *deemph_text[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static const struct soc_enum rec_src_enum =
SOC_ENUM_SINGLE(TLV320AIC23_ANLG, 2, 2, rec_src_text);
static const struct snd_kcontrol_new tlv320aic23_rec_src_mux_controls =
SOC_DAPM_ENUM("Input Select", rec_src_enum);
static const struct soc_enum tlv320aic23_rec_src =
SOC_ENUM_SINGLE(TLV320AIC23_ANLG, 2, 2, rec_src_text);
static const struct soc_enum tlv320aic23_deemph =
SOC_ENUM_SINGLE(TLV320AIC23_DIGT, 1, 4, deemph_text);
static const DECLARE_TLV_DB_SCALE(out_gain_tlv, -12100, 100, 0);
static const DECLARE_TLV_DB_SCALE(input_gain_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(sidetone_vol_tlv, -1800, 300, 0);
static int snd_soc_tlv320aic23_put_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
u16 val, reg;
val = (ucontrol->value.integer.value[0] & 0x07);
/* linear conversion to userspace
* 000 = -6db
* 001 = -9db
* 010 = -12db
* 011 = -18db (Min)
* 100 = 0db (Max)
*/
val = (val >= 4) ? 4 : (3 - val);
reg = tlv320aic23_read_reg_cache(codec, TLV320AIC23_ANLG) & (~0x1C0);
tlv320aic23_write(codec, TLV320AIC23_ANLG, reg | (val << 6));
return 0;
}
static int snd_soc_tlv320aic23_get_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
u16 val;
val = tlv320aic23_read_reg_cache(codec, TLV320AIC23_ANLG) & (0x1C0);
val = val >> 6;
val = (val >= 4) ? 4 : (3 - val);
ucontrol->value.integer.value[0] = val;
return 0;
}
#define SOC_TLV320AIC23_SINGLE_TLV(xname, reg, shift, max, invert, tlv_array) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
SNDRV_CTL_ELEM_ACCESS_READWRITE,\
.tlv.p = (tlv_array), \
.info = snd_soc_info_volsw, .get = snd_soc_tlv320aic23_get_volsw,\
.put = snd_soc_tlv320aic23_put_volsw, \
.private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
static const struct snd_kcontrol_new tlv320aic23_snd_controls[] = {
SOC_DOUBLE_R_TLV("Digital Playback Volume", TLV320AIC23_LCHNVOL,
TLV320AIC23_RCHNVOL, 0, 127, 0, out_gain_tlv),
SOC_SINGLE("Digital Playback Switch", TLV320AIC23_DIGT, 3, 1, 1),
SOC_DOUBLE_R("Line Input Switch", TLV320AIC23_LINVOL,
TLV320AIC23_RINVOL, 7, 1, 0),
SOC_DOUBLE_R_TLV("Line Input Volume", TLV320AIC23_LINVOL,
TLV320AIC23_RINVOL, 0, 31, 0, input_gain_tlv),
SOC_SINGLE("Mic Input Switch", TLV320AIC23_ANLG, 1, 1, 1),
SOC_SINGLE("Mic Booster Switch", TLV320AIC23_ANLG, 0, 1, 0),
SOC_TLV320AIC23_SINGLE_TLV("Sidetone Volume", TLV320AIC23_ANLG,
6, 4, 0, sidetone_vol_tlv),
SOC_ENUM("Playback De-emphasis", tlv320aic23_deemph),
};
/* PGA Mixer controls for Line and Mic switch */
static const struct snd_kcontrol_new tlv320aic23_output_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", TLV320AIC23_ANLG, 3, 1, 0),
SOC_DAPM_SINGLE("Mic Sidetone Switch", TLV320AIC23_ANLG, 5, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", TLV320AIC23_ANLG, 4, 1, 0),
};
static const struct snd_soc_dapm_widget tlv320aic23_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", TLV320AIC23_PWR, 3, 1),
SND_SOC_DAPM_ADC("ADC", "Capture", TLV320AIC23_PWR, 2, 1),
SND_SOC_DAPM_MUX("Capture Source", SND_SOC_NOPM, 0, 0,
&tlv320aic23_rec_src_mux_controls),
SND_SOC_DAPM_MIXER("Output Mixer", TLV320AIC23_PWR, 4, 1,
&tlv320aic23_output_mixer_controls[0],
ARRAY_SIZE(tlv320aic23_output_mixer_controls)),
SND_SOC_DAPM_PGA("Line Input", TLV320AIC23_PWR, 0, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mic Input", TLV320AIC23_PWR, 1, 1, NULL, 0),
SND_SOC_DAPM_OUTPUT("LHPOUT"),
SND_SOC_DAPM_OUTPUT("RHPOUT"),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_INPUT("LLINEIN"),
SND_SOC_DAPM_INPUT("RLINEIN"),
SND_SOC_DAPM_INPUT("MICIN"),
};
static const struct snd_soc_dapm_route intercon[] = {
/* Output Mixer */
{"Output Mixer", "Line Bypass Switch", "Line Input"},
{"Output Mixer", "Playback Switch", "DAC"},
{"Output Mixer", "Mic Sidetone Switch", "Mic Input"},
/* Outputs */
{"RHPOUT", NULL, "Output Mixer"},
{"LHPOUT", NULL, "Output Mixer"},
{"LOUT", NULL, "Output Mixer"},
{"ROUT", NULL, "Output Mixer"},
/* Inputs */
{"Line Input", "NULL", "LLINEIN"},
{"Line Input", "NULL", "RLINEIN"},
{"Mic Input", "NULL", "MICIN"},
/* input mux */
{"Capture Source", "Line", "Line Input"},
{"Capture Source", "Mic", "Mic Input"},
{"ADC", NULL, "Capture Source"},
};
/* AIC23 driver data */
struct aic23 {
struct snd_soc_codec codec;
int mclk;
int requested_adc;
int requested_dac;
};
/*
* Common Crystals used
* 11.2896 Mhz /128 = *88.2k /192 = 58.8k
* 12.0000 Mhz /125 = *96k /136 = 88.235K
* 12.2880 Mhz /128 = *96k /192 = 64k
* 16.9344 Mhz /128 = 132.3k /192 = *88.2k
* 18.4320 Mhz /128 = 144k /192 = *96k
*/
/*
* Normal BOSR 0-256/2 = 128, 1-384/2 = 192
* USB BOSR 0-250/2 = 125, 1-272/2 = 136
*/
static const int bosr_usb_divisor_table[] = {
128, 125, 192, 136
};
#define LOWER_GROUP ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<6) | (1<<7))
#define UPPER_GROUP ((1<<8) | (1<<9) | (1<<10) | (1<<11) | (1<<15))
static const unsigned short sr_valid_mask[] = {
LOWER_GROUP|UPPER_GROUP, /* Normal, bosr - 0*/
LOWER_GROUP, /* Usb, bosr - 0*/
LOWER_GROUP|UPPER_GROUP, /* Normal, bosr - 1*/
UPPER_GROUP, /* Usb, bosr - 1*/
};
/*
* Every divisor is a factor of 11*12
*/
#define SR_MULT (11*12)
#define A(x) (SR_MULT/x)
static const unsigned char sr_adc_mult_table[] = {
A(2), A(2), A(12), A(12), 0, 0, A(3), A(1),
A(2), A(2), A(11), A(11), 0, 0, 0, A(1)
};
static const unsigned char sr_dac_mult_table[] = {
A(2), A(12), A(2), A(12), 0, 0, A(3), A(1),
A(2), A(11), A(2), A(11), 0, 0, 0, A(1)
};
static unsigned get_score(int adc, int adc_l, int adc_h, int need_adc,
int dac, int dac_l, int dac_h, int need_dac)
{
if ((adc >= adc_l) && (adc <= adc_h) &&
(dac >= dac_l) && (dac <= dac_h)) {
int diff_adc = need_adc - adc;
int diff_dac = need_dac - dac;
return abs(diff_adc) + abs(diff_dac);
}
return UINT_MAX;
}
static int find_rate(int mclk, u32 need_adc, u32 need_dac)
{
int i, j;
int best_i = -1;
int best_j = -1;
int best_div = 0;
unsigned best_score = UINT_MAX;
int adc_l, adc_h, dac_l, dac_h;
need_adc *= SR_MULT;
need_dac *= SR_MULT;
/*
* rates given are +/- 1/32
*/
adc_l = need_adc - (need_adc >> 5);
adc_h = need_adc + (need_adc >> 5);
dac_l = need_dac - (need_dac >> 5);
dac_h = need_dac + (need_dac >> 5);
for (i = 0; i < ARRAY_SIZE(bosr_usb_divisor_table); i++) {
int base = mclk / bosr_usb_divisor_table[i];
int mask = sr_valid_mask[i];
for (j = 0; j < ARRAY_SIZE(sr_adc_mult_table);
j++, mask >>= 1) {
int adc;
int dac;
int score;
if ((mask & 1) == 0)
continue;
adc = base * sr_adc_mult_table[j];
dac = base * sr_dac_mult_table[j];
score = get_score(adc, adc_l, adc_h, need_adc,
dac, dac_l, dac_h, need_dac);
if (best_score > score) {
best_score = score;
best_i = i;
best_j = j;
best_div = 0;
}
score = get_score((adc >> 1), adc_l, adc_h, need_adc,
(dac >> 1), dac_l, dac_h, need_dac);
/* prefer to have a /2 */
if ((score != UINT_MAX) && (best_score >= score)) {
best_score = score;
best_i = i;
best_j = j;
best_div = 1;
}
}
}
return (best_j << 2) | best_i | (best_div << TLV320AIC23_CLKIN_SHIFT);
}
#ifdef DEBUG
static void get_current_sample_rates(struct snd_soc_codec *codec, int mclk,
u32 *sample_rate_adc, u32 *sample_rate_dac)
{
int src = tlv320aic23_read_reg_cache(codec, TLV320AIC23_SRATE);
int sr = (src >> 2) & 0x0f;
int val = (mclk / bosr_usb_divisor_table[src & 3]);
int adc = (val * sr_adc_mult_table[sr]) / SR_MULT;
int dac = (val * sr_dac_mult_table[sr]) / SR_MULT;
if (src & TLV320AIC23_CLKIN_HALF) {
adc >>= 1;
dac >>= 1;
}
*sample_rate_adc = adc;
*sample_rate_dac = dac;
}
#endif
static int set_sample_rate_control(struct snd_soc_codec *codec, int mclk,
u32 sample_rate_adc, u32 sample_rate_dac)
{
/* Search for the right sample rate */
int data = find_rate(mclk, sample_rate_adc, sample_rate_dac);
if (data < 0) {
printk(KERN_ERR "%s:Invalid rate %u,%u requested\n",
__func__, sample_rate_adc, sample_rate_dac);
return -EINVAL;
}
tlv320aic23_write(codec, TLV320AIC23_SRATE, data);
#ifdef DEBUG
{
u32 adc, dac;
get_current_sample_rates(codec, mclk, &adc, &dac);
printk(KERN_DEBUG "actual samplerate = %u,%u reg=%x\n",
adc, dac, data);
}
#endif
return 0;
}
static int tlv320aic23_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, tlv320aic23_dapm_widgets,
ARRAY_SIZE(tlv320aic23_dapm_widgets));
/* set up audio path interconnects */
snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
snd_soc_dapm_new_widgets(codec);
return 0;
}
static int tlv320aic23_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
u16 iface_reg;
int ret;
struct aic23 *aic23 = container_of(codec, struct aic23, codec);
u32 sample_rate_adc = aic23->requested_adc;
u32 sample_rate_dac = aic23->requested_dac;
u32 sample_rate = params_rate(params);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
aic23->requested_dac = sample_rate_dac = sample_rate;
if (!sample_rate_adc)
sample_rate_adc = sample_rate;
} else {
aic23->requested_adc = sample_rate_adc = sample_rate;
if (!sample_rate_dac)
sample_rate_dac = sample_rate;
}
ret = set_sample_rate_control(codec, aic23->mclk, sample_rate_adc,
sample_rate_dac);
if (ret < 0)
return ret;
iface_reg =
tlv320aic23_read_reg_cache(codec,
TLV320AIC23_DIGT_FMT) & ~(0x03 << 2);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
iface_reg |= (0x01 << 2);
break;
case SNDRV_PCM_FORMAT_S24_LE:
iface_reg |= (0x02 << 2);
break;
case SNDRV_PCM_FORMAT_S32_LE:
iface_reg |= (0x03 << 2);
break;
}
tlv320aic23_write(codec, TLV320AIC23_DIGT_FMT, iface_reg);
return 0;
}
static int tlv320aic23_pcm_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
/* set active */
tlv320aic23_write(codec, TLV320AIC23_ACTIVE, 0x0001);
return 0;
}
static void tlv320aic23_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct aic23 *aic23 = container_of(codec, struct aic23, codec);
/* deactivate */
if (!codec->active) {
udelay(50);
tlv320aic23_write(codec, TLV320AIC23_ACTIVE, 0x0);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
aic23->requested_dac = 0;
else
aic23->requested_adc = 0;
}
static int tlv320aic23_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
u16 reg;
reg = tlv320aic23_read_reg_cache(codec, TLV320AIC23_DIGT);
if (mute)
reg |= TLV320AIC23_DACM_MUTE;
else
reg &= ~TLV320AIC23_DACM_MUTE;
tlv320aic23_write(codec, TLV320AIC23_DIGT, reg);
return 0;
}
static int tlv320aic23_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 iface_reg;
iface_reg =
tlv320aic23_read_reg_cache(codec, TLV320AIC23_DIGT_FMT) & (~0x03);
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
iface_reg |= TLV320AIC23_MS_MASTER;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface_reg |= TLV320AIC23_FOR_I2S;
break;
case SND_SOC_DAIFMT_DSP_A:
iface_reg |= TLV320AIC23_LRP_ON;
case SND_SOC_DAIFMT_DSP_B:
iface_reg |= TLV320AIC23_FOR_DSP;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface_reg |= TLV320AIC23_FOR_LJUST;
break;
default:
return -EINVAL;
}
tlv320aic23_write(codec, TLV320AIC23_DIGT_FMT, iface_reg);
return 0;
}
static int tlv320aic23_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct aic23 *aic23 = container_of(codec, struct aic23, codec);
aic23->mclk = freq;
return 0;
}
static int tlv320aic23_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
u16 reg = tlv320aic23_read_reg_cache(codec, TLV320AIC23_PWR) & 0xff7f;
switch (level) {
case SND_SOC_BIAS_ON:
/* vref/mid, osc on, dac unmute */
tlv320aic23_write(codec, TLV320AIC23_PWR, reg);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* everything off except vref/vmid, */
tlv320aic23_write(codec, TLV320AIC23_PWR, reg | 0x0040);
break;
case SND_SOC_BIAS_OFF:
/* everything off, dac mute, inactive */
tlv320aic23_write(codec, TLV320AIC23_ACTIVE, 0x0);
tlv320aic23_write(codec, TLV320AIC23_PWR, 0xffff);
break;
}
codec->bias_level = level;
return 0;
}
#define AIC23_RATES SNDRV_PCM_RATE_8000_96000
#define AIC23_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_ops tlv320aic23_dai_ops = {
.prepare = tlv320aic23_pcm_prepare,
.hw_params = tlv320aic23_hw_params,
.shutdown = tlv320aic23_shutdown,
.digital_mute = tlv320aic23_mute,
.set_fmt = tlv320aic23_set_dai_fmt,
.set_sysclk = tlv320aic23_set_dai_sysclk,
};
struct snd_soc_dai tlv320aic23_dai = {
.name = "tlv320aic23",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = AIC23_RATES,
.formats = AIC23_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = AIC23_RATES,
.formats = AIC23_FORMATS,},
.ops = &tlv320aic23_dai_ops,
};
EXPORT_SYMBOL_GPL(tlv320aic23_dai);
static int tlv320aic23_suspend(struct platform_device *pdev,
pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
tlv320aic23_write(codec, TLV320AIC23_ACTIVE, 0x0);
tlv320aic23_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int tlv320aic23_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
u16 reg;
/* Sync reg_cache with the hardware */
for (reg = 0; reg < TLV320AIC23_RESET; reg++) {
u16 val = tlv320aic23_read_reg_cache(codec, reg);
tlv320aic23_write(codec, reg, val);
}
tlv320aic23_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
tlv320aic23_set_bias_level(codec, codec->suspend_bias_level);
return 0;
}
/*
* initialise the AIC23 driver
* register the mixer and dsp interfaces with the kernel
*/
static int tlv320aic23_init(struct snd_soc_device *socdev)
{
struct snd_soc_codec *codec = socdev->card->codec;
int ret = 0;
u16 reg;
codec->name = "tlv320aic23";
codec->owner = THIS_MODULE;
codec->read = tlv320aic23_read_reg_cache;
codec->write = tlv320aic23_write;
codec->set_bias_level = tlv320aic23_set_bias_level;
codec->dai = &tlv320aic23_dai;
codec->num_dai = 1;
codec->reg_cache_size = ARRAY_SIZE(tlv320aic23_reg);
codec->reg_cache =
kmemdup(tlv320aic23_reg, sizeof(tlv320aic23_reg), GFP_KERNEL);
if (codec->reg_cache == NULL)
return -ENOMEM;
/* Reset codec */
tlv320aic23_write(codec, TLV320AIC23_RESET, 0);
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
printk(KERN_ERR "tlv320aic23: failed to create pcms\n");
goto pcm_err;
}
/* power on device */
tlv320aic23_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
tlv320aic23_write(codec, TLV320AIC23_DIGT, TLV320AIC23_DEEMP_44K);
/* Unmute input */
reg = tlv320aic23_read_reg_cache(codec, TLV320AIC23_LINVOL);
tlv320aic23_write(codec, TLV320AIC23_LINVOL,
(reg & (~TLV320AIC23_LIM_MUTED)) |
(TLV320AIC23_LRS_ENABLED));
reg = tlv320aic23_read_reg_cache(codec, TLV320AIC23_RINVOL);
tlv320aic23_write(codec, TLV320AIC23_RINVOL,
(reg & (~TLV320AIC23_LIM_MUTED)) |
TLV320AIC23_LRS_ENABLED);
reg = tlv320aic23_read_reg_cache(codec, TLV320AIC23_ANLG);
tlv320aic23_write(codec, TLV320AIC23_ANLG,
(reg) & (~TLV320AIC23_BYPASS_ON) &
(~TLV320AIC23_MICM_MUTED));
/* Default output volume */
tlv320aic23_write(codec, TLV320AIC23_LCHNVOL,
TLV320AIC23_DEFAULT_OUT_VOL &
TLV320AIC23_OUT_VOL_MASK);
tlv320aic23_write(codec, TLV320AIC23_RCHNVOL,
TLV320AIC23_DEFAULT_OUT_VOL &
TLV320AIC23_OUT_VOL_MASK);
tlv320aic23_write(codec, TLV320AIC23_ACTIVE, 0x1);
snd_soc_add_controls(codec, tlv320aic23_snd_controls,
ARRAY_SIZE(tlv320aic23_snd_controls));
tlv320aic23_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
printk(KERN_ERR "tlv320aic23: failed to register card\n");
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
kfree(codec->reg_cache);
return ret;
}
static struct snd_soc_device *tlv320aic23_socdev;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
/*
* If the i2c layer weren't so broken, we could pass this kind of data
* around
*/
static int tlv320aic23_codec_probe(struct i2c_client *i2c,
const struct i2c_device_id *i2c_id)
{
struct snd_soc_device *socdev = tlv320aic23_socdev;
struct snd_soc_codec *codec = socdev->card->codec;
int ret;
if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return -EINVAL;
i2c_set_clientdata(i2c, codec);
codec->control_data = i2c;
ret = tlv320aic23_init(socdev);
if (ret < 0) {
printk(KERN_ERR "tlv320aic23: failed to initialise AIC23\n");
goto err;
}
return ret;
err:
kfree(codec);
kfree(i2c);
return ret;
}
static int __exit tlv320aic23_i2c_remove(struct i2c_client *i2c)
{
put_device(&i2c->dev);
return 0;
}
static const struct i2c_device_id tlv320aic23_id[] = {
{"tlv320aic23", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, tlv320aic23_id);
static struct i2c_driver tlv320aic23_i2c_driver = {
.driver = {
.name = "tlv320aic23",
},
.probe = tlv320aic23_codec_probe,
.remove = __exit_p(tlv320aic23_i2c_remove),
.id_table = tlv320aic23_id,
};
#endif
static int tlv320aic23_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
struct aic23 *aic23;
int ret = 0;
printk(KERN_INFO "AIC23 Audio Codec %s\n", AIC23_VERSION);
aic23 = kzalloc(sizeof(struct aic23), GFP_KERNEL);
if (aic23 == NULL)
return -ENOMEM;
codec = &aic23->codec;
socdev->card->codec = codec;
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
tlv320aic23_socdev = socdev;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
codec->hw_write = (hw_write_t) i2c_master_send;
codec->hw_read = NULL;
ret = i2c_add_driver(&tlv320aic23_i2c_driver);
if (ret != 0)
printk(KERN_ERR "can't add i2c driver");
#endif
return ret;
}
static int tlv320aic23_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
struct aic23 *aic23 = container_of(codec, struct aic23, codec);
if (codec->control_data)
tlv320aic23_set_bias_level(codec, SND_SOC_BIAS_OFF);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
i2c_del_driver(&tlv320aic23_i2c_driver);
#endif
kfree(codec->reg_cache);
kfree(aic23);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_tlv320aic23 = {
.probe = tlv320aic23_probe,
.remove = tlv320aic23_remove,
.suspend = tlv320aic23_suspend,
.resume = tlv320aic23_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320aic23);
static int __init tlv320aic23_modinit(void)
{
return snd_soc_register_dai(&tlv320aic23_dai);
}
module_init(tlv320aic23_modinit);
static void __exit tlv320aic23_exit(void)
{
snd_soc_unregister_dai(&tlv320aic23_dai);
}
module_exit(tlv320aic23_exit);
MODULE_DESCRIPTION("ASoC TLV320AIC23 codec driver");
MODULE_AUTHOR("Arun KS <arunks@mistralsolutions.com>");
MODULE_LICENSE("GPL");

122
kernel/sound/soc/codecs/tlv320aic23.h Normal file
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@@ -0,0 +1,122 @@
/*
* ALSA SoC TLV320AIC23 codec driver
*
* Author: Arun KS, <arunks@mistralsolutions.com>
* Copyright: (C) 2008 Mistral Solutions Pvt Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _TLV320AIC23_H
#define _TLV320AIC23_H
/* Codec TLV320AIC23 */
#define TLV320AIC23_LINVOL 0x00
#define TLV320AIC23_RINVOL 0x01
#define TLV320AIC23_LCHNVOL 0x02
#define TLV320AIC23_RCHNVOL 0x03
#define TLV320AIC23_ANLG 0x04
#define TLV320AIC23_DIGT 0x05
#define TLV320AIC23_PWR 0x06
#define TLV320AIC23_DIGT_FMT 0x07
#define TLV320AIC23_SRATE 0x08
#define TLV320AIC23_ACTIVE 0x09
#define TLV320AIC23_RESET 0x0F
/* Left (right) line input volume control register */
#define TLV320AIC23_LRS_ENABLED 0x0100
#define TLV320AIC23_LIM_MUTED 0x0080
#define TLV320AIC23_LIV_DEFAULT 0x0017
#define TLV320AIC23_LIV_MAX 0x001f
#define TLV320AIC23_LIV_MIN 0x0000
/* Left (right) channel headphone volume control register */
#define TLV320AIC23_LZC_ON 0x0080
#define TLV320AIC23_LHV_DEFAULT 0x0079
#define TLV320AIC23_LHV_MAX 0x007f
#define TLV320AIC23_LHV_MIN 0x0000
/* Analog audio path control register */
#define TLV320AIC23_STA_REG(x) ((x)<<6)
#define TLV320AIC23_STE_ENABLED 0x0020
#define TLV320AIC23_DAC_SELECTED 0x0010
#define TLV320AIC23_BYPASS_ON 0x0008
#define TLV320AIC23_INSEL_MIC 0x0004
#define TLV320AIC23_MICM_MUTED 0x0002
#define TLV320AIC23_MICB_20DB 0x0001
/* Digital audio path control register */
#define TLV320AIC23_DACM_MUTE 0x0008
#define TLV320AIC23_DEEMP_32K 0x0002
#define TLV320AIC23_DEEMP_44K 0x0004
#define TLV320AIC23_DEEMP_48K 0x0006
#define TLV320AIC23_ADCHP_ON 0x0001
/* Power control down register */
#define TLV320AIC23_DEVICE_PWR_OFF 0x0080
#define TLV320AIC23_CLK_OFF 0x0040
#define TLV320AIC23_OSC_OFF 0x0020
#define TLV320AIC23_OUT_OFF 0x0010
#define TLV320AIC23_DAC_OFF 0x0008
#define TLV320AIC23_ADC_OFF 0x0004
#define TLV320AIC23_MIC_OFF 0x0002
#define TLV320AIC23_LINE_OFF 0x0001
/* Digital audio interface register */
#define TLV320AIC23_MS_MASTER 0x0040
#define TLV320AIC23_LRSWAP_ON 0x0020
#define TLV320AIC23_LRP_ON 0x0010
#define TLV320AIC23_IWL_16 0x0000
#define TLV320AIC23_IWL_20 0x0004
#define TLV320AIC23_IWL_24 0x0008
#define TLV320AIC23_IWL_32 0x000C
#define TLV320AIC23_FOR_I2S 0x0002
#define TLV320AIC23_FOR_DSP 0x0003
#define TLV320AIC23_FOR_LJUST 0x0001
/* Sample rate control register */
#define TLV320AIC23_CLKOUT_HALF 0x0080
#define TLV320AIC23_CLKIN_HALF 0x0040
#define TLV320AIC23_BOSR_384fs 0x0002 /* BOSR_272fs in USB mode */
#define TLV320AIC23_USB_CLK_ON 0x0001
#define TLV320AIC23_SR_MASK 0xf
#define TLV320AIC23_CLKOUT_SHIFT 7
#define TLV320AIC23_CLKIN_SHIFT 6
#define TLV320AIC23_SR_SHIFT 2
#define TLV320AIC23_BOSR_SHIFT 1
/* Digital interface register */
#define TLV320AIC23_ACT_ON 0x0001
/*
* AUDIO related MACROS
*/
#define TLV320AIC23_DEFAULT_OUT_VOL 0x70
#define TLV320AIC23_DEFAULT_IN_VOLUME 0x10
#define TLV320AIC23_OUT_VOL_MIN TLV320AIC23_LHV_MIN
#define TLV320AIC23_OUT_VOL_MAX TLV320AIC23_LHV_MAX
#define TLV320AIC23_OUT_VO_RANGE (TLV320AIC23_OUT_VOL_MAX - \
TLV320AIC23_OUT_VOL_MIN)
#define TLV320AIC23_OUT_VOL_MASK TLV320AIC23_OUT_VOL_MAX
#define TLV320AIC23_IN_VOL_MIN TLV320AIC23_LIV_MIN
#define TLV320AIC23_IN_VOL_MAX TLV320AIC23_LIV_MAX
#define TLV320AIC23_IN_VOL_RANGE (TLV320AIC23_IN_VOL_MAX - \
TLV320AIC23_IN_VOL_MIN)
#define TLV320AIC23_IN_VOL_MASK TLV320AIC23_IN_VOL_MAX
#define TLV320AIC23_SIDETONE_MASK 0x1c0
#define TLV320AIC23_SIDETONE_0 0x100
#define TLV320AIC23_SIDETONE_6 0x000
#define TLV320AIC23_SIDETONE_9 0x040
#define TLV320AIC23_SIDETONE_12 0x080
#define TLV320AIC23_SIDETONE_18 0x0c0
extern struct snd_soc_dai tlv320aic23_dai;
extern struct snd_soc_codec_device soc_codec_dev_tlv320aic23;
#endif /* _TLV320AIC23_H */

527
kernel/sound/soc/codecs/tlv320aic26.c Normal file
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/*
* Texas Instruments TLV320AIC26 low power audio CODEC
* ALSA SoC CODEC driver
*
* Copyright (C) 2008 Secret Lab Technologies Ltd.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/device.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/soc-of-simple.h>
#include <sound/initval.h>
#include "tlv320aic26.h"
MODULE_DESCRIPTION("ASoC TLV320AIC26 codec driver");
MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
MODULE_LICENSE("GPL");
/* AIC26 driver private data */
struct aic26 {
struct spi_device *spi;
struct snd_soc_codec codec;
u16 reg_cache[AIC26_NUM_REGS]; /* shadow registers */
int master;
int datfm;
int mclk;
/* Keyclick parameters */
int keyclick_amplitude;
int keyclick_freq;
int keyclick_len;
};
/* ---------------------------------------------------------------------
* Register access routines
*/
static unsigned int aic26_reg_read(struct snd_soc_codec *codec,
unsigned int reg)
{
struct aic26 *aic26 = codec->private_data;
u16 *cache = codec->reg_cache;
u16 cmd, value;
u8 buffer[2];
int rc;
if (reg >= AIC26_NUM_REGS) {
WARN_ON_ONCE(1);
return 0;
}
/* Do SPI transfer; first 16bits are command; remaining is
* register contents */
cmd = AIC26_READ_COMMAND_WORD(reg);
buffer[0] = (cmd >> 8) & 0xff;
buffer[1] = cmd & 0xff;
rc = spi_write_then_read(aic26->spi, buffer, 2, buffer, 2);
if (rc) {
dev_err(&aic26->spi->dev, "AIC26 reg read error\n");
return -EIO;
}
value = (buffer[0] << 8) | buffer[1];
/* Update the cache before returning with the value */
cache[reg] = value;
return value;
}
static unsigned int aic26_reg_read_cache(struct snd_soc_codec *codec,
unsigned int reg)
{
u16 *cache = codec->reg_cache;
if (reg >= AIC26_NUM_REGS) {
WARN_ON_ONCE(1);
return 0;
}
return cache[reg];
}
static int aic26_reg_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
struct aic26 *aic26 = codec->private_data;
u16 *cache = codec->reg_cache;
u16 cmd;
u8 buffer[4];
int rc;
if (reg >= AIC26_NUM_REGS) {
WARN_ON_ONCE(1);
return -EINVAL;
}
/* Do SPI transfer; first 16bits are command; remaining is data
* to write into register */
cmd = AIC26_WRITE_COMMAND_WORD(reg);
buffer[0] = (cmd >> 8) & 0xff;
buffer[1] = cmd & 0xff;
buffer[2] = value >> 8;
buffer[3] = value;
rc = spi_write(aic26->spi, buffer, 4);
if (rc) {
dev_err(&aic26->spi->dev, "AIC26 reg read error\n");
return -EIO;
}
/* update cache before returning */
cache[reg] = value;
return 0;
}
/* ---------------------------------------------------------------------
* Digital Audio Interface Operations
*/
static int aic26_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct aic26 *aic26 = codec->private_data;
int fsref, divisor, wlen, pval, jval, dval, qval;
u16 reg;
dev_dbg(&aic26->spi->dev, "aic26_hw_params(substream=%p, params=%p)\n",
substream, params);
dev_dbg(&aic26->spi->dev, "rate=%i format=%i\n", params_rate(params),
params_format(params));
switch (params_rate(params)) {
case 8000: fsref = 48000; divisor = AIC26_DIV_6; break;
case 11025: fsref = 44100; divisor = AIC26_DIV_4; break;
case 12000: fsref = 48000; divisor = AIC26_DIV_4; break;
case 16000: fsref = 48000; divisor = AIC26_DIV_3; break;
case 22050: fsref = 44100; divisor = AIC26_DIV_2; break;
case 24000: fsref = 48000; divisor = AIC26_DIV_2; break;
case 32000: fsref = 48000; divisor = AIC26_DIV_1_5; break;
case 44100: fsref = 44100; divisor = AIC26_DIV_1; break;
case 48000: fsref = 48000; divisor = AIC26_DIV_1; break;
default:
dev_dbg(&aic26->spi->dev, "bad rate\n"); return -EINVAL;
}
/* select data word length */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8: wlen = AIC26_WLEN_16; break;
case SNDRV_PCM_FORMAT_S16_BE: wlen = AIC26_WLEN_16; break;
case SNDRV_PCM_FORMAT_S24_BE: wlen = AIC26_WLEN_24; break;
case SNDRV_PCM_FORMAT_S32_BE: wlen = AIC26_WLEN_32; break;
default:
dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL;
}
/* Configure PLL */
pval = 1;
jval = (fsref == 44100) ? 7 : 8;
dval = (fsref == 44100) ? 5264 : 1920;
qval = 0;
reg = 0x8000 | qval << 11 | pval << 8 | jval << 2;
aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg);
reg = dval << 2;
aic26_reg_write(codec, AIC26_REG_PLL_PROG2, reg);
/* Audio Control 3 (master mode, fsref rate) */
reg = aic26_reg_read_cache(codec, AIC26_REG_AUDIO_CTRL3);
reg &= ~0xf800;
if (aic26->master)
reg |= 0x0800;
if (fsref == 48000)
reg |= 0x2000;
aic26_reg_write(codec, AIC26_REG_AUDIO_CTRL3, reg);
/* Audio Control 1 (FSref divisor) */
reg = aic26_reg_read_cache(codec, AIC26_REG_AUDIO_CTRL1);
reg &= ~0x0fff;
reg |= wlen | aic26->datfm | (divisor << 3) | divisor;
aic26_reg_write(codec, AIC26_REG_AUDIO_CTRL1, reg);
return 0;
}
/**
* aic26_mute - Mute control to reduce noise when changing audio format
*/
static int aic26_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
struct aic26 *aic26 = codec->private_data;
u16 reg = aic26_reg_read_cache(codec, AIC26_REG_DAC_GAIN);
dev_dbg(&aic26->spi->dev, "aic26_mute(dai=%p, mute=%i)\n",
dai, mute);
if (mute)
reg |= 0x8080;
else
reg &= ~0x8080;
aic26_reg_write(codec, AIC26_REG_DAC_GAIN, reg);
return 0;
}
static int aic26_set_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct aic26 *aic26 = codec->private_data;
dev_dbg(&aic26->spi->dev, "aic26_set_sysclk(dai=%p, clk_id==%i,"
" freq=%i, dir=%i)\n",
codec_dai, clk_id, freq, dir);
/* MCLK needs to fall between 2MHz and 50 MHz */
if ((freq < 2000000) || (freq > 50000000))
return -EINVAL;
aic26->mclk = freq;
return 0;
}
static int aic26_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct aic26 *aic26 = codec->private_data;
dev_dbg(&aic26->spi->dev, "aic26_set_fmt(dai=%p, fmt==%i)\n",
codec_dai, fmt);
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM: aic26->master = 1; break;
case SND_SOC_DAIFMT_CBS_CFS: aic26->master = 0; break;
default:
dev_dbg(&aic26->spi->dev, "bad master\n"); return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S: aic26->datfm = AIC26_DATFM_I2S; break;
case SND_SOC_DAIFMT_DSP_A: aic26->datfm = AIC26_DATFM_DSP; break;
case SND_SOC_DAIFMT_RIGHT_J: aic26->datfm = AIC26_DATFM_RIGHTJ; break;
case SND_SOC_DAIFMT_LEFT_J: aic26->datfm = AIC26_DATFM_LEFTJ; break;
default:
dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL;
}
return 0;
}
/* ---------------------------------------------------------------------
* Digital Audio Interface Definition
*/
#define AIC26_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000)
#define AIC26_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |\
SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE)
static struct snd_soc_dai_ops aic26_dai_ops = {
.hw_params = aic26_hw_params,
.digital_mute = aic26_mute,
.set_sysclk = aic26_set_sysclk,
.set_fmt = aic26_set_fmt,
};
struct snd_soc_dai aic26_dai = {
.name = "tlv320aic26",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = AIC26_RATES,
.formats = AIC26_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = AIC26_RATES,
.formats = AIC26_FORMATS,
},
.ops = &aic26_dai_ops,
};
EXPORT_SYMBOL_GPL(aic26_dai);
/* ---------------------------------------------------------------------
* ALSA controls
*/
static const char *aic26_capture_src_text[] = {"Mic", "Aux"};
static const struct soc_enum aic26_capture_src_enum =
SOC_ENUM_SINGLE(AIC26_REG_AUDIO_CTRL1, 12, 2, aic26_capture_src_text);
static const struct snd_kcontrol_new aic26_snd_controls[] = {
/* Output */
SOC_DOUBLE("PCM Playback Volume", AIC26_REG_DAC_GAIN, 8, 0, 0x7f, 1),
SOC_DOUBLE("PCM Playback Switch", AIC26_REG_DAC_GAIN, 15, 7, 1, 1),
SOC_SINGLE("PCM Capture Volume", AIC26_REG_ADC_GAIN, 8, 0x7f, 0),
SOC_SINGLE("PCM Capture Mute", AIC26_REG_ADC_GAIN, 15, 1, 1),
SOC_SINGLE("Keyclick activate", AIC26_REG_AUDIO_CTRL2, 15, 0x1, 0),
SOC_SINGLE("Keyclick amplitude", AIC26_REG_AUDIO_CTRL2, 12, 0x7, 0),
SOC_SINGLE("Keyclick frequency", AIC26_REG_AUDIO_CTRL2, 8, 0x7, 0),
SOC_SINGLE("Keyclick period", AIC26_REG_AUDIO_CTRL2, 4, 0xf, 0),
SOC_ENUM("Capture Source", aic26_capture_src_enum),
};
/* ---------------------------------------------------------------------
* SoC CODEC portion of driver: probe and release routines
*/
static int aic26_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
struct aic26 *aic26;
int ret, err;
dev_info(&pdev->dev, "Probing AIC26 SoC CODEC driver\n");
dev_dbg(&pdev->dev, "socdev=%p\n", socdev);
dev_dbg(&pdev->dev, "codec_data=%p\n", socdev->codec_data);
/* Fetch the relevant aic26 private data here (it's already been
* stored in the .codec pointer) */
aic26 = socdev->codec_data;
if (aic26 == NULL) {
dev_err(&pdev->dev, "aic26: missing codec pointer\n");
return -ENODEV;
}
codec = &aic26->codec;
socdev->card->codec = codec;
dev_dbg(&pdev->dev, "Registering PCMs, dev=%p, socdev->dev=%p\n",
&pdev->dev, socdev->dev);
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(&pdev->dev, "aic26: failed to create pcms\n");
return -ENODEV;
}
/* register controls */
dev_dbg(&pdev->dev, "Registering controls\n");
err = snd_soc_add_controls(codec, aic26_snd_controls,
ARRAY_SIZE(aic26_snd_controls));
WARN_ON(err < 0);
/* CODEC is setup, we can register the card now */
dev_dbg(&pdev->dev, "Registering card\n");
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(&pdev->dev, "aic26: failed to register card\n");
goto card_err;
}
return 0;
card_err:
snd_soc_free_pcms(socdev);
return ret;
}
static int aic26_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
return 0;
}
struct snd_soc_codec_device aic26_soc_codec_dev = {
.probe = aic26_probe,
.remove = aic26_remove,
};
EXPORT_SYMBOL_GPL(aic26_soc_codec_dev);
/* ---------------------------------------------------------------------
* SPI device portion of driver: sysfs files for debugging
*/
static ssize_t aic26_keyclick_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct aic26 *aic26 = dev_get_drvdata(dev);
int val, amp, freq, len;
val = aic26_reg_read_cache(&aic26->codec, AIC26_REG_AUDIO_CTRL2);
amp = (val >> 12) & 0x7;
freq = (125 << ((val >> 8) & 0x7)) >> 1;
len = 2 * (1 + ((val >> 4) & 0xf));
return sprintf(buf, "amp=%x freq=%iHz len=%iclks\n", amp, freq, len);
}
/* Any write to the keyclick attribute will trigger the keyclick event */
static ssize_t aic26_keyclick_set(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct aic26 *aic26 = dev_get_drvdata(dev);
int val;
val = aic26_reg_read_cache(&aic26->codec, AIC26_REG_AUDIO_CTRL2);
val |= 0x8000;
aic26_reg_write(&aic26->codec, AIC26_REG_AUDIO_CTRL2, val);
return count;
}
static DEVICE_ATTR(keyclick, 0644, aic26_keyclick_show, aic26_keyclick_set);
/* ---------------------------------------------------------------------
* SPI device portion of driver: probe and release routines and SPI
* driver registration.
*/
static int aic26_spi_probe(struct spi_device *spi)
{
struct aic26 *aic26;
int ret, i, reg;
dev_dbg(&spi->dev, "probing tlv320aic26 spi device\n");
/* Allocate driver data */
aic26 = kzalloc(sizeof *aic26, GFP_KERNEL);
if (!aic26)
return -ENOMEM;
/* Initialize the driver data */
aic26->spi = spi;
dev_set_drvdata(&spi->dev, aic26);
/* Setup what we can in the codec structure so that the register
* access functions will work as expected. More will be filled
* out when it is probed by the SoC CODEC part of this driver */
aic26->codec.private_data = aic26;
aic26->codec.name = "aic26";
aic26->codec.owner = THIS_MODULE;
aic26->codec.dai = &aic26_dai;
aic26->codec.num_dai = 1;
aic26->codec.read = aic26_reg_read;
aic26->codec.write = aic26_reg_write;
aic26->master = 1;
mutex_init(&aic26->codec.mutex);
INIT_LIST_HEAD(&aic26->codec.dapm_widgets);
INIT_LIST_HEAD(&aic26->codec.dapm_paths);
aic26->codec.reg_cache_size = AIC26_NUM_REGS;
aic26->codec.reg_cache = aic26->reg_cache;
aic26_dai.dev = &spi->dev;
ret = snd_soc_register_dai(&aic26_dai);
if (ret != 0) {
dev_err(&spi->dev, "Failed to register DAI: %d\n", ret);
kfree(aic26);
return ret;
}
/* Reset the codec to power on defaults */
aic26_reg_write(&aic26->codec, AIC26_REG_RESET, 0xBB00);
/* Power up CODEC */
aic26_reg_write(&aic26->codec, AIC26_REG_POWER_CTRL, 0);
/* Audio Control 3 (master mode, fsref rate) */
reg = aic26_reg_read(&aic26->codec, AIC26_REG_AUDIO_CTRL3);
reg &= ~0xf800;
reg |= 0x0800; /* set master mode */
aic26_reg_write(&aic26->codec, AIC26_REG_AUDIO_CTRL3, reg);
/* Fill register cache */
for (i = 0; i < ARRAY_SIZE(aic26->reg_cache); i++)
aic26_reg_read(&aic26->codec, i);
/* Register the sysfs files for debugging */
/* Create SysFS files */
ret = device_create_file(&spi->dev, &dev_attr_keyclick);
if (ret)
dev_info(&spi->dev, "error creating sysfs files\n");
#if defined(CONFIG_SND_SOC_OF_SIMPLE)
/* Tell the of_soc helper about this codec */
of_snd_soc_register_codec(&aic26_soc_codec_dev, aic26, &aic26_dai,
spi->dev.archdata.of_node);
#endif
dev_dbg(&spi->dev, "SPI device initialized\n");
return 0;
}
static int aic26_spi_remove(struct spi_device *spi)
{
struct aic26 *aic26 = dev_get_drvdata(&spi->dev);
snd_soc_unregister_dai(&aic26_dai);
kfree(aic26);
return 0;
}
static struct spi_driver aic26_spi = {
.driver = {
.name = "tlv320aic26",
.owner = THIS_MODULE,
},
.probe = aic26_spi_probe,
.remove = aic26_spi_remove,
};
static int __init aic26_init(void)
{
return spi_register_driver(&aic26_spi);
}
module_init(aic26_init);
static void __exit aic26_exit(void)
{
spi_unregister_driver(&aic26_spi);
}
module_exit(aic26_exit);

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kernel/sound/soc/codecs/tlv320aic26.h Normal file
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/*
* Texas Instruments TLV320AIC26 low power audio CODEC
* register definitions
*
* Copyright (C) 2008 Secret Lab Technologies Ltd.
*/
#ifndef _TLV320AIC16_H_
#define _TLV320AIC16_H_
/* AIC26 Registers */
#define AIC26_READ_COMMAND_WORD(addr) ((1 << 15) | (addr << 5))
#define AIC26_WRITE_COMMAND_WORD(addr) ((0 << 15) | (addr << 5))
#define AIC26_PAGE_ADDR(page, offset) ((page << 6) | offset)
#define AIC26_NUM_REGS AIC26_PAGE_ADDR(3, 0)
/* Page 0: Auxillary data registers */
#define AIC26_REG_BAT1 AIC26_PAGE_ADDR(0, 0x05)
#define AIC26_REG_BAT2 AIC26_PAGE_ADDR(0, 0x06)
#define AIC26_REG_AUX AIC26_PAGE_ADDR(0, 0x07)
#define AIC26_REG_TEMP1 AIC26_PAGE_ADDR(0, 0x09)
#define AIC26_REG_TEMP2 AIC26_PAGE_ADDR(0, 0x0A)
/* Page 1: Auxillary control registers */
#define AIC26_REG_AUX_ADC AIC26_PAGE_ADDR(1, 0x00)
#define AIC26_REG_STATUS AIC26_PAGE_ADDR(1, 0x01)
#define AIC26_REG_REFERENCE AIC26_PAGE_ADDR(1, 0x03)
#define AIC26_REG_RESET AIC26_PAGE_ADDR(1, 0x04)
/* Page 2: Audio control registers */
#define AIC26_REG_AUDIO_CTRL1 AIC26_PAGE_ADDR(2, 0x00)
#define AIC26_REG_ADC_GAIN AIC26_PAGE_ADDR(2, 0x01)
#define AIC26_REG_DAC_GAIN AIC26_PAGE_ADDR(2, 0x02)
#define AIC26_REG_SIDETONE AIC26_PAGE_ADDR(2, 0x03)
#define AIC26_REG_AUDIO_CTRL2 AIC26_PAGE_ADDR(2, 0x04)
#define AIC26_REG_POWER_CTRL AIC26_PAGE_ADDR(2, 0x05)
#define AIC26_REG_AUDIO_CTRL3 AIC26_PAGE_ADDR(2, 0x06)
#define AIC26_REG_FILTER_COEFF_L_N0 AIC26_PAGE_ADDR(2, 0x07)
#define AIC26_REG_FILTER_COEFF_L_N1 AIC26_PAGE_ADDR(2, 0x08)
#define AIC26_REG_FILTER_COEFF_L_N2 AIC26_PAGE_ADDR(2, 0x09)
#define AIC26_REG_FILTER_COEFF_L_N3 AIC26_PAGE_ADDR(2, 0x0A)
#define AIC26_REG_FILTER_COEFF_L_N4 AIC26_PAGE_ADDR(2, 0x0B)
#define AIC26_REG_FILTER_COEFF_L_N5 AIC26_PAGE_ADDR(2, 0x0C)
#define AIC26_REG_FILTER_COEFF_L_D1 AIC26_PAGE_ADDR(2, 0x0D)
#define AIC26_REG_FILTER_COEFF_L_D2 AIC26_PAGE_ADDR(2, 0x0E)
#define AIC26_REG_FILTER_COEFF_L_D4 AIC26_PAGE_ADDR(2, 0x0F)
#define AIC26_REG_FILTER_COEFF_L_D5 AIC26_PAGE_ADDR(2, 0x10)
#define AIC26_REG_FILTER_COEFF_R_N0 AIC26_PAGE_ADDR(2, 0x11)
#define AIC26_REG_FILTER_COEFF_R_N1 AIC26_PAGE_ADDR(2, 0x12)
#define AIC26_REG_FILTER_COEFF_R_N2 AIC26_PAGE_ADDR(2, 0x13)
#define AIC26_REG_FILTER_COEFF_R_N3 AIC26_PAGE_ADDR(2, 0x14)
#define AIC26_REG_FILTER_COEFF_R_N4 AIC26_PAGE_ADDR(2, 0x15)
#define AIC26_REG_FILTER_COEFF_R_N5 AIC26_PAGE_ADDR(2, 0x16)
#define AIC26_REG_FILTER_COEFF_R_D1 AIC26_PAGE_ADDR(2, 0x17)
#define AIC26_REG_FILTER_COEFF_R_D2 AIC26_PAGE_ADDR(2, 0x18)
#define AIC26_REG_FILTER_COEFF_R_D4 AIC26_PAGE_ADDR(2, 0x19)
#define AIC26_REG_FILTER_COEFF_R_D5 AIC26_PAGE_ADDR(2, 0x1A)
#define AIC26_REG_PLL_PROG1 AIC26_PAGE_ADDR(2, 0x1B)
#define AIC26_REG_PLL_PROG2 AIC26_PAGE_ADDR(2, 0x1C)
#define AIC26_REG_AUDIO_CTRL4 AIC26_PAGE_ADDR(2, 0x1D)
#define AIC26_REG_AUDIO_CTRL5 AIC26_PAGE_ADDR(2, 0x1E)
/* fsref dividers; used in register 'Audio Control 1' */
enum aic26_divisors {
AIC26_DIV_1 = 0,
AIC26_DIV_1_5 = 1,
AIC26_DIV_2 = 2,
AIC26_DIV_3 = 3,
AIC26_DIV_4 = 4,
AIC26_DIV_5 = 5,
AIC26_DIV_5_5 = 6,
AIC26_DIV_6 = 7,
};
/* Digital data format */
enum aic26_datfm {
AIC26_DATFM_I2S = 0 << 8,
AIC26_DATFM_DSP = 1 << 8,
AIC26_DATFM_RIGHTJ = 2 << 8, /* right justified */
AIC26_DATFM_LEFTJ = 3 << 8, /* left justified */
};
/* Sample word length in bits; used in register 'Audio Control 1' */
enum aic26_wlen {
AIC26_WLEN_16 = 0 << 10,
AIC26_WLEN_20 = 1 << 10,
AIC26_WLEN_24 = 2 << 10,
AIC26_WLEN_32 = 3 << 10,
};
extern struct snd_soc_dai aic26_dai;
extern struct snd_soc_codec_device aic26_soc_codec_dev;
#endif /* _TLV320AIC16_H_ */

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kernel/sound/soc/codecs/tlv320aic3x.c Normal file
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/*
* ALSA SoC TLV320AIC3X codec driver
*
* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _AIC3X_H
#define _AIC3X_H
/* AIC3X register space */
#define AIC3X_CACHEREGNUM 103
/* Page select register */
#define AIC3X_PAGE_SELECT 0
/* Software reset register */
#define AIC3X_RESET 1
/* Codec Sample rate select register */
#define AIC3X_SAMPLE_RATE_SEL_REG 2
/* PLL progrramming register A */
#define AIC3X_PLL_PROGA_REG 3
/* PLL progrramming register B */
#define AIC3X_PLL_PROGB_REG 4
/* PLL progrramming register C */
#define AIC3X_PLL_PROGC_REG 5
/* PLL progrramming register D */
#define AIC3X_PLL_PROGD_REG 6
/* Codec datapath setup register */
#define AIC3X_CODEC_DATAPATH_REG 7
/* Audio serial data interface control register A */
#define AIC3X_ASD_INTF_CTRLA 8
/* Audio serial data interface control register B */
#define AIC3X_ASD_INTF_CTRLB 9
/* Audio serial data interface control register C */
#define AIC3X_ASD_INTF_CTRLC 10
/* Audio overflow status and PLL R value programming register */
#define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
/* Audio codec digital filter control register */
#define AIC3X_CODEC_DFILT_CTRL 12
/* Headset/button press detection register */
#define AIC3X_HEADSET_DETECT_CTRL_A 13
#define AIC3X_HEADSET_DETECT_CTRL_B 14
/* ADC PGA Gain control registers */
#define LADC_VOL 15
#define RADC_VOL 16
/* MIC3 control registers */
#define MIC3LR_2_LADC_CTRL 17
#define MIC3LR_2_RADC_CTRL 18
/* Line1 Input control registers */
#define LINE1L_2_LADC_CTRL 19
#define LINE1R_2_LADC_CTRL 21
#define LINE1R_2_RADC_CTRL 22
#define LINE1L_2_RADC_CTRL 24
/* Line2 Input control registers */
#define LINE2L_2_LADC_CTRL 20
#define LINE2R_2_RADC_CTRL 23
/* MICBIAS Control Register */
#define MICBIAS_CTRL 25
/* AGC Control Registers A, B, C */
#define LAGC_CTRL_A 26
#define LAGC_CTRL_B 27
#define LAGC_CTRL_C 28
#define RAGC_CTRL_A 29
#define RAGC_CTRL_B 30
#define RAGC_CTRL_C 31
/* DAC Power and Left High Power Output control registers */
#define DAC_PWR 37
#define HPLCOM_CFG 37
/* Right High Power Output control registers */
#define HPRCOM_CFG 38
/* DAC Output Switching control registers */
#define DAC_LINE_MUX 41
/* High Power Output Driver Pop Reduction registers */
#define HPOUT_POP_REDUCTION 42
/* DAC Digital control registers */
#define LDAC_VOL 43
#define RDAC_VOL 44
/* High Power Output control registers */
#define LINE2L_2_HPLOUT_VOL 45
#define LINE2R_2_HPROUT_VOL 62
#define PGAL_2_HPLOUT_VOL 46
#define PGAL_2_HPROUT_VOL 60
#define PGAR_2_HPLOUT_VOL 49
#define PGAR_2_HPROUT_VOL 63
#define DACL1_2_HPLOUT_VOL 47
#define DACR1_2_HPROUT_VOL 64
#define HPLOUT_CTRL 51
#define HPROUT_CTRL 65
/* High Power COM control registers */
#define LINE2L_2_HPLCOM_VOL 52
#define LINE2R_2_HPRCOM_VOL 69
#define PGAL_2_HPLCOM_VOL 53
#define PGAR_2_HPLCOM_VOL 56
#define PGAL_2_HPRCOM_VOL 67
#define PGAR_2_HPRCOM_VOL 70
#define DACL1_2_HPLCOM_VOL 54
#define DACR1_2_HPRCOM_VOL 71
#define HPLCOM_CTRL 58
#define HPRCOM_CTRL 72
/* Mono Line Output Plus/Minus control registers */
#define LINE2L_2_MONOLOPM_VOL 73
#define LINE2R_2_MONOLOPM_VOL 76
#define PGAL_2_MONOLOPM_VOL 74
#define PGAR_2_MONOLOPM_VOL 77
#define DACL1_2_MONOLOPM_VOL 75
#define DACR1_2_MONOLOPM_VOL 78
#define MONOLOPM_CTRL 79
/* Line Output Plus/Minus control registers */
#define LINE2L_2_LLOPM_VOL 80
#define LINE2L_2_RLOPM_VOL 87
#define LINE2R_2_LLOPM_VOL 83
#define LINE2R_2_RLOPM_VOL 90
#define PGAL_2_LLOPM_VOL 81
#define PGAL_2_RLOPM_VOL 88
#define PGAR_2_LLOPM_VOL 84
#define PGAR_2_RLOPM_VOL 91
#define DACL1_2_LLOPM_VOL 82
#define DACL1_2_RLOPM_VOL 89
#define DACR1_2_RLOPM_VOL 92
#define DACR1_2_LLOPM_VOL 85
#define LLOPM_CTRL 86
#define RLOPM_CTRL 93
/* GPIO/IRQ registers */
#define AIC3X_STICKY_IRQ_FLAGS_REG 96
#define AIC3X_RT_IRQ_FLAGS_REG 97
#define AIC3X_GPIO1_REG 98
#define AIC3X_GPIO2_REG 99
#define AIC3X_GPIOA_REG 100
#define AIC3X_GPIOB_REG 101
/* Clock generation control register */
#define AIC3X_CLKGEN_CTRL_REG 102
/* Page select register bits */
#define PAGE0_SELECT 0
#define PAGE1_SELECT 1
/* Audio serial data interface control register A bits */
#define BIT_CLK_MASTER 0x80
#define WORD_CLK_MASTER 0x40
/* Codec Datapath setup register 7 */
#define FSREF_44100 (1 << 7)
#define FSREF_48000 (0 << 7)
#define DUAL_RATE_MODE ((1 << 5) | (1 << 6))
#define LDAC2LCH (0x1 << 3)
#define RDAC2RCH (0x1 << 1)
/* PLL registers bitfields */
#define PLLP_SHIFT 0
#define PLLQ_SHIFT 3
#define PLLR_SHIFT 0
#define PLLJ_SHIFT 2
#define PLLD_MSB_SHIFT 0
#define PLLD_LSB_SHIFT 2
/* Clock generation register bits */
#define CODEC_CLKIN_PLLDIV 0
#define CODEC_CLKIN_CLKDIV 1
#define PLL_CLKIN_SHIFT 4
#define MCLK_SOURCE 0x0
#define PLL_CLKDIV_SHIFT 0
/* Software reset register bits */
#define SOFT_RESET 0x80
/* PLL progrramming register A bits */
#define PLL_ENABLE 0x80
/* Route bits */
#define ROUTE_ON 0x80
/* Mute bits */
#define UNMUTE 0x08
#define MUTE_ON 0x80
/* Power bits */
#define LADC_PWR_ON 0x04
#define RADC_PWR_ON 0x04
#define LDAC_PWR_ON 0x80
#define RDAC_PWR_ON 0x40
#define HPLOUT_PWR_ON 0x01
#define HPROUT_PWR_ON 0x01
#define HPLCOM_PWR_ON 0x01
#define HPRCOM_PWR_ON 0x01
#define MONOLOPM_PWR_ON 0x01
#define LLOPM_PWR_ON 0x01
#define RLOPM_PWR_ON 0x01
#define INVERT_VOL(val) (0x7f - val)
/* Default output volume (inverted) */
#define DEFAULT_VOL INVERT_VOL(0x50)
/* Default input volume */
#define DEFAULT_GAIN 0x20
/* GPIO API */
enum {
AIC3X_GPIO1_FUNC_DISABLED = 0,
AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC = 1,
AIC3X_GPIO1_FUNC_CLOCK_MUX = 2,
AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2 = 3,
AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4 = 4,
AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8 = 5,
AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ = 6,
AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ = 7,
AIC3X_GPIO1_FUNC_INPUT = 8,
AIC3X_GPIO1_FUNC_OUTPUT = 9,
AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK = 10,
AIC3X_GPIO1_FUNC_AUDIO_WORDCLK = 11,
AIC3X_GPIO1_FUNC_BUTTON_IRQ = 12,
AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ = 13,
AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 14,
AIC3X_GPIO1_FUNC_ALL_IRQ = 16
};
enum {
AIC3X_GPIO2_FUNC_DISABLED = 0,
AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ = 2,
AIC3X_GPIO2_FUNC_INPUT = 3,
AIC3X_GPIO2_FUNC_OUTPUT = 4,
AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT = 5,
AIC3X_GPIO2_FUNC_AUDIO_BITCLK = 8,
AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9,
AIC3X_GPIO2_FUNC_ALL_IRQ = 10,
AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11,
AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12,
AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ = 13,
AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ = 14,
AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ = 15
};
void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state);
int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio);
/* headset detection / button API */
/* The AIC3x supports detection of stereo headsets (GND + left + right signal)
* and cellular headsets (GND + speaker output + microphone input).
* It is recommended to enable MIC bias for this function to work properly.
* For more information, please refer to the datasheet. */
enum {
AIC3X_HEADSET_DETECT_OFF = 0,
AIC3X_HEADSET_DETECT_STEREO = 1,
AIC3X_HEADSET_DETECT_CELLULAR = 2,
AIC3X_HEADSET_DETECT_BOTH = 3
};
enum {
AIC3X_HEADSET_DEBOUNCE_16MS = 0,
AIC3X_HEADSET_DEBOUNCE_32MS = 1,
AIC3X_HEADSET_DEBOUNCE_64MS = 2,
AIC3X_HEADSET_DEBOUNCE_128MS = 3,
AIC3X_HEADSET_DEBOUNCE_256MS = 4,
AIC3X_HEADSET_DEBOUNCE_512MS = 5
};
enum {
AIC3X_BUTTON_DEBOUNCE_0MS = 0,
AIC3X_BUTTON_DEBOUNCE_8MS = 1,
AIC3X_BUTTON_DEBOUNCE_16MS = 2,
AIC3X_BUTTON_DEBOUNCE_32MS = 3
};
#define AIC3X_HEADSET_DETECT_ENABLED 0x80
#define AIC3X_HEADSET_DETECT_SHIFT 5
#define AIC3X_HEADSET_DETECT_MASK 3
#define AIC3X_HEADSET_DEBOUNCE_SHIFT 2
#define AIC3X_HEADSET_DEBOUNCE_MASK 7
#define AIC3X_BUTTON_DEBOUNCE_SHIFT 0
#define AIC3X_BUTTON_DEBOUNCE_MASK 3
/* see the enums above for valid parameters to this function */
void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
int headset_debounce, int button_debounce);
int aic3x_headset_detected(struct snd_soc_codec *codec);
int aic3x_button_pressed(struct snd_soc_codec *codec);
struct aic3x_setup_data {
unsigned int gpio_func[2];
};
extern struct snd_soc_dai aic3x_dai;
extern struct snd_soc_codec_device soc_codec_dev_aic3x;
#endif /* _AIC3X_H */

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/*
* ALSA SoC TWL4030 codec driver
*
* Author: Steve Sakoman <steve@sakoman.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef __TWL4030_AUDIO_H__
#define __TWL4030_AUDIO_H__
#define TWL4030_REG_CODEC_MODE 0x1
#define TWL4030_REG_OPTION 0x2
#define TWL4030_REG_UNKNOWN 0x3
#define TWL4030_REG_MICBIAS_CTL 0x4
#define TWL4030_REG_ANAMICL 0x5
#define TWL4030_REG_ANAMICR 0x6
#define TWL4030_REG_AVADC_CTL 0x7
#define TWL4030_REG_ADCMICSEL 0x8
#define TWL4030_REG_DIGMIXING 0x9
#define TWL4030_REG_ATXL1PGA 0xA
#define TWL4030_REG_ATXR1PGA 0xB
#define TWL4030_REG_AVTXL2PGA 0xC
#define TWL4030_REG_AVTXR2PGA 0xD
#define TWL4030_REG_AUDIO_IF 0xE
#define TWL4030_REG_VOICE_IF 0xF
#define TWL4030_REG_ARXR1PGA 0x10
#define TWL4030_REG_ARXL1PGA 0x11
#define TWL4030_REG_ARXR2PGA 0x12
#define TWL4030_REG_ARXL2PGA 0x13
#define TWL4030_REG_VRXPGA 0x14
#define TWL4030_REG_VSTPGA 0x15
#define TWL4030_REG_VRX2ARXPGA 0x16
#define TWL4030_REG_AVDAC_CTL 0x17
#define TWL4030_REG_ARX2VTXPGA 0x18
#define TWL4030_REG_ARXL1_APGA_CTL 0x19
#define TWL4030_REG_ARXR1_APGA_CTL 0x1A
#define TWL4030_REG_ARXL2_APGA_CTL 0x1B
#define TWL4030_REG_ARXR2_APGA_CTL 0x1C
#define TWL4030_REG_ATX2ARXPGA 0x1D
#define TWL4030_REG_BT_IF 0x1E
#define TWL4030_REG_BTPGA 0x1F
#define TWL4030_REG_BTSTPGA 0x20
#define TWL4030_REG_EAR_CTL 0x21
#define TWL4030_REG_HS_SEL 0x22
#define TWL4030_REG_HS_GAIN_SET 0x23
#define TWL4030_REG_HS_POPN_SET 0x24
#define TWL4030_REG_PREDL_CTL 0x25
#define TWL4030_REG_PREDR_CTL 0x26
#define TWL4030_REG_PRECKL_CTL 0x27
#define TWL4030_REG_PRECKR_CTL 0x28
#define TWL4030_REG_HFL_CTL 0x29
#define TWL4030_REG_HFR_CTL 0x2A
#define TWL4030_REG_ALC_CTL 0x2B
#define TWL4030_REG_ALC_SET1 0x2C
#define TWL4030_REG_ALC_SET2 0x2D
#define TWL4030_REG_BOOST_CTL 0x2E
#define TWL4030_REG_SOFTVOL_CTL 0x2F
#define TWL4030_REG_DTMF_FREQSEL 0x30
#define TWL4030_REG_DTMF_TONEXT1H 0x31
#define TWL4030_REG_DTMF_TONEXT1L 0x32
#define TWL4030_REG_DTMF_TONEXT2H 0x33
#define TWL4030_REG_DTMF_TONEXT2L 0x34
#define TWL4030_REG_DTMF_TONOFF 0x35
#define TWL4030_REG_DTMF_WANONOFF 0x36
#define TWL4030_REG_I2S_RX_SCRAMBLE_H 0x37
#define TWL4030_REG_I2S_RX_SCRAMBLE_M 0x38
#define TWL4030_REG_I2S_RX_SCRAMBLE_L 0x39
#define TWL4030_REG_APLL_CTL 0x3A
#define TWL4030_REG_DTMF_CTL 0x3B
#define TWL4030_REG_DTMF_PGA_CTL2 0x3C
#define TWL4030_REG_DTMF_PGA_CTL1 0x3D
#define TWL4030_REG_MISC_SET_1 0x3E
#define TWL4030_REG_PCMBTMUX 0x3F
#define TWL4030_REG_RX_PATH_SEL 0x43
#define TWL4030_REG_VDL_APGA_CTL 0x44
#define TWL4030_REG_VIBRA_CTL 0x45
#define TWL4030_REG_VIBRA_SET 0x46
#define TWL4030_REG_VIBRA_PWM_SET 0x47
#define TWL4030_REG_ANAMIC_GAIN 0x48
#define TWL4030_REG_MISC_SET_2 0x49
#define TWL4030_REG_SW_SHADOW 0x4A
#define TWL4030_CACHEREGNUM (TWL4030_REG_SW_SHADOW + 1)
/* Bitfield Definitions */
/* TWL4030_CODEC_MODE (0x01) Fields */
#define TWL4030_APLL_RATE 0xF0
#define TWL4030_APLL_RATE_8000 0x00
#define TWL4030_APLL_RATE_11025 0x10
#define TWL4030_APLL_RATE_12000 0x20
#define TWL4030_APLL_RATE_16000 0x40
#define TWL4030_APLL_RATE_22050 0x50
#define TWL4030_APLL_RATE_24000 0x60
#define TWL4030_APLL_RATE_32000 0x80
#define TWL4030_APLL_RATE_44100 0x90
#define TWL4030_APLL_RATE_48000 0xA0
#define TWL4030_APLL_RATE_96000 0xE0
#define TWL4030_SEL_16K 0x08
#define TWL4030_CODECPDZ 0x02
#define TWL4030_OPT_MODE 0x01
#define TWL4030_OPTION_1 (1 << 0)
#define TWL4030_OPTION_2 (0 << 0)
/* TWL4030_OPTION (0x02) Fields */
#define TWL4030_ATXL1_EN (1 << 0)
#define TWL4030_ATXR1_EN (1 << 1)
#define TWL4030_ATXL2_VTXL_EN (1 << 2)
#define TWL4030_ATXR2_VTXR_EN (1 << 3)
#define TWL4030_ARXL1_VRX_EN (1 << 4)
#define TWL4030_ARXR1_EN (1 << 5)
#define TWL4030_ARXL2_EN (1 << 6)
#define TWL4030_ARXR2_EN (1 << 7)
/* TWL4030_REG_MICBIAS_CTL (0x04) Fields */
#define TWL4030_MICBIAS2_CTL 0x40
#define TWL4030_MICBIAS1_CTL 0x20
#define TWL4030_HSMICBIAS_EN 0x04
#define TWL4030_MICBIAS2_EN 0x02
#define TWL4030_MICBIAS1_EN 0x01
/* ANAMICL (0x05) Fields */
#define TWL4030_CNCL_OFFSET_START 0x80
#define TWL4030_OFFSET_CNCL_SEL 0x60
#define TWL4030_OFFSET_CNCL_SEL_ARX1 0x00
#define TWL4030_OFFSET_CNCL_SEL_ARX2 0x20
#define TWL4030_OFFSET_CNCL_SEL_VRX 0x40
#define TWL4030_OFFSET_CNCL_SEL_ALL 0x60
#define TWL4030_MICAMPL_EN 0x10
#define TWL4030_CKMIC_EN 0x08
#define TWL4030_AUXL_EN 0x04
#define TWL4030_HSMIC_EN 0x02
#define TWL4030_MAINMIC_EN 0x01
/* ANAMICR (0x06) Fields */
#define TWL4030_MICAMPR_EN 0x10
#define TWL4030_AUXR_EN 0x04
#define TWL4030_SUBMIC_EN 0x01
/* AVADC_CTL (0x07) Fields */
#define TWL4030_ADCL_EN 0x08
#define TWL4030_AVADC_CLK_PRIORITY 0x04
#define TWL4030_ADCR_EN 0x02
/* TWL4030_REG_ADCMICSEL (0x08) Fields */
#define TWL4030_DIGMIC1_EN 0x08
#define TWL4030_TX2IN_SEL 0x04
#define TWL4030_DIGMIC0_EN 0x02
#define TWL4030_TX1IN_SEL 0x01
/* AUDIO_IF (0x0E) Fields */
#define TWL4030_AIF_SLAVE_EN 0x80
#define TWL4030_DATA_WIDTH 0x60
#define TWL4030_DATA_WIDTH_16S_16W 0x00
#define TWL4030_DATA_WIDTH_32S_16W 0x40
#define TWL4030_DATA_WIDTH_32S_24W 0x60
#define TWL4030_AIF_FORMAT 0x18
#define TWL4030_AIF_FORMAT_CODEC 0x00
#define TWL4030_AIF_FORMAT_LEFT 0x08
#define TWL4030_AIF_FORMAT_RIGHT 0x10
#define TWL4030_AIF_FORMAT_TDM 0x18
#define TWL4030_AIF_TRI_EN 0x04
#define TWL4030_CLK256FS_EN 0x02
#define TWL4030_AIF_EN 0x01
/* VOICE_IF (0x0F) Fields */
#define TWL4030_VIF_SLAVE_EN 0x80
#define TWL4030_VIF_DIN_EN 0x40
#define TWL4030_VIF_DOUT_EN 0x20
#define TWL4030_VIF_SWAP 0x10
#define TWL4030_VIF_FORMAT 0x08
#define TWL4030_VIF_TRI_EN 0x04
#define TWL4030_VIF_SUB_EN 0x02
#define TWL4030_VIF_EN 0x01
/* EAR_CTL (0x21) */
#define TWL4030_EAR_GAIN 0x30
/* HS_GAIN_SET (0x23) Fields */
#define TWL4030_HSR_GAIN 0x0C
#define TWL4030_HSR_GAIN_PWR_DOWN 0x00
#define TWL4030_HSR_GAIN_PLUS_6DB 0x04
#define TWL4030_HSR_GAIN_0DB 0x08
#define TWL4030_HSR_GAIN_MINUS_6DB 0x0C
#define TWL4030_HSL_GAIN 0x03
#define TWL4030_HSL_GAIN_PWR_DOWN 0x00
#define TWL4030_HSL_GAIN_PLUS_6DB 0x01
#define TWL4030_HSL_GAIN_0DB 0x02
#define TWL4030_HSL_GAIN_MINUS_6DB 0x03
/* HS_POPN_SET (0x24) Fields */
#define TWL4030_VMID_EN 0x40
#define TWL4030_EXTMUTE 0x20
#define TWL4030_RAMP_DELAY 0x1C
#define TWL4030_RAMP_DELAY_20MS 0x00
#define TWL4030_RAMP_DELAY_40MS 0x04
#define TWL4030_RAMP_DELAY_81MS 0x08
#define TWL4030_RAMP_DELAY_161MS 0x0C
#define TWL4030_RAMP_DELAY_323MS 0x10
#define TWL4030_RAMP_DELAY_645MS 0x14
#define TWL4030_RAMP_DELAY_1291MS 0x18
#define TWL4030_RAMP_DELAY_2581MS 0x1C
#define TWL4030_RAMP_EN 0x02
/* PREDL_CTL (0x25) */
#define TWL4030_PREDL_GAIN 0x30
/* PREDR_CTL (0x26) */
#define TWL4030_PREDR_GAIN 0x30
/* PRECKL_CTL (0x27) */
#define TWL4030_PRECKL_GAIN 0x30
/* PRECKR_CTL (0x28) */
#define TWL4030_PRECKR_GAIN 0x30
/* HFL_CTL (0x29, 0x2A) Fields */
#define TWL4030_HF_CTL_HB_EN 0x04
#define TWL4030_HF_CTL_LOOP_EN 0x08
#define TWL4030_HF_CTL_RAMP_EN 0x10
#define TWL4030_HF_CTL_REF_EN 0x20
/* APLL_CTL (0x3A) Fields */
#define TWL4030_APLL_EN 0x10
#define TWL4030_APLL_INFREQ 0x0F
#define TWL4030_APLL_INFREQ_19200KHZ 0x05
#define TWL4030_APLL_INFREQ_26000KHZ 0x06
#define TWL4030_APLL_INFREQ_38400KHZ 0x0F
/* REG_MISC_SET_1 (0x3E) Fields */
#define TWL4030_CLK64_EN 0x80
#define TWL4030_SCRAMBLE_EN 0x40
#define TWL4030_FMLOOP_EN 0x20
#define TWL4030_SMOOTH_ANAVOL_EN 0x02
#define TWL4030_DIGMIC_LR_SWAP_EN 0x01
/* TWL4030_REG_SW_SHADOW (0x4A) Fields */
#define TWL4030_HFL_EN 0x01
#define TWL4030_HFR_EN 0x02
#define TWL4030_DAI_HIFI 0
#define TWL4030_DAI_VOICE 1
extern struct snd_soc_dai twl4030_dai[2];
extern struct snd_soc_codec_device soc_codec_dev_twl4030;
struct twl4030_setup_data {
unsigned int ramp_delay_value;
unsigned int sysclk;
unsigned int hs_extmute:1;
void (*set_hs_extmute)(int mute);
};
#endif /* End of __TWL4030_AUDIO_H__ */

652
kernel/sound/soc/codecs/uda134x.c Normal file
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@@ -0,0 +1,652 @@
/*
* uda134x.c -- UDA134X ALSA SoC Codec driver
*
* Modifications by Christian Pellegrin <chripell@evolware.org>
*
* Copyright 2007 Dension Audio Systems Ltd.
* Author: Zoltan Devai
*
* Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/uda134x.h>
#include <sound/l3.h>
#include "uda134x.h"
#define POWER_OFF_ON_STANDBY 1
/*
ALSA SOC usually puts the device in standby mode when it's not used
for sometime. If you define POWER_OFF_ON_STANDBY the driver will
turn off the ADC/DAC when this callback is invoked and turn it back
on when needed. Unfortunately this will result in a very light bump
(it can be audible only with good earphones). If this bothers you
just comment this line, you will have slightly higher power
consumption . Please note that sending the L3 command for ADC is
enough to make the bump, so it doesn't make difference if you
completely take off power from the codec.
*/
#define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
#define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE)
struct uda134x_priv {
int sysclk;
int dai_fmt;
struct snd_pcm_substream *master_substream;
struct snd_pcm_substream *slave_substream;
};
/* In-data addresses are hard-coded into the reg-cache values */
static const char uda134x_reg[UDA134X_REGS_NUM] = {
/* Extended address registers */
0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
/* Status, data regs */
0x00, 0x83, 0x00, 0x40, 0x80, 0x00,
};
/*
* The codec has no support for reading its registers except for peak level...
*/
static inline unsigned int uda134x_read_reg_cache(struct snd_soc_codec *codec,
unsigned int reg)
{
u8 *cache = codec->reg_cache;
if (reg >= UDA134X_REGS_NUM)
return -1;
return cache[reg];
}
/*
* Write the register cache
*/
static inline void uda134x_write_reg_cache(struct snd_soc_codec *codec,
u8 reg, unsigned int value)
{
u8 *cache = codec->reg_cache;
if (reg >= UDA134X_REGS_NUM)
return;
cache[reg] = value;
}
/*
* Write to the uda134x registers
*
*/
static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
int ret;
u8 addr;
u8 data = value;
struct uda134x_platform_data *pd = codec->control_data;
pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);
if (reg >= UDA134X_REGS_NUM) {
printk(KERN_ERR "%s unkown register: reg: %u",
__func__, reg);
return -EINVAL;
}
uda134x_write_reg_cache(codec, reg, value);
switch (reg) {
case UDA134X_STATUS0:
case UDA134X_STATUS1:
addr = UDA134X_STATUS_ADDR;
break;
case UDA134X_DATA000:
case UDA134X_DATA001:
case UDA134X_DATA010:
addr = UDA134X_DATA0_ADDR;
break;
case UDA134X_DATA1:
addr = UDA134X_DATA1_ADDR;
break;
default:
/* It's an extended address register */
addr = (reg | UDA134X_EXTADDR_PREFIX);
ret = l3_write(&pd->l3,
UDA134X_DATA0_ADDR, &addr, 1);
if (ret != 1)
return -EIO;
addr = UDA134X_DATA0_ADDR;
data = (value | UDA134X_EXTDATA_PREFIX);
break;
}
ret = l3_write(&pd->l3,
addr, &data, 1);
if (ret != 1)
return -EIO;
return 0;
}
static inline void uda134x_reset(struct snd_soc_codec *codec)
{
u8 reset_reg = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
uda134x_write(codec, UDA134X_STATUS0, reset_reg | (1<<6));
msleep(1);
uda134x_write(codec, UDA134X_STATUS0, reset_reg & ~(1<<6));
}
static int uda134x_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
u8 mute_reg = uda134x_read_reg_cache(codec, UDA134X_DATA010);
pr_debug("%s mute: %d\n", __func__, mute);
if (mute)
mute_reg |= (1<<2);
else
mute_reg &= ~(1<<2);
uda134x_write(codec, UDA134X_DATA010, mute_reg);
return 0;
}
static int uda134x_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct uda134x_priv *uda134x = codec->private_data;
struct snd_pcm_runtime *master_runtime;
if (uda134x->master_substream) {
master_runtime = uda134x->master_substream->runtime;
pr_debug("%s constraining to %d bits at %d\n", __func__,
master_runtime->sample_bits,
master_runtime->rate);
snd_pcm_hw_constraint_minmax(substream->runtime,
SNDRV_PCM_HW_PARAM_RATE,
master_runtime->rate,
master_runtime->rate);
snd_pcm_hw_constraint_minmax(substream->runtime,
SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
master_runtime->sample_bits,
master_runtime->sample_bits);
uda134x->slave_substream = substream;
} else
uda134x->master_substream = substream;
return 0;
}
static void uda134x_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct uda134x_priv *uda134x = codec->private_data;
if (uda134x->master_substream == substream)
uda134x->master_substream = uda134x->slave_substream;
uda134x->slave_substream = NULL;
}
static int uda134x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct uda134x_priv *uda134x = codec->private_data;
u8 hw_params;
if (substream == uda134x->slave_substream) {
pr_debug("%s ignoring hw_params for slave substream\n",
__func__);
return 0;
}
hw_params = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
hw_params &= STATUS0_SYSCLK_MASK;
hw_params &= STATUS0_DAIFMT_MASK;
pr_debug("%s sysclk: %d, rate:%d\n", __func__,
uda134x->sysclk, params_rate(params));
/* set SYSCLK / fs ratio */
switch (uda134x->sysclk / params_rate(params)) {
case 512:
break;
case 384:
hw_params |= (1<<4);
break;
case 256:
hw_params |= (1<<5);
break;
default:
printk(KERN_ERR "%s unsupported fs\n", __func__);
return -EINVAL;
}
pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
uda134x->dai_fmt, params_format(params));
/* set DAI format and word length */
switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_RIGHT_J:
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
hw_params |= (1<<1);
break;
case SNDRV_PCM_FORMAT_S18_3LE:
hw_params |= (1<<2);
break;
case SNDRV_PCM_FORMAT_S20_3LE:
hw_params |= ((1<<2) | (1<<1));
break;
default:
printk(KERN_ERR "%s unsupported format (right)\n",
__func__);
return -EINVAL;
}
break;
case SND_SOC_DAIFMT_LEFT_J:
hw_params |= (1<<3);
break;
default:
printk(KERN_ERR "%s unsupported format\n", __func__);
return -EINVAL;
}
uda134x_write(codec, UDA134X_STATUS0, hw_params);
return 0;
}
static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct uda134x_priv *uda134x = codec->private_data;
pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
clk_id, freq, dir);
/* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable
because the codec is slave. Of course limitations of the clock
master (the IIS controller) apply.
We'll error out on set_hw_params if it's not OK */
if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
uda134x->sysclk = freq;
return 0;
}
printk(KERN_ERR "%s unsupported sysclk\n", __func__);
return -EINVAL;
}
static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct uda134x_priv *uda134x = codec->private_data;
pr_debug("%s fmt: %08X\n", __func__, fmt);
/* codec supports only full slave mode */
if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
printk(KERN_ERR "%s unsupported slave mode\n", __func__);
return -EINVAL;
}
/* no support for clock inversion */
if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
return -EINVAL;
}
/* We can't setup DAI format here as it depends on the word bit num */
/* so let's just store the value for later */
uda134x->dai_fmt = fmt;
return 0;
}
static int uda134x_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
u8 reg;
struct uda134x_platform_data *pd = codec->control_data;
int i;
u8 *cache = codec->reg_cache;
pr_debug("%s bias level %d\n", __func__, level);
switch (level) {
case SND_SOC_BIAS_ON:
/* ADC, DAC on */
reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
uda134x_write(codec, UDA134X_STATUS1, reg | 0x03);
break;
case SND_SOC_BIAS_PREPARE:
/* power on */
if (pd->power) {
pd->power(1);
/* Sync reg_cache with the hardware */
for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
codec->write(codec, i, *cache++);
}
break;
case SND_SOC_BIAS_STANDBY:
/* ADC, DAC power off */
reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
uda134x_write(codec, UDA134X_STATUS1, reg & ~(0x03));
break;
case SND_SOC_BIAS_OFF:
/* power off */
if (pd->power)
pd->power(0);
break;
}
codec->bias_level = level;
return 0;
}
static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
"Minimum2", "Maximum"};
static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static const char *uda134x_mixmode[] = {"Differential", "Analog1",
"Analog2", "Both"};
static const struct soc_enum uda134x_mixer_enum[] = {
SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
};
static const struct snd_kcontrol_new uda1341_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),
SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),
SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),
SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),
SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};
static const struct snd_kcontrol_new uda1340_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};
static struct snd_soc_dai_ops uda134x_dai_ops = {
.startup = uda134x_startup,
.shutdown = uda134x_shutdown,
.hw_params = uda134x_hw_params,
.digital_mute = uda134x_mute,
.set_sysclk = uda134x_set_dai_sysclk,
.set_fmt = uda134x_set_dai_fmt,
};
struct snd_soc_dai uda134x_dai = {
.name = "UDA134X",
/* playback capabilities */
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = UDA134X_RATES,
.formats = UDA134X_FORMATS,
},
/* capture capabilities */
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = UDA134X_RATES,
.formats = UDA134X_FORMATS,
},
/* pcm operations */
.ops = &uda134x_dai_ops,
};
EXPORT_SYMBOL(uda134x_dai);
static int uda134x_soc_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
struct uda134x_priv *uda134x;
void *codec_setup_data = socdev->codec_data;
int ret = -ENOMEM;
struct uda134x_platform_data *pd;
printk(KERN_INFO "UDA134X SoC Audio Codec\n");
if (!codec_setup_data) {
printk(KERN_ERR "UDA134X SoC codec: "
"missing L3 bitbang function\n");
return -ENODEV;
}
pd = codec_setup_data;
switch (pd->model) {
case UDA134X_UDA1340:
case UDA134X_UDA1341:
case UDA134X_UDA1344:
break;
default:
printk(KERN_ERR "UDA134X SoC codec: "
"unsupported model %d\n",
pd->model);
return -EINVAL;
}
socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
if (socdev->card->codec == NULL)
return ret;
codec = socdev->card->codec;
uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
if (uda134x == NULL)
goto priv_err;
codec->private_data = uda134x;
codec->reg_cache = kmemdup(uda134x_reg, sizeof(uda134x_reg),
GFP_KERNEL);
if (codec->reg_cache == NULL)
goto reg_err;
mutex_init(&codec->mutex);
codec->reg_cache_size = sizeof(uda134x_reg);
codec->reg_cache_step = 1;
codec->name = "UDA134X";
codec->owner = THIS_MODULE;
codec->dai = &uda134x_dai;
codec->num_dai = 1;
codec->read = uda134x_read_reg_cache;
codec->write = uda134x_write;
#ifdef POWER_OFF_ON_STANDBY
codec->set_bias_level = uda134x_set_bias_level;
#endif
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->control_data = codec_setup_data;
if (pd->power)
pd->power(1);
uda134x_reset(codec);
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
printk(KERN_ERR "UDA134X: failed to register pcms\n");
goto pcm_err;
}
switch (pd->model) {
case UDA134X_UDA1340:
case UDA134X_UDA1344:
ret = snd_soc_add_controls(codec, uda1340_snd_controls,
ARRAY_SIZE(uda1340_snd_controls));
break;
case UDA134X_UDA1341:
ret = snd_soc_add_controls(codec, uda1341_snd_controls,
ARRAY_SIZE(uda1341_snd_controls));
break;
default:
printk(KERN_ERR "%s unkown codec type: %d",
__func__, pd->model);
return -EINVAL;
}
if (ret < 0) {
printk(KERN_ERR "UDA134X: failed to register controls\n");
goto pcm_err;
}
ret = snd_soc_init_card(socdev);
if (ret < 0) {
printk(KERN_ERR "UDA134X: failed to register card\n");
goto card_err;
}
return 0;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
kfree(codec->reg_cache);
reg_err:
kfree(codec->private_data);
priv_err:
kfree(codec);
return ret;
}
/* power down chip */
static int uda134x_soc_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
kfree(codec->private_data);
kfree(codec->reg_cache);
kfree(codec);
return 0;
}
#if defined(CONFIG_PM)
static int uda134x_soc_suspend(struct platform_device *pdev,
pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int uda134x_soc_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
uda134x_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
return 0;
}
#else
#define uda134x_soc_suspend NULL
#define uda134x_soc_resume NULL
#endif /* CONFIG_PM */
struct snd_soc_codec_device soc_codec_dev_uda134x = {
.probe = uda134x_soc_probe,
.remove = uda134x_soc_remove,
.suspend = uda134x_soc_suspend,
.resume = uda134x_soc_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_uda134x);
static int __init uda134x_init(void)
{
return snd_soc_register_dai(&uda134x_dai);
}
module_init(uda134x_init);
static void __exit uda134x_exit(void)
{
snd_soc_unregister_dai(&uda134x_dai);
}
module_exit(uda134x_exit);
MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
MODULE_LICENSE("GPL");

36
kernel/sound/soc/codecs/uda134x.h Normal file
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@@ -0,0 +1,36 @@
#ifndef _UDA134X_CODEC_H
#define _UDA134X_CODEC_H
#define UDA134X_L3ADDR 5
#define UDA134X_DATA0_ADDR ((UDA134X_L3ADDR << 2) | 0)
#define UDA134X_DATA1_ADDR ((UDA134X_L3ADDR << 2) | 1)
#define UDA134X_STATUS_ADDR ((UDA134X_L3ADDR << 2) | 2)
#define UDA134X_EXTADDR_PREFIX 0xC0
#define UDA134X_EXTDATA_PREFIX 0xE0
/* UDA134X registers */
#define UDA134X_EA000 0
#define UDA134X_EA001 1
#define UDA134X_EA010 2
#define UDA134X_EA011 3
#define UDA134X_EA100 4
#define UDA134X_EA101 5
#define UDA134X_EA110 6
#define UDA134X_EA111 7
#define UDA134X_STATUS0 8
#define UDA134X_STATUS1 9
#define UDA134X_DATA000 10
#define UDA134X_DATA001 11
#define UDA134X_DATA010 12
#define UDA134X_DATA1 13
#define UDA134X_REGS_NUM 14
#define STATUS0_DAIFMT_MASK (~(7<<1))
#define STATUS0_SYSCLK_MASK (~(3<<4))
extern struct snd_soc_dai uda134x_dai;
extern struct snd_soc_codec_device soc_codec_dev_uda134x;
#endif

928
kernel/sound/soc/codecs/uda1380.c Normal file
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@@ -0,0 +1,928 @@
/*
* uda1380.c - Philips UDA1380 ALSA SoC audio driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>
*
* Modified by Richard Purdie <richard@openedhand.com> to fit into SoC
* codec model.
*
* Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
* Copyright 2005 Openedhand Ltd.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/workqueue.h>
#include <sound/core.h>
#include <sound/control.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/tlv.h>
#include <sound/uda1380.h>
#include "uda1380.h"
static struct snd_soc_codec *uda1380_codec;
/* codec private data */
struct uda1380_priv {
struct snd_soc_codec codec;
u16 reg_cache[UDA1380_CACHEREGNUM];
unsigned int dac_clk;
struct work_struct work;
};
/*
* uda1380 register cache
*/
static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
0x0502, 0x0000, 0x0000, 0x3f3f,
0x0202, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0xff00, 0x0000, 0x4800,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x8000, 0x0002, 0x0000,
};
static unsigned long uda1380_cache_dirty;
/*
* read uda1380 register cache
*/
static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
unsigned int reg)
{
u16 *cache = codec->reg_cache;
if (reg == UDA1380_RESET)
return 0;
if (reg >= UDA1380_CACHEREGNUM)
return -1;
return cache[reg];
}
/*
* write uda1380 register cache
*/
static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
u16 reg, unsigned int value)
{
u16 *cache = codec->reg_cache;
if (reg >= UDA1380_CACHEREGNUM)
return;
if ((reg >= 0x10) && (cache[reg] != value))
set_bit(reg - 0x10, &uda1380_cache_dirty);
cache[reg] = value;
}
/*
* write to the UDA1380 register space
*/
static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
u8 data[3];
/* data is
* data[0] is register offset
* data[1] is MS byte
* data[2] is LS byte
*/
data[0] = reg;
data[1] = (value & 0xff00) >> 8;
data[2] = value & 0x00ff;
uda1380_write_reg_cache(codec, reg, value);
/* the interpolator & decimator regs must only be written when the
* codec DAI is active.
*/
if (!codec->active && (reg >= UDA1380_MVOL))
return 0;
pr_debug("uda1380: hw write %x val %x\n", reg, value);
if (codec->hw_write(codec->control_data, data, 3) == 3) {
unsigned int val;
i2c_master_send(codec->control_data, data, 1);
i2c_master_recv(codec->control_data, data, 2);
val = (data[0]<<8) | data[1];
if (val != value) {
pr_debug("uda1380: READ BACK VAL %x\n",
(data[0]<<8) | data[1]);
return -EIO;
}
if (reg >= 0x10)
clear_bit(reg - 0x10, &uda1380_cache_dirty);
return 0;
} else
return -EIO;
}
#define uda1380_reset(c) uda1380_write(c, UDA1380_RESET, 0)
static void uda1380_flush_work(struct work_struct *work)
{
int bit, reg;
for_each_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
reg = 0x10 + bit;
pr_debug("uda1380: flush reg %x val %x:\n", reg,
uda1380_read_reg_cache(uda1380_codec, reg));
uda1380_write(uda1380_codec, reg,
uda1380_read_reg_cache(uda1380_codec, reg));
clear_bit(bit, &uda1380_cache_dirty);
}
}
/* declarations of ALSA reg_elem_REAL controls */
static const char *uda1380_deemp[] = {
"None",
"32kHz",
"44.1kHz",
"48kHz",
"96kHz",
};
static const char *uda1380_input_sel[] = {
"Line",
"Mic + Line R",
"Line L",
"Mic",
};
static const char *uda1380_output_sel[] = {
"DAC",
"Analog Mixer",
};
static const char *uda1380_spf_mode[] = {
"Flat",
"Minimum1",
"Minimum2",
"Maximum"
};
static const char *uda1380_capture_sel[] = {
"ADC",
"Digital Mixer"
};
static const char *uda1380_sel_ns[] = {
"3rd-order",
"5th-order"
};
static const char *uda1380_mix_control[] = {
"off",
"PCM only",
"before sound processing",
"after sound processing"
};
static const char *uda1380_sdet_setting[] = {
"3200",
"4800",
"9600",
"19200"
};
static const char *uda1380_os_setting[] = {
"single-speed",
"double-speed (no mixing)",
"quad-speed (no mixing)"
};
static const struct soc_enum uda1380_deemp_enum[] = {
SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, 5, uda1380_deemp),
SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, 5, uda1380_deemp),
};
static const struct soc_enum uda1380_input_sel_enum =
SOC_ENUM_SINGLE(UDA1380_ADC, 2, 4, uda1380_input_sel); /* SEL_MIC, SEL_LNA */
static const struct soc_enum uda1380_output_sel_enum =
SOC_ENUM_SINGLE(UDA1380_PM, 7, 2, uda1380_output_sel); /* R02_EN_AVC */
static const struct soc_enum uda1380_spf_enum =
SOC_ENUM_SINGLE(UDA1380_MODE, 14, 4, uda1380_spf_mode); /* M */
static const struct soc_enum uda1380_capture_sel_enum =
SOC_ENUM_SINGLE(UDA1380_IFACE, 6, 2, uda1380_capture_sel); /* SEL_SOURCE */
static const struct soc_enum uda1380_sel_ns_enum =
SOC_ENUM_SINGLE(UDA1380_MIXER, 14, 2, uda1380_sel_ns); /* SEL_NS */
static const struct soc_enum uda1380_mix_enum =
SOC_ENUM_SINGLE(UDA1380_MIXER, 12, 4, uda1380_mix_control); /* MIX, MIX_POS */
static const struct soc_enum uda1380_sdet_enum =
SOC_ENUM_SINGLE(UDA1380_MIXER, 4, 4, uda1380_sdet_setting); /* SD_VALUE */
static const struct soc_enum uda1380_os_enum =
SOC_ENUM_SINGLE(UDA1380_MIXER, 0, 3, uda1380_os_setting); /* OS */
/*
* from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
*/
static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);
/*
* from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
* from -66 dB in 0.5 dB steps (2 dB steps, really) and
* from -52 dB in 0.25 dB steps
*/
static const unsigned int mvol_tlv[] = {
TLV_DB_RANGE_HEAD(3),
0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0),
};
/*
* from -72 dB in 1.5 dB steps (6 dB steps really),
* from -66 dB in 0.75 dB steps (3 dB steps really),
* from -60 dB in 0.5 dB steps (2 dB steps really) and
* from -46 dB in 0.25 dB steps
*/
static const unsigned int vc_tlv[] = {
TLV_DB_RANGE_HEAD(4),
0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0),
};
/* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);
/* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
* off at 18 dB max) */
static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);
/* from -63 to 24 dB in 0.5 dB steps (-128...48) */
static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);
/* from 0 to 24 dB in 3 dB steps */
static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
/* from 0 to 30 dB in 2 dB steps */
static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);
static const struct snd_kcontrol_new uda1380_snd_controls[] = {
SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */
SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */
SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv), /* VC2 */
SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv), /* VC1 */
SOC_ENUM("Sound Processing Filter", uda1380_spf_enum), /* M */
SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv), /* TRL, TRR */
SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv), /* BBL, BBR */
/**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */
SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */
SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */
SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */
SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */
SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */
SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */
SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */
SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */
SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */
SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */
SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */
/**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */
SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */
SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */
SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0), /* SKIP_DCFIL (before decimator) */
SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0), /* EN_DCFIL (at output of decimator) */
SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0), /* TODO: enum, see table 62 */
SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1), /* AGC_LEVEL */
/* -5.5, -8, -11.5, -14 dBFS */
SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),
};
/* Input mux */
static const struct snd_kcontrol_new uda1380_input_mux_control =
SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);
/* Output mux */
static const struct snd_kcontrol_new uda1380_output_mux_control =
SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);
/* Capture mux */
static const struct snd_kcontrol_new uda1380_capture_mux_control =
SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);
static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {
SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
&uda1380_input_mux_control),
SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,
&uda1380_output_mux_control),
SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
&uda1380_capture_mux_control),
SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),
SND_SOC_DAPM_INPUT("VINM"),
SND_SOC_DAPM_INPUT("VINL"),
SND_SOC_DAPM_INPUT("VINR"),
SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("VOUTLHP"),
SND_SOC_DAPM_OUTPUT("VOUTRHP"),
SND_SOC_DAPM_OUTPUT("VOUTL"),
SND_SOC_DAPM_OUTPUT("VOUTR"),
SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),
SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),
};
static const struct snd_soc_dapm_route audio_map[] = {
/* output mux */
{"HeadPhone Driver", NULL, "Output Mux"},
{"VOUTR", NULL, "Output Mux"},
{"VOUTL", NULL, "Output Mux"},
{"Analog Mixer", NULL, "VINR"},
{"Analog Mixer", NULL, "VINL"},
{"Analog Mixer", NULL, "DAC"},
{"Output Mux", "DAC", "DAC"},
{"Output Mux", "Analog Mixer", "Analog Mixer"},
/* {"DAC", "Digital Mixer", "I2S" } */
/* headphone driver */
{"VOUTLHP", NULL, "HeadPhone Driver"},
{"VOUTRHP", NULL, "HeadPhone Driver"},
/* input mux */
{"Left ADC", NULL, "Input Mux"},
{"Input Mux", "Mic", "Mic LNA"},
{"Input Mux", "Mic + Line R", "Mic LNA"},
{"Input Mux", "Line L", "Left PGA"},
{"Input Mux", "Line", "Left PGA"},
/* right input */
{"Right ADC", "Mic + Line R", "Right PGA"},
{"Right ADC", "Line", "Right PGA"},
/* inputs */
{"Mic LNA", NULL, "VINM"},
{"Left PGA", NULL, "VINL"},
{"Right PGA", NULL, "VINR"},
};
static int uda1380_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, uda1380_dapm_widgets,
ARRAY_SIZE(uda1380_dapm_widgets));
snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
snd_soc_dapm_new_widgets(codec);
return 0;
}
static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
int iface;
/* set up DAI based upon fmt */
iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= R01_SFORI_I2S | R01_SFORO_I2S;
break;
case SND_SOC_DAIFMT_LSB:
iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
break;
case SND_SOC_DAIFMT_MSB:
iface |= R01_SFORI_MSB | R01_SFORO_MSB;
}
/* DATAI is slave only, so in single-link mode, this has to be slave */
if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
return -EINVAL;
uda1380_write(codec, UDA1380_IFACE, iface);
return 0;
}
static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
int iface;
/* set up DAI based upon fmt */
iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
iface &= ~R01_SFORI_MASK;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= R01_SFORI_I2S;
break;
case SND_SOC_DAIFMT_LSB:
iface |= R01_SFORI_LSB16;
break;
case SND_SOC_DAIFMT_MSB:
iface |= R01_SFORI_MSB;
}
/* DATAI is slave only, so this has to be slave */
if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
return -EINVAL;
uda1380_write(codec, UDA1380_IFACE, iface);
return 0;
}
static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
int iface;
/* set up DAI based upon fmt */
iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
iface &= ~(R01_SIM | R01_SFORO_MASK);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= R01_SFORO_I2S;
break;
case SND_SOC_DAIFMT_LSB:
iface |= R01_SFORO_LSB16;
break;
case SND_SOC_DAIFMT_MSB:
iface |= R01_SFORO_MSB;
}
if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
iface |= R01_SIM;
uda1380_write(codec, UDA1380_IFACE, iface);
return 0;
}
static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct uda1380_priv *uda1380 = codec->private_data;
int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
uda1380_write_reg_cache(codec, UDA1380_MIXER,
mixer & ~R14_SILENCE);
schedule_work(&uda1380->work);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
uda1380_write_reg_cache(codec, UDA1380_MIXER,
mixer | R14_SILENCE);
schedule_work(&uda1380->work);
break;
}
return 0;
}
static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
/* set WSPLL power and divider if running from this clock */
if (clk & R00_DAC_CLK) {
int rate = params_rate(params);
u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
clk &= ~0x3; /* clear SEL_LOOP_DIV */
switch (rate) {
case 6250 ... 12500:
clk |= 0x0;
break;
case 12501 ... 25000:
clk |= 0x1;
break;
case 25001 ... 50000:
clk |= 0x2;
break;
case 50001 ... 100000:
clk |= 0x3;
break;
}
uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
clk |= R00_EN_DAC | R00_EN_INT;
else
clk |= R00_EN_ADC | R00_EN_DEC;
uda1380_write(codec, UDA1380_CLK, clk);
return 0;
}
static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
/* shut down WSPLL power if running from this clock */
if (clk & R00_DAC_CLK) {
u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
clk &= ~(R00_EN_DAC | R00_EN_INT);
else
clk &= ~(R00_EN_ADC | R00_EN_DEC);
uda1380_write(codec, UDA1380_CLK, clk);
}
static int uda1380_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
break;
case SND_SOC_BIAS_STANDBY:
uda1380_write(codec, UDA1380_PM, R02_PON_BIAS);
break;
case SND_SOC_BIAS_OFF:
uda1380_write(codec, UDA1380_PM, 0x0);
break;
}
codec->bias_level = level;
return 0;
}
#define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
static struct snd_soc_dai_ops uda1380_dai_ops = {
.hw_params = uda1380_pcm_hw_params,
.shutdown = uda1380_pcm_shutdown,
.trigger = uda1380_trigger,
.set_fmt = uda1380_set_dai_fmt_both,
};
static struct snd_soc_dai_ops uda1380_dai_ops_playback = {
.hw_params = uda1380_pcm_hw_params,
.shutdown = uda1380_pcm_shutdown,
.trigger = uda1380_trigger,
.set_fmt = uda1380_set_dai_fmt_playback,
};
static struct snd_soc_dai_ops uda1380_dai_ops_capture = {
.hw_params = uda1380_pcm_hw_params,
.shutdown = uda1380_pcm_shutdown,
.trigger = uda1380_trigger,
.set_fmt = uda1380_set_dai_fmt_capture,
};
struct snd_soc_dai uda1380_dai[] = {
{
.name = "UDA1380",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = UDA1380_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = UDA1380_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
.ops = &uda1380_dai_ops,
},
{ /* playback only - dual interface */
.name = "UDA1380",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = UDA1380_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &uda1380_dai_ops_playback,
},
{ /* capture only - dual interface*/
.name = "UDA1380",
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = UDA1380_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &uda1380_dai_ops_capture,
},
};
EXPORT_SYMBOL_GPL(uda1380_dai);
static int uda1380_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int uda1380_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
int i;
u8 data[2];
u16 *cache = codec->reg_cache;
/* Sync reg_cache with the hardware */
for (i = 0; i < ARRAY_SIZE(uda1380_reg); i++) {
data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
data[1] = cache[i] & 0x00ff;
codec->hw_write(codec->control_data, data, 2);
}
uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
uda1380_set_bias_level(codec, codec->suspend_bias_level);
return 0;
}
static int uda1380_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
struct uda1380_platform_data *pdata;
int ret = 0;
if (uda1380_codec == NULL) {
dev_err(&pdev->dev, "Codec device not registered\n");
return -ENODEV;
}
socdev->card->codec = uda1380_codec;
codec = uda1380_codec;
pdata = codec->dev->platform_data;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms: %d\n", ret);
goto pcm_err;
}
/* power on device */
uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
/* set clock input */
switch (pdata->dac_clk) {
case UDA1380_DAC_CLK_SYSCLK:
uda1380_write(codec, UDA1380_CLK, 0);
break;
case UDA1380_DAC_CLK_WSPLL:
uda1380_write(codec, UDA1380_CLK, R00_DAC_CLK);
break;
}
snd_soc_add_controls(codec, uda1380_snd_controls,
ARRAY_SIZE(uda1380_snd_controls));
uda1380_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(codec->dev, "failed to register card: %d\n", ret);
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
return ret;
}
/* power down chip */
static int uda1380_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
if (codec->control_data)
uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_uda1380 = {
.probe = uda1380_probe,
.remove = uda1380_remove,
.suspend = uda1380_suspend,
.resume = uda1380_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_uda1380);
static int uda1380_register(struct uda1380_priv *uda1380)
{
int ret, i;
struct snd_soc_codec *codec = &uda1380->codec;
struct uda1380_platform_data *pdata = codec->dev->platform_data;
if (uda1380_codec) {
dev_err(codec->dev, "Another UDA1380 is registered\n");
return -EINVAL;
}
if (!pdata || !pdata->gpio_power || !pdata->gpio_reset)
return -EINVAL;
ret = gpio_request(pdata->gpio_power, "uda1380 power");
if (ret)
goto err_out;
ret = gpio_request(pdata->gpio_reset, "uda1380 reset");
if (ret)
goto err_gpio;
gpio_direction_output(pdata->gpio_power, 1);
/* we may need to have the clock running here - pH5 */
gpio_direction_output(pdata->gpio_reset, 1);
udelay(5);
gpio_set_value(pdata->gpio_reset, 0);
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->private_data = uda1380;
codec->name = "UDA1380";
codec->owner = THIS_MODULE;
codec->read = uda1380_read_reg_cache;
codec->write = uda1380_write;
codec->bias_level = SND_SOC_BIAS_OFF;
codec->set_bias_level = uda1380_set_bias_level;
codec->dai = uda1380_dai;
codec->num_dai = ARRAY_SIZE(uda1380_dai);
codec->reg_cache_size = ARRAY_SIZE(uda1380_reg);
codec->reg_cache = &uda1380->reg_cache;
codec->reg_cache_step = 1;
memcpy(codec->reg_cache, uda1380_reg, sizeof(uda1380_reg));
ret = uda1380_reset(codec);
if (ret < 0) {
dev_err(codec->dev, "Failed to issue reset\n");
goto err_reset;
}
INIT_WORK(&uda1380->work, uda1380_flush_work);
for (i = 0; i < ARRAY_SIZE(uda1380_dai); i++)
uda1380_dai[i].dev = codec->dev;
uda1380_codec = codec;
ret = snd_soc_register_codec(codec);
if (ret != 0) {
dev_err(codec->dev, "Failed to register codec: %d\n", ret);
goto err_reset;
}
ret = snd_soc_register_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai));
if (ret != 0) {
dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
goto err_dai;
}
return 0;
err_dai:
snd_soc_unregister_codec(codec);
err_reset:
gpio_set_value(pdata->gpio_power, 0);
gpio_free(pdata->gpio_reset);
err_gpio:
gpio_free(pdata->gpio_power);
err_out:
return ret;
}
static void uda1380_unregister(struct uda1380_priv *uda1380)
{
struct snd_soc_codec *codec = &uda1380->codec;
struct uda1380_platform_data *pdata = codec->dev->platform_data;
snd_soc_unregister_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai));
snd_soc_unregister_codec(&uda1380->codec);
gpio_set_value(pdata->gpio_power, 0);
gpio_free(pdata->gpio_reset);
gpio_free(pdata->gpio_power);
kfree(uda1380);
uda1380_codec = NULL;
}
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
static __devinit int uda1380_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct uda1380_priv *uda1380;
struct snd_soc_codec *codec;
int ret;
uda1380 = kzalloc(sizeof(struct uda1380_priv), GFP_KERNEL);
if (uda1380 == NULL)
return -ENOMEM;
codec = &uda1380->codec;
codec->hw_write = (hw_write_t)i2c_master_send;
i2c_set_clientdata(i2c, uda1380);
codec->control_data = i2c;
codec->dev = &i2c->dev;
ret = uda1380_register(uda1380);
if (ret != 0)
kfree(uda1380);
return ret;
}
static int __devexit uda1380_i2c_remove(struct i2c_client *i2c)
{
struct uda1380_priv *uda1380 = i2c_get_clientdata(i2c);
uda1380_unregister(uda1380);
return 0;
}
static const struct i2c_device_id uda1380_i2c_id[] = {
{ "uda1380", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
static struct i2c_driver uda1380_i2c_driver = {
.driver = {
.name = "UDA1380 I2C Codec",
.owner = THIS_MODULE,
},
.probe = uda1380_i2c_probe,
.remove = __devexit_p(uda1380_i2c_remove),
.id_table = uda1380_i2c_id,
};
#endif
static int __init uda1380_modinit(void)
{
int ret;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
ret = i2c_add_driver(&uda1380_i2c_driver);
if (ret != 0)
pr_err("Failed to register UDA1380 I2C driver: %d\n", ret);
#endif
return 0;
}
module_init(uda1380_modinit);
static void __exit uda1380_exit(void)
{
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
i2c_del_driver(&uda1380_i2c_driver);
#endif
}
module_exit(uda1380_exit);
MODULE_AUTHOR("Giorgio Padrin");
MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
MODULE_LICENSE("GPL");

82
kernel/sound/soc/codecs/uda1380.h Normal file
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/*
* Audio support for Philips UDA1380
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
*/
#ifndef _UDA1380_H
#define _UDA1380_H
#define UDA1380_CLK 0x00
#define UDA1380_IFACE 0x01
#define UDA1380_PM 0x02
#define UDA1380_AMIX 0x03
#define UDA1380_HP 0x04
#define UDA1380_MVOL 0x10
#define UDA1380_MIXVOL 0x11
#define UDA1380_MODE 0x12
#define UDA1380_DEEMP 0x13
#define UDA1380_MIXER 0x14
#define UDA1380_INTSTAT 0x18
#define UDA1380_DEC 0x20
#define UDA1380_PGA 0x21
#define UDA1380_ADC 0x22
#define UDA1380_AGC 0x23
#define UDA1380_DECSTAT 0x28
#define UDA1380_RESET 0x7f
#define UDA1380_CACHEREGNUM 0x24
/* Register flags */
#define R00_EN_ADC 0x0800
#define R00_EN_DEC 0x0400
#define R00_EN_DAC 0x0200
#define R00_EN_INT 0x0100
#define R00_DAC_CLK 0x0010
#define R01_SFORI_I2S 0x0000
#define R01_SFORI_LSB16 0x0100
#define R01_SFORI_LSB18 0x0200
#define R01_SFORI_LSB20 0x0300
#define R01_SFORI_MSB 0x0500
#define R01_SFORI_MASK 0x0700
#define R01_SFORO_I2S 0x0000
#define R01_SFORO_LSB16 0x0001
#define R01_SFORO_LSB18 0x0002
#define R01_SFORO_LSB20 0x0003
#define R01_SFORO_LSB24 0x0004
#define R01_SFORO_MSB 0x0005
#define R01_SFORO_MASK 0x0007
#define R01_SEL_SOURCE 0x0040
#define R01_SIM 0x0010
#define R02_PON_PLL 0x8000
#define R02_PON_HP 0x2000
#define R02_PON_DAC 0x0400
#define R02_PON_BIAS 0x0100
#define R02_EN_AVC 0x0080
#define R02_PON_AVC 0x0040
#define R02_PON_LNA 0x0010
#define R02_PON_PGAL 0x0008
#define R02_PON_ADCL 0x0004
#define R02_PON_PGAR 0x0002
#define R02_PON_ADCR 0x0001
#define R13_MTM 0x4000
#define R14_SILENCE 0x0080
#define R14_SDET_ON 0x0040
#define R21_MT_ADC 0x8000
#define R22_SEL_LNA 0x0008
#define R22_SEL_MIC 0x0004
#define R22_SKIP_DCFIL 0x0002
#define R23_AGC_EN 0x0001
#define UDA1380_DAI_DUPLEX 0 /* playback and capture on single DAI */
#define UDA1380_DAI_PLAYBACK 1 /* playback DAI */
#define UDA1380_DAI_CAPTURE 2 /* capture DAI */
extern struct snd_soc_dai uda1380_dai[3];
extern struct snd_soc_codec_device soc_codec_dev_uda1380;
#endif /* _UDA1380_H */

1724
kernel/sound/soc/codecs/wm8350.c Normal file
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29
kernel/sound/soc/codecs/wm8350.h Normal file
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/*
* wm8350.h - WM8903 audio codec interface
*
* Copyright 2008 Wolfson Microelectronics PLC.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _WM8350_H
#define _WM8350_H
#include <sound/soc.h>
#include <linux/mfd/wm8350/audio.h>
extern struct snd_soc_dai wm8350_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8350;
enum wm8350_jack {
WM8350_JDL = 1,
WM8350_JDR = 2,
};
int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
struct snd_soc_jack *jack, int report);
#endif

1604
kernel/sound/soc/codecs/wm8400.c Normal file
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62
kernel/sound/soc/codecs/wm8400.h Normal file
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/*
* wm8400.h -- audio driver for WM8400
*
* Copyright 2008 Wolfson Microelectronics PLC.
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef _WM8400_CODEC_H
#define _WM8400_CODEC_H
#define WM8400_MCLK_DIV 0
#define WM8400_DACCLK_DIV 1
#define WM8400_ADCCLK_DIV 2
#define WM8400_BCLK_DIV 3
#define WM8400_MCLK_DIV_1 0x400
#define WM8400_MCLK_DIV_2 0x800
#define WM8400_DAC_CLKDIV_1 0x00
#define WM8400_DAC_CLKDIV_1_5 0x04
#define WM8400_DAC_CLKDIV_2 0x08
#define WM8400_DAC_CLKDIV_3 0x0c
#define WM8400_DAC_CLKDIV_4 0x10
#define WM8400_DAC_CLKDIV_5_5 0x14
#define WM8400_DAC_CLKDIV_6 0x18
#define WM8400_ADC_CLKDIV_1 0x00
#define WM8400_ADC_CLKDIV_1_5 0x20
#define WM8400_ADC_CLKDIV_2 0x40
#define WM8400_ADC_CLKDIV_3 0x60
#define WM8400_ADC_CLKDIV_4 0x80
#define WM8400_ADC_CLKDIV_5_5 0xa0
#define WM8400_ADC_CLKDIV_6 0xc0
#define WM8400_BCLK_DIV_1 (0x0 << 1)
#define WM8400_BCLK_DIV_1_5 (0x1 << 1)
#define WM8400_BCLK_DIV_2 (0x2 << 1)
#define WM8400_BCLK_DIV_3 (0x3 << 1)
#define WM8400_BCLK_DIV_4 (0x4 << 1)
#define WM8400_BCLK_DIV_5_5 (0x5 << 1)
#define WM8400_BCLK_DIV_6 (0x6 << 1)
#define WM8400_BCLK_DIV_8 (0x7 << 1)
#define WM8400_BCLK_DIV_11 (0x8 << 1)
#define WM8400_BCLK_DIV_12 (0x9 << 1)
#define WM8400_BCLK_DIV_16 (0xA << 1)
#define WM8400_BCLK_DIV_22 (0xB << 1)
#define WM8400_BCLK_DIV_24 (0xC << 1)
#define WM8400_BCLK_DIV_32 (0xD << 1)
#define WM8400_BCLK_DIV_44 (0xE << 1)
#define WM8400_BCLK_DIV_48 (0xF << 1)
extern struct snd_soc_dai wm8400_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8400;
#endif

826
kernel/sound/soc/codecs/wm8510.c Normal file
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/*
* wm8510.c -- WM8510 ALSA Soc Audio driver
*
* Copyright 2006 Wolfson Microelectronics PLC.
*
* Author: Liam Girdwood <lrg@slimlogic.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include "wm8510.h"
#define WM8510_VERSION "0.6"
struct snd_soc_codec_device soc_codec_dev_wm8510;
/*
* wm8510 register cache
* We can't read the WM8510 register space when we are
* using 2 wire for device control, so we cache them instead.
*/
static const u16 wm8510_reg[WM8510_CACHEREGNUM] = {
0x0000, 0x0000, 0x0000, 0x0000,
0x0050, 0x0000, 0x0140, 0x0000,
0x0000, 0x0000, 0x0000, 0x00ff,
0x0000, 0x0000, 0x0100, 0x00ff,
0x0000, 0x0000, 0x012c, 0x002c,
0x002c, 0x002c, 0x002c, 0x0000,
0x0032, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0038, 0x000b, 0x0032, 0x0000,
0x0008, 0x000c, 0x0093, 0x00e9,
0x0000, 0x0000, 0x0000, 0x0000,
0x0003, 0x0010, 0x0000, 0x0000,
0x0000, 0x0002, 0x0001, 0x0000,
0x0000, 0x0000, 0x0039, 0x0000,
0x0001,
};
#define WM8510_POWER1_BIASEN 0x08
#define WM8510_POWER1_BUFIOEN 0x10
#define wm8510_reset(c) snd_soc_write(c, WM8510_RESET, 0)
static const char *wm8510_companding[] = { "Off", "NC", "u-law", "A-law" };
static const char *wm8510_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
static const char *wm8510_alc[] = { "ALC", "Limiter" };
static const struct soc_enum wm8510_enum[] = {
SOC_ENUM_SINGLE(WM8510_COMP, 1, 4, wm8510_companding), /* adc */
SOC_ENUM_SINGLE(WM8510_COMP, 3, 4, wm8510_companding), /* dac */
SOC_ENUM_SINGLE(WM8510_DAC, 4, 4, wm8510_deemp),
SOC_ENUM_SINGLE(WM8510_ALC3, 8, 2, wm8510_alc),
};
static const struct snd_kcontrol_new wm8510_snd_controls[] = {
SOC_SINGLE("Digital Loopback Switch", WM8510_COMP, 0, 1, 0),
SOC_ENUM("DAC Companding", wm8510_enum[1]),
SOC_ENUM("ADC Companding", wm8510_enum[0]),
SOC_ENUM("Playback De-emphasis", wm8510_enum[2]),
SOC_SINGLE("DAC Inversion Switch", WM8510_DAC, 0, 1, 0),
SOC_SINGLE("Master Playback Volume", WM8510_DACVOL, 0, 127, 0),
SOC_SINGLE("High Pass Filter Switch", WM8510_ADC, 8, 1, 0),
SOC_SINGLE("High Pass Cut Off", WM8510_ADC, 4, 7, 0),
SOC_SINGLE("ADC Inversion Switch", WM8510_COMP, 0, 1, 0),
SOC_SINGLE("Capture Volume", WM8510_ADCVOL, 0, 127, 0),
SOC_SINGLE("DAC Playback Limiter Switch", WM8510_DACLIM1, 8, 1, 0),
SOC_SINGLE("DAC Playback Limiter Decay", WM8510_DACLIM1, 4, 15, 0),
SOC_SINGLE("DAC Playback Limiter Attack", WM8510_DACLIM1, 0, 15, 0),
SOC_SINGLE("DAC Playback Limiter Threshold", WM8510_DACLIM2, 4, 7, 0),
SOC_SINGLE("DAC Playback Limiter Boost", WM8510_DACLIM2, 0, 15, 0),
SOC_SINGLE("ALC Enable Switch", WM8510_ALC1, 8, 1, 0),
SOC_SINGLE("ALC Capture Max Gain", WM8510_ALC1, 3, 7, 0),
SOC_SINGLE("ALC Capture Min Gain", WM8510_ALC1, 0, 7, 0),
SOC_SINGLE("ALC Capture ZC Switch", WM8510_ALC2, 8, 1, 0),
SOC_SINGLE("ALC Capture Hold", WM8510_ALC2, 4, 7, 0),
SOC_SINGLE("ALC Capture Target", WM8510_ALC2, 0, 15, 0),
SOC_ENUM("ALC Capture Mode", wm8510_enum[3]),
SOC_SINGLE("ALC Capture Decay", WM8510_ALC3, 4, 15, 0),
SOC_SINGLE("ALC Capture Attack", WM8510_ALC3, 0, 15, 0),
SOC_SINGLE("ALC Capture Noise Gate Switch", WM8510_NGATE, 3, 1, 0),
SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8510_NGATE, 0, 7, 0),
SOC_SINGLE("Capture PGA ZC Switch", WM8510_INPPGA, 7, 1, 0),
SOC_SINGLE("Capture PGA Volume", WM8510_INPPGA, 0, 63, 0),
SOC_SINGLE("Speaker Playback ZC Switch", WM8510_SPKVOL, 7, 1, 0),
SOC_SINGLE("Speaker Playback Switch", WM8510_SPKVOL, 6, 1, 1),
SOC_SINGLE("Speaker Playback Volume", WM8510_SPKVOL, 0, 63, 0),
SOC_SINGLE("Speaker Boost", WM8510_OUTPUT, 2, 1, 0),
SOC_SINGLE("Capture Boost(+20dB)", WM8510_ADCBOOST, 8, 1, 0),
SOC_SINGLE("Mono Playback Switch", WM8510_MONOMIX, 6, 1, 1),
};
/* Speaker Output Mixer */
static const struct snd_kcontrol_new wm8510_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8510_SPKMIX, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8510_SPKMIX, 5, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8510_SPKMIX, 0, 1, 0),
};
/* Mono Output Mixer */
static const struct snd_kcontrol_new wm8510_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8510_MONOMIX, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8510_MONOMIX, 2, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8510_MONOMIX, 0, 1, 0),
};
static const struct snd_kcontrol_new wm8510_boost_controls[] = {
SOC_DAPM_SINGLE("Mic PGA Switch", WM8510_INPPGA, 6, 1, 1),
SOC_DAPM_SINGLE("Aux Volume", WM8510_ADCBOOST, 0, 7, 0),
SOC_DAPM_SINGLE("Mic Volume", WM8510_ADCBOOST, 4, 7, 0),
};
static const struct snd_kcontrol_new wm8510_micpga_controls[] = {
SOC_DAPM_SINGLE("MICP Switch", WM8510_INPUT, 0, 1, 0),
SOC_DAPM_SINGLE("MICN Switch", WM8510_INPUT, 1, 1, 0),
SOC_DAPM_SINGLE("AUX Switch", WM8510_INPUT, 2, 1, 0),
};
static const struct snd_soc_dapm_widget wm8510_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Speaker Mixer", WM8510_POWER3, 2, 0,
&wm8510_speaker_mixer_controls[0],
ARRAY_SIZE(wm8510_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", WM8510_POWER3, 3, 0,
&wm8510_mono_mixer_controls[0],
ARRAY_SIZE(wm8510_mono_mixer_controls)),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8510_POWER3, 0, 0),
SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8510_POWER2, 0, 0),
SND_SOC_DAPM_PGA("Aux Input", WM8510_POWER1, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("SpkN Out", WM8510_POWER3, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("SpkP Out", WM8510_POWER3, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out", WM8510_POWER3, 7, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mic PGA", WM8510_POWER2, 2, 0,
&wm8510_micpga_controls[0],
ARRAY_SIZE(wm8510_micpga_controls)),
SND_SOC_DAPM_MIXER("Boost Mixer", WM8510_POWER2, 4, 0,
&wm8510_boost_controls[0],
ARRAY_SIZE(wm8510_boost_controls)),
SND_SOC_DAPM_MICBIAS("Mic Bias", WM8510_POWER1, 4, 0),
SND_SOC_DAPM_INPUT("MICN"),
SND_SOC_DAPM_INPUT("MICP"),
SND_SOC_DAPM_INPUT("AUX"),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_OUTPUT("SPKOUTP"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
};
static const struct snd_soc_dapm_route audio_map[] = {
/* Mono output mixer */
{"Mono Mixer", "PCM Playback Switch", "DAC"},
{"Mono Mixer", "Aux Playback Switch", "Aux Input"},
{"Mono Mixer", "Line Bypass Switch", "Boost Mixer"},
/* Speaker output mixer */
{"Speaker Mixer", "PCM Playback Switch", "DAC"},
{"Speaker Mixer", "Aux Playback Switch", "Aux Input"},
{"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"},
/* Outputs */
{"Mono Out", NULL, "Mono Mixer"},
{"MONOOUT", NULL, "Mono Out"},
{"SpkN Out", NULL, "Speaker Mixer"},
{"SpkP Out", NULL, "Speaker Mixer"},
{"SPKOUTN", NULL, "SpkN Out"},
{"SPKOUTP", NULL, "SpkP Out"},
/* Microphone PGA */
{"Mic PGA", "MICN Switch", "MICN"},
{"Mic PGA", "MICP Switch", "MICP"},
{ "Mic PGA", "AUX Switch", "Aux Input" },
/* Boost Mixer */
{"Boost Mixer", "Mic PGA Switch", "Mic PGA"},
{"Boost Mixer", "Mic Volume", "MICP"},
{"Boost Mixer", "Aux Volume", "Aux Input"},
{"ADC", NULL, "Boost Mixer"},
};
static int wm8510_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, wm8510_dapm_widgets,
ARRAY_SIZE(wm8510_dapm_widgets));
snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
snd_soc_dapm_new_widgets(codec);
return 0;
}
struct pll_ {
unsigned int pre_div:4; /* prescale - 1 */
unsigned int n:4;
unsigned int k;
};
static struct pll_ pll_div;
/* The size in bits of the pll divide multiplied by 10
* to allow rounding later */
#define FIXED_PLL_SIZE ((1 << 24) * 10)
static void pll_factors(unsigned int target, unsigned int source)
{
unsigned long long Kpart;
unsigned int K, Ndiv, Nmod;
Ndiv = target / source;
if (Ndiv < 6) {
source >>= 1;
pll_div.pre_div = 1;
Ndiv = target / source;
} else
pll_div.pre_div = 0;
if ((Ndiv < 6) || (Ndiv > 12))
printk(KERN_WARNING
"WM8510 N value %u outwith recommended range!d\n",
Ndiv);
pll_div.n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (long long)Nmod;
do_div(Kpart, source);
K = Kpart & 0xFFFFFFFF;
/* Check if we need to round */
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
K /= 10;
pll_div.k = K;
}
static int wm8510_set_dai_pll(struct snd_soc_dai *codec_dai,
int pll_id, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 reg;
if (freq_in == 0 || freq_out == 0) {
/* Clock CODEC directly from MCLK */
reg = snd_soc_read(codec, WM8510_CLOCK);
snd_soc_write(codec, WM8510_CLOCK, reg & 0x0ff);
/* Turn off PLL */
reg = snd_soc_read(codec, WM8510_POWER1);
snd_soc_write(codec, WM8510_POWER1, reg & 0x1df);
return 0;
}
pll_factors(freq_out*4, freq_in);
snd_soc_write(codec, WM8510_PLLN, (pll_div.pre_div << 4) | pll_div.n);
snd_soc_write(codec, WM8510_PLLK1, pll_div.k >> 18);
snd_soc_write(codec, WM8510_PLLK2, (pll_div.k >> 9) & 0x1ff);
snd_soc_write(codec, WM8510_PLLK3, pll_div.k & 0x1ff);
reg = snd_soc_read(codec, WM8510_POWER1);
snd_soc_write(codec, WM8510_POWER1, reg | 0x020);
/* Run CODEC from PLL instead of MCLK */
reg = snd_soc_read(codec, WM8510_CLOCK);
snd_soc_write(codec, WM8510_CLOCK, reg | 0x100);
return 0;
}
/*
* Configure WM8510 clock dividers.
*/
static int wm8510_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 reg;
switch (div_id) {
case WM8510_OPCLKDIV:
reg = snd_soc_read(codec, WM8510_GPIO) & 0x1cf;
snd_soc_write(codec, WM8510_GPIO, reg | div);
break;
case WM8510_MCLKDIV:
reg = snd_soc_read(codec, WM8510_CLOCK) & 0x11f;
snd_soc_write(codec, WM8510_CLOCK, reg | div);
break;
case WM8510_ADCCLK:
reg = snd_soc_read(codec, WM8510_ADC) & 0x1f7;
snd_soc_write(codec, WM8510_ADC, reg | div);
break;
case WM8510_DACCLK:
reg = snd_soc_read(codec, WM8510_DAC) & 0x1f7;
snd_soc_write(codec, WM8510_DAC, reg | div);
break;
case WM8510_BCLKDIV:
reg = snd_soc_read(codec, WM8510_CLOCK) & 0x1e3;
snd_soc_write(codec, WM8510_CLOCK, reg | div);
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8510_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 iface = 0;
u16 clk = snd_soc_read(codec, WM8510_CLOCK) & 0x1fe;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
clk |= 0x0001;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0010;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0008;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x00018;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0180;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0100;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0080;
break;
default:
return -EINVAL;
}
snd_soc_write(codec, WM8510_IFACE, iface);
snd_soc_write(codec, WM8510_CLOCK, clk);
return 0;
}
static int wm8510_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
u16 iface = snd_soc_read(codec, WM8510_IFACE) & 0x19f;
u16 adn = snd_soc_read(codec, WM8510_ADD) & 0x1f1;
/* bit size */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
iface |= 0x0020;
break;
case SNDRV_PCM_FORMAT_S24_LE:
iface |= 0x0040;
break;
case SNDRV_PCM_FORMAT_S32_LE:
iface |= 0x0060;
break;
}
/* filter coefficient */
switch (params_rate(params)) {
case 8000:
adn |= 0x5 << 1;
break;
case 11025:
adn |= 0x4 << 1;
break;
case 16000:
adn |= 0x3 << 1;
break;
case 22050:
adn |= 0x2 << 1;
break;
case 32000:
adn |= 0x1 << 1;
break;
case 44100:
case 48000:
break;
}
snd_soc_write(codec, WM8510_IFACE, iface);
snd_soc_write(codec, WM8510_ADD, adn);
return 0;
}
static int wm8510_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
u16 mute_reg = snd_soc_read(codec, WM8510_DAC) & 0xffbf;
if (mute)
snd_soc_write(codec, WM8510_DAC, mute_reg | 0x40);
else
snd_soc_write(codec, WM8510_DAC, mute_reg);
return 0;
}
/* liam need to make this lower power with dapm */
static int wm8510_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
u16 power1 = snd_soc_read(codec, WM8510_POWER1) & ~0x3;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
power1 |= 0x1; /* VMID 50k */
snd_soc_write(codec, WM8510_POWER1, power1);
break;
case SND_SOC_BIAS_STANDBY:
power1 |= WM8510_POWER1_BIASEN | WM8510_POWER1_BUFIOEN;
if (codec->bias_level == SND_SOC_BIAS_OFF) {
/* Initial cap charge at VMID 5k */
snd_soc_write(codec, WM8510_POWER1, power1 | 0x3);
mdelay(100);
}
power1 |= 0x2; /* VMID 500k */
snd_soc_write(codec, WM8510_POWER1, power1);
break;
case SND_SOC_BIAS_OFF:
snd_soc_write(codec, WM8510_POWER1, 0);
snd_soc_write(codec, WM8510_POWER2, 0);
snd_soc_write(codec, WM8510_POWER3, 0);
break;
}
codec->bias_level = level;
return 0;
}
#define WM8510_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define WM8510_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_ops wm8510_dai_ops = {
.hw_params = wm8510_pcm_hw_params,
.digital_mute = wm8510_mute,
.set_fmt = wm8510_set_dai_fmt,
.set_clkdiv = wm8510_set_dai_clkdiv,
.set_pll = wm8510_set_dai_pll,
};
struct snd_soc_dai wm8510_dai = {
.name = "WM8510 HiFi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM8510_RATES,
.formats = WM8510_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = WM8510_RATES,
.formats = WM8510_FORMATS,},
.ops = &wm8510_dai_ops,
.symmetric_rates = 1,
};
EXPORT_SYMBOL_GPL(wm8510_dai);
static int wm8510_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
wm8510_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int wm8510_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
int i;
u8 data[2];
u16 *cache = codec->reg_cache;
/* Sync reg_cache with the hardware */
for (i = 0; i < ARRAY_SIZE(wm8510_reg); i++) {
data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
data[1] = cache[i] & 0x00ff;
codec->hw_write(codec->control_data, data, 2);
}
wm8510_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
wm8510_set_bias_level(codec, codec->suspend_bias_level);
return 0;
}
/*
* initialise the WM8510 driver
* register the mixer and dsp interfaces with the kernel
*/
static int wm8510_init(struct snd_soc_device *socdev,
enum snd_soc_control_type control)
{
struct snd_soc_codec *codec = socdev->card->codec;
int ret = 0;
codec->name = "WM8510";
codec->owner = THIS_MODULE;
codec->set_bias_level = wm8510_set_bias_level;
codec->dai = &wm8510_dai;
codec->num_dai = 1;
codec->reg_cache_size = ARRAY_SIZE(wm8510_reg);
codec->reg_cache = kmemdup(wm8510_reg, sizeof(wm8510_reg), GFP_KERNEL);
if (codec->reg_cache == NULL)
return -ENOMEM;
ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
if (ret < 0) {
printk(KERN_ERR "wm8510: failed to set cache I/O: %d\n",
ret);
goto err;
}
wm8510_reset(codec);
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
printk(KERN_ERR "wm8510: failed to create pcms\n");
goto err;
}
/* power on device */
codec->bias_level = SND_SOC_BIAS_OFF;
wm8510_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
snd_soc_add_controls(codec, wm8510_snd_controls,
ARRAY_SIZE(wm8510_snd_controls));
wm8510_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
printk(KERN_ERR "wm8510: failed to register card\n");
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
err:
kfree(codec->reg_cache);
return ret;
}
static struct snd_soc_device *wm8510_socdev;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
/*
* WM8510 2 wire address is 0x1a
*/
static int wm8510_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct snd_soc_device *socdev = wm8510_socdev;
struct snd_soc_codec *codec = socdev->card->codec;
int ret;
i2c_set_clientdata(i2c, codec);
codec->control_data = i2c;
ret = wm8510_init(socdev, SND_SOC_I2C);
if (ret < 0)
pr_err("failed to initialise WM8510\n");
return ret;
}
static int wm8510_i2c_remove(struct i2c_client *client)
{
struct snd_soc_codec *codec = i2c_get_clientdata(client);
kfree(codec->reg_cache);
return 0;
}
static const struct i2c_device_id wm8510_i2c_id[] = {
{ "wm8510", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8510_i2c_id);
static struct i2c_driver wm8510_i2c_driver = {
.driver = {
.name = "WM8510 I2C Codec",
.owner = THIS_MODULE,
},
.probe = wm8510_i2c_probe,
.remove = wm8510_i2c_remove,
.id_table = wm8510_i2c_id,
};
static int wm8510_add_i2c_device(struct platform_device *pdev,
const struct wm8510_setup_data *setup)
{
struct i2c_board_info info;
struct i2c_adapter *adapter;
struct i2c_client *client;
int ret;
ret = i2c_add_driver(&wm8510_i2c_driver);
if (ret != 0) {
dev_err(&pdev->dev, "can't add i2c driver\n");
return ret;
}
memset(&info, 0, sizeof(struct i2c_board_info));
info.addr = setup->i2c_address;
strlcpy(info.type, "wm8510", I2C_NAME_SIZE);
adapter = i2c_get_adapter(setup->i2c_bus);
if (!adapter) {
dev_err(&pdev->dev, "can't get i2c adapter %d\n",
setup->i2c_bus);
goto err_driver;
}
client = i2c_new_device(adapter, &info);
i2c_put_adapter(adapter);
if (!client) {
dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
(unsigned int)info.addr);
goto err_driver;
}
return 0;
err_driver:
i2c_del_driver(&wm8510_i2c_driver);
return -ENODEV;
}
#endif
#if defined(CONFIG_SPI_MASTER)
static int __devinit wm8510_spi_probe(struct spi_device *spi)
{
struct snd_soc_device *socdev = wm8510_socdev;
struct snd_soc_codec *codec = socdev->card->codec;
int ret;
codec->control_data = spi;
ret = wm8510_init(socdev, SND_SOC_SPI);
if (ret < 0)
dev_err(&spi->dev, "failed to initialise WM8510\n");
return ret;
}
static int __devexit wm8510_spi_remove(struct spi_device *spi)
{
return 0;
}
static struct spi_driver wm8510_spi_driver = {
.driver = {
.name = "wm8510",
.bus = &spi_bus_type,
.owner = THIS_MODULE,
},
.probe = wm8510_spi_probe,
.remove = __devexit_p(wm8510_spi_remove),
};
#endif /* CONFIG_SPI_MASTER */
static int wm8510_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct wm8510_setup_data *setup;
struct snd_soc_codec *codec;
int ret = 0;
pr_info("WM8510 Audio Codec %s", WM8510_VERSION);
setup = socdev->codec_data;
codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
if (codec == NULL)
return -ENOMEM;
socdev->card->codec = codec;
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
wm8510_socdev = socdev;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
if (setup->i2c_address) {
ret = wm8510_add_i2c_device(pdev, setup);
}
#endif
#if defined(CONFIG_SPI_MASTER)
if (setup->spi) {
ret = spi_register_driver(&wm8510_spi_driver);
if (ret != 0)
printk(KERN_ERR "can't add spi driver");
}
#endif
if (ret != 0)
kfree(codec);
return ret;
}
/* power down chip */
static int wm8510_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
if (codec->control_data)
wm8510_set_bias_level(codec, SND_SOC_BIAS_OFF);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
i2c_unregister_device(codec->control_data);
i2c_del_driver(&wm8510_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8510_spi_driver);
#endif
kfree(codec);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_wm8510 = {
.probe = wm8510_probe,
.remove = wm8510_remove,
.suspend = wm8510_suspend,
.resume = wm8510_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm8510);
static int __init wm8510_modinit(void)
{
return snd_soc_register_dai(&wm8510_dai);
}
module_init(wm8510_modinit);
static void __exit wm8510_exit(void)
{
snd_soc_unregister_dai(&wm8510_dai);
}
module_exit(wm8510_exit);
MODULE_DESCRIPTION("ASoC WM8510 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");

105
kernel/sound/soc/codecs/wm8510.h Normal file
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@@ -0,0 +1,105 @@
/*
* wm8510.h -- WM8510 Soc Audio driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM8510_H
#define _WM8510_H
/* WM8510 register space */
#define WM8510_RESET 0x0
#define WM8510_POWER1 0x1
#define WM8510_POWER2 0x2
#define WM8510_POWER3 0x3
#define WM8510_IFACE 0x4
#define WM8510_COMP 0x5
#define WM8510_CLOCK 0x6
#define WM8510_ADD 0x7
#define WM8510_GPIO 0x8
#define WM8510_DAC 0xa
#define WM8510_DACVOL 0xb
#define WM8510_ADC 0xe
#define WM8510_ADCVOL 0xf
#define WM8510_EQ1 0x12
#define WM8510_EQ2 0x13
#define WM8510_EQ3 0x14
#define WM8510_EQ4 0x15
#define WM8510_EQ5 0x16
#define WM8510_DACLIM1 0x18
#define WM8510_DACLIM2 0x19
#define WM8510_NOTCH1 0x1b
#define WM8510_NOTCH2 0x1c
#define WM8510_NOTCH3 0x1d
#define WM8510_NOTCH4 0x1e
#define WM8510_ALC1 0x20
#define WM8510_ALC2 0x21
#define WM8510_ALC3 0x22
#define WM8510_NGATE 0x23
#define WM8510_PLLN 0x24
#define WM8510_PLLK1 0x25
#define WM8510_PLLK2 0x26
#define WM8510_PLLK3 0x27
#define WM8510_ATTEN 0x28
#define WM8510_INPUT 0x2c
#define WM8510_INPPGA 0x2d
#define WM8510_ADCBOOST 0x2f
#define WM8510_OUTPUT 0x31
#define WM8510_SPKMIX 0x32
#define WM8510_SPKVOL 0x36
#define WM8510_MONOMIX 0x38
#define WM8510_CACHEREGNUM 57
/* Clock divider Id's */
#define WM8510_OPCLKDIV 0
#define WM8510_MCLKDIV 1
#define WM8510_ADCCLK 2
#define WM8510_DACCLK 3
#define WM8510_BCLKDIV 4
/* DAC clock dividers */
#define WM8510_DACCLK_F2 (1 << 3)
#define WM8510_DACCLK_F4 (0 << 3)
/* ADC clock dividers */
#define WM8510_ADCCLK_F2 (1 << 3)
#define WM8510_ADCCLK_F4 (0 << 3)
/* PLL Out dividers */
#define WM8510_OPCLKDIV_1 (0 << 4)
#define WM8510_OPCLKDIV_2 (1 << 4)
#define WM8510_OPCLKDIV_3 (2 << 4)
#define WM8510_OPCLKDIV_4 (3 << 4)
/* BCLK clock dividers */
#define WM8510_BCLKDIV_1 (0 << 2)
#define WM8510_BCLKDIV_2 (1 << 2)
#define WM8510_BCLKDIV_4 (2 << 2)
#define WM8510_BCLKDIV_8 (3 << 2)
#define WM8510_BCLKDIV_16 (4 << 2)
#define WM8510_BCLKDIV_32 (5 << 2)
/* MCLK clock dividers */
#define WM8510_MCLKDIV_1 (0 << 5)
#define WM8510_MCLKDIV_1_5 (1 << 5)
#define WM8510_MCLKDIV_2 (2 << 5)
#define WM8510_MCLKDIV_3 (3 << 5)
#define WM8510_MCLKDIV_4 (4 << 5)
#define WM8510_MCLKDIV_6 (5 << 5)
#define WM8510_MCLKDIV_8 (6 << 5)
#define WM8510_MCLKDIV_12 (7 << 5)
struct wm8510_setup_data {
int spi;
int i2c_bus;
unsigned short i2c_address;
};
extern struct snd_soc_dai wm8510_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8510;
#endif

699
kernel/sound/soc/codecs/wm8523.c Normal file
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@@ -0,0 +1,699 @@
/*
* wm8523.c -- WM8523 ALSA SoC Audio driver
*
* Copyright 2009 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8523.h"
static struct snd_soc_codec *wm8523_codec;
struct snd_soc_codec_device soc_codec_dev_wm8523;
#define WM8523_NUM_SUPPLIES 2
static const char *wm8523_supply_names[WM8523_NUM_SUPPLIES] = {
"AVDD",
"LINEVDD",
};
#define WM8523_NUM_RATES 7
/* codec private data */
struct wm8523_priv {
struct snd_soc_codec codec;
u16 reg_cache[WM8523_REGISTER_COUNT];
struct regulator_bulk_data supplies[WM8523_NUM_SUPPLIES];
unsigned int sysclk;
unsigned int rate_constraint_list[WM8523_NUM_RATES];
struct snd_pcm_hw_constraint_list rate_constraint;
};
static const u16 wm8523_reg[WM8523_REGISTER_COUNT] = {
0x8523, /* R0 - DEVICE_ID */
0x0001, /* R1 - REVISION */
0x0000, /* R2 - PSCTRL1 */
0x1812, /* R3 - AIF_CTRL1 */
0x0000, /* R4 - AIF_CTRL2 */
0x0001, /* R5 - DAC_CTRL3 */
0x0190, /* R6 - DAC_GAINL */
0x0190, /* R7 - DAC_GAINR */
0x0000, /* R8 - ZERO_DETECT */
};
static int wm8523_volatile_register(unsigned int reg)
{
switch (reg) {
case WM8523_DEVICE_ID:
case WM8523_REVISION:
return 1;
default:
return 0;
}
}
static int wm8523_reset(struct snd_soc_codec *codec)
{
return snd_soc_write(codec, WM8523_DEVICE_ID, 0);
}
static const DECLARE_TLV_DB_SCALE(dac_tlv, -10000, 25, 0);
static const char *wm8523_zd_count_text[] = {
"1024",
"2048",
};
static const struct soc_enum wm8523_zc_count =
SOC_ENUM_SINGLE(WM8523_ZERO_DETECT, 0, 2, wm8523_zd_count_text);
static const struct snd_kcontrol_new wm8523_snd_controls[] = {
SOC_DOUBLE_R_TLV("Playback Volume", WM8523_DAC_GAINL, WM8523_DAC_GAINR,
0, 448, 0, dac_tlv),
SOC_SINGLE("ZC Switch", WM8523_DAC_CTRL3, 4, 1, 0),
SOC_SINGLE("Playback Deemphasis Switch", WM8523_AIF_CTRL1, 8, 1, 0),
SOC_DOUBLE("Playback Switch", WM8523_DAC_CTRL3, 2, 3, 1, 1),
SOC_SINGLE("Volume Ramp Up Switch", WM8523_DAC_CTRL3, 1, 1, 0),
SOC_SINGLE("Volume Ramp Down Switch", WM8523_DAC_CTRL3, 0, 1, 0),
SOC_ENUM("Zero Detect Count", wm8523_zc_count),
};
static const struct snd_soc_dapm_widget wm8523_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("LINEVOUTL"),
SND_SOC_DAPM_OUTPUT("LINEVOUTR"),
};
static const struct snd_soc_dapm_route intercon[] = {
{ "LINEVOUTL", NULL, "DAC" },
{ "LINEVOUTR", NULL, "DAC" },
};
static int wm8523_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, wm8523_dapm_widgets,
ARRAY_SIZE(wm8523_dapm_widgets));
snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
snd_soc_dapm_new_widgets(codec);
return 0;
}
static struct {
int value;
int ratio;
} lrclk_ratios[WM8523_NUM_RATES] = {
{ 1, 128 },
{ 2, 192 },
{ 3, 256 },
{ 4, 384 },
{ 5, 512 },
{ 6, 768 },
{ 7, 1152 },
};
static int wm8523_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct wm8523_priv *wm8523 = codec->private_data;
/* The set of sample rates that can be supported depends on the
* MCLK supplied to the CODEC - enforce this.
*/
if (!wm8523->sysclk) {
dev_err(codec->dev,
"No MCLK configured, call set_sysclk() on init\n");
return -EINVAL;
}
return 0;
snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&wm8523->rate_constraint);
return 0;
}
static int wm8523_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct wm8523_priv *wm8523 = codec->private_data;
int i;
u16 aifctrl1 = snd_soc_read(codec, WM8523_AIF_CTRL1);
u16 aifctrl2 = snd_soc_read(codec, WM8523_AIF_CTRL2);
/* Find a supported LRCLK ratio */
for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
if (wm8523->sysclk / params_rate(params) ==
lrclk_ratios[i].ratio)
break;
}
/* Should never happen, should be handled by constraints */
if (i == ARRAY_SIZE(lrclk_ratios)) {
dev_err(codec->dev, "MCLK/fs ratio %d unsupported\n",
wm8523->sysclk / params_rate(params));
return -EINVAL;
}
aifctrl2 &= ~WM8523_SR_MASK;
aifctrl2 |= lrclk_ratios[i].value;
aifctrl1 &= ~WM8523_WL_MASK;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
aifctrl1 |= 0x8;
break;
case SNDRV_PCM_FORMAT_S24_LE:
aifctrl1 |= 0x10;
break;
case SNDRV_PCM_FORMAT_S32_LE:
aifctrl1 |= 0x18;
break;
}
snd_soc_write(codec, WM8523_AIF_CTRL1, aifctrl1);
snd_soc_write(codec, WM8523_AIF_CTRL2, aifctrl2);
return 0;
}
static int wm8523_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct wm8523_priv *wm8523 = codec->private_data;
unsigned int val;
int i;
wm8523->sysclk = freq;
wm8523->rate_constraint.count = 0;
for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
val = freq / lrclk_ratios[i].ratio;
/* Check that it's a standard rate since core can't
* cope with others and having the odd rates confuses
* constraint matching.
*/
switch (val) {
case 8000:
case 11025:
case 16000:
case 22050:
case 32000:
case 44100:
case 48000:
case 64000:
case 88200:
case 96000:
case 176400:
case 192000:
dev_dbg(codec->dev, "Supported sample rate: %dHz\n",
val);
wm8523->rate_constraint_list[i] = val;
wm8523->rate_constraint.count++;
break;
default:
dev_dbg(codec->dev, "Skipping sample rate: %dHz\n",
val);
}
}
/* Need at least one supported rate... */
if (wm8523->rate_constraint.count == 0)
return -EINVAL;
return 0;
}
static int wm8523_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 aifctrl1 = snd_soc_read(codec, WM8523_AIF_CTRL1);
aifctrl1 &= ~(WM8523_BCLK_INV_MASK | WM8523_LRCLK_INV_MASK |
WM8523_FMT_MASK | WM8523_AIF_MSTR_MASK);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
aifctrl1 |= WM8523_AIF_MSTR;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
aifctrl1 |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
aifctrl1 |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
aifctrl1 |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
aifctrl1 |= 0x0023;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
aifctrl1 |= WM8523_BCLK_INV | WM8523_LRCLK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
aifctrl1 |= WM8523_BCLK_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
aifctrl1 |= WM8523_LRCLK_INV;
break;
default:
return -EINVAL;
}
snd_soc_write(codec, WM8523_AIF_CTRL1, aifctrl1);
return 0;
}
static int wm8523_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
struct wm8523_priv *wm8523 = codec->private_data;
int ret, i;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* Full power on */
snd_soc_update_bits(codec, WM8523_PSCTRL1,
WM8523_SYS_ENA_MASK, 3);
break;
case SND_SOC_BIAS_STANDBY:
if (codec->bias_level == SND_SOC_BIAS_OFF) {
ret = regulator_bulk_enable(ARRAY_SIZE(wm8523->supplies),
wm8523->supplies);
if (ret != 0) {
dev_err(codec->dev,
"Failed to enable supplies: %d\n",
ret);
return ret;
}
/* Initial power up */
snd_soc_update_bits(codec, WM8523_PSCTRL1,
WM8523_SYS_ENA_MASK, 1);
/* Sync back default/cached values */
for (i = WM8523_AIF_CTRL1;
i < WM8523_MAX_REGISTER; i++)
snd_soc_write(codec, i, wm8523->reg_cache[i]);
msleep(100);
}
/* Power up to mute */
snd_soc_update_bits(codec, WM8523_PSCTRL1,
WM8523_SYS_ENA_MASK, 2);
break;
case SND_SOC_BIAS_OFF:
/* The chip runs through the power down sequence for us. */
snd_soc_update_bits(codec, WM8523_PSCTRL1,
WM8523_SYS_ENA_MASK, 0);
msleep(100);
regulator_bulk_disable(ARRAY_SIZE(wm8523->supplies),
wm8523->supplies);
break;
}
codec->bias_level = level;
return 0;
}
#define WM8523_RATES SNDRV_PCM_RATE_8000_192000
#define WM8523_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_ops wm8523_dai_ops = {
.startup = wm8523_startup,
.hw_params = wm8523_hw_params,
.set_sysclk = wm8523_set_dai_sysclk,
.set_fmt = wm8523_set_dai_fmt,
};
struct snd_soc_dai wm8523_dai = {
.name = "WM8523",
.playback = {
.stream_name = "Playback",
.channels_min = 2, /* Mono modes not yet supported */
.channels_max = 2,
.rates = WM8523_RATES,
.formats = WM8523_FORMATS,
},
.ops = &wm8523_dai_ops,
};
EXPORT_SYMBOL_GPL(wm8523_dai);
#ifdef CONFIG_PM
static int wm8523_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
wm8523_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int wm8523_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
wm8523_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
return 0;
}
#else
#define wm8523_suspend NULL
#define wm8523_resume NULL
#endif
static int wm8523_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
if (wm8523_codec == NULL) {
dev_err(&pdev->dev, "Codec device not registered\n");
return -ENODEV;
}
socdev->card->codec = wm8523_codec;
codec = wm8523_codec;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms: %d\n", ret);
goto pcm_err;
}
snd_soc_add_controls(codec, wm8523_snd_controls,
ARRAY_SIZE(wm8523_snd_controls));
wm8523_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(codec->dev, "failed to register card: %d\n", ret);
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
return ret;
}
static int wm8523_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_wm8523 = {
.probe = wm8523_probe,
.remove = wm8523_remove,
.suspend = wm8523_suspend,
.resume = wm8523_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm8523);
static int wm8523_register(struct wm8523_priv *wm8523,
enum snd_soc_control_type control)
{
int ret;
struct snd_soc_codec *codec = &wm8523->codec;
int i;
if (wm8523_codec) {
dev_err(codec->dev, "Another WM8523 is registered\n");
return -EINVAL;
}
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->private_data = wm8523;
codec->name = "WM8523";
codec->owner = THIS_MODULE;
codec->bias_level = SND_SOC_BIAS_OFF;
codec->set_bias_level = wm8523_set_bias_level;
codec->dai = &wm8523_dai;
codec->num_dai = 1;
codec->reg_cache_size = WM8523_REGISTER_COUNT;
codec->reg_cache = &wm8523->reg_cache;
codec->volatile_register = wm8523_volatile_register;
wm8523->rate_constraint.list = &wm8523->rate_constraint_list[0];
wm8523->rate_constraint.count =
ARRAY_SIZE(wm8523->rate_constraint_list);
memcpy(codec->reg_cache, wm8523_reg, sizeof(wm8523_reg));
ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
if (ret != 0) {
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
goto err;
}
for (i = 0; i < ARRAY_SIZE(wm8523->supplies); i++)
wm8523->supplies[i].supply = wm8523_supply_names[i];
ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8523->supplies),
wm8523->supplies);
if (ret != 0) {
dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
goto err;
}
ret = regulator_bulk_enable(ARRAY_SIZE(wm8523->supplies),
wm8523->supplies);
if (ret != 0) {
dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
goto err_get;
}
ret = snd_soc_read(codec, WM8523_DEVICE_ID);
if (ret < 0) {
dev_err(codec->dev, "Failed to read ID register\n");
goto err_enable;
}
if (ret != wm8523_reg[WM8523_DEVICE_ID]) {
dev_err(codec->dev, "Device is not a WM8523, ID is %x\n", ret);
ret = -EINVAL;
goto err_enable;
}
ret = snd_soc_read(codec, WM8523_REVISION);
if (ret < 0) {
dev_err(codec->dev, "Failed to read revision register\n");
goto err_enable;
}
dev_info(codec->dev, "revision %c\n",
(ret & WM8523_CHIP_REV_MASK) + 'A');
ret = wm8523_reset(codec);
if (ret < 0) {
dev_err(codec->dev, "Failed to issue reset\n");
goto err_enable;
}
wm8523_dai.dev = codec->dev;
/* Change some default settings - latch VU and enable ZC */
wm8523->reg_cache[WM8523_DAC_GAINR] |= WM8523_DACR_VU;
wm8523->reg_cache[WM8523_DAC_CTRL3] |= WM8523_ZC;
wm8523_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
/* Bias level configuration will have done an extra enable */
regulator_bulk_disable(ARRAY_SIZE(wm8523->supplies), wm8523->supplies);
wm8523_codec = codec;
ret = snd_soc_register_codec(codec);
if (ret != 0) {
dev_err(codec->dev, "Failed to register codec: %d\n", ret);
return ret;
}
ret = snd_soc_register_dai(&wm8523_dai);
if (ret != 0) {
dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
snd_soc_unregister_codec(codec);
return ret;
}
return 0;
err_enable:
regulator_bulk_disable(ARRAY_SIZE(wm8523->supplies), wm8523->supplies);
err_get:
regulator_bulk_free(ARRAY_SIZE(wm8523->supplies), wm8523->supplies);
err:
kfree(wm8523);
return ret;
}
static void wm8523_unregister(struct wm8523_priv *wm8523)
{
wm8523_set_bias_level(&wm8523->codec, SND_SOC_BIAS_OFF);
regulator_bulk_free(ARRAY_SIZE(wm8523->supplies), wm8523->supplies);
snd_soc_unregister_dai(&wm8523_dai);
snd_soc_unregister_codec(&wm8523->codec);
kfree(wm8523);
wm8523_codec = NULL;
}
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
static __devinit int wm8523_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct wm8523_priv *wm8523;
struct snd_soc_codec *codec;
wm8523 = kzalloc(sizeof(struct wm8523_priv), GFP_KERNEL);
if (wm8523 == NULL)
return -ENOMEM;
codec = &wm8523->codec;
codec->hw_write = (hw_write_t)i2c_master_send;
i2c_set_clientdata(i2c, wm8523);
codec->control_data = i2c;
codec->dev = &i2c->dev;
return wm8523_register(wm8523, SND_SOC_I2C);
}
static __devexit int wm8523_i2c_remove(struct i2c_client *client)
{
struct wm8523_priv *wm8523 = i2c_get_clientdata(client);
wm8523_unregister(wm8523);
return 0;
}
#ifdef CONFIG_PM
static int wm8523_i2c_suspend(struct i2c_client *i2c, pm_message_t msg)
{
return snd_soc_suspend_device(&i2c->dev);
}
static int wm8523_i2c_resume(struct i2c_client *i2c)
{
return snd_soc_resume_device(&i2c->dev);
}
#else
#define wm8523_i2c_suspend NULL
#define wm8523_i2c_resume NULL
#endif
static const struct i2c_device_id wm8523_i2c_id[] = {
{ "wm8523", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8523_i2c_id);
static struct i2c_driver wm8523_i2c_driver = {
.driver = {
.name = "WM8523",
.owner = THIS_MODULE,
},
.probe = wm8523_i2c_probe,
.remove = __devexit_p(wm8523_i2c_remove),
.suspend = wm8523_i2c_suspend,
.resume = wm8523_i2c_resume,
.id_table = wm8523_i2c_id,
};
#endif
static int __init wm8523_modinit(void)
{
int ret;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
ret = i2c_add_driver(&wm8523_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8523 I2C driver: %d\n",
ret);
}
#endif
return 0;
}
module_init(wm8523_modinit);
static void __exit wm8523_exit(void)
{
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
i2c_del_driver(&wm8523_i2c_driver);
#endif
}
module_exit(wm8523_exit);
MODULE_DESCRIPTION("ASoC WM8523 driver");
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
MODULE_LICENSE("GPL");

160
kernel/sound/soc/codecs/wm8523.h Normal file
View File

@@ -0,0 +1,160 @@
/*
* wm8523.h -- WM8423 ASoC driver
*
* Copyright 2009 Wolfson Microelectronics, plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* Based on wm8753.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM8523_H
#define _WM8523_H
/*
* Register values.
*/
#define WM8523_DEVICE_ID 0x00
#define WM8523_REVISION 0x01
#define WM8523_PSCTRL1 0x02
#define WM8523_AIF_CTRL1 0x03
#define WM8523_AIF_CTRL2 0x04
#define WM8523_DAC_CTRL3 0x05
#define WM8523_DAC_GAINL 0x06
#define WM8523_DAC_GAINR 0x07
#define WM8523_ZERO_DETECT 0x08
#define WM8523_REGISTER_COUNT 9
#define WM8523_MAX_REGISTER 0x08
/*
* Field Definitions.
*/
/*
* R0 (0x00) - DEVICE_ID
*/
#define WM8523_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
#define WM8523_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
#define WM8523_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
/*
* R1 (0x01) - REVISION
*/
#define WM8523_CHIP_REV_MASK 0x0007 /* CHIP_REV - [2:0] */
#define WM8523_CHIP_REV_SHIFT 0 /* CHIP_REV - [2:0] */
#define WM8523_CHIP_REV_WIDTH 3 /* CHIP_REV - [2:0] */
/*
* R2 (0x02) - PSCTRL1
*/
#define WM8523_SYS_ENA_MASK 0x0003 /* SYS_ENA - [1:0] */
#define WM8523_SYS_ENA_SHIFT 0 /* SYS_ENA - [1:0] */
#define WM8523_SYS_ENA_WIDTH 2 /* SYS_ENA - [1:0] */
/*
* R3 (0x03) - AIF_CTRL1
*/
#define WM8523_TDM_MODE_MASK 0x1800 /* TDM_MODE - [12:11] */
#define WM8523_TDM_MODE_SHIFT 11 /* TDM_MODE - [12:11] */
#define WM8523_TDM_MODE_WIDTH 2 /* TDM_MODE - [12:11] */
#define WM8523_TDM_SLOT_MASK 0x0600 /* TDM_SLOT - [10:9] */
#define WM8523_TDM_SLOT_SHIFT 9 /* TDM_SLOT - [10:9] */
#define WM8523_TDM_SLOT_WIDTH 2 /* TDM_SLOT - [10:9] */
#define WM8523_DEEMPH 0x0100 /* DEEMPH */
#define WM8523_DEEMPH_MASK 0x0100 /* DEEMPH */
#define WM8523_DEEMPH_SHIFT 8 /* DEEMPH */
#define WM8523_DEEMPH_WIDTH 1 /* DEEMPH */
#define WM8523_AIF_MSTR 0x0080 /* AIF_MSTR */
#define WM8523_AIF_MSTR_MASK 0x0080 /* AIF_MSTR */
#define WM8523_AIF_MSTR_SHIFT 7 /* AIF_MSTR */
#define WM8523_AIF_MSTR_WIDTH 1 /* AIF_MSTR */
#define WM8523_LRCLK_INV 0x0040 /* LRCLK_INV */
#define WM8523_LRCLK_INV_MASK 0x0040 /* LRCLK_INV */
#define WM8523_LRCLK_INV_SHIFT 6 /* LRCLK_INV */
#define WM8523_LRCLK_INV_WIDTH 1 /* LRCLK_INV */
#define WM8523_BCLK_INV 0x0020 /* BCLK_INV */
#define WM8523_BCLK_INV_MASK 0x0020 /* BCLK_INV */
#define WM8523_BCLK_INV_SHIFT 5 /* BCLK_INV */
#define WM8523_BCLK_INV_WIDTH 1 /* BCLK_INV */
#define WM8523_WL_MASK 0x0018 /* WL - [4:3] */
#define WM8523_WL_SHIFT 3 /* WL - [4:3] */
#define WM8523_WL_WIDTH 2 /* WL - [4:3] */
#define WM8523_FMT_MASK 0x0007 /* FMT - [2:0] */
#define WM8523_FMT_SHIFT 0 /* FMT - [2:0] */
#define WM8523_FMT_WIDTH 3 /* FMT - [2:0] */
/*
* R4 (0x04) - AIF_CTRL2
*/
#define WM8523_DAC_OP_MUX_MASK 0x00C0 /* DAC_OP_MUX - [7:6] */
#define WM8523_DAC_OP_MUX_SHIFT 6 /* DAC_OP_MUX - [7:6] */
#define WM8523_DAC_OP_MUX_WIDTH 2 /* DAC_OP_MUX - [7:6] */
#define WM8523_BCLKDIV_MASK 0x0038 /* BCLKDIV - [5:3] */
#define WM8523_BCLKDIV_SHIFT 3 /* BCLKDIV - [5:3] */
#define WM8523_BCLKDIV_WIDTH 3 /* BCLKDIV - [5:3] */
#define WM8523_SR_MASK 0x0007 /* SR - [2:0] */
#define WM8523_SR_SHIFT 0 /* SR - [2:0] */
#define WM8523_SR_WIDTH 3 /* SR - [2:0] */
/*
* R5 (0x05) - DAC_CTRL3
*/
#define WM8523_ZC 0x0010 /* ZC */
#define WM8523_ZC_MASK 0x0010 /* ZC */
#define WM8523_ZC_SHIFT 4 /* ZC */
#define WM8523_ZC_WIDTH 1 /* ZC */
#define WM8523_DACR 0x0008 /* DACR */
#define WM8523_DACR_MASK 0x0008 /* DACR */
#define WM8523_DACR_SHIFT 3 /* DACR */
#define WM8523_DACR_WIDTH 1 /* DACR */
#define WM8523_DACL 0x0004 /* DACL */
#define WM8523_DACL_MASK 0x0004 /* DACL */
#define WM8523_DACL_SHIFT 2 /* DACL */
#define WM8523_DACL_WIDTH 1 /* DACL */
#define WM8523_VOL_UP_RAMP 0x0002 /* VOL_UP_RAMP */
#define WM8523_VOL_UP_RAMP_MASK 0x0002 /* VOL_UP_RAMP */
#define WM8523_VOL_UP_RAMP_SHIFT 1 /* VOL_UP_RAMP */
#define WM8523_VOL_UP_RAMP_WIDTH 1 /* VOL_UP_RAMP */
#define WM8523_VOL_DOWN_RAMP 0x0001 /* VOL_DOWN_RAMP */
#define WM8523_VOL_DOWN_RAMP_MASK 0x0001 /* VOL_DOWN_RAMP */
#define WM8523_VOL_DOWN_RAMP_SHIFT 0 /* VOL_DOWN_RAMP */
#define WM8523_VOL_DOWN_RAMP_WIDTH 1 /* VOL_DOWN_RAMP */
/*
* R6 (0x06) - DAC_GAINL
*/
#define WM8523_DACL_VU 0x0200 /* DACL_VU */
#define WM8523_DACL_VU_MASK 0x0200 /* DACL_VU */
#define WM8523_DACL_VU_SHIFT 9 /* DACL_VU */
#define WM8523_DACL_VU_WIDTH 1 /* DACL_VU */
#define WM8523_DACL_VOL_MASK 0x01FF /* DACL_VOL - [8:0] */
#define WM8523_DACL_VOL_SHIFT 0 /* DACL_VOL - [8:0] */
#define WM8523_DACL_VOL_WIDTH 9 /* DACL_VOL - [8:0] */
/*
* R7 (0x07) - DAC_GAINR
*/
#define WM8523_DACR_VU 0x0200 /* DACR_VU */
#define WM8523_DACR_VU_MASK 0x0200 /* DACR_VU */
#define WM8523_DACR_VU_SHIFT 9 /* DACR_VU */
#define WM8523_DACR_VU_WIDTH 1 /* DACR_VU */
#define WM8523_DACR_VOL_MASK 0x01FF /* DACR_VOL - [8:0] */
#define WM8523_DACR_VOL_SHIFT 0 /* DACR_VOL - [8:0] */
#define WM8523_DACR_VOL_WIDTH 9 /* DACR_VOL - [8:0] */
/*
* R8 (0x08) - ZERO_DETECT
*/
#define WM8523_ZD_COUNT_MASK 0x0003 /* ZD_COUNT - [1:0] */
#define WM8523_ZD_COUNT_SHIFT 0 /* ZD_COUNT - [1:0] */
#define WM8523_ZD_COUNT_WIDTH 2 /* ZD_COUNT - [1:0] */
extern struct snd_soc_dai wm8523_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8523;
#endif

1023
kernel/sound/soc/codecs/wm8580.c Normal file
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38
kernel/sound/soc/codecs/wm8580.h Normal file
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/*
* wm8580.h -- audio driver for WM8580
*
* Copyright 2008 Samsung Electronics.
* Author: Ryu Euiyoul
* ryu.real@gmail.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef _WM8580_H
#define _WM8580_H
#define WM8580_PLLA 1
#define WM8580_PLLB 2
#define WM8580_MCLK 1
#define WM8580_DAC_CLKSEL 2
#define WM8580_CLKOUTSRC 3
#define WM8580_CLKSRC_MCLK 1
#define WM8580_CLKSRC_PLLA 2
#define WM8580_CLKSRC_PLLB 3
#define WM8580_CLKSRC_OSC 4
#define WM8580_CLKSRC_NONE 5
#define WM8580_DAI_PAIFRX 0
#define WM8580_DAI_PAIFTX 1
extern struct snd_soc_dai wm8580_dai[];
extern struct snd_soc_codec_device soc_codec_dev_wm8580;
#endif

514
kernel/sound/soc/codecs/wm8728.c Normal file
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/*
* wm8728.c -- WM8728 ALSA SoC Audio driver
*
* Copyright 2008 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8728.h"
struct snd_soc_codec_device soc_codec_dev_wm8728;
/*
* We can't read the WM8728 register space so we cache them instead.
* Note that the defaults here aren't the physical defaults, we latch
* the volume update bits, mute the output and enable infinite zero
* detect.
*/
static const u16 wm8728_reg_defaults[] = {
0x1ff,
0x1ff,
0x001,
0x100,
};
static const DECLARE_TLV_DB_SCALE(wm8728_tlv, -12750, 50, 1);
static const struct snd_kcontrol_new wm8728_snd_controls[] = {
SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8728_DACLVOL, WM8728_DACRVOL,
0, 255, 0, wm8728_tlv),
SOC_SINGLE("Deemphasis", WM8728_DACCTL, 1, 1, 0),
};
/*
* DAPM controls.
*/
static const struct snd_soc_dapm_widget wm8728_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_OUTPUT("VOUTL"),
SND_SOC_DAPM_OUTPUT("VOUTR"),
};
static const struct snd_soc_dapm_route intercon[] = {
{"VOUTL", NULL, "DAC"},
{"VOUTR", NULL, "DAC"},
};
static int wm8728_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, wm8728_dapm_widgets,
ARRAY_SIZE(wm8728_dapm_widgets));
snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
snd_soc_dapm_new_widgets(codec);
return 0;
}
static int wm8728_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
u16 mute_reg = snd_soc_read(codec, WM8728_DACCTL);
if (mute)
snd_soc_write(codec, WM8728_DACCTL, mute_reg | 1);
else
snd_soc_write(codec, WM8728_DACCTL, mute_reg & ~1);
return 0;
}
static int wm8728_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
u16 dac = snd_soc_read(codec, WM8728_DACCTL);
dac &= ~0x18;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
dac |= 0x10;
break;
case SNDRV_PCM_FORMAT_S24_LE:
dac |= 0x08;
break;
default:
return -EINVAL;
}
snd_soc_write(codec, WM8728_DACCTL, dac);
return 0;
}
static int wm8728_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 iface = snd_soc_read(codec, WM8728_IFCTL);
/* Currently only I2S is supported by the driver, though the
* hardware is more flexible.
*/
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 1;
break;
default:
return -EINVAL;
}
/* The hardware only support full slave mode */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
iface &= ~0x22;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x20;
iface &= ~0x02;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x02;
iface &= ~0x20;
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x22;
break;
default:
return -EINVAL;
}
snd_soc_write(codec, WM8728_IFCTL, iface);
return 0;
}
static int wm8728_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
u16 reg;
int i;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
case SND_SOC_BIAS_STANDBY:
if (codec->bias_level == SND_SOC_BIAS_OFF) {
/* Power everything up... */
reg = snd_soc_read(codec, WM8728_DACCTL);
snd_soc_write(codec, WM8728_DACCTL, reg & ~0x4);
/* ..then sync in the register cache. */
for (i = 0; i < ARRAY_SIZE(wm8728_reg_defaults); i++)
snd_soc_write(codec, i,
snd_soc_read(codec, i));
}
break;
case SND_SOC_BIAS_OFF:
reg = snd_soc_read(codec, WM8728_DACCTL);
snd_soc_write(codec, WM8728_DACCTL, reg | 0x4);
break;
}
codec->bias_level = level;
return 0;
}
#define WM8728_RATES (SNDRV_PCM_RATE_8000_192000)
#define WM8728_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_ops wm8728_dai_ops = {
.hw_params = wm8728_hw_params,
.digital_mute = wm8728_mute,
.set_fmt = wm8728_set_dai_fmt,
};
struct snd_soc_dai wm8728_dai = {
.name = "WM8728",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM8728_RATES,
.formats = WM8728_FORMATS,
},
.ops = &wm8728_dai_ops,
};
EXPORT_SYMBOL_GPL(wm8728_dai);
static int wm8728_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
wm8728_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int wm8728_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
wm8728_set_bias_level(codec, codec->suspend_bias_level);
return 0;
}
/*
* initialise the WM8728 driver
* register the mixer and dsp interfaces with the kernel
*/
static int wm8728_init(struct snd_soc_device *socdev,
enum snd_soc_control_type control)
{
struct snd_soc_codec *codec = socdev->card->codec;
int ret = 0;
codec->name = "WM8728";
codec->owner = THIS_MODULE;
codec->set_bias_level = wm8728_set_bias_level;
codec->dai = &wm8728_dai;
codec->num_dai = 1;
codec->bias_level = SND_SOC_BIAS_OFF;
codec->reg_cache_size = ARRAY_SIZE(wm8728_reg_defaults);
codec->reg_cache = kmemdup(wm8728_reg_defaults,
sizeof(wm8728_reg_defaults),
GFP_KERNEL);
if (codec->reg_cache == NULL)
return -ENOMEM;
ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
if (ret < 0) {
printk(KERN_ERR "wm8728: failed to configure cache I/O: %d\n",
ret);
goto err;
}
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
printk(KERN_ERR "wm8728: failed to create pcms\n");
goto err;
}
/* power on device */
wm8728_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
snd_soc_add_controls(codec, wm8728_snd_controls,
ARRAY_SIZE(wm8728_snd_controls));
wm8728_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
printk(KERN_ERR "wm8728: failed to register card\n");
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
err:
kfree(codec->reg_cache);
return ret;
}
static struct snd_soc_device *wm8728_socdev;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
/*
* WM8728 2 wire address is determined by GPIO5
* state during powerup.
* low = 0x1a
* high = 0x1b
*/
static int wm8728_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct snd_soc_device *socdev = wm8728_socdev;
struct snd_soc_codec *codec = socdev->card->codec;
int ret;
i2c_set_clientdata(i2c, codec);
codec->control_data = i2c;
ret = wm8728_init(socdev, SND_SOC_I2C);
if (ret < 0)
pr_err("failed to initialise WM8728\n");
return ret;
}
static int wm8728_i2c_remove(struct i2c_client *client)
{
struct snd_soc_codec *codec = i2c_get_clientdata(client);
kfree(codec->reg_cache);
return 0;
}
static const struct i2c_device_id wm8728_i2c_id[] = {
{ "wm8728", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8728_i2c_id);
static struct i2c_driver wm8728_i2c_driver = {
.driver = {
.name = "WM8728 I2C Codec",
.owner = THIS_MODULE,
},
.probe = wm8728_i2c_probe,
.remove = wm8728_i2c_remove,
.id_table = wm8728_i2c_id,
};
static int wm8728_add_i2c_device(struct platform_device *pdev,
const struct wm8728_setup_data *setup)
{
struct i2c_board_info info;
struct i2c_adapter *adapter;
struct i2c_client *client;
int ret;
ret = i2c_add_driver(&wm8728_i2c_driver);
if (ret != 0) {
dev_err(&pdev->dev, "can't add i2c driver\n");
return ret;
}
memset(&info, 0, sizeof(struct i2c_board_info));
info.addr = setup->i2c_address;
strlcpy(info.type, "wm8728", I2C_NAME_SIZE);
adapter = i2c_get_adapter(setup->i2c_bus);
if (!adapter) {
dev_err(&pdev->dev, "can't get i2c adapter %d\n",
setup->i2c_bus);
goto err_driver;
}
client = i2c_new_device(adapter, &info);
i2c_put_adapter(adapter);
if (!client) {
dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
(unsigned int)info.addr);
goto err_driver;
}
return 0;
err_driver:
i2c_del_driver(&wm8728_i2c_driver);
return -ENODEV;
}
#endif
#if defined(CONFIG_SPI_MASTER)
static int __devinit wm8728_spi_probe(struct spi_device *spi)
{
struct snd_soc_device *socdev = wm8728_socdev;
struct snd_soc_codec *codec = socdev->card->codec;
int ret;
codec->control_data = spi;
ret = wm8728_init(socdev, SND_SOC_SPI);
if (ret < 0)
dev_err(&spi->dev, "failed to initialise WM8728\n");
return ret;
}
static int __devexit wm8728_spi_remove(struct spi_device *spi)
{
return 0;
}
static struct spi_driver wm8728_spi_driver = {
.driver = {
.name = "wm8728",
.bus = &spi_bus_type,
.owner = THIS_MODULE,
},
.probe = wm8728_spi_probe,
.remove = __devexit_p(wm8728_spi_remove),
};
#endif /* CONFIG_SPI_MASTER */
static int wm8728_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct wm8728_setup_data *setup;
struct snd_soc_codec *codec;
int ret = 0;
setup = socdev->codec_data;
codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
if (codec == NULL)
return -ENOMEM;
socdev->card->codec = codec;
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
wm8728_socdev = socdev;
ret = -ENODEV;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
if (setup->i2c_address) {
ret = wm8728_add_i2c_device(pdev, setup);
}
#endif
#if defined(CONFIG_SPI_MASTER)
if (setup->spi) {
ret = spi_register_driver(&wm8728_spi_driver);
if (ret != 0)
printk(KERN_ERR "can't add spi driver");
}
#endif
if (ret != 0)
kfree(codec);
return ret;
}
/* power down chip */
static int wm8728_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
if (codec->control_data)
wm8728_set_bias_level(codec, SND_SOC_BIAS_OFF);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
i2c_unregister_device(codec->control_data);
i2c_del_driver(&wm8728_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8728_spi_driver);
#endif
kfree(codec);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_wm8728 = {
.probe = wm8728_probe,
.remove = wm8728_remove,
.suspend = wm8728_suspend,
.resume = wm8728_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm8728);
static int __init wm8728_modinit(void)
{
return snd_soc_register_dai(&wm8728_dai);
}
module_init(wm8728_modinit);
static void __exit wm8728_exit(void)
{
snd_soc_unregister_dai(&wm8728_dai);
}
module_exit(wm8728_exit);
MODULE_DESCRIPTION("ASoC WM8728 driver");
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
MODULE_LICENSE("GPL");

30
kernel/sound/soc/codecs/wm8728.h Normal file
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/*
* wm8728.h -- WM8728 ASoC codec driver
*
* Copyright 2008 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM8728_H
#define _WM8728_H
#define WM8728_DACLVOL 0x00
#define WM8728_DACRVOL 0x01
#define WM8728_DACCTL 0x02
#define WM8728_IFCTL 0x03
struct wm8728_setup_data {
int spi;
int i2c_bus;
unsigned short i2c_address;
};
extern struct snd_soc_dai wm8728_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8728;
#endif

750
kernel/sound/soc/codecs/wm8731.c Normal file
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/*
* wm8731.c -- WM8731 ALSA SoC Audio driver
*
* Copyright 2005 Openedhand Ltd.
*
* Author: Richard Purdie <richard@openedhand.com>
*
* Based on wm8753.c by Liam Girdwood
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8731.h"
static struct snd_soc_codec *wm8731_codec;
struct snd_soc_codec_device soc_codec_dev_wm8731;
/* codec private data */
struct wm8731_priv {
struct snd_soc_codec codec;
u16 reg_cache[WM8731_CACHEREGNUM];
unsigned int sysclk;
};
/*
* wm8731 register cache
* We can't read the WM8731 register space when we are
* using 2 wire for device control, so we cache them instead.
* There is no point in caching the reset register
*/
static const u16 wm8731_reg[WM8731_CACHEREGNUM] = {
0x0097, 0x0097, 0x0079, 0x0079,
0x000a, 0x0008, 0x009f, 0x000a,
0x0000, 0x0000
};
#define wm8731_reset(c) snd_soc_write(c, WM8731_RESET, 0)
static const char *wm8731_input_select[] = {"Line In", "Mic"};
static const char *wm8731_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static const struct soc_enum wm8731_enum[] = {
SOC_ENUM_SINGLE(WM8731_APANA, 2, 2, wm8731_input_select),
SOC_ENUM_SINGLE(WM8731_APDIGI, 1, 4, wm8731_deemph),
};
static const DECLARE_TLV_DB_SCALE(in_tlv, -3450, 150, 0);
static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -1500, 300, 0);
static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
static const struct snd_kcontrol_new wm8731_snd_controls[] = {
SOC_DOUBLE_R_TLV("Master Playback Volume", WM8731_LOUT1V, WM8731_ROUT1V,
0, 127, 0, out_tlv),
SOC_DOUBLE_R("Master Playback ZC Switch", WM8731_LOUT1V, WM8731_ROUT1V,
7, 1, 0),
SOC_DOUBLE_R_TLV("Capture Volume", WM8731_LINVOL, WM8731_RINVOL, 0, 31, 0,
in_tlv),
SOC_DOUBLE_R("Line Capture Switch", WM8731_LINVOL, WM8731_RINVOL, 7, 1, 1),
SOC_SINGLE("Mic Boost (+20dB)", WM8731_APANA, 0, 1, 0),
SOC_SINGLE("Mic Capture Switch", WM8731_APANA, 1, 1, 1),
SOC_SINGLE_TLV("Sidetone Playback Volume", WM8731_APANA, 6, 3, 1,
sidetone_tlv),
SOC_SINGLE("ADC High Pass Filter Switch", WM8731_APDIGI, 0, 1, 1),
SOC_SINGLE("Store DC Offset Switch", WM8731_APDIGI, 4, 1, 0),
SOC_ENUM("Playback De-emphasis", wm8731_enum[1]),
};
/* Output Mixer */
static const struct snd_kcontrol_new wm8731_output_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8731_APANA, 3, 1, 0),
SOC_DAPM_SINGLE("Mic Sidetone Switch", WM8731_APANA, 5, 1, 0),
SOC_DAPM_SINGLE("HiFi Playback Switch", WM8731_APANA, 4, 1, 0),
};
/* Input mux */
static const struct snd_kcontrol_new wm8731_input_mux_controls =
SOC_DAPM_ENUM("Input Select", wm8731_enum[0]);
static const struct snd_soc_dapm_widget wm8731_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Output Mixer", WM8731_PWR, 4, 1,
&wm8731_output_mixer_controls[0],
ARRAY_SIZE(wm8731_output_mixer_controls)),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8731_PWR, 3, 1),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("LHPOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("RHPOUT"),
SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8731_PWR, 2, 1),
SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0, &wm8731_input_mux_controls),
SND_SOC_DAPM_PGA("Line Input", WM8731_PWR, 0, 1, NULL, 0),
SND_SOC_DAPM_MICBIAS("Mic Bias", WM8731_PWR, 1, 1),
SND_SOC_DAPM_INPUT("MICIN"),
SND_SOC_DAPM_INPUT("RLINEIN"),
SND_SOC_DAPM_INPUT("LLINEIN"),
};
static const struct snd_soc_dapm_route intercon[] = {
/* output mixer */
{"Output Mixer", "Line Bypass Switch", "Line Input"},
{"Output Mixer", "HiFi Playback Switch", "DAC"},
{"Output Mixer", "Mic Sidetone Switch", "Mic Bias"},
/* outputs */
{"RHPOUT", NULL, "Output Mixer"},
{"ROUT", NULL, "Output Mixer"},
{"LHPOUT", NULL, "Output Mixer"},
{"LOUT", NULL, "Output Mixer"},
/* input mux */
{"Input Mux", "Line In", "Line Input"},
{"Input Mux", "Mic", "Mic Bias"},
{"ADC", NULL, "Input Mux"},
/* inputs */
{"Line Input", NULL, "LLINEIN"},
{"Line Input", NULL, "RLINEIN"},
{"Mic Bias", NULL, "MICIN"},
};
static int wm8731_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, wm8731_dapm_widgets,
ARRAY_SIZE(wm8731_dapm_widgets));
snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
snd_soc_dapm_new_widgets(codec);
return 0;
}
struct _coeff_div {
u32 mclk;
u32 rate;
u16 fs;
u8 sr:4;
u8 bosr:1;
u8 usb:1;
};
/* codec mclk clock divider coefficients */
static const struct _coeff_div coeff_div[] = {
/* 48k */
{12288000, 48000, 256, 0x0, 0x0, 0x0},
{18432000, 48000, 384, 0x0, 0x1, 0x0},
{12000000, 48000, 250, 0x0, 0x0, 0x1},
/* 32k */
{12288000, 32000, 384, 0x6, 0x0, 0x0},
{18432000, 32000, 576, 0x6, 0x1, 0x0},
{12000000, 32000, 375, 0x6, 0x0, 0x1},
/* 8k */
{12288000, 8000, 1536, 0x3, 0x0, 0x0},
{18432000, 8000, 2304, 0x3, 0x1, 0x0},
{11289600, 8000, 1408, 0xb, 0x0, 0x0},
{16934400, 8000, 2112, 0xb, 0x1, 0x0},
{12000000, 8000, 1500, 0x3, 0x0, 0x1},
/* 96k */
{12288000, 96000, 128, 0x7, 0x0, 0x0},
{18432000, 96000, 192, 0x7, 0x1, 0x0},
{12000000, 96000, 125, 0x7, 0x0, 0x1},
/* 44.1k */
{11289600, 44100, 256, 0x8, 0x0, 0x0},
{16934400, 44100, 384, 0x8, 0x1, 0x0},
{12000000, 44100, 272, 0x8, 0x1, 0x1},
/* 88.2k */
{11289600, 88200, 128, 0xf, 0x0, 0x0},
{16934400, 88200, 192, 0xf, 0x1, 0x0},
{12000000, 88200, 136, 0xf, 0x1, 0x1},
};
static inline int get_coeff(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
return i;
}
return 0;
}
static int wm8731_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct wm8731_priv *wm8731 = codec->private_data;
u16 iface = snd_soc_read(codec, WM8731_IFACE) & 0xfff3;
int i = get_coeff(wm8731->sysclk, params_rate(params));
u16 srate = (coeff_div[i].sr << 2) |
(coeff_div[i].bosr << 1) | coeff_div[i].usb;
snd_soc_write(codec, WM8731_SRATE, srate);
/* bit size */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
iface |= 0x0004;
break;
case SNDRV_PCM_FORMAT_S24_LE:
iface |= 0x0008;
break;
}
snd_soc_write(codec, WM8731_IFACE, iface);
return 0;
}
static int wm8731_pcm_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
/* set active */
snd_soc_write(codec, WM8731_ACTIVE, 0x0001);
return 0;
}
static void wm8731_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
/* deactivate */
if (!codec->active) {
udelay(50);
snd_soc_write(codec, WM8731_ACTIVE, 0x0);
}
}
static int wm8731_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
u16 mute_reg = snd_soc_read(codec, WM8731_APDIGI) & 0xfff7;
if (mute)
snd_soc_write(codec, WM8731_APDIGI, mute_reg | 0x8);
else
snd_soc_write(codec, WM8731_APDIGI, mute_reg);
return 0;
}
static int wm8731_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct wm8731_priv *wm8731 = codec->private_data;
switch (freq) {
case 11289600:
case 12000000:
case 12288000:
case 16934400:
case 18432000:
wm8731->sysclk = freq;
return 0;
}
return -EINVAL;
}
static int wm8731_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 iface = 0;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
iface |= 0x0040;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= 0x0013;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0090;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0010;
break;
default:
return -EINVAL;
}
/* set iface */
snd_soc_write(codec, WM8731_IFACE, iface);
return 0;
}
static int wm8731_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
u16 reg;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* Clear PWROFF, gate CLKOUT, everything else as-is */
reg = snd_soc_read(codec, WM8731_PWR) & 0xff7f;
snd_soc_write(codec, WM8731_PWR, reg | 0x0040);
break;
case SND_SOC_BIAS_OFF:
snd_soc_write(codec, WM8731_ACTIVE, 0x0);
snd_soc_write(codec, WM8731_PWR, 0xffff);
break;
}
codec->bias_level = level;
return 0;
}
#define WM8731_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000)
#define WM8731_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_ops wm8731_dai_ops = {
.prepare = wm8731_pcm_prepare,
.hw_params = wm8731_hw_params,
.shutdown = wm8731_shutdown,
.digital_mute = wm8731_mute,
.set_sysclk = wm8731_set_dai_sysclk,
.set_fmt = wm8731_set_dai_fmt,
};
struct snd_soc_dai wm8731_dai = {
.name = "WM8731",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8731_RATES,
.formats = WM8731_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8731_RATES,
.formats = WM8731_FORMATS,},
.ops = &wm8731_dai_ops,
.symmetric_rates = 1,
};
EXPORT_SYMBOL_GPL(wm8731_dai);
#ifdef CONFIG_PM
static int wm8731_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
snd_soc_write(codec, WM8731_ACTIVE, 0x0);
wm8731_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int wm8731_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
int i;
u8 data[2];
u16 *cache = codec->reg_cache;
/* Sync reg_cache with the hardware */
for (i = 0; i < ARRAY_SIZE(wm8731_reg); i++) {
data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
data[1] = cache[i] & 0x00ff;
codec->hw_write(codec->control_data, data, 2);
}
wm8731_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
wm8731_set_bias_level(codec, codec->suspend_bias_level);
return 0;
}
#else
#define wm8731_suspend NULL
#define wm8731_resume NULL
#endif
static int wm8731_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
if (wm8731_codec == NULL) {
dev_err(&pdev->dev, "Codec device not registered\n");
return -ENODEV;
}
socdev->card->codec = wm8731_codec;
codec = wm8731_codec;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms: %d\n", ret);
goto pcm_err;
}
snd_soc_add_controls(codec, wm8731_snd_controls,
ARRAY_SIZE(wm8731_snd_controls));
wm8731_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(codec->dev, "failed to register card: %d\n", ret);
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
return ret;
}
/* power down chip */
static int wm8731_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_wm8731 = {
.probe = wm8731_probe,
.remove = wm8731_remove,
.suspend = wm8731_suspend,
.resume = wm8731_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm8731);
static int wm8731_register(struct wm8731_priv *wm8731,
enum snd_soc_control_type control)
{
int ret;
struct snd_soc_codec *codec = &wm8731->codec;
if (wm8731_codec) {
dev_err(codec->dev, "Another WM8731 is registered\n");
ret = -EINVAL;
goto err;
}
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->private_data = wm8731;
codec->name = "WM8731";
codec->owner = THIS_MODULE;
codec->bias_level = SND_SOC_BIAS_OFF;
codec->set_bias_level = wm8731_set_bias_level;
codec->dai = &wm8731_dai;
codec->num_dai = 1;
codec->reg_cache_size = WM8731_CACHEREGNUM;
codec->reg_cache = &wm8731->reg_cache;
memcpy(codec->reg_cache, wm8731_reg, sizeof(wm8731_reg));
ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
if (ret < 0) {
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
goto err;
}
ret = wm8731_reset(codec);
if (ret < 0) {
dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
goto err;
}
wm8731_dai.dev = codec->dev;
wm8731_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
/* Latch the update bits */
snd_soc_update_bits(codec, WM8731_LOUT1V, 0x100, 0);
snd_soc_update_bits(codec, WM8731_ROUT1V, 0x100, 0);
snd_soc_update_bits(codec, WM8731_LINVOL, 0x100, 0);
snd_soc_update_bits(codec, WM8731_RINVOL, 0x100, 0);
/* Disable bypass path by default */
snd_soc_update_bits(codec, WM8731_APANA, 0x4, 0);
wm8731_codec = codec;
ret = snd_soc_register_codec(codec);
if (ret != 0) {
dev_err(codec->dev, "Failed to register codec: %d\n", ret);
goto err;
}
ret = snd_soc_register_dai(&wm8731_dai);
if (ret != 0) {
dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
snd_soc_unregister_codec(codec);
goto err_codec;
}
return 0;
err_codec:
snd_soc_unregister_codec(codec);
err:
kfree(wm8731);
return ret;
}
static void wm8731_unregister(struct wm8731_priv *wm8731)
{
wm8731_set_bias_level(&wm8731->codec, SND_SOC_BIAS_OFF);
snd_soc_unregister_dai(&wm8731_dai);
snd_soc_unregister_codec(&wm8731->codec);
kfree(wm8731);
wm8731_codec = NULL;
}
#if defined(CONFIG_SPI_MASTER)
static int __devinit wm8731_spi_probe(struct spi_device *spi)
{
struct snd_soc_codec *codec;
struct wm8731_priv *wm8731;
wm8731 = kzalloc(sizeof(struct wm8731_priv), GFP_KERNEL);
if (wm8731 == NULL)
return -ENOMEM;
codec = &wm8731->codec;
codec->control_data = spi;
codec->dev = &spi->dev;
dev_set_drvdata(&spi->dev, wm8731);
return wm8731_register(wm8731, SND_SOC_SPI);
}
static int __devexit wm8731_spi_remove(struct spi_device *spi)
{
struct wm8731_priv *wm8731 = dev_get_drvdata(&spi->dev);
wm8731_unregister(wm8731);
return 0;
}
#ifdef CONFIG_PM
static int wm8731_spi_suspend(struct spi_device *spi, pm_message_t msg)
{
return snd_soc_suspend_device(&spi->dev);
}
static int wm8731_spi_resume(struct spi_device *spi)
{
return snd_soc_resume_device(&spi->dev);
}
#else
#define wm8731_spi_suspend NULL
#define wm8731_spi_resume NULL
#endif
static struct spi_driver wm8731_spi_driver = {
.driver = {
.name = "wm8731",
.bus = &spi_bus_type,
.owner = THIS_MODULE,
},
.probe = wm8731_spi_probe,
.suspend = wm8731_spi_suspend,
.resume = wm8731_spi_resume,
.remove = __devexit_p(wm8731_spi_remove),
};
#endif /* CONFIG_SPI_MASTER */
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
static __devinit int wm8731_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct wm8731_priv *wm8731;
struct snd_soc_codec *codec;
wm8731 = kzalloc(sizeof(struct wm8731_priv), GFP_KERNEL);
if (wm8731 == NULL)
return -ENOMEM;
codec = &wm8731->codec;
i2c_set_clientdata(i2c, wm8731);
codec->control_data = i2c;
codec->dev = &i2c->dev;
return wm8731_register(wm8731, SND_SOC_I2C);
}
static __devexit int wm8731_i2c_remove(struct i2c_client *client)
{
struct wm8731_priv *wm8731 = i2c_get_clientdata(client);
wm8731_unregister(wm8731);
return 0;
}
#ifdef CONFIG_PM
static int wm8731_i2c_suspend(struct i2c_client *i2c, pm_message_t msg)
{
return snd_soc_suspend_device(&i2c->dev);
}
static int wm8731_i2c_resume(struct i2c_client *i2c)
{
return snd_soc_resume_device(&i2c->dev);
}
#else
#define wm8731_i2c_suspend NULL
#define wm8731_i2c_resume NULL
#endif
static const struct i2c_device_id wm8731_i2c_id[] = {
{ "wm8731", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8731_i2c_id);
static struct i2c_driver wm8731_i2c_driver = {
.driver = {
.name = "WM8731 I2C Codec",
.owner = THIS_MODULE,
},
.probe = wm8731_i2c_probe,
.remove = __devexit_p(wm8731_i2c_remove),
.suspend = wm8731_i2c_suspend,
.resume = wm8731_i2c_resume,
.id_table = wm8731_i2c_id,
};
#endif
static int __init wm8731_modinit(void)
{
int ret;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
ret = i2c_add_driver(&wm8731_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8731 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8731_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8731 SPI driver: %d\n",
ret);
}
#endif
return 0;
}
module_init(wm8731_modinit);
static void __exit wm8731_exit(void)
{
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
i2c_del_driver(&wm8731_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8731_spi_driver);
#endif
}
module_exit(wm8731_exit);
MODULE_DESCRIPTION("ASoC WM8731 driver");
MODULE_AUTHOR("Richard Purdie");
MODULE_LICENSE("GPL");

40
kernel/sound/soc/codecs/wm8731.h Normal file
View File

@@ -0,0 +1,40 @@
/*
* wm8731.h -- WM8731 Soc Audio driver
*
* Copyright 2005 Openedhand Ltd.
*
* Author: Richard Purdie <richard@openedhand.com>
*
* Based on wm8753.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM8731_H
#define _WM8731_H
/* WM8731 register space */
#define WM8731_LINVOL 0x00
#define WM8731_RINVOL 0x01
#define WM8731_LOUT1V 0x02
#define WM8731_ROUT1V 0x03
#define WM8731_APANA 0x04
#define WM8731_APDIGI 0x05
#define WM8731_PWR 0x06
#define WM8731_IFACE 0x07
#define WM8731_SRATE 0x08
#define WM8731_ACTIVE 0x09
#define WM8731_RESET 0x0f
#define WM8731_CACHEREGNUM 10
#define WM8731_SYSCLK 0
#define WM8731_DAI 0
extern struct snd_soc_dai wm8731_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8731;
#endif

1030
kernel/sound/soc/codecs/wm8750.c Normal file
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69
kernel/sound/soc/codecs/wm8750.h Normal file
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/*
* Copyright 2005 Openedhand Ltd.
*
* Author: Richard Purdie <richard@openedhand.com>
*
* Based on WM8753.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _WM8750_H
#define _WM8750_H
/* WM8750 register space */
#define WM8750_LINVOL 0x00
#define WM8750_RINVOL 0x01
#define WM8750_LOUT1V 0x02
#define WM8750_ROUT1V 0x03
#define WM8750_ADCDAC 0x05
#define WM8750_IFACE 0x07
#define WM8750_SRATE 0x08
#define WM8750_LDAC 0x0a
#define WM8750_RDAC 0x0b
#define WM8750_BASS 0x0c
#define WM8750_TREBLE 0x0d
#define WM8750_RESET 0x0f
#define WM8750_3D 0x10
#define WM8750_ALC1 0x11
#define WM8750_ALC2 0x12
#define WM8750_ALC3 0x13
#define WM8750_NGATE 0x14
#define WM8750_LADC 0x15
#define WM8750_RADC 0x16
#define WM8750_ADCTL1 0x17
#define WM8750_ADCTL2 0x18
#define WM8750_PWR1 0x19
#define WM8750_PWR2 0x1a
#define WM8750_ADCTL3 0x1b
#define WM8750_ADCIN 0x1f
#define WM8750_LADCIN 0x20
#define WM8750_RADCIN 0x21
#define WM8750_LOUTM1 0x22
#define WM8750_LOUTM2 0x23
#define WM8750_ROUTM1 0x24
#define WM8750_ROUTM2 0x25
#define WM8750_MOUTM1 0x26
#define WM8750_MOUTM2 0x27
#define WM8750_LOUT2V 0x28
#define WM8750_ROUT2V 0x29
#define WM8750_MOUTV 0x2a
#define WM8750_CACHE_REGNUM 0x2a
#define WM8750_SYSCLK 0
struct wm8750_setup_data {
int spi;
int i2c_bus;
unsigned short i2c_address;
};
extern struct snd_soc_dai wm8750_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8750;
#endif

1914
kernel/sound/soc/codecs/wm8753.c Normal file
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121
kernel/sound/soc/codecs/wm8753.h Normal file
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/*
* wm8753.h -- audio driver for WM8753
*
* Copyright 2003 Wolfson Microelectronics PLC.
* Author: Liam Girdwood <lrg@slimlogic.co.uk>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef _WM8753_H
#define _WM8753_H
/* WM8753 register space */
#define WM8753_DAC 0x01
#define WM8753_ADC 0x02
#define WM8753_PCM 0x03
#define WM8753_HIFI 0x04
#define WM8753_IOCTL 0x05
#define WM8753_SRATE1 0x06
#define WM8753_SRATE2 0x07
#define WM8753_LDAC 0x08
#define WM8753_RDAC 0x09
#define WM8753_BASS 0x0a
#define WM8753_TREBLE 0x0b
#define WM8753_ALC1 0x0c
#define WM8753_ALC2 0x0d
#define WM8753_ALC3 0x0e
#define WM8753_NGATE 0x0f
#define WM8753_LADC 0x10
#define WM8753_RADC 0x11
#define WM8753_ADCTL1 0x12
#define WM8753_3D 0x13
#define WM8753_PWR1 0x14
#define WM8753_PWR2 0x15
#define WM8753_PWR3 0x16
#define WM8753_PWR4 0x17
#define WM8753_ID 0x18
#define WM8753_INTPOL 0x19
#define WM8753_INTEN 0x1a
#define WM8753_GPIO1 0x1b
#define WM8753_GPIO2 0x1c
#define WM8753_RESET 0x1f
#define WM8753_RECMIX1 0x20
#define WM8753_RECMIX2 0x21
#define WM8753_LOUTM1 0x22
#define WM8753_LOUTM2 0x23
#define WM8753_ROUTM1 0x24
#define WM8753_ROUTM2 0x25
#define WM8753_MOUTM1 0x26
#define WM8753_MOUTM2 0x27
#define WM8753_LOUT1V 0x28
#define WM8753_ROUT1V 0x29
#define WM8753_LOUT2V 0x2a
#define WM8753_ROUT2V 0x2b
#define WM8753_MOUTV 0x2c
#define WM8753_OUTCTL 0x2d
#define WM8753_ADCIN 0x2e
#define WM8753_INCTL1 0x2f
#define WM8753_INCTL2 0x30
#define WM8753_LINVOL 0x31
#define WM8753_RINVOL 0x32
#define WM8753_MICBIAS 0x33
#define WM8753_CLOCK 0x34
#define WM8753_PLL1CTL1 0x35
#define WM8753_PLL1CTL2 0x36
#define WM8753_PLL1CTL3 0x37
#define WM8753_PLL1CTL4 0x38
#define WM8753_PLL2CTL1 0x39
#define WM8753_PLL2CTL2 0x3a
#define WM8753_PLL2CTL3 0x3b
#define WM8753_PLL2CTL4 0x3c
#define WM8753_BIASCTL 0x3d
#define WM8753_ADCTL2 0x3f
#define WM8753_PLL1 0
#define WM8753_PLL2 1
/* clock inputs */
#define WM8753_MCLK 0
#define WM8753_PCMCLK 1
/* clock divider id's */
#define WM8753_PCMDIV 0
#define WM8753_BCLKDIV 1
#define WM8753_VXCLKDIV 2
/* PCM clock dividers */
#define WM8753_PCM_DIV_1 (0 << 6)
#define WM8753_PCM_DIV_3 (2 << 6)
#define WM8753_PCM_DIV_5_5 (3 << 6)
#define WM8753_PCM_DIV_2 (4 << 6)
#define WM8753_PCM_DIV_4 (5 << 6)
#define WM8753_PCM_DIV_6 (6 << 6)
#define WM8753_PCM_DIV_8 (7 << 6)
/* BCLK clock dividers */
#define WM8753_BCLK_DIV_1 (0 << 3)
#define WM8753_BCLK_DIV_2 (1 << 3)
#define WM8753_BCLK_DIV_4 (2 << 3)
#define WM8753_BCLK_DIV_8 (3 << 3)
#define WM8753_BCLK_DIV_16 (4 << 3)
/* VXCLK clock dividers */
#define WM8753_VXCLK_DIV_1 (0 << 6)
#define WM8753_VXCLK_DIV_2 (1 << 6)
#define WM8753_VXCLK_DIV_4 (2 << 6)
#define WM8753_VXCLK_DIV_8 (3 << 6)
#define WM8753_VXCLK_DIV_16 (4 << 6)
#define WM8753_DAI_HIFI 0
#define WM8753_DAI_VOICE 1
extern struct snd_soc_dai wm8753_dai[2];
extern struct snd_soc_codec_device soc_codec_dev_wm8753;
#endif

736
kernel/sound/soc/codecs/wm8776.c Normal file
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/*
* wm8776.c -- WM8776 ALSA SoC Audio driver
*
* Copyright 2009 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* TODO: Input ALC/limiter support
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8776.h"
static struct snd_soc_codec *wm8776_codec;
struct snd_soc_codec_device soc_codec_dev_wm8776;
/* codec private data */
struct wm8776_priv {
struct snd_soc_codec codec;
u16 reg_cache[WM8776_CACHEREGNUM];
int sysclk[2];
};
#ifdef CONFIG_SPI_MASTER
static int wm8776_spi_write(struct spi_device *spi, const char *data, int len);
#endif
static const u16 wm8776_reg[WM8776_CACHEREGNUM] = {
0x79, 0x79, 0x79, 0xff, 0xff, /* 4 */
0xff, 0x00, 0x90, 0x00, 0x00, /* 9 */
0x22, 0x22, 0x22, 0x08, 0xcf, /* 14 */
0xcf, 0x7b, 0x00, 0x32, 0x00, /* 19 */
0xa6, 0x01, 0x01
};
static int wm8776_reset(struct snd_soc_codec *codec)
{
return snd_soc_write(codec, WM8776_RESET, 0);
}
static const DECLARE_TLV_DB_SCALE(hp_tlv, -12100, 100, 1);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
static const DECLARE_TLV_DB_SCALE(adc_tlv, -10350, 50, 1);
static const struct snd_kcontrol_new wm8776_snd_controls[] = {
SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8776_HPLVOL, WM8776_HPRVOL,
0, 127, 0, hp_tlv),
SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8776_DACLVOL, WM8776_DACRVOL,
0, 255, 0, dac_tlv),
SOC_SINGLE("Digital Playback ZC Switch", WM8776_DACCTRL1, 0, 1, 0),
SOC_SINGLE("Deemphasis Switch", WM8776_DACCTRL2, 0, 1, 0),
SOC_DOUBLE_R_TLV("Capture Volume", WM8776_ADCLVOL, WM8776_ADCRVOL,
0, 255, 0, adc_tlv),
SOC_DOUBLE("Capture Switch", WM8776_ADCMUX, 7, 6, 1, 1),
SOC_DOUBLE_R("Capture ZC Switch", WM8776_ADCLVOL, WM8776_ADCRVOL, 8, 1, 0),
SOC_SINGLE("Capture HPF Switch", WM8776_ADCIFCTRL, 8, 1, 1),
};
static const struct snd_kcontrol_new inmix_controls[] = {
SOC_DAPM_SINGLE("AIN1 Switch", WM8776_ADCMUX, 0, 1, 0),
SOC_DAPM_SINGLE("AIN2 Switch", WM8776_ADCMUX, 1, 1, 0),
SOC_DAPM_SINGLE("AIN3 Switch", WM8776_ADCMUX, 2, 1, 0),
SOC_DAPM_SINGLE("AIN4 Switch", WM8776_ADCMUX, 3, 1, 0),
SOC_DAPM_SINGLE("AIN5 Switch", WM8776_ADCMUX, 4, 1, 0),
};
static const struct snd_kcontrol_new outmix_controls[] = {
SOC_DAPM_SINGLE("DAC Switch", WM8776_OUTMUX, 0, 1, 0),
SOC_DAPM_SINGLE("AUX Switch", WM8776_OUTMUX, 1, 1, 0),
SOC_DAPM_SINGLE("Bypass Switch", WM8776_OUTMUX, 2, 1, 0),
};
static const struct snd_soc_dapm_widget wm8776_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("AUX"),
SND_SOC_DAPM_INPUT("AIN1"),
SND_SOC_DAPM_INPUT("AIN2"),
SND_SOC_DAPM_INPUT("AIN3"),
SND_SOC_DAPM_INPUT("AIN4"),
SND_SOC_DAPM_INPUT("AIN5"),
SND_SOC_DAPM_MIXER("Input Mixer", WM8776_PWRDOWN, 6, 1,
inmix_controls, ARRAY_SIZE(inmix_controls)),
SND_SOC_DAPM_ADC("ADC", "Capture", WM8776_PWRDOWN, 1, 1),
SND_SOC_DAPM_DAC("DAC", "Playback", WM8776_PWRDOWN, 2, 1),
SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
outmix_controls, ARRAY_SIZE(outmix_controls)),
SND_SOC_DAPM_PGA("Headphone PGA", WM8776_PWRDOWN, 3, 1, NULL, 0),
SND_SOC_DAPM_OUTPUT("VOUT"),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
};
static const struct snd_soc_dapm_route routes[] = {
{ "Input Mixer", "AIN1 Switch", "AIN1" },
{ "Input Mixer", "AIN2 Switch", "AIN2" },
{ "Input Mixer", "AIN3 Switch", "AIN3" },
{ "Input Mixer", "AIN4 Switch", "AIN4" },
{ "Input Mixer", "AIN5 Switch", "AIN5" },
{ "ADC", NULL, "Input Mixer" },
{ "Output Mixer", "DAC Switch", "DAC" },
{ "Output Mixer", "AUX Switch", "AUX" },
{ "Output Mixer", "Bypass Switch", "Input Mixer" },
{ "VOUT", NULL, "Output Mixer" },
{ "Headphone PGA", NULL, "Output Mixer" },
{ "HPOUTL", NULL, "Headphone PGA" },
{ "HPOUTR", NULL, "Headphone PGA" },
};
static int wm8776_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_codec *codec = dai->codec;
int reg, iface, master;
switch (dai->id) {
case WM8776_DAI_DAC:
reg = WM8776_DACIFCTRL;
master = 0x80;
break;
case WM8776_DAI_ADC:
reg = WM8776_ADCIFCTRL;
master = 0x100;
break;
default:
return -EINVAL;
}
iface = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
break;
case SND_SOC_DAIFMT_CBS_CFS:
master = 0;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0001;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x00c;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x008;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x004;
break;
default:
return -EINVAL;
}
/* Finally, write out the values */
snd_soc_update_bits(codec, reg, 0xf, iface);
snd_soc_update_bits(codec, WM8776_MSTRCTRL, 0x180, master);
return 0;
}
static int mclk_ratios[] = {
128,
192,
256,
384,
512,
768,
};
static int wm8776_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct wm8776_priv *wm8776 = codec->private_data;
int iface_reg, iface;
int ratio_shift, master;
int i;
iface = 0;
switch (dai->id) {
case WM8776_DAI_DAC:
iface_reg = WM8776_DACIFCTRL;
master = 0x80;
ratio_shift = 4;
break;
case WM8776_DAI_ADC:
iface_reg = WM8776_ADCIFCTRL;
master = 0x100;
ratio_shift = 0;
break;
default:
return -EINVAL;
}
/* Set word length */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
iface |= 0x10;
break;
case SNDRV_PCM_FORMAT_S24_LE:
iface |= 0x20;
break;
case SNDRV_PCM_FORMAT_S32_LE:
iface |= 0x30;
break;
}
/* Only need to set MCLK/LRCLK ratio if we're master */
if (snd_soc_read(codec, WM8776_MSTRCTRL) & master) {
for (i = 0; i < ARRAY_SIZE(mclk_ratios); i++) {
if (wm8776->sysclk[dai->id] / params_rate(params)
== mclk_ratios[i])
break;
}
if (i == ARRAY_SIZE(mclk_ratios)) {
dev_err(codec->dev,
"Unable to configure MCLK ratio %d/%d\n",
wm8776->sysclk[dai->id], params_rate(params));
return -EINVAL;
}
dev_dbg(codec->dev, "MCLK is %dfs\n", mclk_ratios[i]);
snd_soc_update_bits(codec, WM8776_MSTRCTRL,
0x7 << ratio_shift, i << ratio_shift);
} else {
dev_dbg(codec->dev, "DAI in slave mode\n");
}
snd_soc_update_bits(codec, iface_reg, 0x30, iface);
return 0;
}
static int wm8776_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
return snd_soc_write(codec, WM8776_DACMUTE, !!mute);
}
static int wm8776_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = dai->codec;
struct wm8776_priv *wm8776 = codec->private_data;
BUG_ON(dai->id >= ARRAY_SIZE(wm8776->sysclk));
wm8776->sysclk[dai->id] = freq;
return 0;
}
static int wm8776_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (codec->bias_level == SND_SOC_BIAS_OFF) {
/* Disable the global powerdown; DAPM does the rest */
snd_soc_update_bits(codec, WM8776_PWRDOWN, 1, 0);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_update_bits(codec, WM8776_PWRDOWN, 1, 1);
break;
}
codec->bias_level = level;
return 0;
}
#define WM8776_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000)
#define WM8776_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_ops wm8776_dac_ops = {
.digital_mute = wm8776_mute,
.hw_params = wm8776_hw_params,
.set_fmt = wm8776_set_fmt,
.set_sysclk = wm8776_set_sysclk,
};
static struct snd_soc_dai_ops wm8776_adc_ops = {
.hw_params = wm8776_hw_params,
.set_fmt = wm8776_set_fmt,
.set_sysclk = wm8776_set_sysclk,
};
struct snd_soc_dai wm8776_dai[] = {
{
.name = "WM8776 Playback",
.id = WM8776_DAI_DAC,
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = WM8776_RATES,
.formats = WM8776_FORMATS,
},
.ops = &wm8776_dac_ops,
},
{
.name = "WM8776 Capture",
.id = WM8776_DAI_ADC,
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = WM8776_RATES,
.formats = WM8776_FORMATS,
},
.ops = &wm8776_adc_ops,
},
};
EXPORT_SYMBOL_GPL(wm8776_dai);
#ifdef CONFIG_PM
static int wm8776_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
wm8776_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int wm8776_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
int i;
u8 data[2];
u16 *cache = codec->reg_cache;
/* Sync reg_cache with the hardware */
for (i = 0; i < ARRAY_SIZE(wm8776_reg); i++) {
data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
data[1] = cache[i] & 0x00ff;
codec->hw_write(codec->control_data, data, 2);
}
wm8776_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
return 0;
}
#else
#define wm8776_suspend NULL
#define wm8776_resume NULL
#endif
static int wm8776_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
if (wm8776_codec == NULL) {
dev_err(&pdev->dev, "Codec device not registered\n");
return -ENODEV;
}
socdev->card->codec = wm8776_codec;
codec = wm8776_codec;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms: %d\n", ret);
goto pcm_err;
}
snd_soc_add_controls(codec, wm8776_snd_controls,
ARRAY_SIZE(wm8776_snd_controls));
snd_soc_dapm_new_controls(codec, wm8776_dapm_widgets,
ARRAY_SIZE(wm8776_dapm_widgets));
snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes));
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(codec->dev, "failed to register card: %d\n", ret);
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
return ret;
}
/* power down chip */
static int wm8776_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_wm8776 = {
.probe = wm8776_probe,
.remove = wm8776_remove,
.suspend = wm8776_suspend,
.resume = wm8776_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm8776);
static int wm8776_register(struct wm8776_priv *wm8776,
enum snd_soc_control_type control)
{
int ret, i;
struct snd_soc_codec *codec = &wm8776->codec;
if (wm8776_codec) {
dev_err(codec->dev, "Another WM8776 is registered\n");
ret = -EINVAL;
goto err;
}
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->private_data = wm8776;
codec->name = "WM8776";
codec->owner = THIS_MODULE;
codec->bias_level = SND_SOC_BIAS_OFF;
codec->set_bias_level = wm8776_set_bias_level;
codec->dai = wm8776_dai;
codec->num_dai = ARRAY_SIZE(wm8776_dai);
codec->reg_cache_size = WM8776_CACHEREGNUM;
codec->reg_cache = &wm8776->reg_cache;
memcpy(codec->reg_cache, wm8776_reg, sizeof(wm8776_reg));
ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
if (ret < 0) {
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
goto err;
}
for (i = 0; i < ARRAY_SIZE(wm8776_dai); i++)
wm8776_dai[i].dev = codec->dev;
ret = wm8776_reset(codec);
if (ret < 0) {
dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
goto err;
}
wm8776_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
/* Latch the update bits; right channel only since we always
* update both. */
snd_soc_update_bits(codec, WM8776_HPRVOL, 0x100, 0x100);
snd_soc_update_bits(codec, WM8776_DACRVOL, 0x100, 0x100);
wm8776_codec = codec;
ret = snd_soc_register_codec(codec);
if (ret != 0) {
dev_err(codec->dev, "Failed to register codec: %d\n", ret);
goto err;
}
ret = snd_soc_register_dais(wm8776_dai, ARRAY_SIZE(wm8776_dai));
if (ret != 0) {
dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
goto err_codec;
}
return 0;
err_codec:
snd_soc_unregister_codec(codec);
err:
kfree(wm8776);
return ret;
}
static void wm8776_unregister(struct wm8776_priv *wm8776)
{
wm8776_set_bias_level(&wm8776->codec, SND_SOC_BIAS_OFF);
snd_soc_unregister_dais(wm8776_dai, ARRAY_SIZE(wm8776_dai));
snd_soc_unregister_codec(&wm8776->codec);
kfree(wm8776);
wm8776_codec = NULL;
}
#if defined(CONFIG_SPI_MASTER)
static int wm8776_spi_write(struct spi_device *spi, const char *data, int len)
{
struct spi_transfer t;
struct spi_message m;
u8 msg[2];
if (len <= 0)
return 0;
msg[0] = data[0];
msg[1] = data[1];
spi_message_init(&m);
memset(&t, 0, (sizeof t));
t.tx_buf = &msg[0];
t.len = len;
spi_message_add_tail(&t, &m);
spi_sync(spi, &m);
return len;
}
static int __devinit wm8776_spi_probe(struct spi_device *spi)
{
struct snd_soc_codec *codec;
struct wm8776_priv *wm8776;
wm8776 = kzalloc(sizeof(struct wm8776_priv), GFP_KERNEL);
if (wm8776 == NULL)
return -ENOMEM;
codec = &wm8776->codec;
codec->control_data = spi;
codec->hw_write = (hw_write_t)wm8776_spi_write;
codec->dev = &spi->dev;
dev_set_drvdata(&spi->dev, wm8776);
return wm8776_register(wm8776, SND_SOC_SPI);
}
static int __devexit wm8776_spi_remove(struct spi_device *spi)
{
struct wm8776_priv *wm8776 = dev_get_drvdata(&spi->dev);
wm8776_unregister(wm8776);
return 0;
}
#ifdef CONFIG_PM
static int wm8776_spi_suspend(struct spi_device *spi, pm_message_t msg)
{
return snd_soc_suspend_device(&spi->dev);
}
static int wm8776_spi_resume(struct spi_device *spi)
{
return snd_soc_resume_device(&spi->dev);
}
#else
#define wm8776_spi_suspend NULL
#define wm8776_spi_resume NULL
#endif
static struct spi_driver wm8776_spi_driver = {
.driver = {
.name = "wm8776",
.bus = &spi_bus_type,
.owner = THIS_MODULE,
},
.probe = wm8776_spi_probe,
.suspend = wm8776_spi_suspend,
.resume = wm8776_spi_resume,
.remove = __devexit_p(wm8776_spi_remove),
};
#endif /* CONFIG_SPI_MASTER */
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
static __devinit int wm8776_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct wm8776_priv *wm8776;
struct snd_soc_codec *codec;
wm8776 = kzalloc(sizeof(struct wm8776_priv), GFP_KERNEL);
if (wm8776 == NULL)
return -ENOMEM;
codec = &wm8776->codec;
codec->hw_write = (hw_write_t)i2c_master_send;
i2c_set_clientdata(i2c, wm8776);
codec->control_data = i2c;
codec->dev = &i2c->dev;
return wm8776_register(wm8776, SND_SOC_I2C);
}
static __devexit int wm8776_i2c_remove(struct i2c_client *client)
{
struct wm8776_priv *wm8776 = i2c_get_clientdata(client);
wm8776_unregister(wm8776);
return 0;
}
#ifdef CONFIG_PM
static int wm8776_i2c_suspend(struct i2c_client *i2c, pm_message_t msg)
{
return snd_soc_suspend_device(&i2c->dev);
}
static int wm8776_i2c_resume(struct i2c_client *i2c)
{
return snd_soc_resume_device(&i2c->dev);
}
#else
#define wm8776_i2c_suspend NULL
#define wm8776_i2c_resume NULL
#endif
static const struct i2c_device_id wm8776_i2c_id[] = {
{ "wm8776", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8776_i2c_id);
static struct i2c_driver wm8776_i2c_driver = {
.driver = {
.name = "wm8776",
.owner = THIS_MODULE,
},
.probe = wm8776_i2c_probe,
.remove = __devexit_p(wm8776_i2c_remove),
.suspend = wm8776_i2c_suspend,
.resume = wm8776_i2c_resume,
.id_table = wm8776_i2c_id,
};
#endif
static int __init wm8776_modinit(void)
{
int ret;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
ret = i2c_add_driver(&wm8776_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8776 I2C driver: %d\n",
ret);
}
#endif
#if defined(CONFIG_SPI_MASTER)
ret = spi_register_driver(&wm8776_spi_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8776 SPI driver: %d\n",
ret);
}
#endif
return 0;
}
module_init(wm8776_modinit);
static void __exit wm8776_exit(void)
{
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
i2c_del_driver(&wm8776_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
spi_unregister_driver(&wm8776_spi_driver);
#endif
}
module_exit(wm8776_exit);
MODULE_DESCRIPTION("ASoC WM8776 driver");
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
MODULE_LICENSE("GPL");

51
kernel/sound/soc/codecs/wm8776.h Normal file
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/*
* wm8776.h -- WM8776 ASoC driver
*
* Copyright 2009 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM8776_H
#define _WM8776_H
/* Registers */
#define WM8776_HPLVOL 0x00
#define WM8776_HPRVOL 0x01
#define WM8776_HPMASTER 0x02
#define WM8776_DACLVOL 0x03
#define WM8776_DACRVOL 0x04
#define WM8776_DACMASTER 0x05
#define WM8776_PHASESWAP 0x06
#define WM8776_DACCTRL1 0x07
#define WM8776_DACMUTE 0x08
#define WM8776_DACCTRL2 0x09
#define WM8776_DACIFCTRL 0x0a
#define WM8776_ADCIFCTRL 0x0b
#define WM8776_MSTRCTRL 0x0c
#define WM8776_PWRDOWN 0x0d
#define WM8776_ADCLVOL 0x0e
#define WM8776_ADCRVOL 0x0f
#define WM8776_ALCCTRL1 0x10
#define WM8776_ALCCTRL2 0x11
#define WM8776_ALCCTRL3 0x12
#define WM8776_NOISEGATE 0x13
#define WM8776_LIMITER 0x14
#define WM8776_ADCMUX 0x15
#define WM8776_OUTMUX 0x16
#define WM8776_RESET 0x17
#define WM8776_CACHEREGNUM 0x17
#define WM8776_DAI_DAC 0
#define WM8776_DAI_ADC 1
extern struct snd_soc_dai wm8776_dai[];
extern struct snd_soc_codec_device soc_codec_dev_wm8776;
#endif

1421
kernel/sound/soc/codecs/wm8900.c Normal file
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58
kernel/sound/soc/codecs/wm8900.h Normal file
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/*
* wm8900.h -- WM890 Soc Audio driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM8900_H
#define _WM8900_H
#define WM8900_FLL 1
#define WM8900_BCLK_DIV 1
#define WM8900_ADC_CLKDIV 2
#define WM8900_DAC_CLKDIV 3
#define WM8900_ADC_LRCLK 4
#define WM8900_DAC_LRCLK 5
#define WM8900_OPCLK_DIV 6
#define WM8900_LRCLK_MODE 7
#define WM8900_BCLK_DIV_1 0x00
#define WM8900_BCLK_DIV_1_5 0x02
#define WM8900_BCLK_DIV_2 0x04
#define WM8900_BCLK_DIV_3 0x06
#define WM8900_BCLK_DIV_4 0x08
#define WM8900_BCLK_DIV_5_5 0x0a
#define WM8900_BCLK_DIV_6 0x0c
#define WM8900_BCLK_DIV_8 0x0e
#define WM8900_BCLK_DIV_11 0x10
#define WM8900_BCLK_DIV_12 0x12
#define WM8900_BCLK_DIV_16 0x14
#define WM8900_BCLK_DIV_22 0x16
#define WM8900_BCLK_DIV_24 0x18
#define WM8900_BCLK_DIV_32 0x1a
#define WM8900_BCLK_DIV_44 0x1c
#define WM8900_BCLK_DIV_48 0x1e
#define WM8900_ADC_CLKDIV_1 0x00
#define WM8900_ADC_CLKDIV_1_5 0x20
#define WM8900_ADC_CLKDIV_2 0x40
#define WM8900_ADC_CLKDIV_3 0x60
#define WM8900_ADC_CLKDIV_4 0x80
#define WM8900_ADC_CLKDIV_5_5 0xa0
#define WM8900_ADC_CLKDIV_6 0xc0
#define WM8900_DAC_CLKDIV_1 0x00
#define WM8900_DAC_CLKDIV_1_5 0x04
#define WM8900_DAC_CLKDIV_2 0x08
#define WM8900_DAC_CLKDIV_3 0x0c
#define WM8900_DAC_CLKDIV_4 0x10
#define WM8900_DAC_CLKDIV_5_5 0x14
#define WM8900_DAC_CLKDIV_6 0x18
extern struct snd_soc_dai wm8900_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8900;
#endif

1768
kernel/sound/soc/codecs/wm8903.c Normal file
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1458
kernel/sound/soc/codecs/wm8903.h Normal file
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933
kernel/sound/soc/codecs/wm8940.c Normal file
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/*
* wm8940.c -- WM8940 ALSA Soc Audio driver
*
* Author: Jonathan Cameron <jic23@cam.ac.uk>
*
* Based on wm8510.c
* Copyright 2006 Wolfson Microelectronics PLC.
* Author: Liam Girdwood <lrg@slimlogic.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Not currently handled:
* Notch filter control
* AUXMode (inverting vs mixer)
* No means to obtain current gain if alc enabled.
* No use made of gpio
* Fast VMID discharge for power down
* Soft Start
* DLR and ALR Swaps not enabled
* Digital Sidetone not supported
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8940.h"
struct wm8940_priv {
unsigned int sysclk;
u16 reg_cache[WM8940_CACHEREGNUM];
struct snd_soc_codec codec;
};
static u16 wm8940_reg_defaults[] = {
0x8940, /* Soft Reset */
0x0000, /* Power 1 */
0x0000, /* Power 2 */
0x0000, /* Power 3 */
0x0010, /* Interface Control */
0x0000, /* Companding Control */
0x0140, /* Clock Control */
0x0000, /* Additional Controls */
0x0000, /* GPIO Control */
0x0002, /* Auto Increment Control */
0x0000, /* DAC Control */
0x00FF, /* DAC Volume */
0,
0,
0x0100, /* ADC Control */
0x00FF, /* ADC Volume */
0x0000, /* Notch Filter 1 Control 1 */
0x0000, /* Notch Filter 1 Control 2 */
0x0000, /* Notch Filter 2 Control 1 */
0x0000, /* Notch Filter 2 Control 2 */
0x0000, /* Notch Filter 3 Control 1 */
0x0000, /* Notch Filter 3 Control 2 */
0x0000, /* Notch Filter 4 Control 1 */
0x0000, /* Notch Filter 4 Control 2 */
0x0032, /* DAC Limit Control 1 */
0x0000, /* DAC Limit Control 2 */
0,
0,
0,
0,
0,
0,
0x0038, /* ALC Control 1 */
0x000B, /* ALC Control 2 */
0x0032, /* ALC Control 3 */
0x0000, /* Noise Gate */
0x0041, /* PLLN */
0x000C, /* PLLK1 */
0x0093, /* PLLK2 */
0x00E9, /* PLLK3 */
0,
0,
0x0030, /* ALC Control 4 */
0,
0x0002, /* Input Control */
0x0050, /* PGA Gain */
0,
0x0002, /* ADC Boost Control */
0,
0x0002, /* Output Control */
0x0000, /* Speaker Mixer Control */
0,
0,
0,
0x0079, /* Speaker Volume */
0,
0x0000, /* Mono Mixer Control */
};
static const char *wm8940_companding[] = { "Off", "NC", "u-law", "A-law" };
static const struct soc_enum wm8940_adc_companding_enum
= SOC_ENUM_SINGLE(WM8940_COMPANDINGCTL, 1, 4, wm8940_companding);
static const struct soc_enum wm8940_dac_companding_enum
= SOC_ENUM_SINGLE(WM8940_COMPANDINGCTL, 3, 4, wm8940_companding);
static const char *wm8940_alc_mode_text[] = {"ALC", "Limiter"};
static const struct soc_enum wm8940_alc_mode_enum
= SOC_ENUM_SINGLE(WM8940_ALC3, 8, 2, wm8940_alc_mode_text);
static const char *wm8940_mic_bias_level_text[] = {"0.9", "0.65"};
static const struct soc_enum wm8940_mic_bias_level_enum
= SOC_ENUM_SINGLE(WM8940_INPUTCTL, 8, 2, wm8940_mic_bias_level_text);
static const char *wm8940_filter_mode_text[] = {"Audio", "Application"};
static const struct soc_enum wm8940_filter_mode_enum
= SOC_ENUM_SINGLE(WM8940_ADC, 7, 2, wm8940_filter_mode_text);
static DECLARE_TLV_DB_SCALE(wm8940_spk_vol_tlv, -5700, 100, 1);
static DECLARE_TLV_DB_SCALE(wm8940_att_tlv, -1000, 1000, 0);
static DECLARE_TLV_DB_SCALE(wm8940_pga_vol_tlv, -1200, 75, 0);
static DECLARE_TLV_DB_SCALE(wm8940_alc_min_tlv, -1200, 600, 0);
static DECLARE_TLV_DB_SCALE(wm8940_alc_max_tlv, 675, 600, 0);
static DECLARE_TLV_DB_SCALE(wm8940_alc_tar_tlv, -2250, 50, 0);
static DECLARE_TLV_DB_SCALE(wm8940_lim_boost_tlv, 0, 100, 0);
static DECLARE_TLV_DB_SCALE(wm8940_lim_thresh_tlv, -600, 100, 0);
static DECLARE_TLV_DB_SCALE(wm8940_adc_tlv, -12750, 50, 1);
static DECLARE_TLV_DB_SCALE(wm8940_capture_boost_vol_tlv, 0, 2000, 0);
static const struct snd_kcontrol_new wm8940_snd_controls[] = {
SOC_SINGLE("Digital Loopback Switch", WM8940_COMPANDINGCTL,
6, 1, 0),
SOC_ENUM("DAC Companding", wm8940_dac_companding_enum),
SOC_ENUM("ADC Companding", wm8940_adc_companding_enum),
SOC_ENUM("ALC Mode", wm8940_alc_mode_enum),
SOC_SINGLE("ALC Switch", WM8940_ALC1, 8, 1, 0),
SOC_SINGLE_TLV("ALC Capture Max Gain", WM8940_ALC1,
3, 7, 1, wm8940_alc_max_tlv),
SOC_SINGLE_TLV("ALC Capture Min Gain", WM8940_ALC1,
0, 7, 0, wm8940_alc_min_tlv),
SOC_SINGLE_TLV("ALC Capture Target", WM8940_ALC2,
0, 14, 0, wm8940_alc_tar_tlv),
SOC_SINGLE("ALC Capture Hold", WM8940_ALC2, 4, 10, 0),
SOC_SINGLE("ALC Capture Decay", WM8940_ALC3, 4, 10, 0),
SOC_SINGLE("ALC Capture Attach", WM8940_ALC3, 0, 10, 0),
SOC_SINGLE("ALC ZC Switch", WM8940_ALC4, 1, 1, 0),
SOC_SINGLE("ALC Capture Noise Gate Switch", WM8940_NOISEGATE,
3, 1, 0),
SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8940_NOISEGATE,
0, 7, 0),
SOC_SINGLE("DAC Playback Limiter Switch", WM8940_DACLIM1, 8, 1, 0),
SOC_SINGLE("DAC Playback Limiter Attack", WM8940_DACLIM1, 0, 9, 0),
SOC_SINGLE("DAC Playback Limiter Decay", WM8940_DACLIM1, 4, 11, 0),
SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8940_DACLIM2,
4, 9, 1, wm8940_lim_thresh_tlv),
SOC_SINGLE_TLV("DAC Playback Limiter Boost", WM8940_DACLIM2,
0, 12, 0, wm8940_lim_boost_tlv),
SOC_SINGLE("Capture PGA ZC Switch", WM8940_PGAGAIN, 7, 1, 0),
SOC_SINGLE_TLV("Capture PGA Volume", WM8940_PGAGAIN,
0, 63, 0, wm8940_pga_vol_tlv),
SOC_SINGLE_TLV("Digital Playback Volume", WM8940_DACVOL,
0, 255, 0, wm8940_adc_tlv),
SOC_SINGLE_TLV("Digital Capture Volume", WM8940_ADCVOL,
0, 255, 0, wm8940_adc_tlv),
SOC_ENUM("Mic Bias Level", wm8940_mic_bias_level_enum),
SOC_SINGLE_TLV("Capture Boost Volue", WM8940_ADCBOOST,
8, 1, 0, wm8940_capture_boost_vol_tlv),
SOC_SINGLE_TLV("Speaker Playback Volume", WM8940_SPKVOL,
0, 63, 0, wm8940_spk_vol_tlv),
SOC_SINGLE("Speaker Playback Switch", WM8940_SPKVOL, 6, 1, 1),
SOC_SINGLE_TLV("Speaker Mixer Line Bypass Volume", WM8940_SPKVOL,
8, 1, 1, wm8940_att_tlv),
SOC_SINGLE("Speaker Playback ZC Switch", WM8940_SPKVOL, 7, 1, 0),
SOC_SINGLE("Mono Out Switch", WM8940_MONOMIX, 6, 1, 1),
SOC_SINGLE_TLV("Mono Mixer Line Bypass Volume", WM8940_MONOMIX,
7, 1, 1, wm8940_att_tlv),
SOC_SINGLE("High Pass Filter Switch", WM8940_ADC, 8, 1, 0),
SOC_ENUM("High Pass Filter Mode", wm8940_filter_mode_enum),
SOC_SINGLE("High Pass Filter Cut Off", WM8940_ADC, 4, 7, 0),
SOC_SINGLE("ADC Inversion Switch", WM8940_ADC, 0, 1, 0),
SOC_SINGLE("DAC Inversion Switch", WM8940_DAC, 0, 1, 0),
SOC_SINGLE("DAC Auto Mute Switch", WM8940_DAC, 2, 1, 0),
SOC_SINGLE("ZC Timeout Clock Switch", WM8940_ADDCNTRL, 0, 1, 0),
};
static const struct snd_kcontrol_new wm8940_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8940_SPKMIX, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8940_SPKMIX, 5, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8940_SPKMIX, 0, 1, 0),
};
static const struct snd_kcontrol_new wm8940_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8940_MONOMIX, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8940_MONOMIX, 2, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8940_MONOMIX, 0, 1, 0),
};
static DECLARE_TLV_DB_SCALE(wm8940_boost_vol_tlv, -1500, 300, 1);
static const struct snd_kcontrol_new wm8940_input_boost_controls[] = {
SOC_DAPM_SINGLE("Mic PGA Switch", WM8940_PGAGAIN, 6, 1, 1),
SOC_DAPM_SINGLE_TLV("Aux Volume", WM8940_ADCBOOST,
0, 7, 0, wm8940_boost_vol_tlv),
SOC_DAPM_SINGLE_TLV("Mic Volume", WM8940_ADCBOOST,
4, 7, 0, wm8940_boost_vol_tlv),
};
static const struct snd_kcontrol_new wm8940_micpga_controls[] = {
SOC_DAPM_SINGLE("AUX Switch", WM8940_INPUTCTL, 2, 1, 0),
SOC_DAPM_SINGLE("MICP Switch", WM8940_INPUTCTL, 0, 1, 0),
SOC_DAPM_SINGLE("MICN Switch", WM8940_INPUTCTL, 1, 1, 0),
};
static const struct snd_soc_dapm_widget wm8940_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Speaker Mixer", WM8940_POWER3, 2, 0,
&wm8940_speaker_mixer_controls[0],
ARRAY_SIZE(wm8940_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", WM8940_POWER3, 3, 0,
&wm8940_mono_mixer_controls[0],
ARRAY_SIZE(wm8940_mono_mixer_controls)),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8940_POWER3, 0, 0),
SND_SOC_DAPM_PGA("SpkN Out", WM8940_POWER3, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("SpkP Out", WM8940_POWER3, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out", WM8940_POWER3, 7, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_OUTPUT("SPKOUTP"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
SND_SOC_DAPM_PGA("Aux Input", WM8940_POWER1, 6, 0, NULL, 0),
SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8940_POWER2, 0, 0),
SND_SOC_DAPM_MIXER("Mic PGA", WM8940_POWER2, 2, 0,
&wm8940_micpga_controls[0],
ARRAY_SIZE(wm8940_micpga_controls)),
SND_SOC_DAPM_MIXER("Boost Mixer", WM8940_POWER2, 4, 0,
&wm8940_input_boost_controls[0],
ARRAY_SIZE(wm8940_input_boost_controls)),
SND_SOC_DAPM_MICBIAS("Mic Bias", WM8940_POWER1, 4, 0),
SND_SOC_DAPM_INPUT("MICN"),
SND_SOC_DAPM_INPUT("MICP"),
SND_SOC_DAPM_INPUT("AUX"),
};
static const struct snd_soc_dapm_route audio_map[] = {
/* Mono output mixer */
{"Mono Mixer", "PCM Playback Switch", "DAC"},
{"Mono Mixer", "Aux Playback Switch", "Aux Input"},
{"Mono Mixer", "Line Bypass Switch", "Boost Mixer"},
/* Speaker output mixer */
{"Speaker Mixer", "PCM Playback Switch", "DAC"},
{"Speaker Mixer", "Aux Playback Switch", "Aux Input"},
{"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"},
/* Outputs */
{"Mono Out", NULL, "Mono Mixer"},
{"MONOOUT", NULL, "Mono Out"},
{"SpkN Out", NULL, "Speaker Mixer"},
{"SpkP Out", NULL, "Speaker Mixer"},
{"SPKOUTN", NULL, "SpkN Out"},
{"SPKOUTP", NULL, "SpkP Out"},
/* Microphone PGA */
{"Mic PGA", "MICN Switch", "MICN"},
{"Mic PGA", "MICP Switch", "MICP"},
{"Mic PGA", "AUX Switch", "AUX"},
/* Boost Mixer */
{"Boost Mixer", "Mic PGA Switch", "Mic PGA"},
{"Boost Mixer", "Mic Volume", "MICP"},
{"Boost Mixer", "Aux Volume", "Aux Input"},
{"ADC", NULL, "Boost Mixer"},
};
static int wm8940_add_widgets(struct snd_soc_codec *codec)
{
int ret;
ret = snd_soc_dapm_new_controls(codec, wm8940_dapm_widgets,
ARRAY_SIZE(wm8940_dapm_widgets));
if (ret)
goto error_ret;
ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
if (ret)
goto error_ret;
ret = snd_soc_dapm_new_widgets(codec);
error_ret:
return ret;
}
#define wm8940_reset(c) snd_soc_write(c, WM8940_SOFTRESET, 0);
static int wm8940_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 iface = snd_soc_read(codec, WM8940_IFACE) & 0xFE67;
u16 clk = snd_soc_read(codec, WM8940_CLOCK) & 0x1fe;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
clk |= 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
snd_soc_write(codec, WM8940_CLOCK, clk);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= (2 << 3);
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= (1 << 3);
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= (3 << 3);
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= (3 << 3) | (1 << 7);
break;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= (1 << 7);
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= (1 << 8);
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= (1 << 8) | (1 << 7);
break;
}
snd_soc_write(codec, WM8940_IFACE, iface);
return 0;
}
static int wm8940_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
u16 iface = snd_soc_read(codec, WM8940_IFACE) & 0xFD9F;
u16 addcntrl = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFF1;
u16 companding = snd_soc_read(codec,
WM8940_COMPANDINGCTL) & 0xFFDF;
int ret;
/* LoutR control */
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
&& params_channels(params) == 2)
iface |= (1 << 9);
switch (params_rate(params)) {
case 8000:
addcntrl |= (0x5 << 1);
break;
case 11025:
addcntrl |= (0x4 << 1);
break;
case 16000:
addcntrl |= (0x3 << 1);
break;
case 22050:
addcntrl |= (0x2 << 1);
break;
case 32000:
addcntrl |= (0x1 << 1);
break;
case 44100:
case 48000:
break;
}
ret = snd_soc_write(codec, WM8940_ADDCNTRL, addcntrl);
if (ret)
goto error_ret;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
companding = companding | (1 << 5);
break;
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
iface |= (1 << 5);
break;
case SNDRV_PCM_FORMAT_S24_LE:
iface |= (2 << 5);
break;
case SNDRV_PCM_FORMAT_S32_LE:
iface |= (3 << 5);
break;
}
ret = snd_soc_write(codec, WM8940_COMPANDINGCTL, companding);
if (ret)
goto error_ret;
ret = snd_soc_write(codec, WM8940_IFACE, iface);
error_ret:
return ret;
}
static int wm8940_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
u16 mute_reg = snd_soc_read(codec, WM8940_DAC) & 0xffbf;
if (mute)
mute_reg |= 0x40;
return snd_soc_write(codec, WM8940_DAC, mute_reg);
}
static int wm8940_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
u16 val;
u16 pwr_reg = snd_soc_read(codec, WM8940_POWER1) & 0x1F0;
int ret = 0;
switch (level) {
case SND_SOC_BIAS_ON:
/* ensure bufioen and biasen */
pwr_reg |= (1 << 2) | (1 << 3);
/* Enable thermal shutdown */
val = snd_soc_read(codec, WM8940_OUTPUTCTL);
ret = snd_soc_write(codec, WM8940_OUTPUTCTL, val | 0x2);
if (ret)
break;
/* set vmid to 75k */
ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x1);
break;
case SND_SOC_BIAS_PREPARE:
/* ensure bufioen and biasen */
pwr_reg |= (1 << 2) | (1 << 3);
ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x1);
break;
case SND_SOC_BIAS_STANDBY:
/* ensure bufioen and biasen */
pwr_reg |= (1 << 2) | (1 << 3);
/* set vmid to 300k for standby */
ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x2);
break;
case SND_SOC_BIAS_OFF:
ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg);
break;
}
return ret;
}
struct pll_ {
unsigned int pre_scale:2;
unsigned int n:4;
unsigned int k;
};
static struct pll_ pll_div;
/* The size in bits of the pll divide multiplied by 10
* to allow rounding later */
#define FIXED_PLL_SIZE ((1 << 24) * 10)
static void pll_factors(unsigned int target, unsigned int source)
{
unsigned long long Kpart;
unsigned int K, Ndiv, Nmod;
/* The left shift ist to avoid accuracy loss when right shifting */
Ndiv = target / source;
if (Ndiv > 12) {
source <<= 1;
/* Multiply by 2 */
pll_div.pre_scale = 0;
Ndiv = target / source;
} else if (Ndiv < 3) {
source >>= 2;
/* Divide by 4 */
pll_div.pre_scale = 3;
Ndiv = target / source;
} else if (Ndiv < 6) {
source >>= 1;
/* divide by 2 */
pll_div.pre_scale = 2;
Ndiv = target / source;
} else
pll_div.pre_scale = 1;
if ((Ndiv < 6) || (Ndiv > 12))
printk(KERN_WARNING
"WM8940 N value %d outwith recommended range!d\n",
Ndiv);
pll_div.n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (long long)Nmod;
do_div(Kpart, source);
K = Kpart & 0xFFFFFFFF;
/* Check if we need to round */
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
K /= 10;
pll_div.k = K;
}
/* Untested at the moment */
static int wm8940_set_dai_pll(struct snd_soc_dai *codec_dai,
int pll_id, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 reg;
/* Turn off PLL */
reg = snd_soc_read(codec, WM8940_POWER1);
snd_soc_write(codec, WM8940_POWER1, reg & 0x1df);
if (freq_in == 0 || freq_out == 0) {
/* Clock CODEC directly from MCLK */
reg = snd_soc_read(codec, WM8940_CLOCK);
snd_soc_write(codec, WM8940_CLOCK, reg & 0x0ff);
/* Pll power down */
snd_soc_write(codec, WM8940_PLLN, (1 << 7));
return 0;
}
/* Pll is followed by a frequency divide by 4 */
pll_factors(freq_out*4, freq_in);
if (pll_div.k)
snd_soc_write(codec, WM8940_PLLN,
(pll_div.pre_scale << 4) | pll_div.n | (1 << 6));
else /* No factional component */
snd_soc_write(codec, WM8940_PLLN,
(pll_div.pre_scale << 4) | pll_div.n);
snd_soc_write(codec, WM8940_PLLK1, pll_div.k >> 18);
snd_soc_write(codec, WM8940_PLLK2, (pll_div.k >> 9) & 0x1ff);
snd_soc_write(codec, WM8940_PLLK3, pll_div.k & 0x1ff);
/* Enable the PLL */
reg = snd_soc_read(codec, WM8940_POWER1);
snd_soc_write(codec, WM8940_POWER1, reg | 0x020);
/* Run CODEC from PLL instead of MCLK */
reg = snd_soc_read(codec, WM8940_CLOCK);
snd_soc_write(codec, WM8940_CLOCK, reg | 0x100);
return 0;
}
static int wm8940_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct wm8940_priv *wm8940 = codec->private_data;
switch (freq) {
case 11289600:
case 12000000:
case 12288000:
case 16934400:
case 18432000:
wm8940->sysclk = freq;
return 0;
}
return -EINVAL;
}
static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 reg;
int ret = 0;
switch (div_id) {
case WM8940_BCLKDIV:
reg = snd_soc_read(codec, WM8940_CLOCK) & 0xFFEF3;
ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 2));
break;
case WM8940_MCLKDIV:
reg = snd_soc_read(codec, WM8940_CLOCK) & 0xFF1F;
ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 5));
break;
case WM8940_OPCLKDIV:
reg = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFCF;
ret = snd_soc_write(codec, WM8940_ADDCNTRL, reg | (div << 4));
break;
}
return ret;
}
#define WM8940_RATES SNDRV_PCM_RATE_8000_48000
#define WM8940_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_ops wm8940_dai_ops = {
.hw_params = wm8940_i2s_hw_params,
.set_sysclk = wm8940_set_dai_sysclk,
.digital_mute = wm8940_mute,
.set_fmt = wm8940_set_dai_fmt,
.set_clkdiv = wm8940_set_dai_clkdiv,
.set_pll = wm8940_set_dai_pll,
};
struct snd_soc_dai wm8940_dai = {
.name = "WM8940",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8940_RATES,
.formats = WM8940_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8940_RATES,
.formats = WM8940_FORMATS,
},
.ops = &wm8940_dai_ops,
.symmetric_rates = 1,
};
EXPORT_SYMBOL_GPL(wm8940_dai);
static int wm8940_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
return wm8940_set_bias_level(codec, SND_SOC_BIAS_OFF);
}
static int wm8940_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
int i;
int ret;
u8 data[3];
u16 *cache = codec->reg_cache;
/* Sync reg_cache with the hardware
* Could use auto incremented writes to speed this up
*/
for (i = 0; i < ARRAY_SIZE(wm8940_reg_defaults); i++) {
data[0] = i;
data[1] = (cache[i] & 0xFF00) >> 8;
data[2] = cache[i] & 0x00FF;
ret = codec->hw_write(codec->control_data, data, 3);
if (ret < 0)
goto error_ret;
else if (ret != 3) {
ret = -EIO;
goto error_ret;
}
}
ret = wm8940_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
if (ret)
goto error_ret;
ret = wm8940_set_bias_level(codec, codec->suspend_bias_level);
error_ret:
return ret;
}
static struct snd_soc_codec *wm8940_codec;
static int wm8940_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
if (wm8940_codec == NULL) {
dev_err(&pdev->dev, "Codec device not registered\n");
return -ENODEV;
}
socdev->card->codec = wm8940_codec;
codec = wm8940_codec;
mutex_init(&codec->mutex);
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms: %d\n", ret);
goto pcm_err;
}
ret = snd_soc_add_controls(codec, wm8940_snd_controls,
ARRAY_SIZE(wm8940_snd_controls));
if (ret)
goto error_free_pcms;
ret = wm8940_add_widgets(codec);
if (ret)
goto error_free_pcms;
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(codec->dev, "failed to register card: %d\n", ret);
goto error_free_pcms;
}
return ret;
error_free_pcms:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
return ret;
}
static int wm8940_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_wm8940 = {
.probe = wm8940_probe,
.remove = wm8940_remove,
.suspend = wm8940_suspend,
.resume = wm8940_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm8940);
static int wm8940_register(struct wm8940_priv *wm8940,
enum snd_soc_control_type control)
{
struct wm8940_setup_data *pdata = wm8940->codec.dev->platform_data;
struct snd_soc_codec *codec = &wm8940->codec;
int ret;
u16 reg;
if (wm8940_codec) {
dev_err(codec->dev, "Another WM8940 is registered\n");
return -EINVAL;
}
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->private_data = wm8940;
codec->name = "WM8940";
codec->owner = THIS_MODULE;
codec->bias_level = SND_SOC_BIAS_OFF;
codec->set_bias_level = wm8940_set_bias_level;
codec->dai = &wm8940_dai;
codec->num_dai = 1;
codec->reg_cache_size = ARRAY_SIZE(wm8940_reg_defaults);
codec->reg_cache = &wm8940->reg_cache;
ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
if (ret < 0) {
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
return ret;
}
memcpy(codec->reg_cache, wm8940_reg_defaults,
sizeof(wm8940_reg_defaults));
ret = wm8940_reset(codec);
if (ret < 0) {
dev_err(codec->dev, "Failed to issue reset\n");
return ret;
}
wm8940_dai.dev = codec->dev;
wm8940_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
ret = snd_soc_write(codec, WM8940_POWER1, 0x180);
if (ret < 0)
return ret;
if (!pdata)
dev_warn(codec->dev, "No platform data supplied\n");
else {
reg = snd_soc_read(codec, WM8940_OUTPUTCTL);
ret = snd_soc_write(codec, WM8940_OUTPUTCTL, reg | pdata->vroi);
if (ret < 0)
return ret;
}
wm8940_codec = codec;
ret = snd_soc_register_codec(codec);
if (ret) {
dev_err(codec->dev, "Failed to register codec: %d\n", ret);
return ret;
}
ret = snd_soc_register_dai(&wm8940_dai);
if (ret) {
dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
snd_soc_unregister_codec(codec);
return ret;
}
return 0;
}
static void wm8940_unregister(struct wm8940_priv *wm8940)
{
wm8940_set_bias_level(&wm8940->codec, SND_SOC_BIAS_OFF);
snd_soc_unregister_dai(&wm8940_dai);
snd_soc_unregister_codec(&wm8940->codec);
kfree(wm8940);
wm8940_codec = NULL;
}
static int wm8940_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct wm8940_priv *wm8940;
struct snd_soc_codec *codec;
wm8940 = kzalloc(sizeof *wm8940, GFP_KERNEL);
if (wm8940 == NULL)
return -ENOMEM;
codec = &wm8940->codec;
codec->hw_write = (hw_write_t)i2c_master_send;
i2c_set_clientdata(i2c, wm8940);
codec->control_data = i2c;
codec->dev = &i2c->dev;
return wm8940_register(wm8940, SND_SOC_I2C);
}
static int __devexit wm8940_i2c_remove(struct i2c_client *client)
{
struct wm8940_priv *wm8940 = i2c_get_clientdata(client);
wm8940_unregister(wm8940);
return 0;
}
#ifdef CONFIG_PM
static int wm8940_i2c_suspend(struct i2c_client *client, pm_message_t msg)
{
return snd_soc_suspend_device(&client->dev);
}
static int wm8940_i2c_resume(struct i2c_client *client)
{
return snd_soc_resume_device(&client->dev);
}
#else
#define wm8940_i2c_suspend NULL
#define wm8940_i2c_resume NULL
#endif
static const struct i2c_device_id wm8940_i2c_id[] = {
{ "wm8940", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8940_i2c_id);
static struct i2c_driver wm8940_i2c_driver = {
.driver = {
.name = "WM8940 I2C Codec",
.owner = THIS_MODULE,
},
.probe = wm8940_i2c_probe,
.remove = __devexit_p(wm8940_i2c_remove),
.suspend = wm8940_i2c_suspend,
.resume = wm8940_i2c_resume,
.id_table = wm8940_i2c_id,
};
static int __init wm8940_modinit(void)
{
int ret;
ret = i2c_add_driver(&wm8940_i2c_driver);
if (ret)
printk(KERN_ERR "Failed to register WM8940 I2C driver: %d\n",
ret);
return ret;
}
module_init(wm8940_modinit);
static void __exit wm8940_exit(void)
{
i2c_del_driver(&wm8940_i2c_driver);
}
module_exit(wm8940_exit);
MODULE_DESCRIPTION("ASoC WM8940 driver");
MODULE_AUTHOR("Jonathan Cameron");
MODULE_LICENSE("GPL");

104
kernel/sound/soc/codecs/wm8940.h Normal file
View File

@@ -0,0 +1,104 @@
/*
* wm8940.h -- WM8940 Soc Audio driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM8940_H
#define _WM8940_H
struct wm8940_setup_data {
/* Vref to analogue output resistance */
#define WM8940_VROI_1K 0
#define WM8940_VROI_30K 1
unsigned int vroi:1;
};
extern struct snd_soc_dai wm8940_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8940;
/* WM8940 register space */
#define WM8940_SOFTRESET 0x00
#define WM8940_POWER1 0x01
#define WM8940_POWER2 0x02
#define WM8940_POWER3 0x03
#define WM8940_IFACE 0x04
#define WM8940_COMPANDINGCTL 0x05
#define WM8940_CLOCK 0x06
#define WM8940_ADDCNTRL 0x07
#define WM8940_GPIO 0x08
#define WM8940_CTLINT 0x09
#define WM8940_DAC 0x0A
#define WM8940_DACVOL 0x0B
#define WM8940_ADC 0x0E
#define WM8940_ADCVOL 0x0F
#define WM8940_NOTCH1 0x10
#define WM8940_NOTCH2 0x11
#define WM8940_NOTCH3 0x12
#define WM8940_NOTCH4 0x13
#define WM8940_NOTCH5 0x14
#define WM8940_NOTCH6 0x15
#define WM8940_NOTCH7 0x16
#define WM8940_NOTCH8 0x17
#define WM8940_DACLIM1 0x18
#define WM8940_DACLIM2 0x19
#define WM8940_ALC1 0x20
#define WM8940_ALC2 0x21
#define WM8940_ALC3 0x22
#define WM8940_NOISEGATE 0x23
#define WM8940_PLLN 0x24
#define WM8940_PLLK1 0x25
#define WM8940_PLLK2 0x26
#define WM8940_PLLK3 0x27
#define WM8940_ALC4 0x2A
#define WM8940_INPUTCTL 0x2C
#define WM8940_PGAGAIN 0x2D
#define WM8940_ADCBOOST 0x2F
#define WM8940_OUTPUTCTL 0x31
#define WM8940_SPKMIX 0x32
#define WM8940_SPKVOL 0x36
#define WM8940_MONOMIX 0x38
#define WM8940_CACHEREGNUM 0x57
/* Clock divider Id's */
#define WM8940_BCLKDIV 0
#define WM8940_MCLKDIV 1
#define WM8940_OPCLKDIV 2
/* MCLK clock dividers */
#define WM8940_MCLKDIV_1 0
#define WM8940_MCLKDIV_1_5 1
#define WM8940_MCLKDIV_2 2
#define WM8940_MCLKDIV_3 3
#define WM8940_MCLKDIV_4 4
#define WM8940_MCLKDIV_6 5
#define WM8940_MCLKDIV_8 6
#define WM8940_MCLKDIV_12 7
/* BCLK clock dividers */
#define WM8940_BCLKDIV_1 0
#define WM8940_BCLKDIV_2 1
#define WM8940_BCLKDIV_4 2
#define WM8940_BCLKDIV_8 3
#define WM8940_BCLKDIV_16 4
#define WM8940_BCLKDIV_32 5
/* PLL Out Dividers */
#define WM8940_OPCLKDIV_1 0
#define WM8940_OPCLKDIV_2 1
#define WM8940_OPCLKDIV_3 2
#define WM8940_OPCLKDIV_4 3
#endif /* _WM8940_H */

942
kernel/sound/soc/codecs/wm8960.c Normal file
View File

@@ -0,0 +1,942 @@
/*
* wm8960.c -- WM8960 ALSA SoC Audio driver
*
* Author: Liam Girdwood
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8960.h"
#define AUDIO_NAME "wm8960"
struct snd_soc_codec_device soc_codec_dev_wm8960;
/* R25 - Power 1 */
#define WM8960_VREF 0x40
/* R28 - Anti-pop 1 */
#define WM8960_POBCTRL 0x80
#define WM8960_BUFDCOPEN 0x10
#define WM8960_BUFIOEN 0x08
#define WM8960_SOFT_ST 0x04
#define WM8960_HPSTBY 0x01
/* R29 - Anti-pop 2 */
#define WM8960_DISOP 0x40
/*
* wm8960 register cache
* We can't read the WM8960 register space when we are
* using 2 wire for device control, so we cache them instead.
*/
static const u16 wm8960_reg[WM8960_CACHEREGNUM] = {
0x0097, 0x0097, 0x0000, 0x0000,
0x0000, 0x0008, 0x0000, 0x000a,
0x01c0, 0x0000, 0x00ff, 0x00ff,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x007b, 0x0100, 0x0032,
0x0000, 0x00c3, 0x00c3, 0x01c0,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0100, 0x0100, 0x0050, 0x0050,
0x0050, 0x0050, 0x0000, 0x0000,
0x0000, 0x0000, 0x0040, 0x0000,
0x0000, 0x0050, 0x0050, 0x0000,
0x0002, 0x0037, 0x004d, 0x0080,
0x0008, 0x0031, 0x0026, 0x00e9,
};
struct wm8960_priv {
u16 reg_cache[WM8960_CACHEREGNUM];
struct snd_soc_codec codec;
};
#define wm8960_reset(c) snd_soc_write(c, WM8960_RESET, 0)
/* enumerated controls */
static const char *wm8960_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted",
"Right Inverted", "Stereo Inversion"};
static const char *wm8960_3d_upper_cutoff[] = {"High", "Low"};
static const char *wm8960_3d_lower_cutoff[] = {"Low", "High"};
static const char *wm8960_alcfunc[] = {"Off", "Right", "Left", "Stereo"};
static const char *wm8960_alcmode[] = {"ALC", "Limiter"};
static const struct soc_enum wm8960_enum[] = {
SOC_ENUM_SINGLE(WM8960_DACCTL1, 1, 4, wm8960_deemph),
SOC_ENUM_SINGLE(WM8960_DACCTL1, 5, 4, wm8960_polarity),
SOC_ENUM_SINGLE(WM8960_DACCTL2, 5, 4, wm8960_polarity),
SOC_ENUM_SINGLE(WM8960_3D, 6, 2, wm8960_3d_upper_cutoff),
SOC_ENUM_SINGLE(WM8960_3D, 5, 2, wm8960_3d_lower_cutoff),
SOC_ENUM_SINGLE(WM8960_ALC1, 7, 4, wm8960_alcfunc),
SOC_ENUM_SINGLE(WM8960_ALC3, 8, 2, wm8960_alcmode),
};
static const DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 50, 0);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0);
static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
static const struct snd_kcontrol_new wm8960_snd_controls[] = {
SOC_DOUBLE_R_TLV("Capture Volume", WM8960_LINVOL, WM8960_RINVOL,
0, 63, 0, adc_tlv),
SOC_DOUBLE_R("Capture Volume ZC Switch", WM8960_LINVOL, WM8960_RINVOL,
6, 1, 0),
SOC_DOUBLE_R("Capture Switch", WM8960_LINVOL, WM8960_RINVOL,
7, 1, 0),
SOC_DOUBLE_R_TLV("Playback Volume", WM8960_LDAC, WM8960_RDAC,
0, 255, 0, dac_tlv),
SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8960_LOUT1, WM8960_ROUT1,
0, 127, 0, out_tlv),
SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8960_LOUT1, WM8960_ROUT1,
7, 1, 0),
SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8960_LOUT2, WM8960_ROUT2,
0, 127, 0, out_tlv),
SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8960_LOUT2, WM8960_ROUT2,
7, 1, 0),
SOC_SINGLE("Speaker DC Volume", WM8960_CLASSD3, 3, 5, 0),
SOC_SINGLE("Speaker AC Volume", WM8960_CLASSD3, 0, 5, 0),
SOC_SINGLE("PCM Playback -6dB Switch", WM8960_DACCTL1, 7, 1, 0),
SOC_ENUM("ADC Polarity", wm8960_enum[1]),
SOC_ENUM("Playback De-emphasis", wm8960_enum[0]),
SOC_SINGLE("ADC High Pass Filter Switch", WM8960_DACCTL1, 0, 1, 0),
SOC_ENUM("DAC Polarity", wm8960_enum[2]),
SOC_ENUM("3D Filter Upper Cut-Off", wm8960_enum[3]),
SOC_ENUM("3D Filter Lower Cut-Off", wm8960_enum[4]),
SOC_SINGLE("3D Volume", WM8960_3D, 1, 15, 0),
SOC_SINGLE("3D Switch", WM8960_3D, 0, 1, 0),
SOC_ENUM("ALC Function", wm8960_enum[5]),
SOC_SINGLE("ALC Max Gain", WM8960_ALC1, 4, 7, 0),
SOC_SINGLE("ALC Target", WM8960_ALC1, 0, 15, 1),
SOC_SINGLE("ALC Min Gain", WM8960_ALC2, 4, 7, 0),
SOC_SINGLE("ALC Hold Time", WM8960_ALC2, 0, 15, 0),
SOC_ENUM("ALC Mode", wm8960_enum[6]),
SOC_SINGLE("ALC Decay", WM8960_ALC3, 4, 15, 0),
SOC_SINGLE("ALC Attack", WM8960_ALC3, 0, 15, 0),
SOC_SINGLE("Noise Gate Threshold", WM8960_NOISEG, 3, 31, 0),
SOC_SINGLE("Noise Gate Switch", WM8960_NOISEG, 0, 1, 0),
SOC_DOUBLE_R("ADC PCM Capture Volume", WM8960_LINPATH, WM8960_RINPATH,
0, 127, 0),
SOC_SINGLE_TLV("Left Output Mixer Boost Bypass Volume",
WM8960_BYPASS1, 4, 7, 1, bypass_tlv),
SOC_SINGLE_TLV("Left Output Mixer LINPUT3 Volume",
WM8960_LOUTMIX, 4, 7, 1, bypass_tlv),
SOC_SINGLE_TLV("Right Output Mixer Boost Bypass Volume",
WM8960_BYPASS2, 4, 7, 1, bypass_tlv),
SOC_SINGLE_TLV("Right Output Mixer RINPUT3 Volume",
WM8960_ROUTMIX, 4, 7, 1, bypass_tlv),
};
static const struct snd_kcontrol_new wm8960_lin_boost[] = {
SOC_DAPM_SINGLE("LINPUT2 Switch", WM8960_LINPATH, 6, 1, 0),
SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LINPATH, 7, 1, 0),
SOC_DAPM_SINGLE("LINPUT1 Switch", WM8960_LINPATH, 8, 1, 0),
};
static const struct snd_kcontrol_new wm8960_lin[] = {
SOC_DAPM_SINGLE("Boost Switch", WM8960_LINPATH, 3, 1, 0),
};
static const struct snd_kcontrol_new wm8960_rin_boost[] = {
SOC_DAPM_SINGLE("RINPUT2 Switch", WM8960_RINPATH, 6, 1, 0),
SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_RINPATH, 7, 1, 0),
SOC_DAPM_SINGLE("RINPUT1 Switch", WM8960_RINPATH, 8, 1, 0),
};
static const struct snd_kcontrol_new wm8960_rin[] = {
SOC_DAPM_SINGLE("Boost Switch", WM8960_RINPATH, 3, 1, 0),
};
static const struct snd_kcontrol_new wm8960_loutput_mixer[] = {
SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_LOUTMIX, 8, 1, 0),
SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LOUTMIX, 7, 1, 0),
SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS1, 7, 1, 0),
};
static const struct snd_kcontrol_new wm8960_routput_mixer[] = {
SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_ROUTMIX, 8, 1, 0),
SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_ROUTMIX, 7, 1, 0),
SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS2, 7, 1, 0),
};
static const struct snd_kcontrol_new wm8960_mono_out[] = {
SOC_DAPM_SINGLE("Left Switch", WM8960_MONOMIX1, 7, 1, 0),
SOC_DAPM_SINGLE("Right Switch", WM8960_MONOMIX2, 7, 1, 0),
};
static const struct snd_soc_dapm_widget wm8960_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("LINPUT1"),
SND_SOC_DAPM_INPUT("RINPUT1"),
SND_SOC_DAPM_INPUT("LINPUT2"),
SND_SOC_DAPM_INPUT("RINPUT2"),
SND_SOC_DAPM_INPUT("LINPUT3"),
SND_SOC_DAPM_INPUT("RINPUT3"),
SND_SOC_DAPM_MICBIAS("MICB", WM8960_POWER1, 1, 0),
SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8960_POWER1, 5, 0,
wm8960_lin_boost, ARRAY_SIZE(wm8960_lin_boost)),
SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8960_POWER1, 4, 0,
wm8960_rin_boost, ARRAY_SIZE(wm8960_rin_boost)),
SND_SOC_DAPM_MIXER("Left Input Mixer", WM8960_POWER3, 5, 0,
wm8960_lin, ARRAY_SIZE(wm8960_lin)),
SND_SOC_DAPM_MIXER("Right Input Mixer", WM8960_POWER3, 4, 0,
wm8960_rin, ARRAY_SIZE(wm8960_rin)),
SND_SOC_DAPM_ADC("Left ADC", "Capture", WM8960_POWER2, 3, 0),
SND_SOC_DAPM_ADC("Right ADC", "Capture", WM8960_POWER2, 2, 0),
SND_SOC_DAPM_DAC("Left DAC", "Playback", WM8960_POWER2, 8, 0),
SND_SOC_DAPM_DAC("Right DAC", "Playback", WM8960_POWER2, 7, 0),
SND_SOC_DAPM_MIXER("Left Output Mixer", WM8960_POWER3, 3, 0,
&wm8960_loutput_mixer[0],
ARRAY_SIZE(wm8960_loutput_mixer)),
SND_SOC_DAPM_MIXER("Right Output Mixer", WM8960_POWER3, 2, 0,
&wm8960_routput_mixer[0],
ARRAY_SIZE(wm8960_routput_mixer)),
SND_SOC_DAPM_MIXER("Mono Output Mixer", WM8960_POWER2, 1, 0,
&wm8960_mono_out[0],
ARRAY_SIZE(wm8960_mono_out)),
SND_SOC_DAPM_PGA("LOUT1 PGA", WM8960_POWER2, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("ROUT1 PGA", WM8960_POWER2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Speaker PGA", WM8960_POWER2, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Speaker PGA", WM8960_POWER2, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Speaker Output", WM8960_CLASSD1, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Speaker Output", WM8960_CLASSD1, 6, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPK_LP"),
SND_SOC_DAPM_OUTPUT("SPK_LN"),
SND_SOC_DAPM_OUTPUT("HP_L"),
SND_SOC_DAPM_OUTPUT("HP_R"),
SND_SOC_DAPM_OUTPUT("SPK_RP"),
SND_SOC_DAPM_OUTPUT("SPK_RN"),
SND_SOC_DAPM_OUTPUT("OUT3"),
};
static const struct snd_soc_dapm_route audio_paths[] = {
{ "Left Boost Mixer", "LINPUT1 Switch", "LINPUT1" },
{ "Left Boost Mixer", "LINPUT2 Switch", "LINPUT2" },
{ "Left Boost Mixer", "LINPUT3 Switch", "LINPUT3" },
{ "Left Input Mixer", "Boost Switch", "Left Boost Mixer", },
{ "Left Input Mixer", NULL, "LINPUT1", }, /* Really Boost Switch */
{ "Left Input Mixer", NULL, "LINPUT2" },
{ "Left Input Mixer", NULL, "LINPUT3" },
{ "Right Boost Mixer", "RINPUT1 Switch", "RINPUT1" },
{ "Right Boost Mixer", "RINPUT2 Switch", "RINPUT2" },
{ "Right Boost Mixer", "RINPUT3 Switch", "RINPUT3" },
{ "Right Input Mixer", "Boost Switch", "Right Boost Mixer", },
{ "Right Input Mixer", NULL, "RINPUT1", }, /* Really Boost Switch */
{ "Right Input Mixer", NULL, "RINPUT2" },
{ "Right Input Mixer", NULL, "LINPUT3" },
{ "Left ADC", NULL, "Left Input Mixer" },
{ "Right ADC", NULL, "Right Input Mixer" },
{ "Left Output Mixer", "LINPUT3 Switch", "LINPUT3" },
{ "Left Output Mixer", "Boost Bypass Switch", "Left Boost Mixer"} ,
{ "Left Output Mixer", "PCM Playback Switch", "Left DAC" },
{ "Right Output Mixer", "RINPUT3 Switch", "RINPUT3" },
{ "Right Output Mixer", "Boost Bypass Switch", "Right Boost Mixer" } ,
{ "Right Output Mixer", "PCM Playback Switch", "Right DAC" },
{ "Mono Output Mixer", "Left Switch", "Left Output Mixer" },
{ "Mono Output Mixer", "Right Switch", "Right Output Mixer" },
{ "LOUT1 PGA", NULL, "Left Output Mixer" },
{ "ROUT1 PGA", NULL, "Right Output Mixer" },
{ "HP_L", NULL, "LOUT1 PGA" },
{ "HP_R", NULL, "ROUT1 PGA" },
{ "Left Speaker PGA", NULL, "Left Output Mixer" },
{ "Right Speaker PGA", NULL, "Right Output Mixer" },
{ "Left Speaker Output", NULL, "Left Speaker PGA" },
{ "Right Speaker Output", NULL, "Right Speaker PGA" },
{ "SPK_LN", NULL, "Left Speaker Output" },
{ "SPK_LP", NULL, "Left Speaker Output" },
{ "SPK_RN", NULL, "Right Speaker Output" },
{ "SPK_RP", NULL, "Right Speaker Output" },
{ "OUT3", NULL, "Mono Output Mixer", }
};
static int wm8960_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, wm8960_dapm_widgets,
ARRAY_SIZE(wm8960_dapm_widgets));
snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
snd_soc_dapm_new_widgets(codec);
return 0;
}
static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 iface = 0;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
iface |= 0x0040;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= 0x0013;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0090;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0010;
break;
default:
return -EINVAL;
}
/* set iface */
snd_soc_write(codec, WM8960_IFACE1, iface);
return 0;
}
static int wm8960_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
u16 iface = snd_soc_read(codec, WM8960_IFACE1) & 0xfff3;
/* bit size */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
iface |= 0x0004;
break;
case SNDRV_PCM_FORMAT_S24_LE:
iface |= 0x0008;
break;
}
/* set iface */
snd_soc_write(codec, WM8960_IFACE1, iface);
return 0;
}
static int wm8960_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
u16 mute_reg = snd_soc_read(codec, WM8960_DACCTL1) & 0xfff7;
if (mute)
snd_soc_write(codec, WM8960_DACCTL1, mute_reg | 0x8);
else
snd_soc_write(codec, WM8960_DACCTL1, mute_reg);
return 0;
}
static int wm8960_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
struct wm8960_data *pdata = codec->dev->platform_data;
u16 reg;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
/* Set VMID to 2x50k */
reg = snd_soc_read(codec, WM8960_POWER1);
reg &= ~0x180;
reg |= 0x80;
snd_soc_write(codec, WM8960_POWER1, reg);
break;
case SND_SOC_BIAS_STANDBY:
if (codec->bias_level == SND_SOC_BIAS_OFF) {
/* Enable anti-pop features */
snd_soc_write(codec, WM8960_APOP1,
WM8960_POBCTRL | WM8960_SOFT_ST |
WM8960_BUFDCOPEN | WM8960_BUFIOEN);
/* Discharge HP output */
reg = WM8960_DISOP;
if (pdata)
reg |= pdata->dres << 4;
snd_soc_write(codec, WM8960_APOP2, reg);
msleep(400);
snd_soc_write(codec, WM8960_APOP2, 0);
/* Enable & ramp VMID at 2x50k */
reg = snd_soc_read(codec, WM8960_POWER1);
reg |= 0x80;
snd_soc_write(codec, WM8960_POWER1, reg);
msleep(100);
/* Enable VREF */
snd_soc_write(codec, WM8960_POWER1, reg | WM8960_VREF);
/* Disable anti-pop features */
snd_soc_write(codec, WM8960_APOP1, WM8960_BUFIOEN);
}
/* Set VMID to 2x250k */
reg = snd_soc_read(codec, WM8960_POWER1);
reg &= ~0x180;
reg |= 0x100;
snd_soc_write(codec, WM8960_POWER1, reg);
break;
case SND_SOC_BIAS_OFF:
/* Enable anti-pop features */
snd_soc_write(codec, WM8960_APOP1,
WM8960_POBCTRL | WM8960_SOFT_ST |
WM8960_BUFDCOPEN | WM8960_BUFIOEN);
/* Disable VMID and VREF, let them discharge */
snd_soc_write(codec, WM8960_POWER1, 0);
msleep(600);
snd_soc_write(codec, WM8960_APOP1, 0);
break;
}
codec->bias_level = level;
return 0;
}
/* PLL divisors */
struct _pll_div {
u32 pre_div:1;
u32 n:4;
u32 k:24;
};
/* The size in bits of the pll divide multiplied by 10
* to allow rounding later */
#define FIXED_PLL_SIZE ((1 << 24) * 10)
static int pll_factors(unsigned int source, unsigned int target,
struct _pll_div *pll_div)
{
unsigned long long Kpart;
unsigned int K, Ndiv, Nmod;
pr_debug("WM8960 PLL: setting %dHz->%dHz\n", source, target);
/* Scale up target to PLL operating frequency */
target *= 4;
Ndiv = target / source;
if (Ndiv < 6) {
source >>= 1;
pll_div->pre_div = 1;
Ndiv = target / source;
} else
pll_div->pre_div = 0;
if ((Ndiv < 6) || (Ndiv > 12)) {
pr_err("WM8960 PLL: Unsupported N=%d\n", Ndiv);
return -EINVAL;
}
pll_div->n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (long long)Nmod;
do_div(Kpart, source);
K = Kpart & 0xFFFFFFFF;
/* Check if we need to round */
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
K /= 10;
pll_div->k = K;
pr_debug("WM8960 PLL: N=%x K=%x pre_div=%d\n",
pll_div->n, pll_div->k, pll_div->pre_div);
return 0;
}
static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai,
int pll_id, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 reg;
static struct _pll_div pll_div;
int ret;
if (freq_in && freq_out) {
ret = pll_factors(freq_in, freq_out, &pll_div);
if (ret != 0)
return ret;
}
/* Disable the PLL: even if we are changing the frequency the
* PLL needs to be disabled while we do so. */
snd_soc_write(codec, WM8960_CLOCK1,
snd_soc_read(codec, WM8960_CLOCK1) & ~1);
snd_soc_write(codec, WM8960_POWER2,
snd_soc_read(codec, WM8960_POWER2) & ~1);
if (!freq_in || !freq_out)
return 0;
reg = snd_soc_read(codec, WM8960_PLL1) & ~0x3f;
reg |= pll_div.pre_div << 4;
reg |= pll_div.n;
if (pll_div.k) {
reg |= 0x20;
snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 18) & 0x3f);
snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 9) & 0x1ff);
snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0x1ff);
}
snd_soc_write(codec, WM8960_PLL1, reg);
/* Turn it on */
snd_soc_write(codec, WM8960_POWER2,
snd_soc_read(codec, WM8960_POWER2) | 1);
msleep(250);
snd_soc_write(codec, WM8960_CLOCK1,
snd_soc_read(codec, WM8960_CLOCK1) | 1);
return 0;
}
static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 reg;
switch (div_id) {
case WM8960_SYSCLKSEL:
reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1fe;
snd_soc_write(codec, WM8960_CLOCK1, reg | div);
break;
case WM8960_SYSCLKDIV:
reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9;
snd_soc_write(codec, WM8960_CLOCK1, reg | div);
break;
case WM8960_DACDIV:
reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1c7;
snd_soc_write(codec, WM8960_CLOCK1, reg | div);
break;
case WM8960_OPCLKDIV:
reg = snd_soc_read(codec, WM8960_PLL1) & 0x03f;
snd_soc_write(codec, WM8960_PLL1, reg | div);
break;
case WM8960_DCLKDIV:
reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f;
snd_soc_write(codec, WM8960_CLOCK2, reg | div);
break;
case WM8960_TOCLKSEL:
reg = snd_soc_read(codec, WM8960_ADDCTL1) & 0x1fd;
snd_soc_write(codec, WM8960_ADDCTL1, reg | div);
break;
default:
return -EINVAL;
}
return 0;
}
#define WM8960_RATES SNDRV_PCM_RATE_8000_48000
#define WM8960_FORMATS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_ops wm8960_dai_ops = {
.hw_params = wm8960_hw_params,
.digital_mute = wm8960_mute,
.set_fmt = wm8960_set_dai_fmt,
.set_clkdiv = wm8960_set_dai_clkdiv,
.set_pll = wm8960_set_dai_pll,
};
struct snd_soc_dai wm8960_dai = {
.name = "WM8960",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8960_RATES,
.formats = WM8960_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8960_RATES,
.formats = WM8960_FORMATS,},
.ops = &wm8960_dai_ops,
.symmetric_rates = 1,
};
EXPORT_SYMBOL_GPL(wm8960_dai);
static int wm8960_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
wm8960_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int wm8960_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
int i;
u8 data[2];
u16 *cache = codec->reg_cache;
/* Sync reg_cache with the hardware */
for (i = 0; i < ARRAY_SIZE(wm8960_reg); i++) {
data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
data[1] = cache[i] & 0x00ff;
codec->hw_write(codec->control_data, data, 2);
}
wm8960_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
wm8960_set_bias_level(codec, codec->suspend_bias_level);
return 0;
}
static struct snd_soc_codec *wm8960_codec;
static int wm8960_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
if (wm8960_codec == NULL) {
dev_err(&pdev->dev, "Codec device not registered\n");
return -ENODEV;
}
socdev->card->codec = wm8960_codec;
codec = wm8960_codec;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms: %d\n", ret);
goto pcm_err;
}
snd_soc_add_controls(codec, wm8960_snd_controls,
ARRAY_SIZE(wm8960_snd_controls));
wm8960_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(codec->dev, "failed to register card: %d\n", ret);
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
return ret;
}
/* power down chip */
static int wm8960_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_wm8960 = {
.probe = wm8960_probe,
.remove = wm8960_remove,
.suspend = wm8960_suspend,
.resume = wm8960_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm8960);
static int wm8960_register(struct wm8960_priv *wm8960,
enum snd_soc_control_type control)
{
struct wm8960_data *pdata = wm8960->codec.dev->platform_data;
struct snd_soc_codec *codec = &wm8960->codec;
int ret;
u16 reg;
if (wm8960_codec) {
dev_err(codec->dev, "Another WM8960 is registered\n");
ret = -EINVAL;
goto err;
}
if (!pdata) {
dev_warn(codec->dev, "No platform data supplied\n");
} else {
if (pdata->dres > WM8960_DRES_MAX) {
dev_err(codec->dev, "Invalid DRES: %d\n", pdata->dres);
pdata->dres = 0;
}
}
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->private_data = wm8960;
codec->name = "WM8960";
codec->owner = THIS_MODULE;
codec->bias_level = SND_SOC_BIAS_OFF;
codec->set_bias_level = wm8960_set_bias_level;
codec->dai = &wm8960_dai;
codec->num_dai = 1;
codec->reg_cache_size = WM8960_CACHEREGNUM;
codec->reg_cache = &wm8960->reg_cache;
memcpy(codec->reg_cache, wm8960_reg, sizeof(wm8960_reg));
ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
if (ret < 0) {
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
goto err;
}
ret = wm8960_reset(codec);
if (ret < 0) {
dev_err(codec->dev, "Failed to issue reset\n");
goto err;
}
wm8960_dai.dev = codec->dev;
wm8960_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
/* Latch the update bits */
reg = snd_soc_read(codec, WM8960_LINVOL);
snd_soc_write(codec, WM8960_LINVOL, reg | 0x100);
reg = snd_soc_read(codec, WM8960_RINVOL);
snd_soc_write(codec, WM8960_RINVOL, reg | 0x100);
reg = snd_soc_read(codec, WM8960_LADC);
snd_soc_write(codec, WM8960_LADC, reg | 0x100);
reg = snd_soc_read(codec, WM8960_RADC);
snd_soc_write(codec, WM8960_RADC, reg | 0x100);
reg = snd_soc_read(codec, WM8960_LDAC);
snd_soc_write(codec, WM8960_LDAC, reg | 0x100);
reg = snd_soc_read(codec, WM8960_RDAC);
snd_soc_write(codec, WM8960_RDAC, reg | 0x100);
reg = snd_soc_read(codec, WM8960_LOUT1);
snd_soc_write(codec, WM8960_LOUT1, reg | 0x100);
reg = snd_soc_read(codec, WM8960_ROUT1);
snd_soc_write(codec, WM8960_ROUT1, reg | 0x100);
reg = snd_soc_read(codec, WM8960_LOUT2);
snd_soc_write(codec, WM8960_LOUT2, reg | 0x100);
reg = snd_soc_read(codec, WM8960_ROUT2);
snd_soc_write(codec, WM8960_ROUT2, reg | 0x100);
wm8960_codec = codec;
ret = snd_soc_register_codec(codec);
if (ret != 0) {
dev_err(codec->dev, "Failed to register codec: %d\n", ret);
goto err;
}
ret = snd_soc_register_dai(&wm8960_dai);
if (ret != 0) {
dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
goto err_codec;
}
return 0;
err_codec:
snd_soc_unregister_codec(codec);
err:
kfree(wm8960);
return ret;
}
static void wm8960_unregister(struct wm8960_priv *wm8960)
{
wm8960_set_bias_level(&wm8960->codec, SND_SOC_BIAS_OFF);
snd_soc_unregister_dai(&wm8960_dai);
snd_soc_unregister_codec(&wm8960->codec);
kfree(wm8960);
wm8960_codec = NULL;
}
static __devinit int wm8960_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct wm8960_priv *wm8960;
struct snd_soc_codec *codec;
wm8960 = kzalloc(sizeof(struct wm8960_priv), GFP_KERNEL);
if (wm8960 == NULL)
return -ENOMEM;
codec = &wm8960->codec;
i2c_set_clientdata(i2c, wm8960);
codec->control_data = i2c;
codec->dev = &i2c->dev;
return wm8960_register(wm8960, SND_SOC_I2C);
}
static __devexit int wm8960_i2c_remove(struct i2c_client *client)
{
struct wm8960_priv *wm8960 = i2c_get_clientdata(client);
wm8960_unregister(wm8960);
return 0;
}
#ifdef CONFIG_PM
static int wm8960_i2c_suspend(struct i2c_client *client, pm_message_t msg)
{
return snd_soc_suspend_device(&client->dev);
}
static int wm8960_i2c_resume(struct i2c_client *client)
{
return snd_soc_resume_device(&client->dev);
}
#else
#define wm8960_i2c_suspend NULL
#define wm8960_i2c_resume NULL
#endif
static const struct i2c_device_id wm8960_i2c_id[] = {
{ "wm8960", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id);
static struct i2c_driver wm8960_i2c_driver = {
.driver = {
.name = "WM8960 I2C Codec",
.owner = THIS_MODULE,
},
.probe = wm8960_i2c_probe,
.remove = __devexit_p(wm8960_i2c_remove),
.suspend = wm8960_i2c_suspend,
.resume = wm8960_i2c_resume,
.id_table = wm8960_i2c_id,
};
static int __init wm8960_modinit(void)
{
int ret;
ret = i2c_add_driver(&wm8960_i2c_driver);
if (ret != 0) {
printk(KERN_ERR "Failed to register WM8960 I2C driver: %d\n",
ret);
}
return ret;
}
module_init(wm8960_modinit);
static void __exit wm8960_exit(void)
{
i2c_del_driver(&wm8960_i2c_driver);
}
module_exit(wm8960_exit);
MODULE_DESCRIPTION("ASoC WM8960 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");

127
kernel/sound/soc/codecs/wm8960.h Normal file
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/*
* wm8960.h -- WM8960 Soc Audio driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM8960_H
#define _WM8960_H
/* WM8960 register space */
#define WM8960_CACHEREGNUM 56
#define WM8960_LINVOL 0x0
#define WM8960_RINVOL 0x1
#define WM8960_LOUT1 0x2
#define WM8960_ROUT1 0x3
#define WM8960_CLOCK1 0x4
#define WM8960_DACCTL1 0x5
#define WM8960_DACCTL2 0x6
#define WM8960_IFACE1 0x7
#define WM8960_CLOCK2 0x8
#define WM8960_IFACE2 0x9
#define WM8960_LDAC 0xa
#define WM8960_RDAC 0xb
#define WM8960_RESET 0xf
#define WM8960_3D 0x10
#define WM8960_ALC1 0x11
#define WM8960_ALC2 0x12
#define WM8960_ALC3 0x13
#define WM8960_NOISEG 0x14
#define WM8960_LADC 0x15
#define WM8960_RADC 0x16
#define WM8960_ADDCTL1 0x17
#define WM8960_ADDCTL2 0x18
#define WM8960_POWER1 0x19
#define WM8960_POWER2 0x1a
#define WM8960_ADDCTL3 0x1b
#define WM8960_APOP1 0x1c
#define WM8960_APOP2 0x1d
#define WM8960_LINPATH 0x20
#define WM8960_RINPATH 0x21
#define WM8960_LOUTMIX 0x22
#define WM8960_ROUTMIX 0x25
#define WM8960_MONOMIX1 0x26
#define WM8960_MONOMIX2 0x27
#define WM8960_LOUT2 0x28
#define WM8960_ROUT2 0x29
#define WM8960_MONO 0x2a
#define WM8960_INBMIX1 0x2b
#define WM8960_INBMIX2 0x2c
#define WM8960_BYPASS1 0x2d
#define WM8960_BYPASS2 0x2e
#define WM8960_POWER3 0x2f
#define WM8960_ADDCTL4 0x30
#define WM8960_CLASSD1 0x31
#define WM8960_CLASSD3 0x33
#define WM8960_PLL1 0x34
#define WM8960_PLL2 0x35
#define WM8960_PLL3 0x36
#define WM8960_PLL4 0x37
/*
* WM8960 Clock dividers
*/
#define WM8960_SYSCLKDIV 0
#define WM8960_DACDIV 1
#define WM8960_OPCLKDIV 2
#define WM8960_DCLKDIV 3
#define WM8960_TOCLKSEL 4
#define WM8960_SYSCLKSEL 5
#define WM8960_SYSCLK_DIV_1 (0 << 1)
#define WM8960_SYSCLK_DIV_2 (2 << 1)
#define WM8960_SYSCLK_MCLK (0 << 0)
#define WM8960_SYSCLK_PLL (1 << 0)
#define WM8960_DAC_DIV_1 (0 << 3)
#define WM8960_DAC_DIV_1_5 (1 << 3)
#define WM8960_DAC_DIV_2 (2 << 3)
#define WM8960_DAC_DIV_3 (3 << 3)
#define WM8960_DAC_DIV_4 (4 << 3)
#define WM8960_DAC_DIV_5_5 (5 << 3)
#define WM8960_DAC_DIV_6 (6 << 3)
#define WM8960_DCLK_DIV_1_5 (0 << 6)
#define WM8960_DCLK_DIV_2 (1 << 6)
#define WM8960_DCLK_DIV_3 (2 << 6)
#define WM8960_DCLK_DIV_4 (3 << 6)
#define WM8960_DCLK_DIV_6 (4 << 6)
#define WM8960_DCLK_DIV_8 (5 << 6)
#define WM8960_DCLK_DIV_12 (6 << 6)
#define WM8960_DCLK_DIV_16 (7 << 6)
#define WM8960_TOCLK_F19 (0 << 1)
#define WM8960_TOCLK_F21 (1 << 1)
#define WM8960_OPCLK_DIV_1 (0 << 0)
#define WM8960_OPCLK_DIV_2 (1 << 0)
#define WM8960_OPCLK_DIV_3 (2 << 0)
#define WM8960_OPCLK_DIV_4 (3 << 0)
#define WM8960_OPCLK_DIV_5_5 (4 << 0)
#define WM8960_OPCLK_DIV_6 (5 << 0)
extern struct snd_soc_dai wm8960_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8960;
#define WM8960_DRES_400R 0
#define WM8960_DRES_200R 1
#define WM8960_DRES_600R 2
#define WM8960_DRES_150R 3
#define WM8960_DRES_MAX 3
struct wm8960_data {
int dres;
};
#endif

1265
kernel/sound/soc/codecs/wm8961.c Normal file
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866
kernel/sound/soc/codecs/wm8961.h Normal file
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/*
* wm8961.h -- WM8961 Soc Audio driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM8961_H
#define _WM8961_H
#include <sound/soc.h>
extern struct snd_soc_codec_device soc_codec_dev_wm8961;
extern struct snd_soc_dai wm8961_dai;
#define WM8961_BCLK 1
#define WM8961_LRCLK 2
#define WM8961_BCLK_DIV_1 0
#define WM8961_BCLK_DIV_1_5 1
#define WM8961_BCLK_DIV_2 2
#define WM8961_BCLK_DIV_3 3
#define WM8961_BCLK_DIV_4 4
#define WM8961_BCLK_DIV_5_5 5
#define WM8961_BCLK_DIV_6 6
#define WM8961_BCLK_DIV_8 7
#define WM8961_BCLK_DIV_11 8
#define WM8961_BCLK_DIV_12 9
#define WM8961_BCLK_DIV_16 10
#define WM8961_BCLK_DIV_24 11
#define WM8961_BCLK_DIV_32 13
/*
* Register values.
*/
#define WM8961_LEFT_INPUT_VOLUME 0x00
#define WM8961_RIGHT_INPUT_VOLUME 0x01
#define WM8961_LOUT1_VOLUME 0x02
#define WM8961_ROUT1_VOLUME 0x03
#define WM8961_CLOCKING1 0x04
#define WM8961_ADC_DAC_CONTROL_1 0x05
#define WM8961_ADC_DAC_CONTROL_2 0x06
#define WM8961_AUDIO_INTERFACE_0 0x07
#define WM8961_CLOCKING2 0x08
#define WM8961_AUDIO_INTERFACE_1 0x09
#define WM8961_LEFT_DAC_VOLUME 0x0A
#define WM8961_RIGHT_DAC_VOLUME 0x0B
#define WM8961_AUDIO_INTERFACE_2 0x0E
#define WM8961_SOFTWARE_RESET 0x0F
#define WM8961_ALC1 0x11
#define WM8961_ALC2 0x12
#define WM8961_ALC3 0x13
#define WM8961_NOISE_GATE 0x14
#define WM8961_LEFT_ADC_VOLUME 0x15
#define WM8961_RIGHT_ADC_VOLUME 0x16
#define WM8961_ADDITIONAL_CONTROL_1 0x17
#define WM8961_ADDITIONAL_CONTROL_2 0x18
#define WM8961_PWR_MGMT_1 0x19
#define WM8961_PWR_MGMT_2 0x1A
#define WM8961_ADDITIONAL_CONTROL_3 0x1B
#define WM8961_ANTI_POP 0x1C
#define WM8961_CLOCKING_3 0x1E
#define WM8961_ADCL_SIGNAL_PATH 0x20
#define WM8961_ADCR_SIGNAL_PATH 0x21
#define WM8961_LOUT2_VOLUME 0x28
#define WM8961_ROUT2_VOLUME 0x29
#define WM8961_PWR_MGMT_3 0x2F
#define WM8961_ADDITIONAL_CONTROL_4 0x30
#define WM8961_CLASS_D_CONTROL_1 0x31
#define WM8961_CLASS_D_CONTROL_2 0x33
#define WM8961_CLOCKING_4 0x38
#define WM8961_DSP_SIDETONE_0 0x39
#define WM8961_DSP_SIDETONE_1 0x3A
#define WM8961_DC_SERVO_0 0x3C
#define WM8961_DC_SERVO_1 0x3D
#define WM8961_DC_SERVO_3 0x3F
#define WM8961_DC_SERVO_5 0x41
#define WM8961_ANALOGUE_PGA_BIAS 0x44
#define WM8961_ANALOGUE_HP_0 0x45
#define WM8961_ANALOGUE_HP_2 0x47
#define WM8961_CHARGE_PUMP_1 0x48
#define WM8961_CHARGE_PUMP_B 0x52
#define WM8961_WRITE_SEQUENCER_1 0x57
#define WM8961_WRITE_SEQUENCER_2 0x58
#define WM8961_WRITE_SEQUENCER_3 0x59
#define WM8961_WRITE_SEQUENCER_4 0x5A
#define WM8961_WRITE_SEQUENCER_5 0x5B
#define WM8961_WRITE_SEQUENCER_6 0x5C
#define WM8961_WRITE_SEQUENCER_7 0x5D
#define WM8961_GENERAL_TEST_1 0xFC
/*
* Field Definitions.
*/
/*
* R0 (0x00) - Left Input volume
*/
#define WM8961_IPVU 0x0100 /* IPVU */
#define WM8961_IPVU_MASK 0x0100 /* IPVU */
#define WM8961_IPVU_SHIFT 8 /* IPVU */
#define WM8961_IPVU_WIDTH 1 /* IPVU */
#define WM8961_LINMUTE 0x0080 /* LINMUTE */
#define WM8961_LINMUTE_MASK 0x0080 /* LINMUTE */
#define WM8961_LINMUTE_SHIFT 7 /* LINMUTE */
#define WM8961_LINMUTE_WIDTH 1 /* LINMUTE */
#define WM8961_LIZC 0x0040 /* LIZC */
#define WM8961_LIZC_MASK 0x0040 /* LIZC */
#define WM8961_LIZC_SHIFT 6 /* LIZC */
#define WM8961_LIZC_WIDTH 1 /* LIZC */
#define WM8961_LINVOL_MASK 0x003F /* LINVOL - [5:0] */
#define WM8961_LINVOL_SHIFT 0 /* LINVOL - [5:0] */
#define WM8961_LINVOL_WIDTH 6 /* LINVOL - [5:0] */
/*
* R1 (0x01) - Right Input volume
*/
#define WM8961_DEVICE_ID_MASK 0xF000 /* DEVICE_ID - [15:12] */
#define WM8961_DEVICE_ID_SHIFT 12 /* DEVICE_ID - [15:12] */
#define WM8961_DEVICE_ID_WIDTH 4 /* DEVICE_ID - [15:12] */
#define WM8961_CHIP_REV_MASK 0x0E00 /* CHIP_REV - [11:9] */
#define WM8961_CHIP_REV_SHIFT 9 /* CHIP_REV - [11:9] */
#define WM8961_CHIP_REV_WIDTH 3 /* CHIP_REV - [11:9] */
#define WM8961_IPVU 0x0100 /* IPVU */
#define WM8961_IPVU_MASK 0x0100 /* IPVU */
#define WM8961_IPVU_SHIFT 8 /* IPVU */
#define WM8961_IPVU_WIDTH 1 /* IPVU */
#define WM8961_RINMUTE 0x0080 /* RINMUTE */
#define WM8961_RINMUTE_MASK 0x0080 /* RINMUTE */
#define WM8961_RINMUTE_SHIFT 7 /* RINMUTE */
#define WM8961_RINMUTE_WIDTH 1 /* RINMUTE */
#define WM8961_RIZC 0x0040 /* RIZC */
#define WM8961_RIZC_MASK 0x0040 /* RIZC */
#define WM8961_RIZC_SHIFT 6 /* RIZC */
#define WM8961_RIZC_WIDTH 1 /* RIZC */
#define WM8961_RINVOL_MASK 0x003F /* RINVOL - [5:0] */
#define WM8961_RINVOL_SHIFT 0 /* RINVOL - [5:0] */
#define WM8961_RINVOL_WIDTH 6 /* RINVOL - [5:0] */
/*
* R2 (0x02) - LOUT1 volume
*/
#define WM8961_OUT1VU 0x0100 /* OUT1VU */
#define WM8961_OUT1VU_MASK 0x0100 /* OUT1VU */
#define WM8961_OUT1VU_SHIFT 8 /* OUT1VU */
#define WM8961_OUT1VU_WIDTH 1 /* OUT1VU */
#define WM8961_LO1ZC 0x0080 /* LO1ZC */
#define WM8961_LO1ZC_MASK 0x0080 /* LO1ZC */
#define WM8961_LO1ZC_SHIFT 7 /* LO1ZC */
#define WM8961_LO1ZC_WIDTH 1 /* LO1ZC */
#define WM8961_LOUT1VOL_MASK 0x007F /* LOUT1VOL - [6:0] */
#define WM8961_LOUT1VOL_SHIFT 0 /* LOUT1VOL - [6:0] */
#define WM8961_LOUT1VOL_WIDTH 7 /* LOUT1VOL - [6:0] */
/*
* R3 (0x03) - ROUT1 volume
*/
#define WM8961_OUT1VU 0x0100 /* OUT1VU */
#define WM8961_OUT1VU_MASK 0x0100 /* OUT1VU */
#define WM8961_OUT1VU_SHIFT 8 /* OUT1VU */
#define WM8961_OUT1VU_WIDTH 1 /* OUT1VU */
#define WM8961_RO1ZC 0x0080 /* RO1ZC */
#define WM8961_RO1ZC_MASK 0x0080 /* RO1ZC */
#define WM8961_RO1ZC_SHIFT 7 /* RO1ZC */
#define WM8961_RO1ZC_WIDTH 1 /* RO1ZC */
#define WM8961_ROUT1VOL_MASK 0x007F /* ROUT1VOL - [6:0] */
#define WM8961_ROUT1VOL_SHIFT 0 /* ROUT1VOL - [6:0] */
#define WM8961_ROUT1VOL_WIDTH 7 /* ROUT1VOL - [6:0] */
/*
* R4 (0x04) - Clocking1
*/
#define WM8961_ADCDIV_MASK 0x01C0 /* ADCDIV - [8:6] */
#define WM8961_ADCDIV_SHIFT 6 /* ADCDIV - [8:6] */
#define WM8961_ADCDIV_WIDTH 3 /* ADCDIV - [8:6] */
#define WM8961_DACDIV_MASK 0x0038 /* DACDIV - [5:3] */
#define WM8961_DACDIV_SHIFT 3 /* DACDIV - [5:3] */
#define WM8961_DACDIV_WIDTH 3 /* DACDIV - [5:3] */
#define WM8961_MCLKDIV 0x0004 /* MCLKDIV */
#define WM8961_MCLKDIV_MASK 0x0004 /* MCLKDIV */
#define WM8961_MCLKDIV_SHIFT 2 /* MCLKDIV */
#define WM8961_MCLKDIV_WIDTH 1 /* MCLKDIV */
/*
* R5 (0x05) - ADC & DAC Control 1
*/
#define WM8961_ADCPOL_MASK 0x0060 /* ADCPOL - [6:5] */
#define WM8961_ADCPOL_SHIFT 5 /* ADCPOL - [6:5] */
#define WM8961_ADCPOL_WIDTH 2 /* ADCPOL - [6:5] */
#define WM8961_DACMU 0x0008 /* DACMU */
#define WM8961_DACMU_MASK 0x0008 /* DACMU */
#define WM8961_DACMU_SHIFT 3 /* DACMU */
#define WM8961_DACMU_WIDTH 1 /* DACMU */
#define WM8961_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */
#define WM8961_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */
#define WM8961_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */
#define WM8961_ADCHPD 0x0001 /* ADCHPD */
#define WM8961_ADCHPD_MASK 0x0001 /* ADCHPD */
#define WM8961_ADCHPD_SHIFT 0 /* ADCHPD */
#define WM8961_ADCHPD_WIDTH 1 /* ADCHPD */
/*
* R6 (0x06) - ADC & DAC Control 2
*/
#define WM8961_ADC_HPF_CUT_MASK 0x0180 /* ADC_HPF_CUT - [8:7] */
#define WM8961_ADC_HPF_CUT_SHIFT 7 /* ADC_HPF_CUT - [8:7] */
#define WM8961_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [8:7] */
#define WM8961_DACPOL_MASK 0x0060 /* DACPOL - [6:5] */
#define WM8961_DACPOL_SHIFT 5 /* DACPOL - [6:5] */
#define WM8961_DACPOL_WIDTH 2 /* DACPOL - [6:5] */
#define WM8961_DACSMM 0x0008 /* DACSMM */
#define WM8961_DACSMM_MASK 0x0008 /* DACSMM */
#define WM8961_DACSMM_SHIFT 3 /* DACSMM */
#define WM8961_DACSMM_WIDTH 1 /* DACSMM */
#define WM8961_DACMR 0x0004 /* DACMR */
#define WM8961_DACMR_MASK 0x0004 /* DACMR */
#define WM8961_DACMR_SHIFT 2 /* DACMR */
#define WM8961_DACMR_WIDTH 1 /* DACMR */
#define WM8961_DACSLOPE 0x0002 /* DACSLOPE */
#define WM8961_DACSLOPE_MASK 0x0002 /* DACSLOPE */
#define WM8961_DACSLOPE_SHIFT 1 /* DACSLOPE */
#define WM8961_DACSLOPE_WIDTH 1 /* DACSLOPE */
#define WM8961_DAC_OSR128 0x0001 /* DAC_OSR128 */
#define WM8961_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */
#define WM8961_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */
#define WM8961_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */
/*
* R7 (0x07) - Audio Interface 0
*/
#define WM8961_ALRSWAP 0x0100 /* ALRSWAP */
#define WM8961_ALRSWAP_MASK 0x0100 /* ALRSWAP */
#define WM8961_ALRSWAP_SHIFT 8 /* ALRSWAP */
#define WM8961_ALRSWAP_WIDTH 1 /* ALRSWAP */
#define WM8961_BCLKINV 0x0080 /* BCLKINV */
#define WM8961_BCLKINV_MASK 0x0080 /* BCLKINV */
#define WM8961_BCLKINV_SHIFT 7 /* BCLKINV */
#define WM8961_BCLKINV_WIDTH 1 /* BCLKINV */
#define WM8961_MS 0x0040 /* MS */
#define WM8961_MS_MASK 0x0040 /* MS */
#define WM8961_MS_SHIFT 6 /* MS */
#define WM8961_MS_WIDTH 1 /* MS */
#define WM8961_DLRSWAP 0x0020 /* DLRSWAP */
#define WM8961_DLRSWAP_MASK 0x0020 /* DLRSWAP */
#define WM8961_DLRSWAP_SHIFT 5 /* DLRSWAP */
#define WM8961_DLRSWAP_WIDTH 1 /* DLRSWAP */
#define WM8961_LRP 0x0010 /* LRP */
#define WM8961_LRP_MASK 0x0010 /* LRP */
#define WM8961_LRP_SHIFT 4 /* LRP */
#define WM8961_LRP_WIDTH 1 /* LRP */
#define WM8961_WL_MASK 0x000C /* WL - [3:2] */
#define WM8961_WL_SHIFT 2 /* WL - [3:2] */
#define WM8961_WL_WIDTH 2 /* WL - [3:2] */
#define WM8961_FORMAT_MASK 0x0003 /* FORMAT - [1:0] */
#define WM8961_FORMAT_SHIFT 0 /* FORMAT - [1:0] */
#define WM8961_FORMAT_WIDTH 2 /* FORMAT - [1:0] */
/*
* R8 (0x08) - Clocking2
*/
#define WM8961_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */
#define WM8961_DCLKDIV_SHIFT 6 /* DCLKDIV - [8:6] */
#define WM8961_DCLKDIV_WIDTH 3 /* DCLKDIV - [8:6] */
#define WM8961_CLK_SYS_ENA 0x0020 /* CLK_SYS_ENA */
#define WM8961_CLK_SYS_ENA_MASK 0x0020 /* CLK_SYS_ENA */
#define WM8961_CLK_SYS_ENA_SHIFT 5 /* CLK_SYS_ENA */
#define WM8961_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */
#define WM8961_CLK_DSP_ENA 0x0010 /* CLK_DSP_ENA */
#define WM8961_CLK_DSP_ENA_MASK 0x0010 /* CLK_DSP_ENA */
#define WM8961_CLK_DSP_ENA_SHIFT 4 /* CLK_DSP_ENA */
#define WM8961_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */
#define WM8961_BCLKDIV_MASK 0x000F /* BCLKDIV - [3:0] */
#define WM8961_BCLKDIV_SHIFT 0 /* BCLKDIV - [3:0] */
#define WM8961_BCLKDIV_WIDTH 4 /* BCLKDIV - [3:0] */
/*
* R9 (0x09) - Audio Interface 1
*/
#define WM8961_DACCOMP_MASK 0x0018 /* DACCOMP - [4:3] */
#define WM8961_DACCOMP_SHIFT 3 /* DACCOMP - [4:3] */
#define WM8961_DACCOMP_WIDTH 2 /* DACCOMP - [4:3] */
#define WM8961_ADCCOMP_MASK 0x0006 /* ADCCOMP - [2:1] */
#define WM8961_ADCCOMP_SHIFT 1 /* ADCCOMP - [2:1] */
#define WM8961_ADCCOMP_WIDTH 2 /* ADCCOMP - [2:1] */
#define WM8961_LOOPBACK 0x0001 /* LOOPBACK */
#define WM8961_LOOPBACK_MASK 0x0001 /* LOOPBACK */
#define WM8961_LOOPBACK_SHIFT 0 /* LOOPBACK */
#define WM8961_LOOPBACK_WIDTH 1 /* LOOPBACK */
/*
* R10 (0x0A) - Left DAC volume
*/
#define WM8961_DACVU 0x0100 /* DACVU */
#define WM8961_DACVU_MASK 0x0100 /* DACVU */
#define WM8961_DACVU_SHIFT 8 /* DACVU */
#define WM8961_DACVU_WIDTH 1 /* DACVU */
#define WM8961_LDACVOL_MASK 0x00FF /* LDACVOL - [7:0] */
#define WM8961_LDACVOL_SHIFT 0 /* LDACVOL - [7:0] */
#define WM8961_LDACVOL_WIDTH 8 /* LDACVOL - [7:0] */
/*
* R11 (0x0B) - Right DAC volume
*/
#define WM8961_DACVU 0x0100 /* DACVU */
#define WM8961_DACVU_MASK 0x0100 /* DACVU */
#define WM8961_DACVU_SHIFT 8 /* DACVU */
#define WM8961_DACVU_WIDTH 1 /* DACVU */
#define WM8961_RDACVOL_MASK 0x00FF /* RDACVOL - [7:0] */
#define WM8961_RDACVOL_SHIFT 0 /* RDACVOL - [7:0] */
#define WM8961_RDACVOL_WIDTH 8 /* RDACVOL - [7:0] */
/*
* R14 (0x0E) - Audio Interface 2
*/
#define WM8961_LRCLK_RATE_MASK 0x01FF /* LRCLK_RATE - [8:0] */
#define WM8961_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [8:0] */
#define WM8961_LRCLK_RATE_WIDTH 9 /* LRCLK_RATE - [8:0] */
/*
* R15 (0x0F) - Software Reset
*/
#define WM8961_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
#define WM8961_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
#define WM8961_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
/*
* R17 (0x11) - ALC1
*/
#define WM8961_ALCSEL_MASK 0x0180 /* ALCSEL - [8:7] */
#define WM8961_ALCSEL_SHIFT 7 /* ALCSEL - [8:7] */
#define WM8961_ALCSEL_WIDTH 2 /* ALCSEL - [8:7] */
#define WM8961_MAXGAIN_MASK 0x0070 /* MAXGAIN - [6:4] */
#define WM8961_MAXGAIN_SHIFT 4 /* MAXGAIN - [6:4] */
#define WM8961_MAXGAIN_WIDTH 3 /* MAXGAIN - [6:4] */
#define WM8961_ALCL_MASK 0x000F /* ALCL - [3:0] */
#define WM8961_ALCL_SHIFT 0 /* ALCL - [3:0] */
#define WM8961_ALCL_WIDTH 4 /* ALCL - [3:0] */
/*
* R18 (0x12) - ALC2
*/
#define WM8961_ALCZC 0x0080 /* ALCZC */
#define WM8961_ALCZC_MASK 0x0080 /* ALCZC */
#define WM8961_ALCZC_SHIFT 7 /* ALCZC */
#define WM8961_ALCZC_WIDTH 1 /* ALCZC */
#define WM8961_MINGAIN_MASK 0x0070 /* MINGAIN - [6:4] */
#define WM8961_MINGAIN_SHIFT 4 /* MINGAIN - [6:4] */
#define WM8961_MINGAIN_WIDTH 3 /* MINGAIN - [6:4] */
#define WM8961_HLD_MASK 0x000F /* HLD - [3:0] */
#define WM8961_HLD_SHIFT 0 /* HLD - [3:0] */
#define WM8961_HLD_WIDTH 4 /* HLD - [3:0] */
/*
* R19 (0x13) - ALC3
*/
#define WM8961_ALCMODE 0x0100 /* ALCMODE */
#define WM8961_ALCMODE_MASK 0x0100 /* ALCMODE */
#define WM8961_ALCMODE_SHIFT 8 /* ALCMODE */
#define WM8961_ALCMODE_WIDTH 1 /* ALCMODE */
#define WM8961_DCY_MASK 0x00F0 /* DCY - [7:4] */
#define WM8961_DCY_SHIFT 4 /* DCY - [7:4] */
#define WM8961_DCY_WIDTH 4 /* DCY - [7:4] */
#define WM8961_ATK_MASK 0x000F /* ATK - [3:0] */
#define WM8961_ATK_SHIFT 0 /* ATK - [3:0] */
#define WM8961_ATK_WIDTH 4 /* ATK - [3:0] */
/*
* R20 (0x14) - Noise Gate
*/
#define WM8961_NGTH_MASK 0x00F8 /* NGTH - [7:3] */
#define WM8961_NGTH_SHIFT 3 /* NGTH - [7:3] */
#define WM8961_NGTH_WIDTH 5 /* NGTH - [7:3] */
#define WM8961_NGG 0x0002 /* NGG */
#define WM8961_NGG_MASK 0x0002 /* NGG */
#define WM8961_NGG_SHIFT 1 /* NGG */
#define WM8961_NGG_WIDTH 1 /* NGG */
#define WM8961_NGAT 0x0001 /* NGAT */
#define WM8961_NGAT_MASK 0x0001 /* NGAT */
#define WM8961_NGAT_SHIFT 0 /* NGAT */
#define WM8961_NGAT_WIDTH 1 /* NGAT */
/*
* R21 (0x15) - Left ADC volume
*/
#define WM8961_ADCVU 0x0100 /* ADCVU */
#define WM8961_ADCVU_MASK 0x0100 /* ADCVU */
#define WM8961_ADCVU_SHIFT 8 /* ADCVU */
#define WM8961_ADCVU_WIDTH 1 /* ADCVU */
#define WM8961_LADCVOL_MASK 0x00FF /* LADCVOL - [7:0] */
#define WM8961_LADCVOL_SHIFT 0 /* LADCVOL - [7:0] */
#define WM8961_LADCVOL_WIDTH 8 /* LADCVOL - [7:0] */
/*
* R22 (0x16) - Right ADC volume
*/
#define WM8961_ADCVU 0x0100 /* ADCVU */
#define WM8961_ADCVU_MASK 0x0100 /* ADCVU */
#define WM8961_ADCVU_SHIFT 8 /* ADCVU */
#define WM8961_ADCVU_WIDTH 1 /* ADCVU */
#define WM8961_RADCVOL_MASK 0x00FF /* RADCVOL - [7:0] */
#define WM8961_RADCVOL_SHIFT 0 /* RADCVOL - [7:0] */
#define WM8961_RADCVOL_WIDTH 8 /* RADCVOL - [7:0] */
/*
* R23 (0x17) - Additional control(1)
*/
#define WM8961_TSDEN 0x0100 /* TSDEN */
#define WM8961_TSDEN_MASK 0x0100 /* TSDEN */
#define WM8961_TSDEN_SHIFT 8 /* TSDEN */
#define WM8961_TSDEN_WIDTH 1 /* TSDEN */
#define WM8961_DMONOMIX 0x0010 /* DMONOMIX */
#define WM8961_DMONOMIX_MASK 0x0010 /* DMONOMIX */
#define WM8961_DMONOMIX_SHIFT 4 /* DMONOMIX */
#define WM8961_DMONOMIX_WIDTH 1 /* DMONOMIX */
#define WM8961_TOEN 0x0001 /* TOEN */
#define WM8961_TOEN_MASK 0x0001 /* TOEN */
#define WM8961_TOEN_SHIFT 0 /* TOEN */
#define WM8961_TOEN_WIDTH 1 /* TOEN */
/*
* R24 (0x18) - Additional control(2)
*/
#define WM8961_TRIS 0x0008 /* TRIS */
#define WM8961_TRIS_MASK 0x0008 /* TRIS */
#define WM8961_TRIS_SHIFT 3 /* TRIS */
#define WM8961_TRIS_WIDTH 1 /* TRIS */
/*
* R25 (0x19) - Pwr Mgmt (1)
*/
#define WM8961_VMIDSEL_MASK 0x0180 /* VMIDSEL - [8:7] */
#define WM8961_VMIDSEL_SHIFT 7 /* VMIDSEL - [8:7] */
#define WM8961_VMIDSEL_WIDTH 2 /* VMIDSEL - [8:7] */
#define WM8961_VREF 0x0040 /* VREF */
#define WM8961_VREF_MASK 0x0040 /* VREF */
#define WM8961_VREF_SHIFT 6 /* VREF */
#define WM8961_VREF_WIDTH 1 /* VREF */
#define WM8961_AINL 0x0020 /* AINL */
#define WM8961_AINL_MASK 0x0020 /* AINL */
#define WM8961_AINL_SHIFT 5 /* AINL */
#define WM8961_AINL_WIDTH 1 /* AINL */
#define WM8961_AINR 0x0010 /* AINR */
#define WM8961_AINR_MASK 0x0010 /* AINR */
#define WM8961_AINR_SHIFT 4 /* AINR */
#define WM8961_AINR_WIDTH 1 /* AINR */
#define WM8961_ADCL 0x0008 /* ADCL */
#define WM8961_ADCL_MASK 0x0008 /* ADCL */
#define WM8961_ADCL_SHIFT 3 /* ADCL */
#define WM8961_ADCL_WIDTH 1 /* ADCL */
#define WM8961_ADCR 0x0004 /* ADCR */
#define WM8961_ADCR_MASK 0x0004 /* ADCR */
#define WM8961_ADCR_SHIFT 2 /* ADCR */
#define WM8961_ADCR_WIDTH 1 /* ADCR */
#define WM8961_MICB 0x0002 /* MICB */
#define WM8961_MICB_MASK 0x0002 /* MICB */
#define WM8961_MICB_SHIFT 1 /* MICB */
#define WM8961_MICB_WIDTH 1 /* MICB */
/*
* R26 (0x1A) - Pwr Mgmt (2)
*/
#define WM8961_DACL 0x0100 /* DACL */
#define WM8961_DACL_MASK 0x0100 /* DACL */
#define WM8961_DACL_SHIFT 8 /* DACL */
#define WM8961_DACL_WIDTH 1 /* DACL */
#define WM8961_DACR 0x0080 /* DACR */
#define WM8961_DACR_MASK 0x0080 /* DACR */
#define WM8961_DACR_SHIFT 7 /* DACR */
#define WM8961_DACR_WIDTH 1 /* DACR */
#define WM8961_LOUT1_PGA 0x0040 /* LOUT1_PGA */
#define WM8961_LOUT1_PGA_MASK 0x0040 /* LOUT1_PGA */
#define WM8961_LOUT1_PGA_SHIFT 6 /* LOUT1_PGA */
#define WM8961_LOUT1_PGA_WIDTH 1 /* LOUT1_PGA */
#define WM8961_ROUT1_PGA 0x0020 /* ROUT1_PGA */
#define WM8961_ROUT1_PGA_MASK 0x0020 /* ROUT1_PGA */
#define WM8961_ROUT1_PGA_SHIFT 5 /* ROUT1_PGA */
#define WM8961_ROUT1_PGA_WIDTH 1 /* ROUT1_PGA */
#define WM8961_SPKL_PGA 0x0010 /* SPKL_PGA */
#define WM8961_SPKL_PGA_MASK 0x0010 /* SPKL_PGA */
#define WM8961_SPKL_PGA_SHIFT 4 /* SPKL_PGA */
#define WM8961_SPKL_PGA_WIDTH 1 /* SPKL_PGA */
#define WM8961_SPKR_PGA 0x0008 /* SPKR_PGA */
#define WM8961_SPKR_PGA_MASK 0x0008 /* SPKR_PGA */
#define WM8961_SPKR_PGA_SHIFT 3 /* SPKR_PGA */
#define WM8961_SPKR_PGA_WIDTH 1 /* SPKR_PGA */
/*
* R27 (0x1B) - Additional Control (3)
*/
#define WM8961_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */
#define WM8961_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */
#define WM8961_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */
/*
* R28 (0x1C) - Anti-pop
*/
#define WM8961_BUFDCOPEN 0x0010 /* BUFDCOPEN */
#define WM8961_BUFDCOPEN_MASK 0x0010 /* BUFDCOPEN */
#define WM8961_BUFDCOPEN_SHIFT 4 /* BUFDCOPEN */
#define WM8961_BUFDCOPEN_WIDTH 1 /* BUFDCOPEN */
#define WM8961_BUFIOEN 0x0008 /* BUFIOEN */
#define WM8961_BUFIOEN_MASK 0x0008 /* BUFIOEN */
#define WM8961_BUFIOEN_SHIFT 3 /* BUFIOEN */
#define WM8961_BUFIOEN_WIDTH 1 /* BUFIOEN */
#define WM8961_SOFT_ST 0x0004 /* SOFT_ST */
#define WM8961_SOFT_ST_MASK 0x0004 /* SOFT_ST */
#define WM8961_SOFT_ST_SHIFT 2 /* SOFT_ST */
#define WM8961_SOFT_ST_WIDTH 1 /* SOFT_ST */
/*
* R30 (0x1E) - Clocking 3
*/
#define WM8961_CLK_TO_DIV_MASK 0x0180 /* CLK_TO_DIV - [8:7] */
#define WM8961_CLK_TO_DIV_SHIFT 7 /* CLK_TO_DIV - [8:7] */
#define WM8961_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [8:7] */
#define WM8961_CLK_256K_DIV_MASK 0x007E /* CLK_256K_DIV - [6:1] */
#define WM8961_CLK_256K_DIV_SHIFT 1 /* CLK_256K_DIV - [6:1] */
#define WM8961_CLK_256K_DIV_WIDTH 6 /* CLK_256K_DIV - [6:1] */
#define WM8961_MANUAL_MODE 0x0001 /* MANUAL_MODE */
#define WM8961_MANUAL_MODE_MASK 0x0001 /* MANUAL_MODE */
#define WM8961_MANUAL_MODE_SHIFT 0 /* MANUAL_MODE */
#define WM8961_MANUAL_MODE_WIDTH 1 /* MANUAL_MODE */
/*
* R32 (0x20) - ADCL signal path
*/
#define WM8961_LMICBOOST_MASK 0x0030 /* LMICBOOST - [5:4] */
#define WM8961_LMICBOOST_SHIFT 4 /* LMICBOOST - [5:4] */
#define WM8961_LMICBOOST_WIDTH 2 /* LMICBOOST - [5:4] */
/*
* R33 (0x21) - ADCR signal path
*/
#define WM8961_RMICBOOST_MASK 0x0030 /* RMICBOOST - [5:4] */
#define WM8961_RMICBOOST_SHIFT 4 /* RMICBOOST - [5:4] */
#define WM8961_RMICBOOST_WIDTH 2 /* RMICBOOST - [5:4] */
/*
* R40 (0x28) - LOUT2 volume
*/
#define WM8961_SPKVU 0x0100 /* SPKVU */
#define WM8961_SPKVU_MASK 0x0100 /* SPKVU */
#define WM8961_SPKVU_SHIFT 8 /* SPKVU */
#define WM8961_SPKVU_WIDTH 1 /* SPKVU */
#define WM8961_SPKLZC 0x0080 /* SPKLZC */
#define WM8961_SPKLZC_MASK 0x0080 /* SPKLZC */
#define WM8961_SPKLZC_SHIFT 7 /* SPKLZC */
#define WM8961_SPKLZC_WIDTH 1 /* SPKLZC */
#define WM8961_SPKLVOL_MASK 0x007F /* SPKLVOL - [6:0] */
#define WM8961_SPKLVOL_SHIFT 0 /* SPKLVOL - [6:0] */
#define WM8961_SPKLVOL_WIDTH 7 /* SPKLVOL - [6:0] */
/*
* R41 (0x29) - ROUT2 volume
*/
#define WM8961_SPKVU 0x0100 /* SPKVU */
#define WM8961_SPKVU_MASK 0x0100 /* SPKVU */
#define WM8961_SPKVU_SHIFT 8 /* SPKVU */
#define WM8961_SPKVU_WIDTH 1 /* SPKVU */
#define WM8961_SPKRZC 0x0080 /* SPKRZC */
#define WM8961_SPKRZC_MASK 0x0080 /* SPKRZC */
#define WM8961_SPKRZC_SHIFT 7 /* SPKRZC */
#define WM8961_SPKRZC_WIDTH 1 /* SPKRZC */
#define WM8961_SPKRVOL_MASK 0x007F /* SPKRVOL - [6:0] */
#define WM8961_SPKRVOL_SHIFT 0 /* SPKRVOL - [6:0] */
#define WM8961_SPKRVOL_WIDTH 7 /* SPKRVOL - [6:0] */
/*
* R47 (0x2F) - Pwr Mgmt (3)
*/
#define WM8961_TEMP_SHUT 0x0002 /* TEMP_SHUT */
#define WM8961_TEMP_SHUT_MASK 0x0002 /* TEMP_SHUT */
#define WM8961_TEMP_SHUT_SHIFT 1 /* TEMP_SHUT */
#define WM8961_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */
#define WM8961_TEMP_WARN 0x0001 /* TEMP_WARN */
#define WM8961_TEMP_WARN_MASK 0x0001 /* TEMP_WARN */
#define WM8961_TEMP_WARN_SHIFT 0 /* TEMP_WARN */
#define WM8961_TEMP_WARN_WIDTH 1 /* TEMP_WARN */
/*
* R48 (0x30) - Additional Control (4)
*/
#define WM8961_TSENSEN 0x0002 /* TSENSEN */
#define WM8961_TSENSEN_MASK 0x0002 /* TSENSEN */
#define WM8961_TSENSEN_SHIFT 1 /* TSENSEN */
#define WM8961_TSENSEN_WIDTH 1 /* TSENSEN */
#define WM8961_MBSEL 0x0001 /* MBSEL */
#define WM8961_MBSEL_MASK 0x0001 /* MBSEL */
#define WM8961_MBSEL_SHIFT 0 /* MBSEL */
#define WM8961_MBSEL_WIDTH 1 /* MBSEL */
/*
* R49 (0x31) - Class D Control 1
*/
#define WM8961_SPKR_ENA 0x0080 /* SPKR_ENA */
#define WM8961_SPKR_ENA_MASK 0x0080 /* SPKR_ENA */
#define WM8961_SPKR_ENA_SHIFT 7 /* SPKR_ENA */
#define WM8961_SPKR_ENA_WIDTH 1 /* SPKR_ENA */
#define WM8961_SPKL_ENA 0x0040 /* SPKL_ENA */
#define WM8961_SPKL_ENA_MASK 0x0040 /* SPKL_ENA */
#define WM8961_SPKL_ENA_SHIFT 6 /* SPKL_ENA */
#define WM8961_SPKL_ENA_WIDTH 1 /* SPKL_ENA */
/*
* R51 (0x33) - Class D Control 2
*/
#define WM8961_CLASSD_ACGAIN_MASK 0x0007 /* CLASSD_ACGAIN - [2:0] */
#define WM8961_CLASSD_ACGAIN_SHIFT 0 /* CLASSD_ACGAIN - [2:0] */
#define WM8961_CLASSD_ACGAIN_WIDTH 3 /* CLASSD_ACGAIN - [2:0] */
/*
* R56 (0x38) - Clocking 4
*/
#define WM8961_CLK_DCS_DIV_MASK 0x01E0 /* CLK_DCS_DIV - [8:5] */
#define WM8961_CLK_DCS_DIV_SHIFT 5 /* CLK_DCS_DIV - [8:5] */
#define WM8961_CLK_DCS_DIV_WIDTH 4 /* CLK_DCS_DIV - [8:5] */
#define WM8961_CLK_SYS_RATE_MASK 0x001E /* CLK_SYS_RATE - [4:1] */
#define WM8961_CLK_SYS_RATE_SHIFT 1 /* CLK_SYS_RATE - [4:1] */
#define WM8961_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [4:1] */
/*
* R57 (0x39) - DSP Sidetone 0
*/
#define WM8961_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */
#define WM8961_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */
#define WM8961_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */
#define WM8961_ADC_TO_DACR_MASK 0x000C /* ADC_TO_DACR - [3:2] */
#define WM8961_ADC_TO_DACR_SHIFT 2 /* ADC_TO_DACR - [3:2] */
#define WM8961_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [3:2] */
/*
* R58 (0x3A) - DSP Sidetone 1
*/
#define WM8961_ADCL_DAC_SVOL_MASK 0x00F0 /* ADCL_DAC_SVOL - [7:4] */
#define WM8961_ADCL_DAC_SVOL_SHIFT 4 /* ADCL_DAC_SVOL - [7:4] */
#define WM8961_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [7:4] */
#define WM8961_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */
#define WM8961_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */
#define WM8961_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */
/*
* R60 (0x3C) - DC Servo 0
*/
#define WM8961_DCS_ENA_CHAN_INL 0x0080 /* DCS_ENA_CHAN_INL */
#define WM8961_DCS_ENA_CHAN_INL_MASK 0x0080 /* DCS_ENA_CHAN_INL */
#define WM8961_DCS_ENA_CHAN_INL_SHIFT 7 /* DCS_ENA_CHAN_INL */
#define WM8961_DCS_ENA_CHAN_INL_WIDTH 1 /* DCS_ENA_CHAN_INL */
#define WM8961_DCS_TRIG_STARTUP_INL 0x0040 /* DCS_TRIG_STARTUP_INL */
#define WM8961_DCS_TRIG_STARTUP_INL_MASK 0x0040 /* DCS_TRIG_STARTUP_INL */
#define WM8961_DCS_TRIG_STARTUP_INL_SHIFT 6 /* DCS_TRIG_STARTUP_INL */
#define WM8961_DCS_TRIG_STARTUP_INL_WIDTH 1 /* DCS_TRIG_STARTUP_INL */
#define WM8961_DCS_TRIG_SERIES_INL 0x0010 /* DCS_TRIG_SERIES_INL */
#define WM8961_DCS_TRIG_SERIES_INL_MASK 0x0010 /* DCS_TRIG_SERIES_INL */
#define WM8961_DCS_TRIG_SERIES_INL_SHIFT 4 /* DCS_TRIG_SERIES_INL */
#define WM8961_DCS_TRIG_SERIES_INL_WIDTH 1 /* DCS_TRIG_SERIES_INL */
#define WM8961_DCS_ENA_CHAN_INR 0x0008 /* DCS_ENA_CHAN_INR */
#define WM8961_DCS_ENA_CHAN_INR_MASK 0x0008 /* DCS_ENA_CHAN_INR */
#define WM8961_DCS_ENA_CHAN_INR_SHIFT 3 /* DCS_ENA_CHAN_INR */
#define WM8961_DCS_ENA_CHAN_INR_WIDTH 1 /* DCS_ENA_CHAN_INR */
#define WM8961_DCS_TRIG_STARTUP_INR 0x0004 /* DCS_TRIG_STARTUP_INR */
#define WM8961_DCS_TRIG_STARTUP_INR_MASK 0x0004 /* DCS_TRIG_STARTUP_INR */
#define WM8961_DCS_TRIG_STARTUP_INR_SHIFT 2 /* DCS_TRIG_STARTUP_INR */
#define WM8961_DCS_TRIG_STARTUP_INR_WIDTH 1 /* DCS_TRIG_STARTUP_INR */
#define WM8961_DCS_TRIG_SERIES_INR 0x0001 /* DCS_TRIG_SERIES_INR */
#define WM8961_DCS_TRIG_SERIES_INR_MASK 0x0001 /* DCS_TRIG_SERIES_INR */
#define WM8961_DCS_TRIG_SERIES_INR_SHIFT 0 /* DCS_TRIG_SERIES_INR */
#define WM8961_DCS_TRIG_SERIES_INR_WIDTH 1 /* DCS_TRIG_SERIES_INR */
/*
* R61 (0x3D) - DC Servo 1
*/
#define WM8961_DCS_ENA_CHAN_HPL 0x0080 /* DCS_ENA_CHAN_HPL */
#define WM8961_DCS_ENA_CHAN_HPL_MASK 0x0080 /* DCS_ENA_CHAN_HPL */
#define WM8961_DCS_ENA_CHAN_HPL_SHIFT 7 /* DCS_ENA_CHAN_HPL */
#define WM8961_DCS_ENA_CHAN_HPL_WIDTH 1 /* DCS_ENA_CHAN_HPL */
#define WM8961_DCS_TRIG_STARTUP_HPL 0x0040 /* DCS_TRIG_STARTUP_HPL */
#define WM8961_DCS_TRIG_STARTUP_HPL_MASK 0x0040 /* DCS_TRIG_STARTUP_HPL */
#define WM8961_DCS_TRIG_STARTUP_HPL_SHIFT 6 /* DCS_TRIG_STARTUP_HPL */
#define WM8961_DCS_TRIG_STARTUP_HPL_WIDTH 1 /* DCS_TRIG_STARTUP_HPL */
#define WM8961_DCS_TRIG_SERIES_HPL 0x0010 /* DCS_TRIG_SERIES_HPL */
#define WM8961_DCS_TRIG_SERIES_HPL_MASK 0x0010 /* DCS_TRIG_SERIES_HPL */
#define WM8961_DCS_TRIG_SERIES_HPL_SHIFT 4 /* DCS_TRIG_SERIES_HPL */
#define WM8961_DCS_TRIG_SERIES_HPL_WIDTH 1 /* DCS_TRIG_SERIES_HPL */
#define WM8961_DCS_ENA_CHAN_HPR 0x0008 /* DCS_ENA_CHAN_HPR */
#define WM8961_DCS_ENA_CHAN_HPR_MASK 0x0008 /* DCS_ENA_CHAN_HPR */
#define WM8961_DCS_ENA_CHAN_HPR_SHIFT 3 /* DCS_ENA_CHAN_HPR */
#define WM8961_DCS_ENA_CHAN_HPR_WIDTH 1 /* DCS_ENA_CHAN_HPR */
#define WM8961_DCS_TRIG_STARTUP_HPR 0x0004 /* DCS_TRIG_STARTUP_HPR */
#define WM8961_DCS_TRIG_STARTUP_HPR_MASK 0x0004 /* DCS_TRIG_STARTUP_HPR */
#define WM8961_DCS_TRIG_STARTUP_HPR_SHIFT 2 /* DCS_TRIG_STARTUP_HPR */
#define WM8961_DCS_TRIG_STARTUP_HPR_WIDTH 1 /* DCS_TRIG_STARTUP_HPR */
#define WM8961_DCS_TRIG_SERIES_HPR 0x0001 /* DCS_TRIG_SERIES_HPR */
#define WM8961_DCS_TRIG_SERIES_HPR_MASK 0x0001 /* DCS_TRIG_SERIES_HPR */
#define WM8961_DCS_TRIG_SERIES_HPR_SHIFT 0 /* DCS_TRIG_SERIES_HPR */
#define WM8961_DCS_TRIG_SERIES_HPR_WIDTH 1 /* DCS_TRIG_SERIES_HPR */
/*
* R63 (0x3F) - DC Servo 3
*/
#define WM8961_DCS_FILT_BW_SERIES_MASK 0x0030 /* DCS_FILT_BW_SERIES - [5:4] */
#define WM8961_DCS_FILT_BW_SERIES_SHIFT 4 /* DCS_FILT_BW_SERIES - [5:4] */
#define WM8961_DCS_FILT_BW_SERIES_WIDTH 2 /* DCS_FILT_BW_SERIES - [5:4] */
/*
* R65 (0x41) - DC Servo 5
*/
#define WM8961_DCS_SERIES_NO_HP_MASK 0x007F /* DCS_SERIES_NO_HP - [6:0] */
#define WM8961_DCS_SERIES_NO_HP_SHIFT 0 /* DCS_SERIES_NO_HP - [6:0] */
#define WM8961_DCS_SERIES_NO_HP_WIDTH 7 /* DCS_SERIES_NO_HP - [6:0] */
/*
* R68 (0x44) - Analogue PGA Bias
*/
#define WM8961_HP_PGAS_BIAS_MASK 0x0007 /* HP_PGAS_BIAS - [2:0] */
#define WM8961_HP_PGAS_BIAS_SHIFT 0 /* HP_PGAS_BIAS - [2:0] */
#define WM8961_HP_PGAS_BIAS_WIDTH 3 /* HP_PGAS_BIAS - [2:0] */
/*
* R69 (0x45) - Analogue HP 0
*/
#define WM8961_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */
#define WM8961_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */
#define WM8961_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */
#define WM8961_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */
#define WM8961_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */
#define WM8961_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */
#define WM8961_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */
#define WM8961_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */
#define WM8961_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */
#define WM8961_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */
#define WM8961_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */
#define WM8961_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */
#define WM8961_HPL_ENA 0x0010 /* HPL_ENA */
#define WM8961_HPL_ENA_MASK 0x0010 /* HPL_ENA */
#define WM8961_HPL_ENA_SHIFT 4 /* HPL_ENA */
#define WM8961_HPL_ENA_WIDTH 1 /* HPL_ENA */
#define WM8961_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */
#define WM8961_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */
#define WM8961_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */
#define WM8961_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */
#define WM8961_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */
#define WM8961_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */
#define WM8961_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */
#define WM8961_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */
#define WM8961_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */
#define WM8961_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */
#define WM8961_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */
#define WM8961_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */
#define WM8961_HPR_ENA 0x0001 /* HPR_ENA */
#define WM8961_HPR_ENA_MASK 0x0001 /* HPR_ENA */
#define WM8961_HPR_ENA_SHIFT 0 /* HPR_ENA */
#define WM8961_HPR_ENA_WIDTH 1 /* HPR_ENA */
/*
* R71 (0x47) - Analogue HP 2
*/
#define WM8961_HPL_VOL_MASK 0x01C0 /* HPL_VOL - [8:6] */
#define WM8961_HPL_VOL_SHIFT 6 /* HPL_VOL - [8:6] */
#define WM8961_HPL_VOL_WIDTH 3 /* HPL_VOL - [8:6] */
#define WM8961_HPR_VOL_MASK 0x0038 /* HPR_VOL - [5:3] */
#define WM8961_HPR_VOL_SHIFT 3 /* HPR_VOL - [5:3] */
#define WM8961_HPR_VOL_WIDTH 3 /* HPR_VOL - [5:3] */
#define WM8961_HP_BIAS_BOOST_MASK 0x0007 /* HP_BIAS_BOOST - [2:0] */
#define WM8961_HP_BIAS_BOOST_SHIFT 0 /* HP_BIAS_BOOST - [2:0] */
#define WM8961_HP_BIAS_BOOST_WIDTH 3 /* HP_BIAS_BOOST - [2:0] */
/*
* R72 (0x48) - Charge Pump 1
*/
#define WM8961_CP_ENA 0x0001 /* CP_ENA */
#define WM8961_CP_ENA_MASK 0x0001 /* CP_ENA */
#define WM8961_CP_ENA_SHIFT 0 /* CP_ENA */
#define WM8961_CP_ENA_WIDTH 1 /* CP_ENA */
/*
* R82 (0x52) - Charge Pump B
*/
#define WM8961_CP_DYN_PWR_MASK 0x0003 /* CP_DYN_PWR - [1:0] */
#define WM8961_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR - [1:0] */
#define WM8961_CP_DYN_PWR_WIDTH 2 /* CP_DYN_PWR - [1:0] */
/*
* R87 (0x57) - Write Sequencer 1
*/
#define WM8961_WSEQ_ENA 0x0020 /* WSEQ_ENA */
#define WM8961_WSEQ_ENA_MASK 0x0020 /* WSEQ_ENA */
#define WM8961_WSEQ_ENA_SHIFT 5 /* WSEQ_ENA */
#define WM8961_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
#define WM8961_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */
#define WM8961_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */
#define WM8961_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */
/*
* R88 (0x58) - Write Sequencer 2
*/
#define WM8961_WSEQ_EOS 0x0100 /* WSEQ_EOS */
#define WM8961_WSEQ_EOS_MASK 0x0100 /* WSEQ_EOS */
#define WM8961_WSEQ_EOS_SHIFT 8 /* WSEQ_EOS */
#define WM8961_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */
#define WM8961_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */
#define WM8961_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */
#define WM8961_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */
/*
* R89 (0x59) - Write Sequencer 3
*/
#define WM8961_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */
#define WM8961_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */
#define WM8961_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */
/*
* R90 (0x5A) - Write Sequencer 4
*/
#define WM8961_WSEQ_ABORT 0x0100 /* WSEQ_ABORT */
#define WM8961_WSEQ_ABORT_MASK 0x0100 /* WSEQ_ABORT */
#define WM8961_WSEQ_ABORT_SHIFT 8 /* WSEQ_ABORT */
#define WM8961_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
#define WM8961_WSEQ_START 0x0080 /* WSEQ_START */
#define WM8961_WSEQ_START_MASK 0x0080 /* WSEQ_START */
#define WM8961_WSEQ_START_SHIFT 7 /* WSEQ_START */
#define WM8961_WSEQ_START_WIDTH 1 /* WSEQ_START */
#define WM8961_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */
#define WM8961_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */
#define WM8961_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */
/*
* R91 (0x5B) - Write Sequencer 5
*/
#define WM8961_WSEQ_DATA_WIDTH_MASK 0x0070 /* WSEQ_DATA_WIDTH - [6:4] */
#define WM8961_WSEQ_DATA_WIDTH_SHIFT 4 /* WSEQ_DATA_WIDTH - [6:4] */
#define WM8961_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [6:4] */
#define WM8961_WSEQ_DATA_START_MASK 0x000F /* WSEQ_DATA_START - [3:0] */
#define WM8961_WSEQ_DATA_START_SHIFT 0 /* WSEQ_DATA_START - [3:0] */
#define WM8961_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [3:0] */
/*
* R92 (0x5C) - Write Sequencer 6
*/
#define WM8961_WSEQ_DELAY_MASK 0x000F /* WSEQ_DELAY - [3:0] */
#define WM8961_WSEQ_DELAY_SHIFT 0 /* WSEQ_DELAY - [3:0] */
#define WM8961_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [3:0] */
/*
* R93 (0x5D) - Write Sequencer 7
*/
#define WM8961_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
#define WM8961_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
#define WM8961_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */
#define WM8961_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
/*
* R252 (0xFC) - General test 1
*/
#define WM8961_ARA_ENA 0x0002 /* ARA_ENA */
#define WM8961_ARA_ENA_MASK 0x0002 /* ARA_ENA */
#define WM8961_ARA_ENA_SHIFT 1 /* ARA_ENA */
#define WM8961_ARA_ENA_WIDTH 1 /* ARA_ENA */
#define WM8961_AUTO_INC 0x0001 /* AUTO_INC */
#define WM8961_AUTO_INC_MASK 0x0001 /* AUTO_INC */
#define WM8961_AUTO_INC_SHIFT 0 /* AUTO_INC */
#define WM8961_AUTO_INC_WIDTH 1 /* AUTO_INC */
#endif

907
kernel/sound/soc/codecs/wm8971.c Normal file
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@@ -0,0 +1,907 @@
/*
* wm8971.c -- WM8971 ALSA SoC Audio driver
*
* Copyright 2005 Lab126, Inc.
*
* Author: Kenneth Kiraly <kiraly@lab126.com>
*
* Based on wm8753.c by Liam Girdwood
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include "wm8971.h"
#define WM8971_VERSION "0.9"
#define WM8971_REG_COUNT 43
static struct workqueue_struct *wm8971_workq = NULL;
/* codec private data */
struct wm8971_priv {
unsigned int sysclk;
};
/*
* wm8971 register cache
* We can't read the WM8971 register space when we
* are using 2 wire for device control, so we cache them instead.
*/
static const u16 wm8971_reg[] = {
0x0097, 0x0097, 0x0079, 0x0079, /* 0 */
0x0000, 0x0008, 0x0000, 0x000a, /* 4 */
0x0000, 0x0000, 0x00ff, 0x00ff, /* 8 */
0x000f, 0x000f, 0x0000, 0x0000, /* 12 */
0x0000, 0x007b, 0x0000, 0x0032, /* 16 */
0x0000, 0x00c3, 0x00c3, 0x00c0, /* 20 */
0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
0x0000, 0x0000, 0x0050, 0x0050, /* 32 */
0x0050, 0x0050, 0x0050, 0x0050, /* 36 */
0x0079, 0x0079, 0x0079, /* 40 */
};
#define wm8971_reset(c) snd_soc_write(c, WM8971_RESET, 0)
/* WM8971 Controls */
static const char *wm8971_bass[] = { "Linear Control", "Adaptive Boost" };
static const char *wm8971_bass_filter[] = { "130Hz @ 48kHz",
"200Hz @ 48kHz" };
static const char *wm8971_treble[] = { "8kHz", "4kHz" };
static const char *wm8971_alc_func[] = { "Off", "Right", "Left", "Stereo" };
static const char *wm8971_ng_type[] = { "Constant PGA Gain",
"Mute ADC Output" };
static const char *wm8971_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
static const char *wm8971_mono_mux[] = {"Stereo", "Mono (Left)",
"Mono (Right)", "Digital Mono"};
static const char *wm8971_dac_phase[] = { "Non Inverted", "Inverted" };
static const char *wm8971_lline_mux[] = {"Line", "NC", "NC", "PGA",
"Differential"};
static const char *wm8971_rline_mux[] = {"Line", "Mic", "NC", "PGA",
"Differential"};
static const char *wm8971_lpga_sel[] = {"Line", "NC", "NC", "Differential"};
static const char *wm8971_rpga_sel[] = {"Line", "Mic", "NC", "Differential"};
static const char *wm8971_adcpol[] = {"Normal", "L Invert", "R Invert",
"L + R Invert"};
static const struct soc_enum wm8971_enum[] = {
SOC_ENUM_SINGLE(WM8971_BASS, 7, 2, wm8971_bass), /* 0 */
SOC_ENUM_SINGLE(WM8971_BASS, 6, 2, wm8971_bass_filter),
SOC_ENUM_SINGLE(WM8971_TREBLE, 6, 2, wm8971_treble),
SOC_ENUM_SINGLE(WM8971_ALC1, 7, 4, wm8971_alc_func),
SOC_ENUM_SINGLE(WM8971_NGATE, 1, 2, wm8971_ng_type), /* 4 */
SOC_ENUM_SINGLE(WM8971_ADCDAC, 1, 4, wm8971_deemp),
SOC_ENUM_SINGLE(WM8971_ADCTL1, 4, 4, wm8971_mono_mux),
SOC_ENUM_SINGLE(WM8971_ADCTL1, 1, 2, wm8971_dac_phase),
SOC_ENUM_SINGLE(WM8971_LOUTM1, 0, 5, wm8971_lline_mux), /* 8 */
SOC_ENUM_SINGLE(WM8971_ROUTM1, 0, 5, wm8971_rline_mux),
SOC_ENUM_SINGLE(WM8971_LADCIN, 6, 4, wm8971_lpga_sel),
SOC_ENUM_SINGLE(WM8971_RADCIN, 6, 4, wm8971_rpga_sel),
SOC_ENUM_SINGLE(WM8971_ADCDAC, 5, 4, wm8971_adcpol), /* 12 */
SOC_ENUM_SINGLE(WM8971_ADCIN, 6, 4, wm8971_mono_mux),
};
static const struct snd_kcontrol_new wm8971_snd_controls[] = {
SOC_DOUBLE_R("Capture Volume", WM8971_LINVOL, WM8971_RINVOL, 0, 63, 0),
SOC_DOUBLE_R("Capture ZC Switch", WM8971_LINVOL, WM8971_RINVOL,
6, 1, 0),
SOC_DOUBLE_R("Capture Switch", WM8971_LINVOL, WM8971_RINVOL, 7, 1, 1),
SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8971_LOUT1V,
WM8971_ROUT1V, 7, 1, 0),
SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8971_LOUT2V,
WM8971_ROUT2V, 7, 1, 0),
SOC_SINGLE("Mono Playback ZC Switch", WM8971_MOUTV, 7, 1, 0),
SOC_DOUBLE_R("PCM Volume", WM8971_LDAC, WM8971_RDAC, 0, 255, 0),
SOC_DOUBLE_R("Bypass Left Playback Volume", WM8971_LOUTM1,
WM8971_LOUTM2, 4, 7, 1),
SOC_DOUBLE_R("Bypass Right Playback Volume", WM8971_ROUTM1,
WM8971_ROUTM2, 4, 7, 1),
SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8971_MOUTM1,
WM8971_MOUTM2, 4, 7, 1),
SOC_DOUBLE_R("Headphone Playback Volume", WM8971_LOUT1V,
WM8971_ROUT1V, 0, 127, 0),
SOC_DOUBLE_R("Speaker Playback Volume", WM8971_LOUT2V,
WM8971_ROUT2V, 0, 127, 0),
SOC_ENUM("Bass Boost", wm8971_enum[0]),
SOC_ENUM("Bass Filter", wm8971_enum[1]),
SOC_SINGLE("Bass Volume", WM8971_BASS, 0, 7, 1),
SOC_SINGLE("Treble Volume", WM8971_TREBLE, 0, 7, 0),
SOC_ENUM("Treble Cut-off", wm8971_enum[2]),
SOC_SINGLE("Capture Filter Switch", WM8971_ADCDAC, 0, 1, 1),
SOC_SINGLE("ALC Target Volume", WM8971_ALC1, 0, 7, 0),
SOC_SINGLE("ALC Max Volume", WM8971_ALC1, 4, 7, 0),
SOC_SINGLE("ALC Capture Target Volume", WM8971_ALC1, 0, 7, 0),
SOC_SINGLE("ALC Capture Max Volume", WM8971_ALC1, 4, 7, 0),
SOC_ENUM("ALC Capture Function", wm8971_enum[3]),
SOC_SINGLE("ALC Capture ZC Switch", WM8971_ALC2, 7, 1, 0),
SOC_SINGLE("ALC Capture Hold Time", WM8971_ALC2, 0, 15, 0),
SOC_SINGLE("ALC Capture Decay Time", WM8971_ALC3, 4, 15, 0),
SOC_SINGLE("ALC Capture Attack Time", WM8971_ALC3, 0, 15, 0),
SOC_SINGLE("ALC Capture NG Threshold", WM8971_NGATE, 3, 31, 0),
SOC_ENUM("ALC Capture NG Type", wm8971_enum[4]),
SOC_SINGLE("ALC Capture NG Switch", WM8971_NGATE, 0, 1, 0),
SOC_SINGLE("Capture 6dB Attenuate", WM8971_ADCDAC, 8, 1, 0),
SOC_SINGLE("Playback 6dB Attenuate", WM8971_ADCDAC, 7, 1, 0),
SOC_ENUM("Playback De-emphasis", wm8971_enum[5]),
SOC_ENUM("Playback Function", wm8971_enum[6]),
SOC_ENUM("Playback Phase", wm8971_enum[7]),
SOC_DOUBLE_R("Mic Boost", WM8971_LADCIN, WM8971_RADCIN, 4, 3, 0),
};
/*
* DAPM Controls
*/
/* Left Mixer */
static const struct snd_kcontrol_new wm8971_left_mixer_controls[] = {
SOC_DAPM_SINGLE("Playback Switch", WM8971_LOUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8971_LOUTM1, 7, 1, 0),
SOC_DAPM_SINGLE("Right Playback Switch", WM8971_LOUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8971_LOUTM2, 7, 1, 0),
};
/* Right Mixer */
static const struct snd_kcontrol_new wm8971_right_mixer_controls[] = {
SOC_DAPM_SINGLE("Left Playback Switch", WM8971_ROUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8971_ROUTM1, 7, 1, 0),
SOC_DAPM_SINGLE("Playback Switch", WM8971_ROUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8971_ROUTM2, 7, 1, 0),
};
/* Mono Mixer */
static const struct snd_kcontrol_new wm8971_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("Left Playback Switch", WM8971_MOUTM1, 8, 1, 0),
SOC_DAPM_SINGLE("Left Bypass Switch", WM8971_MOUTM1, 7, 1, 0),
SOC_DAPM_SINGLE("Right Playback Switch", WM8971_MOUTM2, 8, 1, 0),
SOC_DAPM_SINGLE("Right Bypass Switch", WM8971_MOUTM2, 7, 1, 0),
};
/* Left Line Mux */
static const struct snd_kcontrol_new wm8971_left_line_controls =
SOC_DAPM_ENUM("Route", wm8971_enum[8]);
/* Right Line Mux */
static const struct snd_kcontrol_new wm8971_right_line_controls =
SOC_DAPM_ENUM("Route", wm8971_enum[9]);
/* Left PGA Mux */
static const struct snd_kcontrol_new wm8971_left_pga_controls =
SOC_DAPM_ENUM("Route", wm8971_enum[10]);
/* Right PGA Mux */
static const struct snd_kcontrol_new wm8971_right_pga_controls =
SOC_DAPM_ENUM("Route", wm8971_enum[11]);
/* Mono ADC Mux */
static const struct snd_kcontrol_new wm8971_monomux_controls =
SOC_DAPM_ENUM("Route", wm8971_enum[13]);
static const struct snd_soc_dapm_widget wm8971_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
&wm8971_left_mixer_controls[0],
ARRAY_SIZE(wm8971_left_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
&wm8971_right_mixer_controls[0],
ARRAY_SIZE(wm8971_right_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", WM8971_PWR2, 2, 0,
&wm8971_mono_mixer_controls[0],
ARRAY_SIZE(wm8971_mono_mixer_controls)),
SND_SOC_DAPM_PGA("Right Out 2", WM8971_PWR2, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Out 2", WM8971_PWR2, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Out 1", WM8971_PWR2, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Out 1", WM8971_PWR2, 6, 0, NULL, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8971_PWR2, 7, 0),
SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8971_PWR2, 8, 0),
SND_SOC_DAPM_PGA("Mono Out 1", WM8971_PWR2, 2, 0, NULL, 0),
SND_SOC_DAPM_MICBIAS("Mic Bias", WM8971_PWR1, 1, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8971_PWR1, 2, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8971_PWR1, 3, 0),
SND_SOC_DAPM_MUX("Left PGA Mux", WM8971_PWR1, 5, 0,
&wm8971_left_pga_controls),
SND_SOC_DAPM_MUX("Right PGA Mux", WM8971_PWR1, 4, 0,
&wm8971_right_pga_controls),
SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
&wm8971_left_line_controls),
SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
&wm8971_right_line_controls),
SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
&wm8971_monomux_controls),
SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
&wm8971_monomux_controls),
SND_SOC_DAPM_OUTPUT("LOUT1"),
SND_SOC_DAPM_OUTPUT("ROUT1"),
SND_SOC_DAPM_OUTPUT("LOUT2"),
SND_SOC_DAPM_OUTPUT("ROUT2"),
SND_SOC_DAPM_OUTPUT("MONO"),
SND_SOC_DAPM_INPUT("LINPUT1"),
SND_SOC_DAPM_INPUT("RINPUT1"),
SND_SOC_DAPM_INPUT("MIC"),
};
static const struct snd_soc_dapm_route audio_map[] = {
/* left mixer */
{"Left Mixer", "Playback Switch", "Left DAC"},
{"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
{"Left Mixer", "Right Playback Switch", "Right DAC"},
{"Left Mixer", "Right Bypass Switch", "Right Line Mux"},
/* right mixer */
{"Right Mixer", "Left Playback Switch", "Left DAC"},
{"Right Mixer", "Left Bypass Switch", "Left Line Mux"},
{"Right Mixer", "Playback Switch", "Right DAC"},
{"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
/* left out 1 */
{"Left Out 1", NULL, "Left Mixer"},
{"LOUT1", NULL, "Left Out 1"},
/* left out 2 */
{"Left Out 2", NULL, "Left Mixer"},
{"LOUT2", NULL, "Left Out 2"},
/* right out 1 */
{"Right Out 1", NULL, "Right Mixer"},
{"ROUT1", NULL, "Right Out 1"},
/* right out 2 */
{"Right Out 2", NULL, "Right Mixer"},
{"ROUT2", NULL, "Right Out 2"},
/* mono mixer */
{"Mono Mixer", "Left Playback Switch", "Left DAC"},
{"Mono Mixer", "Left Bypass Switch", "Left Line Mux"},
{"Mono Mixer", "Right Playback Switch", "Right DAC"},
{"Mono Mixer", "Right Bypass Switch", "Right Line Mux"},
/* mono out */
{"Mono Out", NULL, "Mono Mixer"},
{"MONO1", NULL, "Mono Out"},
/* Left Line Mux */
{"Left Line Mux", "Line", "LINPUT1"},
{"Left Line Mux", "PGA", "Left PGA Mux"},
{"Left Line Mux", "Differential", "Differential Mux"},
/* Right Line Mux */
{"Right Line Mux", "Line", "RINPUT1"},
{"Right Line Mux", "Mic", "MIC"},
{"Right Line Mux", "PGA", "Right PGA Mux"},
{"Right Line Mux", "Differential", "Differential Mux"},
/* Left PGA Mux */
{"Left PGA Mux", "Line", "LINPUT1"},
{"Left PGA Mux", "Differential", "Differential Mux"},
/* Right PGA Mux */
{"Right PGA Mux", "Line", "RINPUT1"},
{"Right PGA Mux", "Differential", "Differential Mux"},
/* Differential Mux */
{"Differential Mux", "Line", "LINPUT1"},
{"Differential Mux", "Line", "RINPUT1"},
/* Left ADC Mux */
{"Left ADC Mux", "Stereo", "Left PGA Mux"},
{"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
{"Left ADC Mux", "Digital Mono", "Left PGA Mux"},
/* Right ADC Mux */
{"Right ADC Mux", "Stereo", "Right PGA Mux"},
{"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
{"Right ADC Mux", "Digital Mono", "Right PGA Mux"},
/* ADC */
{"Left ADC", NULL, "Left ADC Mux"},
{"Right ADC", NULL, "Right ADC Mux"},
};
static int wm8971_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, wm8971_dapm_widgets,
ARRAY_SIZE(wm8971_dapm_widgets));
snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
snd_soc_dapm_new_widgets(codec);
return 0;
}
struct _coeff_div {
u32 mclk;
u32 rate;
u16 fs;
u8 sr:5;
u8 usb:1;
};
/* codec hifi mclk clock divider coefficients */
static const struct _coeff_div coeff_div[] = {
/* 8k */
{12288000, 8000, 1536, 0x6, 0x0},
{11289600, 8000, 1408, 0x16, 0x0},
{18432000, 8000, 2304, 0x7, 0x0},
{16934400, 8000, 2112, 0x17, 0x0},
{12000000, 8000, 1500, 0x6, 0x1},
/* 11.025k */
{11289600, 11025, 1024, 0x18, 0x0},
{16934400, 11025, 1536, 0x19, 0x0},
{12000000, 11025, 1088, 0x19, 0x1},
/* 16k */
{12288000, 16000, 768, 0xa, 0x0},
{18432000, 16000, 1152, 0xb, 0x0},
{12000000, 16000, 750, 0xa, 0x1},
/* 22.05k */
{11289600, 22050, 512, 0x1a, 0x0},
{16934400, 22050, 768, 0x1b, 0x0},
{12000000, 22050, 544, 0x1b, 0x1},
/* 32k */
{12288000, 32000, 384, 0xc, 0x0},
{18432000, 32000, 576, 0xd, 0x0},
{12000000, 32000, 375, 0xa, 0x1},
/* 44.1k */
{11289600, 44100, 256, 0x10, 0x0},
{16934400, 44100, 384, 0x11, 0x0},
{12000000, 44100, 272, 0x11, 0x1},
/* 48k */
{12288000, 48000, 256, 0x0, 0x0},
{18432000, 48000, 384, 0x1, 0x0},
{12000000, 48000, 250, 0x0, 0x1},
/* 88.2k */
{11289600, 88200, 128, 0x1e, 0x0},
{16934400, 88200, 192, 0x1f, 0x0},
{12000000, 88200, 136, 0x1f, 0x1},
/* 96k */
{12288000, 96000, 128, 0xe, 0x0},
{18432000, 96000, 192, 0xf, 0x0},
{12000000, 96000, 125, 0xe, 0x1},
};
static int get_coeff(int mclk, int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
return i;
}
return -EINVAL;
}
static int wm8971_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct wm8971_priv *wm8971 = codec->private_data;
switch (freq) {
case 11289600:
case 12000000:
case 12288000:
case 16934400:
case 18432000:
wm8971->sysclk = freq;
return 0;
}
return -EINVAL;
}
static int wm8971_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 iface = 0;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
iface = 0x0040;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0002;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0001;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x0003;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= 0x0013;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0090;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0080;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0010;
break;
default:
return -EINVAL;
}
snd_soc_write(codec, WM8971_IFACE, iface);
return 0;
}
static int wm8971_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
struct wm8971_priv *wm8971 = codec->private_data;
u16 iface = snd_soc_read(codec, WM8971_IFACE) & 0x1f3;
u16 srate = snd_soc_read(codec, WM8971_SRATE) & 0x1c0;
int coeff = get_coeff(wm8971->sysclk, params_rate(params));
/* bit size */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
iface |= 0x0004;
break;
case SNDRV_PCM_FORMAT_S24_LE:
iface |= 0x0008;
break;
case SNDRV_PCM_FORMAT_S32_LE:
iface |= 0x000c;
break;
}
/* set iface & srate */
snd_soc_write(codec, WM8971_IFACE, iface);
if (coeff >= 0)
snd_soc_write(codec, WM8971_SRATE, srate |
(coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
return 0;
}
static int wm8971_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
u16 mute_reg = snd_soc_read(codec, WM8971_ADCDAC) & 0xfff7;
if (mute)
snd_soc_write(codec, WM8971_ADCDAC, mute_reg | 0x8);
else
snd_soc_write(codec, WM8971_ADCDAC, mute_reg);
return 0;
}
static int wm8971_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
u16 pwr_reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e;
switch (level) {
case SND_SOC_BIAS_ON:
/* set vmid to 50k and unmute dac */
snd_soc_write(codec, WM8971_PWR1, pwr_reg | 0x00c1);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* mute dac and set vmid to 500k, enable VREF */
snd_soc_write(codec, WM8971_PWR1, pwr_reg | 0x0140);
break;
case SND_SOC_BIAS_OFF:
snd_soc_write(codec, WM8971_PWR1, 0x0001);
break;
}
codec->bias_level = level;
return 0;
}
#define WM8971_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define WM8971_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_ops wm8971_dai_ops = {
.hw_params = wm8971_pcm_hw_params,
.digital_mute = wm8971_mute,
.set_fmt = wm8971_set_dai_fmt,
.set_sysclk = wm8971_set_dai_sysclk,
};
struct snd_soc_dai wm8971_dai = {
.name = "WM8971",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM8971_RATES,
.formats = WM8971_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM8971_RATES,
.formats = WM8971_FORMATS,},
.ops = &wm8971_dai_ops,
};
EXPORT_SYMBOL_GPL(wm8971_dai);
static void wm8971_work(struct work_struct *work)
{
struct snd_soc_codec *codec =
container_of(work, struct snd_soc_codec, delayed_work.work);
wm8971_set_bias_level(codec, codec->bias_level);
}
static int wm8971_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
wm8971_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int wm8971_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
int i;
u8 data[2];
u16 *cache = codec->reg_cache;
u16 reg;
/* Sync reg_cache with the hardware */
for (i = 0; i < ARRAY_SIZE(wm8971_reg); i++) {
if (i + 1 == WM8971_RESET)
continue;
data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
data[1] = cache[i] & 0x00ff;
codec->hw_write(codec->control_data, data, 2);
}
wm8971_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
/* charge wm8971 caps */
if (codec->suspend_bias_level == SND_SOC_BIAS_ON) {
reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e;
snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0);
codec->bias_level = SND_SOC_BIAS_ON;
queue_delayed_work(wm8971_workq, &codec->delayed_work,
msecs_to_jiffies(1000));
}
return 0;
}
static int wm8971_init(struct snd_soc_device *socdev,
enum snd_soc_control_type control)
{
struct snd_soc_codec *codec = socdev->card->codec;
int reg, ret = 0;
codec->name = "WM8971";
codec->owner = THIS_MODULE;
codec->set_bias_level = wm8971_set_bias_level;
codec->dai = &wm8971_dai;
codec->reg_cache_size = ARRAY_SIZE(wm8971_reg);
codec->num_dai = 1;
codec->reg_cache = kmemdup(wm8971_reg, sizeof(wm8971_reg), GFP_KERNEL);
if (codec->reg_cache == NULL)
return -ENOMEM;
ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
if (ret < 0) {
printk(KERN_ERR "wm8971: failed to set cache I/O: %d\n", ret);
goto err;
}
wm8971_reset(codec);
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
printk(KERN_ERR "wm8971: failed to create pcms\n");
goto err;
}
/* charge output caps - set vmid to 5k for quick power up */
reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e;
snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0);
codec->bias_level = SND_SOC_BIAS_STANDBY;
queue_delayed_work(wm8971_workq, &codec->delayed_work,
msecs_to_jiffies(1000));
/* set the update bits */
reg = snd_soc_read(codec, WM8971_LDAC);
snd_soc_write(codec, WM8971_LDAC, reg | 0x0100);
reg = snd_soc_read(codec, WM8971_RDAC);
snd_soc_write(codec, WM8971_RDAC, reg | 0x0100);
reg = snd_soc_read(codec, WM8971_LOUT1V);
snd_soc_write(codec, WM8971_LOUT1V, reg | 0x0100);
reg = snd_soc_read(codec, WM8971_ROUT1V);
snd_soc_write(codec, WM8971_ROUT1V, reg | 0x0100);
reg = snd_soc_read(codec, WM8971_LOUT2V);
snd_soc_write(codec, WM8971_LOUT2V, reg | 0x0100);
reg = snd_soc_read(codec, WM8971_ROUT2V);
snd_soc_write(codec, WM8971_ROUT2V, reg | 0x0100);
reg = snd_soc_read(codec, WM8971_LINVOL);
snd_soc_write(codec, WM8971_LINVOL, reg | 0x0100);
reg = snd_soc_read(codec, WM8971_RINVOL);
snd_soc_write(codec, WM8971_RINVOL, reg | 0x0100);
snd_soc_add_controls(codec, wm8971_snd_controls,
ARRAY_SIZE(wm8971_snd_controls));
wm8971_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
printk(KERN_ERR "wm8971: failed to register card\n");
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
err:
kfree(codec->reg_cache);
return ret;
}
/* If the i2c layer weren't so broken, we could pass this kind of data
around */
static struct snd_soc_device *wm8971_socdev;
#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
static int wm8971_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct snd_soc_device *socdev = wm8971_socdev;
struct snd_soc_codec *codec = socdev->card->codec;
int ret;
i2c_set_clientdata(i2c, codec);
codec->control_data = i2c;
ret = wm8971_init(socdev, SND_SOC_I2C);
if (ret < 0)
pr_err("failed to initialise WM8971\n");
return ret;
}
static int wm8971_i2c_remove(struct i2c_client *client)
{
struct snd_soc_codec *codec = i2c_get_clientdata(client);
kfree(codec->reg_cache);
return 0;
}
static const struct i2c_device_id wm8971_i2c_id[] = {
{ "wm8971", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8971_i2c_id);
static struct i2c_driver wm8971_i2c_driver = {
.driver = {
.name = "WM8971 I2C Codec",
.owner = THIS_MODULE,
},
.probe = wm8971_i2c_probe,
.remove = wm8971_i2c_remove,
.id_table = wm8971_i2c_id,
};
static int wm8971_add_i2c_device(struct platform_device *pdev,
const struct wm8971_setup_data *setup)
{
struct i2c_board_info info;
struct i2c_adapter *adapter;
struct i2c_client *client;
int ret;
ret = i2c_add_driver(&wm8971_i2c_driver);
if (ret != 0) {
dev_err(&pdev->dev, "can't add i2c driver\n");
return ret;
}
memset(&info, 0, sizeof(struct i2c_board_info));
info.addr = setup->i2c_address;
strlcpy(info.type, "wm8971", I2C_NAME_SIZE);
adapter = i2c_get_adapter(setup->i2c_bus);
if (!adapter) {
dev_err(&pdev->dev, "can't get i2c adapter %d\n",
setup->i2c_bus);
goto err_driver;
}
client = i2c_new_device(adapter, &info);
i2c_put_adapter(adapter);
if (!client) {
dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
(unsigned int)info.addr);
goto err_driver;
}
return 0;
err_driver:
i2c_del_driver(&wm8971_i2c_driver);
return -ENODEV;
}
#endif
static int wm8971_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct wm8971_setup_data *setup;
struct snd_soc_codec *codec;
struct wm8971_priv *wm8971;
int ret = 0;
pr_info("WM8971 Audio Codec %s", WM8971_VERSION);
setup = socdev->codec_data;
codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
if (codec == NULL)
return -ENOMEM;
wm8971 = kzalloc(sizeof(struct wm8971_priv), GFP_KERNEL);
if (wm8971 == NULL) {
kfree(codec);
return -ENOMEM;
}
codec->private_data = wm8971;
socdev->card->codec = codec;
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
wm8971_socdev = socdev;
INIT_DELAYED_WORK(&codec->delayed_work, wm8971_work);
wm8971_workq = create_workqueue("wm8971");
if (wm8971_workq == NULL) {
kfree(codec->private_data);
kfree(codec);
return -ENOMEM;
}
#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
if (setup->i2c_address) {
ret = wm8971_add_i2c_device(pdev, setup);
}
#endif
/* Add other interfaces here */
if (ret != 0) {
destroy_workqueue(wm8971_workq);
kfree(codec->private_data);
kfree(codec);
}
return ret;
}
/* power down chip */
static int wm8971_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
if (codec->control_data)
wm8971_set_bias_level(codec, SND_SOC_BIAS_OFF);
if (wm8971_workq)
destroy_workqueue(wm8971_workq);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
i2c_unregister_device(codec->control_data);
i2c_del_driver(&wm8971_i2c_driver);
#endif
kfree(codec->private_data);
kfree(codec);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_wm8971 = {
.probe = wm8971_probe,
.remove = wm8971_remove,
.suspend = wm8971_suspend,
.resume = wm8971_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm8971);
static int __init wm8971_modinit(void)
{
return snd_soc_register_dai(&wm8971_dai);
}
module_init(wm8971_modinit);
static void __exit wm8971_exit(void)
{
snd_soc_unregister_dai(&wm8971_dai);
}
module_exit(wm8971_exit);
MODULE_DESCRIPTION("ASoC WM8971 driver");
MODULE_AUTHOR("Lab126");
MODULE_LICENSE("GPL");

64
kernel/sound/soc/codecs/wm8971.h Normal file
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/*
* wm8971.h -- audio driver for WM8971
*
* Copyright 2005 Lab126, Inc.
*
* Author: Kenneth Kiraly <kiraly@lab126.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef _WM8971_H
#define _WM8971_H
#define WM8971_LINVOL 0x00
#define WM8971_RINVOL 0x01
#define WM8971_LOUT1V 0x02
#define WM8971_ROUT1V 0x03
#define WM8971_ADCDAC 0x05
#define WM8971_IFACE 0x07
#define WM8971_SRATE 0x08
#define WM8971_LDAC 0x0a
#define WM8971_RDAC 0x0b
#define WM8971_BASS 0x0c
#define WM8971_TREBLE 0x0d
#define WM8971_RESET 0x0f
#define WM8971_ALC1 0x11
#define WM8971_ALC2 0x12
#define WM8971_ALC3 0x13
#define WM8971_NGATE 0x14
#define WM8971_LADC 0x15
#define WM8971_RADC 0x16
#define WM8971_ADCTL1 0x17
#define WM8971_ADCTL2 0x18
#define WM8971_PWR1 0x19
#define WM8971_PWR2 0x1a
#define WM8971_ADCTL3 0x1b
#define WM8971_ADCIN 0x1f
#define WM8971_LADCIN 0x20
#define WM8971_RADCIN 0x21
#define WM8971_LOUTM1 0x22
#define WM8971_LOUTM2 0x23
#define WM8971_ROUTM1 0x24
#define WM8971_ROUTM2 0x25
#define WM8971_MOUTM1 0x26
#define WM8971_MOUTM2 0x27
#define WM8971_LOUT2V 0x28
#define WM8971_ROUT2V 0x29
#define WM8971_MOUTV 0x2A
#define WM8971_SYSCLK 0
struct wm8971_setup_data {
int i2c_bus;
unsigned short i2c_address;
};
extern struct snd_soc_dai wm8971_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8971;
#endif

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kernel/sound/soc/codecs/wm8974.c Normal file
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/*
* wm8974.c -- WM8974 ALSA Soc Audio driver
*
* Copyright 2006-2009 Wolfson Microelectronics PLC.
*
* Author: Liam Girdwood <linux@wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8974.h"
static const u16 wm8974_reg[WM8974_CACHEREGNUM] = {
0x0000, 0x0000, 0x0000, 0x0000,
0x0050, 0x0000, 0x0140, 0x0000,
0x0000, 0x0000, 0x0000, 0x00ff,
0x0000, 0x0000, 0x0100, 0x00ff,
0x0000, 0x0000, 0x012c, 0x002c,
0x002c, 0x002c, 0x002c, 0x0000,
0x0032, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0038, 0x000b, 0x0032, 0x0000,
0x0008, 0x000c, 0x0093, 0x00e9,
0x0000, 0x0000, 0x0000, 0x0000,
0x0003, 0x0010, 0x0000, 0x0000,
0x0000, 0x0002, 0x0000, 0x0000,
0x0000, 0x0000, 0x0039, 0x0000,
0x0000,
};
#define WM8974_POWER1_BIASEN 0x08
#define WM8974_POWER1_BUFIOEN 0x04
struct wm8974_priv {
struct snd_soc_codec codec;
u16 reg_cache[WM8974_CACHEREGNUM];
};
static struct snd_soc_codec *wm8974_codec;
#define wm8974_reset(c) snd_soc_write(c, WM8974_RESET, 0)
static const char *wm8974_companding[] = {"Off", "NC", "u-law", "A-law" };
static const char *wm8974_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz" };
static const char *wm8974_eqmode[] = {"Capture", "Playback" };
static const char *wm8974_bw[] = {"Narrow", "Wide" };
static const char *wm8974_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz" };
static const char *wm8974_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz" };
static const char *wm8974_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz" };
static const char *wm8974_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" };
static const char *wm8974_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz" };
static const char *wm8974_alc[] = {"ALC", "Limiter" };
static const struct soc_enum wm8974_enum[] = {
SOC_ENUM_SINGLE(WM8974_COMP, 1, 4, wm8974_companding), /* adc */
SOC_ENUM_SINGLE(WM8974_COMP, 3, 4, wm8974_companding), /* dac */
SOC_ENUM_SINGLE(WM8974_DAC, 4, 4, wm8974_deemp),
SOC_ENUM_SINGLE(WM8974_EQ1, 8, 2, wm8974_eqmode),
SOC_ENUM_SINGLE(WM8974_EQ1, 5, 4, wm8974_eq1),
SOC_ENUM_SINGLE(WM8974_EQ2, 8, 2, wm8974_bw),
SOC_ENUM_SINGLE(WM8974_EQ2, 5, 4, wm8974_eq2),
SOC_ENUM_SINGLE(WM8974_EQ3, 8, 2, wm8974_bw),
SOC_ENUM_SINGLE(WM8974_EQ3, 5, 4, wm8974_eq3),
SOC_ENUM_SINGLE(WM8974_EQ4, 8, 2, wm8974_bw),
SOC_ENUM_SINGLE(WM8974_EQ4, 5, 4, wm8974_eq4),
SOC_ENUM_SINGLE(WM8974_EQ5, 8, 2, wm8974_bw),
SOC_ENUM_SINGLE(WM8974_EQ5, 5, 4, wm8974_eq5),
SOC_ENUM_SINGLE(WM8974_ALC3, 8, 2, wm8974_alc),
};
static const char *wm8974_auxmode_text[] = { "Buffer", "Mixer" };
static const struct soc_enum wm8974_auxmode =
SOC_ENUM_SINGLE(WM8974_INPUT, 3, 2, wm8974_auxmode_text);
static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
static const struct snd_kcontrol_new wm8974_snd_controls[] = {
SOC_SINGLE("Digital Loopback Switch", WM8974_COMP, 0, 1, 0),
SOC_ENUM("DAC Companding", wm8974_enum[1]),
SOC_ENUM("ADC Companding", wm8974_enum[0]),
SOC_ENUM("Playback De-emphasis", wm8974_enum[2]),
SOC_SINGLE("DAC Inversion Switch", WM8974_DAC, 0, 1, 0),
SOC_SINGLE_TLV("PCM Volume", WM8974_DACVOL, 0, 255, 0, digital_tlv),
SOC_SINGLE("High Pass Filter Switch", WM8974_ADC, 8, 1, 0),
SOC_SINGLE("High Pass Cut Off", WM8974_ADC, 4, 7, 0),
SOC_SINGLE("ADC Inversion Switch", WM8974_ADC, 0, 1, 0),
SOC_SINGLE_TLV("Capture Volume", WM8974_ADCVOL, 0, 255, 0, digital_tlv),
SOC_ENUM("Equaliser Function", wm8974_enum[3]),
SOC_ENUM("EQ1 Cut Off", wm8974_enum[4]),
SOC_SINGLE_TLV("EQ1 Volume", WM8974_EQ1, 0, 24, 1, eq_tlv),
SOC_ENUM("Equaliser EQ2 Bandwith", wm8974_enum[5]),
SOC_ENUM("EQ2 Cut Off", wm8974_enum[6]),
SOC_SINGLE_TLV("EQ2 Volume", WM8974_EQ2, 0, 24, 1, eq_tlv),
SOC_ENUM("Equaliser EQ3 Bandwith", wm8974_enum[7]),
SOC_ENUM("EQ3 Cut Off", wm8974_enum[8]),
SOC_SINGLE_TLV("EQ3 Volume", WM8974_EQ3, 0, 24, 1, eq_tlv),
SOC_ENUM("Equaliser EQ4 Bandwith", wm8974_enum[9]),
SOC_ENUM("EQ4 Cut Off", wm8974_enum[10]),
SOC_SINGLE_TLV("EQ4 Volume", WM8974_EQ4, 0, 24, 1, eq_tlv),
SOC_ENUM("Equaliser EQ5 Bandwith", wm8974_enum[11]),
SOC_ENUM("EQ5 Cut Off", wm8974_enum[12]),
SOC_SINGLE_TLV("EQ5 Volume", WM8974_EQ5, 0, 24, 1, eq_tlv),
SOC_SINGLE("DAC Playback Limiter Switch", WM8974_DACLIM1, 8, 1, 0),
SOC_SINGLE("DAC Playback Limiter Decay", WM8974_DACLIM1, 4, 15, 0),
SOC_SINGLE("DAC Playback Limiter Attack", WM8974_DACLIM1, 0, 15, 0),
SOC_SINGLE("DAC Playback Limiter Threshold", WM8974_DACLIM2, 4, 7, 0),
SOC_SINGLE("DAC Playback Limiter Boost", WM8974_DACLIM2, 0, 15, 0),
SOC_SINGLE("ALC Enable Switch", WM8974_ALC1, 8, 1, 0),
SOC_SINGLE("ALC Capture Max Gain", WM8974_ALC1, 3, 7, 0),
SOC_SINGLE("ALC Capture Min Gain", WM8974_ALC1, 0, 7, 0),
SOC_SINGLE("ALC Capture ZC Switch", WM8974_ALC2, 8, 1, 0),
SOC_SINGLE("ALC Capture Hold", WM8974_ALC2, 4, 7, 0),
SOC_SINGLE("ALC Capture Target", WM8974_ALC2, 0, 15, 0),
SOC_ENUM("ALC Capture Mode", wm8974_enum[13]),
SOC_SINGLE("ALC Capture Decay", WM8974_ALC3, 4, 15, 0),
SOC_SINGLE("ALC Capture Attack", WM8974_ALC3, 0, 15, 0),
SOC_SINGLE("ALC Capture Noise Gate Switch", WM8974_NGATE, 3, 1, 0),
SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8974_NGATE, 0, 7, 0),
SOC_SINGLE("Capture PGA ZC Switch", WM8974_INPPGA, 7, 1, 0),
SOC_SINGLE_TLV("Capture PGA Volume", WM8974_INPPGA, 0, 63, 0, inpga_tlv),
SOC_SINGLE("Speaker Playback ZC Switch", WM8974_SPKVOL, 7, 1, 0),
SOC_SINGLE("Speaker Playback Switch", WM8974_SPKVOL, 6, 1, 1),
SOC_SINGLE_TLV("Speaker Playback Volume", WM8974_SPKVOL, 0, 63, 0, spk_tlv),
SOC_ENUM("Aux Mode", wm8974_auxmode),
SOC_SINGLE("Capture Boost(+20dB)", WM8974_ADCBOOST, 8, 1, 0),
SOC_SINGLE("Mono Playback Switch", WM8974_MONOMIX, 6, 1, 1),
};
/* Speaker Output Mixer */
static const struct snd_kcontrol_new wm8974_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8974_SPKMIX, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8974_SPKMIX, 5, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8974_SPKMIX, 0, 1, 1),
};
/* Mono Output Mixer */
static const struct snd_kcontrol_new wm8974_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("Line Bypass Switch", WM8974_MONOMIX, 1, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", WM8974_MONOMIX, 2, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", WM8974_MONOMIX, 0, 1, 0),
};
/* Boost mixer */
static const struct snd_kcontrol_new wm8974_boost_mixer[] = {
SOC_DAPM_SINGLE("Aux Switch", WM8974_INPPGA, 6, 1, 0),
};
/* Input PGA */
static const struct snd_kcontrol_new wm8974_inpga[] = {
SOC_DAPM_SINGLE("Aux Switch", WM8974_INPUT, 2, 1, 0),
SOC_DAPM_SINGLE("MicN Switch", WM8974_INPUT, 1, 1, 0),
SOC_DAPM_SINGLE("MicP Switch", WM8974_INPUT, 0, 1, 0),
};
/* AUX Input boost vol */
static const struct snd_kcontrol_new wm8974_aux_boost_controls =
SOC_DAPM_SINGLE("Aux Volume", WM8974_ADCBOOST, 0, 7, 0);
/* Mic Input boost vol */
static const struct snd_kcontrol_new wm8974_mic_boost_controls =
SOC_DAPM_SINGLE("Mic Volume", WM8974_ADCBOOST, 4, 7, 0);
static const struct snd_soc_dapm_widget wm8974_dapm_widgets[] = {
SND_SOC_DAPM_MIXER("Speaker Mixer", WM8974_POWER3, 2, 0,
&wm8974_speaker_mixer_controls[0],
ARRAY_SIZE(wm8974_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", WM8974_POWER3, 3, 0,
&wm8974_mono_mixer_controls[0],
ARRAY_SIZE(wm8974_mono_mixer_controls)),
SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8974_POWER3, 0, 0),
SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8974_POWER2, 0, 0),
SND_SOC_DAPM_PGA("Aux Input", WM8974_POWER1, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("SpkN Out", WM8974_POWER3, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("SpkP Out", WM8974_POWER3, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono Out", WM8974_POWER3, 7, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Input PGA", WM8974_POWER2, 2, 0, wm8974_inpga,
ARRAY_SIZE(wm8974_inpga)),
SND_SOC_DAPM_MIXER("Boost Mixer", WM8974_POWER2, 4, 0,
wm8974_boost_mixer, ARRAY_SIZE(wm8974_boost_mixer)),
SND_SOC_DAPM_MICBIAS("Mic Bias", WM8974_POWER1, 4, 0),
SND_SOC_DAPM_INPUT("MICN"),
SND_SOC_DAPM_INPUT("MICP"),
SND_SOC_DAPM_INPUT("AUX"),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_OUTPUT("SPKOUTP"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
};
static const struct snd_soc_dapm_route audio_map[] = {
/* Mono output mixer */
{"Mono Mixer", "PCM Playback Switch", "DAC"},
{"Mono Mixer", "Aux Playback Switch", "Aux Input"},
{"Mono Mixer", "Line Bypass Switch", "Boost Mixer"},
/* Speaker output mixer */
{"Speaker Mixer", "PCM Playback Switch", "DAC"},
{"Speaker Mixer", "Aux Playback Switch", "Aux Input"},
{"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"},
/* Outputs */
{"Mono Out", NULL, "Mono Mixer"},
{"MONOOUT", NULL, "Mono Out"},
{"SpkN Out", NULL, "Speaker Mixer"},
{"SpkP Out", NULL, "Speaker Mixer"},
{"SPKOUTN", NULL, "SpkN Out"},
{"SPKOUTP", NULL, "SpkP Out"},
/* Boost Mixer */
{"ADC", NULL, "Boost Mixer"},
{"Boost Mixer", "Aux Switch", "Aux Input"},
{"Boost Mixer", NULL, "Input PGA"},
{"Boost Mixer", NULL, "MICP"},
/* Input PGA */
{"Input PGA", "Aux Switch", "Aux Input"},
{"Input PGA", "MicN Switch", "MICN"},
{"Input PGA", "MicP Switch", "MICP"},
/* Inputs */
{"Aux Input", NULL, "AUX"},
};
static int wm8974_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, wm8974_dapm_widgets,
ARRAY_SIZE(wm8974_dapm_widgets));
snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
snd_soc_dapm_new_widgets(codec);
return 0;
}
struct pll_ {
unsigned int pre_div:4; /* prescale - 1 */
unsigned int n:4;
unsigned int k;
};
static struct pll_ pll_div;
/* The size in bits of the pll divide multiplied by 10
* to allow rounding later */
#define FIXED_PLL_SIZE ((1 << 24) * 10)
static void pll_factors(unsigned int target, unsigned int source)
{
unsigned long long Kpart;
unsigned int K, Ndiv, Nmod;
Ndiv = target / source;
if (Ndiv < 6) {
source >>= 1;
pll_div.pre_div = 1;
Ndiv = target / source;
} else
pll_div.pre_div = 0;
if ((Ndiv < 6) || (Ndiv > 12))
printk(KERN_WARNING
"WM8974 N value %u outwith recommended range!\n",
Ndiv);
pll_div.n = Ndiv;
Nmod = target % source;
Kpart = FIXED_PLL_SIZE * (long long)Nmod;
do_div(Kpart, source);
K = Kpart & 0xFFFFFFFF;
/* Check if we need to round */
if ((K % 10) >= 5)
K += 5;
/* Move down to proper range now rounding is done */
K /= 10;
pll_div.k = K;
}
static int wm8974_set_dai_pll(struct snd_soc_dai *codec_dai,
int pll_id, unsigned int freq_in, unsigned int freq_out)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 reg;
if (freq_in == 0 || freq_out == 0) {
/* Clock CODEC directly from MCLK */
reg = snd_soc_read(codec, WM8974_CLOCK);
snd_soc_write(codec, WM8974_CLOCK, reg & 0x0ff);
/* Turn off PLL */
reg = snd_soc_read(codec, WM8974_POWER1);
snd_soc_write(codec, WM8974_POWER1, reg & 0x1df);
return 0;
}
pll_factors(freq_out*4, freq_in);
snd_soc_write(codec, WM8974_PLLN, (pll_div.pre_div << 4) | pll_div.n);
snd_soc_write(codec, WM8974_PLLK1, pll_div.k >> 18);
snd_soc_write(codec, WM8974_PLLK2, (pll_div.k >> 9) & 0x1ff);
snd_soc_write(codec, WM8974_PLLK3, pll_div.k & 0x1ff);
reg = snd_soc_read(codec, WM8974_POWER1);
snd_soc_write(codec, WM8974_POWER1, reg | 0x020);
/* Run CODEC from PLL instead of MCLK */
reg = snd_soc_read(codec, WM8974_CLOCK);
snd_soc_write(codec, WM8974_CLOCK, reg | 0x100);
return 0;
}
/*
* Configure WM8974 clock dividers.
*/
static int wm8974_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
int div_id, int div)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 reg;
switch (div_id) {
case WM8974_OPCLKDIV:
reg = snd_soc_read(codec, WM8974_GPIO) & 0x1cf;
snd_soc_write(codec, WM8974_GPIO, reg | div);
break;
case WM8974_MCLKDIV:
reg = snd_soc_read(codec, WM8974_CLOCK) & 0x11f;
snd_soc_write(codec, WM8974_CLOCK, reg | div);
break;
case WM8974_ADCCLK:
reg = snd_soc_read(codec, WM8974_ADC) & 0x1f7;
snd_soc_write(codec, WM8974_ADC, reg | div);
break;
case WM8974_DACCLK:
reg = snd_soc_read(codec, WM8974_DAC) & 0x1f7;
snd_soc_write(codec, WM8974_DAC, reg | div);
break;
case WM8974_BCLKDIV:
reg = snd_soc_read(codec, WM8974_CLOCK) & 0x1e3;
snd_soc_write(codec, WM8974_CLOCK, reg | div);
break;
default:
return -EINVAL;
}
return 0;
}
static int wm8974_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 iface = 0;
u16 clk = snd_soc_read(codec, WM8974_CLOCK) & 0x1fe;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
clk |= 0x0001;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= 0x0010;
break;
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= 0x0008;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= 0x00018;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= 0x0180;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= 0x0100;
break;
case SND_SOC_DAIFMT_NB_IF:
iface |= 0x0080;
break;
default:
return -EINVAL;
}
snd_soc_write(codec, WM8974_IFACE, iface);
snd_soc_write(codec, WM8974_CLOCK, clk);
return 0;
}
static int wm8974_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
u16 iface = snd_soc_read(codec, WM8974_IFACE) & 0x19f;
u16 adn = snd_soc_read(codec, WM8974_ADD) & 0x1f1;
/* bit size */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
break;
case SNDRV_PCM_FORMAT_S20_3LE:
iface |= 0x0020;
break;
case SNDRV_PCM_FORMAT_S24_LE:
iface |= 0x0040;
break;
case SNDRV_PCM_FORMAT_S32_LE:
iface |= 0x0060;
break;
}
/* filter coefficient */
switch (params_rate(params)) {
case 8000:
adn |= 0x5 << 1;
break;
case 11025:
adn |= 0x4 << 1;
break;
case 16000:
adn |= 0x3 << 1;
break;
case 22050:
adn |= 0x2 << 1;
break;
case 32000:
adn |= 0x1 << 1;
break;
case 44100:
case 48000:
break;
}
snd_soc_write(codec, WM8974_IFACE, iface);
snd_soc_write(codec, WM8974_ADD, adn);
return 0;
}
static int wm8974_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
u16 mute_reg = snd_soc_read(codec, WM8974_DAC) & 0xffbf;
if (mute)
snd_soc_write(codec, WM8974_DAC, mute_reg | 0x40);
else
snd_soc_write(codec, WM8974_DAC, mute_reg);
return 0;
}
/* liam need to make this lower power with dapm */
static int wm8974_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
u16 power1 = snd_soc_read(codec, WM8974_POWER1) & ~0x3;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
power1 |= 0x1; /* VMID 50k */
snd_soc_write(codec, WM8974_POWER1, power1);
break;
case SND_SOC_BIAS_STANDBY:
power1 |= WM8974_POWER1_BIASEN | WM8974_POWER1_BUFIOEN;
if (codec->bias_level == SND_SOC_BIAS_OFF) {
/* Initial cap charge at VMID 5k */
snd_soc_write(codec, WM8974_POWER1, power1 | 0x3);
mdelay(100);
}
power1 |= 0x2; /* VMID 500k */
snd_soc_write(codec, WM8974_POWER1, power1);
break;
case SND_SOC_BIAS_OFF:
snd_soc_write(codec, WM8974_POWER1, 0);
snd_soc_write(codec, WM8974_POWER2, 0);
snd_soc_write(codec, WM8974_POWER3, 0);
break;
}
codec->bias_level = level;
return 0;
}
#define WM8974_RATES (SNDRV_PCM_RATE_8000_48000)
#define WM8974_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_ops wm8974_ops = {
.hw_params = wm8974_pcm_hw_params,
.digital_mute = wm8974_mute,
.set_fmt = wm8974_set_dai_fmt,
.set_clkdiv = wm8974_set_dai_clkdiv,
.set_pll = wm8974_set_dai_pll,
};
struct snd_soc_dai wm8974_dai = {
.name = "WM8974 HiFi",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2, /* Only 1 channel of data */
.rates = WM8974_RATES,
.formats = WM8974_FORMATS,},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2, /* Only 1 channel of data */
.rates = WM8974_RATES,
.formats = WM8974_FORMATS,},
.ops = &wm8974_ops,
.symmetric_rates = 1,
};
EXPORT_SYMBOL_GPL(wm8974_dai);
static int wm8974_suspend(struct platform_device *pdev, pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
wm8974_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int wm8974_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
int i;
u8 data[2];
u16 *cache = codec->reg_cache;
/* Sync reg_cache with the hardware */
for (i = 0; i < ARRAY_SIZE(wm8974_reg); i++) {
data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
data[1] = cache[i] & 0x00ff;
codec->hw_write(codec->control_data, data, 2);
}
wm8974_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
wm8974_set_bias_level(codec, codec->suspend_bias_level);
return 0;
}
static int wm8974_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
if (wm8974_codec == NULL) {
dev_err(&pdev->dev, "Codec device not registered\n");
return -ENODEV;
}
socdev->card->codec = wm8974_codec;
codec = wm8974_codec;
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0) {
dev_err(codec->dev, "failed to create pcms: %d\n", ret);
goto pcm_err;
}
snd_soc_add_controls(codec, wm8974_snd_controls,
ARRAY_SIZE(wm8974_snd_controls));
wm8974_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
dev_err(codec->dev, "failed to register card: %d\n", ret);
goto card_err;
}
return ret;
card_err:
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
pcm_err:
return ret;
}
/* power down chip */
static int wm8974_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_wm8974 = {
.probe = wm8974_probe,
.remove = wm8974_remove,
.suspend = wm8974_suspend,
.resume = wm8974_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm8974);
static __devinit int wm8974_register(struct wm8974_priv *wm8974)
{
int ret;
struct snd_soc_codec *codec = &wm8974->codec;
if (wm8974_codec) {
dev_err(codec->dev, "Another WM8974 is registered\n");
return -EINVAL;
}
mutex_init(&codec->mutex);
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
codec->private_data = wm8974;
codec->name = "WM8974";
codec->owner = THIS_MODULE;
codec->bias_level = SND_SOC_BIAS_OFF;
codec->set_bias_level = wm8974_set_bias_level;
codec->dai = &wm8974_dai;
codec->num_dai = 1;
codec->reg_cache_size = WM8974_CACHEREGNUM;
codec->reg_cache = &wm8974->reg_cache;
ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C);
if (ret < 0) {
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
goto err;
}
memcpy(codec->reg_cache, wm8974_reg, sizeof(wm8974_reg));
ret = wm8974_reset(codec);
if (ret < 0) {
dev_err(codec->dev, "Failed to issue reset\n");
goto err;
}
wm8974_dai.dev = codec->dev;
wm8974_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
wm8974_codec = codec;
ret = snd_soc_register_codec(codec);
if (ret != 0) {
dev_err(codec->dev, "Failed to register codec: %d\n", ret);
goto err;
}
ret = snd_soc_register_dai(&wm8974_dai);
if (ret != 0) {
dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
goto err_codec;
}
return 0;
err_codec:
snd_soc_unregister_codec(codec);
err:
kfree(wm8974);
return ret;
}
static __devexit void wm8974_unregister(struct wm8974_priv *wm8974)
{
wm8974_set_bias_level(&wm8974->codec, SND_SOC_BIAS_OFF);
snd_soc_unregister_dai(&wm8974_dai);
snd_soc_unregister_codec(&wm8974->codec);
kfree(wm8974);
wm8974_codec = NULL;
}
static __devinit int wm8974_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct wm8974_priv *wm8974;
struct snd_soc_codec *codec;
wm8974 = kzalloc(sizeof(struct wm8974_priv), GFP_KERNEL);
if (wm8974 == NULL)
return -ENOMEM;
codec = &wm8974->codec;
codec->hw_write = (hw_write_t)i2c_master_send;
i2c_set_clientdata(i2c, wm8974);
codec->control_data = i2c;
codec->dev = &i2c->dev;
return wm8974_register(wm8974);
}
static __devexit int wm8974_i2c_remove(struct i2c_client *client)
{
struct wm8974_priv *wm8974 = i2c_get_clientdata(client);
wm8974_unregister(wm8974);
return 0;
}
static const struct i2c_device_id wm8974_i2c_id[] = {
{ "wm8974", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wm8974_i2c_id);
static struct i2c_driver wm8974_i2c_driver = {
.driver = {
.name = "WM8974",
.owner = THIS_MODULE,
},
.probe = wm8974_i2c_probe,
.remove = __devexit_p(wm8974_i2c_remove),
.id_table = wm8974_i2c_id,
};
static int __init wm8974_modinit(void)
{
return i2c_add_driver(&wm8974_i2c_driver);
}
module_init(wm8974_modinit);
static void __exit wm8974_exit(void)
{
i2c_del_driver(&wm8974_i2c_driver);
}
module_exit(wm8974_exit);
MODULE_DESCRIPTION("ASoC WM8974 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");

99
kernel/sound/soc/codecs/wm8974.h Normal file
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/*
* wm8974.h -- WM8974 Soc Audio driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM8974_H
#define _WM8974_H
/* WM8974 register space */
#define WM8974_RESET 0x0
#define WM8974_POWER1 0x1
#define WM8974_POWER2 0x2
#define WM8974_POWER3 0x3
#define WM8974_IFACE 0x4
#define WM8974_COMP 0x5
#define WM8974_CLOCK 0x6
#define WM8974_ADD 0x7
#define WM8974_GPIO 0x8
#define WM8974_DAC 0xa
#define WM8974_DACVOL 0xb
#define WM8974_ADC 0xe
#define WM8974_ADCVOL 0xf
#define WM8974_EQ1 0x12
#define WM8974_EQ2 0x13
#define WM8974_EQ3 0x14
#define WM8974_EQ4 0x15
#define WM8974_EQ5 0x16
#define WM8974_DACLIM1 0x18
#define WM8974_DACLIM2 0x19
#define WM8974_NOTCH1 0x1b
#define WM8974_NOTCH2 0x1c
#define WM8974_NOTCH3 0x1d
#define WM8974_NOTCH4 0x1e
#define WM8974_ALC1 0x20
#define WM8974_ALC2 0x21
#define WM8974_ALC3 0x22
#define WM8974_NGATE 0x23
#define WM8974_PLLN 0x24
#define WM8974_PLLK1 0x25
#define WM8974_PLLK2 0x26
#define WM8974_PLLK3 0x27
#define WM8974_ATTEN 0x28
#define WM8974_INPUT 0x2c
#define WM8974_INPPGA 0x2d
#define WM8974_ADCBOOST 0x2f
#define WM8974_OUTPUT 0x31
#define WM8974_SPKMIX 0x32
#define WM8974_SPKVOL 0x36
#define WM8974_MONOMIX 0x38
#define WM8974_CACHEREGNUM 57
/* Clock divider Id's */
#define WM8974_OPCLKDIV 0
#define WM8974_MCLKDIV 1
#define WM8974_ADCCLK 2
#define WM8974_DACCLK 3
#define WM8974_BCLKDIV 4
/* DAC clock dividers */
#define WM8974_DACCLK_F2 (1 << 3)
#define WM8974_DACCLK_F4 (0 << 3)
/* ADC clock dividers */
#define WM8974_ADCCLK_F2 (1 << 3)
#define WM8974_ADCCLK_F4 (0 << 3)
/* PLL Out dividers */
#define WM8974_OPCLKDIV_1 (0 << 4)
#define WM8974_OPCLKDIV_2 (1 << 4)
#define WM8974_OPCLKDIV_3 (2 << 4)
#define WM8974_OPCLKDIV_4 (3 << 4)
/* BCLK clock dividers */
#define WM8974_BCLKDIV_1 (0 << 2)
#define WM8974_BCLKDIV_2 (1 << 2)
#define WM8974_BCLKDIV_4 (2 << 2)
#define WM8974_BCLKDIV_8 (3 << 2)
#define WM8974_BCLKDIV_16 (4 << 2)
#define WM8974_BCLKDIV_32 (5 << 2)
/* MCLK clock dividers */
#define WM8974_MCLKDIV_1 (0 << 5)
#define WM8974_MCLKDIV_1_5 (1 << 5)
#define WM8974_MCLKDIV_2 (2 << 5)
#define WM8974_MCLKDIV_3 (3 << 5)
#define WM8974_MCLKDIV_4 (4 << 5)
#define WM8974_MCLKDIV_6 (5 << 5)
#define WM8974_MCLKDIV_8 (6 << 5)
#define WM8974_MCLKDIV_12 (7 << 5)
extern struct snd_soc_dai wm8974_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8974;
#endif

1069
kernel/sound/soc/codecs/wm8988.c Normal file
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60
kernel/sound/soc/codecs/wm8988.h Normal file
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/*
* Copyright 2005 Openedhand Ltd.
*
* Author: Richard Purdie <richard@openedhand.com>
*
* Based on WM8753.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _WM8988_H
#define _WM8988_H
/* WM8988 register space */
#define WM8988_LINVOL 0x00
#define WM8988_RINVOL 0x01
#define WM8988_LOUT1V 0x02
#define WM8988_ROUT1V 0x03
#define WM8988_ADCDAC 0x05
#define WM8988_IFACE 0x07
#define WM8988_SRATE 0x08
#define WM8988_LDAC 0x0a
#define WM8988_RDAC 0x0b
#define WM8988_BASS 0x0c
#define WM8988_TREBLE 0x0d
#define WM8988_RESET 0x0f
#define WM8988_3D 0x10
#define WM8988_ALC1 0x11
#define WM8988_ALC2 0x12
#define WM8988_ALC3 0x13
#define WM8988_NGATE 0x14
#define WM8988_LADC 0x15
#define WM8988_RADC 0x16
#define WM8988_ADCTL1 0x17
#define WM8988_ADCTL2 0x18
#define WM8988_PWR1 0x19
#define WM8988_PWR2 0x1a
#define WM8988_ADCTL3 0x1b
#define WM8988_ADCIN 0x1f
#define WM8988_LADCIN 0x20
#define WM8988_RADCIN 0x21
#define WM8988_LOUTM1 0x22
#define WM8988_LOUTM2 0x23
#define WM8988_ROUTM1 0x24
#define WM8988_ROUTM2 0x25
#define WM8988_LOUT2V 0x28
#define WM8988_ROUT2V 0x29
#define WM8988_LPPB 0x43
#define WM8988_NUM_REG 0x44
#define WM8988_SYSCLK 0
extern struct snd_soc_dai wm8988_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8988;
#endif

1607
kernel/sound/soc/codecs/wm8990.c Normal file
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843
kernel/sound/soc/codecs/wm8990.h Normal file
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/*
* wm8990.h -- audio driver for WM8990
*
* Copyright 2007 Wolfson Microelectronics PLC.
* Author: Graeme Gregory
* graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __WM8990REGISTERDEFS_H__
#define __WM8990REGISTERDEFS_H__
/*
* Register values.
*/
#define WM8990_RESET 0x00
#define WM8990_POWER_MANAGEMENT_1 0x01
#define WM8990_POWER_MANAGEMENT_2 0x02
#define WM8990_POWER_MANAGEMENT_3 0x03
#define WM8990_AUDIO_INTERFACE_1 0x04
#define WM8990_AUDIO_INTERFACE_2 0x05
#define WM8990_CLOCKING_1 0x06
#define WM8990_CLOCKING_2 0x07
#define WM8990_AUDIO_INTERFACE_3 0x08
#define WM8990_AUDIO_INTERFACE_4 0x09
#define WM8990_DAC_CTRL 0x0A
#define WM8990_LEFT_DAC_DIGITAL_VOLUME 0x0B
#define WM8990_RIGHT_DAC_DIGITAL_VOLUME 0x0C
#define WM8990_DIGITAL_SIDE_TONE 0x0D
#define WM8990_ADC_CTRL 0x0E
#define WM8990_LEFT_ADC_DIGITAL_VOLUME 0x0F
#define WM8990_RIGHT_ADC_DIGITAL_VOLUME 0x10
#define WM8990_GPIO_CTRL_1 0x12
#define WM8990_GPIO1_GPIO2 0x13
#define WM8990_GPIO3_GPIO4 0x14
#define WM8990_GPIO5_GPIO6 0x15
#define WM8990_GPIOCTRL_2 0x16
#define WM8990_GPIO_POL 0x17
#define WM8990_LEFT_LINE_INPUT_1_2_VOLUME 0x18
#define WM8990_LEFT_LINE_INPUT_3_4_VOLUME 0x19
#define WM8990_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A
#define WM8990_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B
#define WM8990_LEFT_OUTPUT_VOLUME 0x1C
#define WM8990_RIGHT_OUTPUT_VOLUME 0x1D
#define WM8990_LINE_OUTPUTS_VOLUME 0x1E
#define WM8990_OUT3_4_VOLUME 0x1F
#define WM8990_LEFT_OPGA_VOLUME 0x20
#define WM8990_RIGHT_OPGA_VOLUME 0x21
#define WM8990_SPEAKER_VOLUME 0x22
#define WM8990_CLASSD1 0x23
#define WM8990_CLASSD3 0x25
#define WM8990_CLASSD4 0x26
#define WM8990_INPUT_MIXER1 0x27
#define WM8990_INPUT_MIXER2 0x28
#define WM8990_INPUT_MIXER3 0x29
#define WM8990_INPUT_MIXER4 0x2A
#define WM8990_INPUT_MIXER5 0x2B
#define WM8990_INPUT_MIXER6 0x2C
#define WM8990_OUTPUT_MIXER1 0x2D
#define WM8990_OUTPUT_MIXER2 0x2E
#define WM8990_OUTPUT_MIXER3 0x2F
#define WM8990_OUTPUT_MIXER4 0x30
#define WM8990_OUTPUT_MIXER5 0x31
#define WM8990_OUTPUT_MIXER6 0x32
#define WM8990_OUT3_4_MIXER 0x33
#define WM8990_LINE_MIXER1 0x34
#define WM8990_LINE_MIXER2 0x35
#define WM8990_SPEAKER_MIXER 0x36
#define WM8990_ADDITIONAL_CONTROL 0x37
#define WM8990_ANTIPOP1 0x38
#define WM8990_ANTIPOP2 0x39
#define WM8990_MICBIAS 0x3A
#define WM8990_PLL1 0x3C
#define WM8990_PLL2 0x3D
#define WM8990_PLL3 0x3E
#define WM8990_INTDRIVBITS 0x3F
#define WM8990_EXT_ACCESS_ENA 0x75
#define WM8990_EXT_CTL1 0x7a
/*
* Field Definitions.
*/
/*
* R0 (0x00) - Reset
*/
#define WM8990_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET_CHIP_ID */
/*
* R1 (0x01) - Power Management (1)
*/
#define WM8990_SPK_ENA 0x1000 /* SPK_ENA */
#define WM8990_SPK_ENA_BIT 12
#define WM8990_OUT3_ENA 0x0800 /* OUT3_ENA */
#define WM8990_OUT3_ENA_BIT 11
#define WM8990_OUT4_ENA 0x0400 /* OUT4_ENA */
#define WM8990_OUT4_ENA_BIT 10
#define WM8990_LOUT_ENA 0x0200 /* LOUT_ENA */
#define WM8990_LOUT_ENA_BIT 9
#define WM8990_ROUT_ENA 0x0100 /* ROUT_ENA */
#define WM8990_ROUT_ENA_BIT 8
#define WM8990_MICBIAS_ENA 0x0010 /* MICBIAS_ENA */
#define WM8990_MICBIAS_ENA_BIT 4
#define WM8990_VMID_MODE_MASK 0x0006 /* VMID_MODE - [2:1] */
#define WM8990_VREF_ENA 0x0001 /* VREF_ENA */
#define WM8990_VREF_ENA_BIT 0
/*
* R2 (0x02) - Power Management (2)
*/
#define WM8990_PLL_ENA 0x8000 /* PLL_ENA */
#define WM8990_PLL_ENA_BIT 15
#define WM8990_TSHUT_ENA 0x4000 /* TSHUT_ENA */
#define WM8990_TSHUT_ENA_BIT 14
#define WM8990_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
#define WM8990_TSHUT_OPDIS_BIT 13
#define WM8990_OPCLK_ENA 0x0800 /* OPCLK_ENA */
#define WM8990_OPCLK_ENA_BIT 11
#define WM8990_AINL_ENA 0x0200 /* AINL_ENA */
#define WM8990_AINL_ENA_BIT 9
#define WM8990_AINR_ENA 0x0100 /* AINR_ENA */
#define WM8990_AINR_ENA_BIT 8
#define WM8990_LIN34_ENA 0x0080 /* LIN34_ENA */
#define WM8990_LIN34_ENA_BIT 7
#define WM8990_LIN12_ENA 0x0040 /* LIN12_ENA */
#define WM8990_LIN12_ENA_BIT 6
#define WM8990_RIN34_ENA 0x0020 /* RIN34_ENA */
#define WM8990_RIN34_ENA_BIT 5
#define WM8990_RIN12_ENA 0x0010 /* RIN12_ENA */
#define WM8990_RIN12_ENA_BIT 4
#define WM8990_ADCL_ENA 0x0002 /* ADCL_ENA */
#define WM8990_ADCL_ENA_BIT 1
#define WM8990_ADCR_ENA 0x0001 /* ADCR_ENA */
#define WM8990_ADCR_ENA_BIT 0
/*
* R3 (0x03) - Power Management (3)
*/
#define WM8990_LON_ENA 0x2000 /* LON_ENA */
#define WM8990_LON_ENA_BIT 13
#define WM8990_LOP_ENA 0x1000 /* LOP_ENA */
#define WM8990_LOP_ENA_BIT 12
#define WM8990_RON_ENA 0x0800 /* RON_ENA */
#define WM8990_RON_ENA_BIT 11
#define WM8990_ROP_ENA 0x0400 /* ROP_ENA */
#define WM8990_ROP_ENA_BIT 10
#define WM8990_LOPGA_ENA 0x0080 /* LOPGA_ENA */
#define WM8990_LOPGA_ENA_BIT 7
#define WM8990_ROPGA_ENA 0x0040 /* ROPGA_ENA */
#define WM8990_ROPGA_ENA_BIT 6
#define WM8990_LOMIX_ENA 0x0020 /* LOMIX_ENA */
#define WM8990_LOMIX_ENA_BIT 5
#define WM8990_ROMIX_ENA 0x0010 /* ROMIX_ENA */
#define WM8990_ROMIX_ENA_BIT 4
#define WM8990_DACL_ENA 0x0002 /* DACL_ENA */
#define WM8990_DACL_ENA_BIT 1
#define WM8990_DACR_ENA 0x0001 /* DACR_ENA */
#define WM8990_DACR_ENA_BIT 0
/*
* R4 (0x04) - Audio Interface (1)
*/
#define WM8990_AIFADCL_SRC 0x8000 /* AIFADCL_SRC */
#define WM8990_AIFADCR_SRC 0x4000 /* AIFADCR_SRC */
#define WM8990_AIFADC_TDM 0x2000 /* AIFADC_TDM */
#define WM8990_AIFADC_TDM_CHAN 0x1000 /* AIFADC_TDM_CHAN */
#define WM8990_AIF_BCLK_INV 0x0100 /* AIF_BCLK_INV */
#define WM8990_AIF_LRCLK_INV 0x0080 /* AIF_LRCLK_INV */
#define WM8990_AIF_WL_MASK 0x0060 /* AIF_WL - [6:5] */
#define WM8990_AIF_WL_16BITS (0 << 5)
#define WM8990_AIF_WL_20BITS (1 << 5)
#define WM8990_AIF_WL_24BITS (2 << 5)
#define WM8990_AIF_WL_32BITS (3 << 5)
#define WM8990_AIF_FMT_MASK 0x0018 /* AIF_FMT - [4:3] */
#define WM8990_AIF_TMF_RIGHTJ (0 << 3)
#define WM8990_AIF_TMF_LEFTJ (1 << 3)
#define WM8990_AIF_TMF_I2S (2 << 3)
#define WM8990_AIF_TMF_DSP (3 << 3)
/*
* R5 (0x05) - Audio Interface (2)
*/
#define WM8990_DACL_SRC 0x8000 /* DACL_SRC */
#define WM8990_DACR_SRC 0x4000 /* DACR_SRC */
#define WM8990_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */
#define WM8990_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */
#define WM8990_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST */
#define WM8990_DAC_COMP 0x0010 /* DAC_COMP */
#define WM8990_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */
#define WM8990_ADC_COMP 0x0004 /* ADC_COMP */
#define WM8990_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */
#define WM8990_LOOPBACK 0x0001 /* LOOPBACK */
/*
* R6 (0x06) - Clocking (1)
*/
#define WM8990_TOCLK_RATE 0x8000 /* TOCLK_RATE */
#define WM8990_TOCLK_ENA 0x4000 /* TOCLK_ENA */
#define WM8990_OPCLKDIV_MASK 0x1E00 /* OPCLKDIV - [12:9] */
#define WM8990_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */
#define WM8990_BCLK_DIV_MASK 0x001E /* BCLK_DIV - [4:1] */
#define WM8990_BCLK_DIV_1 (0x0 << 1)
#define WM8990_BCLK_DIV_1_5 (0x1 << 1)
#define WM8990_BCLK_DIV_2 (0x2 << 1)
#define WM8990_BCLK_DIV_3 (0x3 << 1)
#define WM8990_BCLK_DIV_4 (0x4 << 1)
#define WM8990_BCLK_DIV_5_5 (0x5 << 1)
#define WM8990_BCLK_DIV_6 (0x6 << 1)
#define WM8990_BCLK_DIV_8 (0x7 << 1)
#define WM8990_BCLK_DIV_11 (0x8 << 1)
#define WM8990_BCLK_DIV_12 (0x9 << 1)
#define WM8990_BCLK_DIV_16 (0xA << 1)
#define WM8990_BCLK_DIV_22 (0xB << 1)
#define WM8990_BCLK_DIV_24 (0xC << 1)
#define WM8990_BCLK_DIV_32 (0xD << 1)
#define WM8990_BCLK_DIV_44 (0xE << 1)
#define WM8990_BCLK_DIV_48 (0xF << 1)
/*
* R7 (0x07) - Clocking (2)
*/
#define WM8990_MCLK_SRC 0x8000 /* MCLK_SRC */
#define WM8990_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */
#define WM8990_CLK_FORCE 0x2000 /* CLK_FORCE */
#define WM8990_MCLK_DIV_MASK 0x1800 /* MCLK_DIV - [12:11] */
#define WM8990_MCLK_DIV_1 (0 << 11)
#define WM8990_MCLK_DIV_2 (2 << 11)
#define WM8990_MCLK_INV 0x0400 /* MCLK_INV */
#define WM8990_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV */
#define WM8990_ADC_CLKDIV_1 (0 << 5)
#define WM8990_ADC_CLKDIV_1_5 (1 << 5)
#define WM8990_ADC_CLKDIV_2 (2 << 5)
#define WM8990_ADC_CLKDIV_3 (3 << 5)
#define WM8990_ADC_CLKDIV_4 (4 << 5)
#define WM8990_ADC_CLKDIV_5_5 (5 << 5)
#define WM8990_ADC_CLKDIV_6 (6 << 5)
#define WM8990_DAC_CLKDIV_MASK 0x001C /* DAC_CLKDIV - [4:2] */
#define WM8990_DAC_CLKDIV_1 (0 << 2)
#define WM8990_DAC_CLKDIV_1_5 (1 << 2)
#define WM8990_DAC_CLKDIV_2 (2 << 2)
#define WM8990_DAC_CLKDIV_3 (3 << 2)
#define WM8990_DAC_CLKDIV_4 (4 << 2)
#define WM8990_DAC_CLKDIV_5_5 (5 << 2)
#define WM8990_DAC_CLKDIV_6 (6 << 2)
/*
* R8 (0x08) - Audio Interface (3)
*/
#define WM8990_AIF_MSTR1 0x8000 /* AIF_MSTR1 */
#define WM8990_AIF_MSTR2 0x4000 /* AIF_MSTR2 */
#define WM8990_AIF_SEL 0x2000 /* AIF_SEL */
#define WM8990_ADCLRC_DIR 0x0800 /* ADCLRC_DIR */
#define WM8990_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE */
/*
* R9 (0x09) - Audio Interface (4)
*/
#define WM8990_ALRCGPIO1 0x8000 /* ALRCGPIO1 */
#define WM8990_ALRCBGPIO6 0x4000 /* ALRCBGPIO6 */
#define WM8990_AIF_TRIS 0x2000 /* AIF_TRIS */
#define WM8990_DACLRC_DIR 0x0800 /* DACLRC_DIR */
#define WM8990_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE */
/*
* R10 (0x0A) - DAC CTRL
*/
#define WM8990_AIF_LRCLKRATE 0x0400 /* AIF_LRCLKRATE */
#define WM8990_DAC_MONO 0x0200 /* DAC_MONO */
#define WM8990_DAC_SB_FILT 0x0100 /* DAC_SB_FILT */
#define WM8990_DAC_MUTERATE 0x0080 /* DAC_MUTERATE */
#define WM8990_DAC_MUTEMODE 0x0040 /* DAC_MUTEMODE */
#define WM8990_DEEMP_MASK 0x0030 /* DEEMP - [5:4] */
#define WM8990_DAC_MUTE 0x0004 /* DAC_MUTE */
#define WM8990_DACL_DATINV 0x0002 /* DACL_DATINV */
#define WM8990_DACR_DATINV 0x0001 /* DACR_DATINV */
/*
* R11 (0x0B) - Left DAC Digital Volume
*/
#define WM8990_DAC_VU 0x0100 /* DAC_VU */
#define WM8990_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */
#define WM8990_DACL_VOL_SHIFT 0
/*
* R12 (0x0C) - Right DAC Digital Volume
*/
#define WM8990_DAC_VU 0x0100 /* DAC_VU */
#define WM8990_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */
#define WM8990_DACR_VOL_SHIFT 0
/*
* R13 (0x0D) - Digital Side Tone
*/
#define WM8990_ADCL_DAC_SVOL_MASK 0x0F /* ADCL_DAC_SVOL */
#define WM8990_ADCL_DAC_SVOL_SHIFT 9
#define WM8990_ADCR_DAC_SVOL_MASK 0x0F /* ADCR_DAC_SVOL */
#define WM8990_ADCR_DAC_SVOL_SHIFT 5
#define WM8990_ADC_TO_DACL_MASK 0x03 /* ADC_TO_DACL - [3:2] */
#define WM8990_ADC_TO_DACL_SHIFT 2
#define WM8990_ADC_TO_DACR_MASK 0x03 /* ADC_TO_DACR - [1:0] */
#define WM8990_ADC_TO_DACR_SHIFT 0
/*
* R14 (0x0E) - ADC CTRL
*/
#define WM8990_ADC_HPF_ENA 0x0100 /* ADC_HPF_ENA */
#define WM8990_ADC_HPF_ENA_BIT 8
#define WM8990_ADC_HPF_CUT_MASK 0x03 /* ADC_HPF_CUT - [6:5] */
#define WM8990_ADC_HPF_CUT_SHIFT 5
#define WM8990_ADCL_DATINV 0x0002 /* ADCL_DATINV */
#define WM8990_ADCL_DATINV_BIT 1
#define WM8990_ADCR_DATINV 0x0001 /* ADCR_DATINV */
#define WM8990_ADCR_DATINV_BIT 0
/*
* R15 (0x0F) - Left ADC Digital Volume
*/
#define WM8990_ADC_VU 0x0100 /* ADC_VU */
#define WM8990_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */
#define WM8990_ADCL_VOL_SHIFT 0
/*
* R16 (0x10) - Right ADC Digital Volume
*/
#define WM8990_ADC_VU 0x0100 /* ADC_VU */
#define WM8990_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */
#define WM8990_ADCR_VOL_SHIFT 0
/*
* R18 (0x12) - GPIO CTRL 1
*/
#define WM8990_IRQ 0x1000 /* IRQ */
#define WM8990_TEMPOK 0x0800 /* TEMPOK */
#define WM8990_MICSHRT 0x0400 /* MICSHRT */
#define WM8990_MICDET 0x0200 /* MICDET */
#define WM8990_PLL_LCK 0x0100 /* PLL_LCK */
#define WM8990_GPI8_STATUS 0x0080 /* GPI8_STATUS */
#define WM8990_GPI7_STATUS 0x0040 /* GPI7_STATUS */
#define WM8990_GPIO6_STATUS 0x0020 /* GPIO6_STATUS */
#define WM8990_GPIO5_STATUS 0x0010 /* GPIO5_STATUS */
#define WM8990_GPIO4_STATUS 0x0008 /* GPIO4_STATUS */
#define WM8990_GPIO3_STATUS 0x0004 /* GPIO3_STATUS */
#define WM8990_GPIO2_STATUS 0x0002 /* GPIO2_STATUS */
#define WM8990_GPIO1_STATUS 0x0001 /* GPIO1_STATUS */
/*
* R19 (0x13) - GPIO1 & GPIO2
*/
#define WM8990_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */
#define WM8990_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */
#define WM8990_GPIO2_PU 0x2000 /* GPIO2_PU */
#define WM8990_GPIO2_PD 0x1000 /* GPIO2_PD */
#define WM8990_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */
#define WM8990_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */
#define WM8990_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */
#define WM8990_GPIO1_PU 0x0020 /* GPIO1_PU */
#define WM8990_GPIO1_PD 0x0010 /* GPIO1_PD */
#define WM8990_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
/*
* R20 (0x14) - GPIO3 & GPIO4
*/
#define WM8990_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */
#define WM8990_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */
#define WM8990_GPIO4_PU 0x2000 /* GPIO4_PU */
#define WM8990_GPIO4_PD 0x1000 /* GPIO4_PD */
#define WM8990_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */
#define WM8990_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */
#define WM8990_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */
#define WM8990_GPIO3_PU 0x0020 /* GPIO3_PU */
#define WM8990_GPIO3_PD 0x0010 /* GPIO3_PD */
#define WM8990_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
/*
* R21 (0x15) - GPIO5 & GPIO6
*/
#define WM8990_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */
#define WM8990_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */
#define WM8990_GPIO6_PU 0x2000 /* GPIO6_PU */
#define WM8990_GPIO6_PD 0x1000 /* GPIO6_PD */
#define WM8990_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */
#define WM8990_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */
#define WM8990_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */
#define WM8990_GPIO5_PU 0x0020 /* GPIO5_PU */
#define WM8990_GPIO5_PD 0x0010 /* GPIO5_PD */
#define WM8990_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */
/*
* R22 (0x16) - GPIOCTRL 2
*/
#define WM8990_RD_3W_ENA 0x8000 /* RD_3W_ENA */
#define WM8990_MODE_3W4W 0x4000 /* MODE_3W4W */
#define WM8990_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */
#define WM8990_MICSHRT_IRQ_ENA 0x0400 /* MICSHRT_IRQ_ENA */
#define WM8990_MICDET_IRQ_ENA 0x0200 /* MICDET_IRQ_ENA */
#define WM8990_PLL_LCK_IRQ_ENA 0x0100 /* PLL_LCK_IRQ_ENA */
#define WM8990_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */
#define WM8990_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */
#define WM8990_GPI8_ENA 0x0010 /* GPI8_ENA */
#define WM8990_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */
#define WM8990_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */
#define WM8990_GPI7_ENA 0x0001 /* GPI7_ENA */
/*
* R23 (0x17) - GPIO_POL
*/
#define WM8990_IRQ_INV 0x1000 /* IRQ_INV */
#define WM8990_TEMPOK_POL 0x0800 /* TEMPOK_POL */
#define WM8990_MICSHRT_POL 0x0400 /* MICSHRT_POL */
#define WM8990_MICDET_POL 0x0200 /* MICDET_POL */
#define WM8990_PLL_LCK_POL 0x0100 /* PLL_LCK_POL */
#define WM8990_GPI8_POL 0x0080 /* GPI8_POL */
#define WM8990_GPI7_POL 0x0040 /* GPI7_POL */
#define WM8990_GPIO6_POL 0x0020 /* GPIO6_POL */
#define WM8990_GPIO5_POL 0x0010 /* GPIO5_POL */
#define WM8990_GPIO4_POL 0x0008 /* GPIO4_POL */
#define WM8990_GPIO3_POL 0x0004 /* GPIO3_POL */
#define WM8990_GPIO2_POL 0x0002 /* GPIO2_POL */
#define WM8990_GPIO1_POL 0x0001 /* GPIO1_POL */
/*
* R24 (0x18) - Left Line Input 1&2 Volume
*/
#define WM8990_IPVU 0x0100 /* IPVU */
#define WM8990_LI12MUTE 0x0080 /* LI12MUTE */
#define WM8990_LI12MUTE_BIT 7
#define WM8990_LI12ZC 0x0040 /* LI12ZC */
#define WM8990_LI12ZC_BIT 6
#define WM8990_LIN12VOL_MASK 0x001F /* LIN12VOL - [4:0] */
#define WM8990_LIN12VOL_SHIFT 0
/*
* R25 (0x19) - Left Line Input 3&4 Volume
*/
#define WM8990_IPVU 0x0100 /* IPVU */
#define WM8990_LI34MUTE 0x0080 /* LI34MUTE */
#define WM8990_LI34MUTE_BIT 7
#define WM8990_LI34ZC 0x0040 /* LI34ZC */
#define WM8990_LI34ZC_BIT 6
#define WM8990_LIN34VOL_MASK 0x001F /* LIN34VOL - [4:0] */
#define WM8990_LIN34VOL_SHIFT 0
/*
* R26 (0x1A) - Right Line Input 1&2 Volume
*/
#define WM8990_IPVU 0x0100 /* IPVU */
#define WM8990_RI12MUTE 0x0080 /* RI12MUTE */
#define WM8990_RI12MUTE_BIT 7
#define WM8990_RI12ZC 0x0040 /* RI12ZC */
#define WM8990_RI12ZC_BIT 6
#define WM8990_RIN12VOL_MASK 0x001F /* RIN12VOL - [4:0] */
#define WM8990_RIN12VOL_SHIFT 0
/*
* R27 (0x1B) - Right Line Input 3&4 Volume
*/
#define WM8990_IPVU 0x0100 /* IPVU */
#define WM8990_RI34MUTE 0x0080 /* RI34MUTE */
#define WM8990_RI34MUTE_BIT 7
#define WM8990_RI34ZC 0x0040 /* RI34ZC */
#define WM8990_RI34ZC_BIT 6
#define WM8990_RIN34VOL_MASK 0x001F /* RIN34VOL - [4:0] */
#define WM8990_RIN34VOL_SHIFT 0
/*
* R28 (0x1C) - Left Output Volume
*/
#define WM8990_OPVU 0x0100 /* OPVU */
#define WM8990_LOZC 0x0080 /* LOZC */
#define WM8990_LOZC_BIT 7
#define WM8990_LOUTVOL_MASK 0x007F /* LOUTVOL - [6:0] */
#define WM8990_LOUTVOL_SHIFT 0
/*
* R29 (0x1D) - Right Output Volume
*/
#define WM8990_OPVU 0x0100 /* OPVU */
#define WM8990_ROZC 0x0080 /* ROZC */
#define WM8990_ROZC_BIT 7
#define WM8990_ROUTVOL_MASK 0x007F /* ROUTVOL - [6:0] */
#define WM8990_ROUTVOL_SHIFT 0
/*
* R30 (0x1E) - Line Outputs Volume
*/
#define WM8990_LONMUTE 0x0040 /* LONMUTE */
#define WM8990_LONMUTE_BIT 6
#define WM8990_LOPMUTE 0x0020 /* LOPMUTE */
#define WM8990_LOPMUTE_BIT 5
#define WM8990_LOATTN 0x0010 /* LOATTN */
#define WM8990_LOATTN_BIT 4
#define WM8990_RONMUTE 0x0004 /* RONMUTE */
#define WM8990_RONMUTE_BIT 2
#define WM8990_ROPMUTE 0x0002 /* ROPMUTE */
#define WM8990_ROPMUTE_BIT 1
#define WM8990_ROATTN 0x0001 /* ROATTN */
#define WM8990_ROATTN_BIT 0
/*
* R31 (0x1F) - Out3/4 Volume
*/
#define WM8990_OUT3MUTE 0x0020 /* OUT3MUTE */
#define WM8990_OUT3MUTE_BIT 5
#define WM8990_OUT3ATTN 0x0010 /* OUT3ATTN */
#define WM8990_OUT3ATTN_BIT 4
#define WM8990_OUT4MUTE 0x0002 /* OUT4MUTE */
#define WM8990_OUT4MUTE_BIT 1
#define WM8990_OUT4ATTN 0x0001 /* OUT4ATTN */
#define WM8990_OUT4ATTN_BIT 0
/*
* R32 (0x20) - Left OPGA Volume
*/
#define WM8990_OPVU 0x0100 /* OPVU */
#define WM8990_LOPGAZC 0x0080 /* LOPGAZC */
#define WM8990_LOPGAZC_BIT 7
#define WM8990_LOPGAVOL_MASK 0x007F /* LOPGAVOL - [6:0] */
#define WM8990_LOPGAVOL_SHIFT 0
/*
* R33 (0x21) - Right OPGA Volume
*/
#define WM8990_OPVU 0x0100 /* OPVU */
#define WM8990_ROPGAZC 0x0080 /* ROPGAZC */
#define WM8990_ROPGAZC_BIT 7
#define WM8990_ROPGAVOL_MASK 0x007F /* ROPGAVOL - [6:0] */
#define WM8990_ROPGAVOL_SHIFT 0
/*
* R34 (0x22) - Speaker Volume
*/
#define WM8990_SPKATTN_MASK 0x0003 /* SPKATTN - [1:0] */
#define WM8990_SPKATTN_SHIFT 0
/*
* R35 (0x23) - ClassD1
*/
#define WM8990_CDMODE 0x0100 /* CDMODE */
#define WM8990_CDMODE_BIT 8
/*
* R37 (0x25) - ClassD3
*/
#define WM8990_DCGAIN_MASK 0x0007 /* DCGAIN - [5:3] */
#define WM8990_DCGAIN_SHIFT 3
#define WM8990_ACGAIN_MASK 0x0007 /* ACGAIN - [2:0] */
#define WM8990_ACGAIN_SHIFT 0
/*
* R38 (0x26) - ClassD4
*/
#define WM8990_SPKZC_MASK 0x0001 /* SPKZC */
#define WM8990_SPKZC_SHIFT 7 /* SPKZC */
#define WM8990_SPKVOL_MASK 0x007F /* SPKVOL - [6:0] */
#define WM8990_SPKVOL_SHIFT 0 /* SPKVOL - [6:0] */
/*
* R39 (0x27) - Input Mixer1
*/
#define WM8990_AINLMODE_MASK 0x000C /* AINLMODE - [3:2] */
#define WM8990_AINLMODE_SHIFT 2
#define WM8990_AINRMODE_MASK 0x0003 /* AINRMODE - [1:0] */
#define WM8990_AINRMODE_SHIFT 0
/*
* R40 (0x28) - Input Mixer2
*/
#define WM8990_LMP4 0x0080 /* LMP4 */
#define WM8990_LMP4_BIT 7 /* LMP4 */
#define WM8990_LMN3 0x0040 /* LMN3 */
#define WM8990_LMN3_BIT 6 /* LMN3 */
#define WM8990_LMP2 0x0020 /* LMP2 */
#define WM8990_LMP2_BIT 5 /* LMP2 */
#define WM8990_LMN1 0x0010 /* LMN1 */
#define WM8990_LMN1_BIT 4 /* LMN1 */
#define WM8990_RMP4 0x0008 /* RMP4 */
#define WM8990_RMP4_BIT 3 /* RMP4 */
#define WM8990_RMN3 0x0004 /* RMN3 */
#define WM8990_RMN3_BIT 2 /* RMN3 */
#define WM8990_RMP2 0x0002 /* RMP2 */
#define WM8990_RMP2_BIT 1 /* RMP2 */
#define WM8990_RMN1 0x0001 /* RMN1 */
#define WM8990_RMN1_BIT 0 /* RMN1 */
/*
* R41 (0x29) - Input Mixer3
*/
#define WM8990_L34MNB 0x0100 /* L34MNB */
#define WM8990_L34MNB_BIT 8
#define WM8990_L34MNBST 0x0080 /* L34MNBST */
#define WM8990_L34MNBST_BIT 7
#define WM8990_L12MNB 0x0020 /* L12MNB */
#define WM8990_L12MNB_BIT 5
#define WM8990_L12MNBST 0x0010 /* L12MNBST */
#define WM8990_L12MNBST_BIT 4
#define WM8990_LDBVOL_MASK 0x0007 /* LDBVOL - [2:0] */
#define WM8990_LDBVOL_SHIFT 0
/*
* R42 (0x2A) - Input Mixer4
*/
#define WM8990_R34MNB 0x0100 /* R34MNB */
#define WM8990_R34MNB_BIT 8
#define WM8990_R34MNBST 0x0080 /* R34MNBST */
#define WM8990_R34MNBST_BIT 7
#define WM8990_R12MNB 0x0020 /* R12MNB */
#define WM8990_R12MNB_BIT 5
#define WM8990_R12MNBST 0x0010 /* R12MNBST */
#define WM8990_R12MNBST_BIT 4
#define WM8990_RDBVOL_MASK 0x0007 /* RDBVOL - [2:0] */
#define WM8990_RDBVOL_SHIFT 0
/*
* R43 (0x2B) - Input Mixer5
*/
#define WM8990_LI2BVOL_MASK 0x07 /* LI2BVOL - [8:6] */
#define WM8990_LI2BVOL_SHIFT 6
#define WM8990_LR4BVOL_MASK 0x07 /* LR4BVOL - [5:3] */
#define WM8990_LR4BVOL_SHIFT 3
#define WM8990_LL4BVOL_MASK 0x07 /* LL4BVOL - [2:0] */
#define WM8990_LL4BVOL_SHIFT 0
/*
* R44 (0x2C) - Input Mixer6
*/
#define WM8990_RI2BVOL_MASK 0x07 /* RI2BVOL - [8:6] */
#define WM8990_RI2BVOL_SHIFT 6
#define WM8990_RL4BVOL_MASK 0x07 /* RL4BVOL - [5:3] */
#define WM8990_RL4BVOL_SHIFT 3
#define WM8990_RR4BVOL_MASK 0x07 /* RR4BVOL - [2:0] */
#define WM8990_RR4BVOL_SHIFT 0
/*
* R45 (0x2D) - Output Mixer1
*/
#define WM8990_LRBLO 0x0080 /* LRBLO */
#define WM8990_LRBLO_BIT 7
#define WM8990_LLBLO 0x0040 /* LLBLO */
#define WM8990_LLBLO_BIT 6
#define WM8990_LRI3LO 0x0020 /* LRI3LO */
#define WM8990_LRI3LO_BIT 5
#define WM8990_LLI3LO 0x0010 /* LLI3LO */
#define WM8990_LLI3LO_BIT 4
#define WM8990_LR12LO 0x0008 /* LR12LO */
#define WM8990_LR12LO_BIT 3
#define WM8990_LL12LO 0x0004 /* LL12LO */
#define WM8990_LL12LO_BIT 2
#define WM8990_LDLO 0x0001 /* LDLO */
#define WM8990_LDLO_BIT 0
/*
* R46 (0x2E) - Output Mixer2
*/
#define WM8990_RLBRO 0x0080 /* RLBRO */
#define WM8990_RLBRO_BIT 7
#define WM8990_RRBRO 0x0040 /* RRBRO */
#define WM8990_RRBRO_BIT 6
#define WM8990_RLI3RO 0x0020 /* RLI3RO */
#define WM8990_RLI3RO_BIT 5
#define WM8990_RRI3RO 0x0010 /* RRI3RO */
#define WM8990_RRI3RO_BIT 4
#define WM8990_RL12RO 0x0008 /* RL12RO */
#define WM8990_RL12RO_BIT 3
#define WM8990_RR12RO 0x0004 /* RR12RO */
#define WM8990_RR12RO_BIT 2
#define WM8990_RDRO 0x0001 /* RDRO */
#define WM8990_RDRO_BIT 0
/*
* R47 (0x2F) - Output Mixer3
*/
#define WM8990_LLI3LOVOL_MASK 0x07 /* LLI3LOVOL - [8:6] */
#define WM8990_LLI3LOVOL_SHIFT 6
#define WM8990_LR12LOVOL_MASK 0x07 /* LR12LOVOL - [5:3] */
#define WM8990_LR12LOVOL_SHIFT 3
#define WM8990_LL12LOVOL_MASK 0x07 /* LL12LOVOL - [2:0] */
#define WM8990_LL12LOVOL_SHIFT 0
/*
* R48 (0x30) - Output Mixer4
*/
#define WM8990_RRI3ROVOL_MASK 0x07 /* RRI3ROVOL - [8:6] */
#define WM8990_RRI3ROVOL_SHIFT 6
#define WM8990_RL12ROVOL_MASK 0x07 /* RL12ROVOL - [5:3] */
#define WM8990_RL12ROVOL_SHIFT 3
#define WM8990_RR12ROVOL_MASK 0x07 /* RR12ROVOL - [2:0] */
#define WM8990_RR12ROVOL_SHIFT 0
/*
* R49 (0x31) - Output Mixer5
*/
#define WM8990_LRI3LOVOL_MASK 0x07 /* LRI3LOVOL - [8:6] */
#define WM8990_LRI3LOVOL_SHIFT 6
#define WM8990_LRBLOVOL_MASK 0x07 /* LRBLOVOL - [5:3] */
#define WM8990_LRBLOVOL_SHIFT 3
#define WM8990_LLBLOVOL_MASK 0x07 /* LLBLOVOL - [2:0] */
#define WM8990_LLBLOVOL_SHIFT 0
/*
* R50 (0x32) - Output Mixer6
*/
#define WM8990_RLI3ROVOL_MASK 0x07 /* RLI3ROVOL - [8:6] */
#define WM8990_RLI3ROVOL_SHIFT 6
#define WM8990_RLBROVOL_MASK 0x07 /* RLBROVOL - [5:3] */
#define WM8990_RLBROVOL_SHIFT 3
#define WM8990_RRBROVOL_MASK 0x07 /* RRBROVOL - [2:0] */
#define WM8990_RRBROVOL_SHIFT 0
/*
* R51 (0x33) - Out3/4 Mixer
*/
#define WM8990_VSEL_MASK 0x0180 /* VSEL - [8:7] */
#define WM8990_LI4O3 0x0020 /* LI4O3 */
#define WM8990_LI4O3_BIT 5
#define WM8990_LPGAO3 0x0010 /* LPGAO3 */
#define WM8990_LPGAO3_BIT 4
#define WM8990_RI4O4 0x0002 /* RI4O4 */
#define WM8990_RI4O4_BIT 1
#define WM8990_RPGAO4 0x0001 /* RPGAO4 */
#define WM8990_RPGAO4_BIT 0
/*
* R52 (0x34) - Line Mixer1
*/
#define WM8990_LLOPGALON 0x0040 /* LLOPGALON */
#define WM8990_LLOPGALON_BIT 6
#define WM8990_LROPGALON 0x0020 /* LROPGALON */
#define WM8990_LROPGALON_BIT 5
#define WM8990_LOPLON 0x0010 /* LOPLON */
#define WM8990_LOPLON_BIT 4
#define WM8990_LR12LOP 0x0004 /* LR12LOP */
#define WM8990_LR12LOP_BIT 2
#define WM8990_LL12LOP 0x0002 /* LL12LOP */
#define WM8990_LL12LOP_BIT 1
#define WM8990_LLOPGALOP 0x0001 /* LLOPGALOP */
#define WM8990_LLOPGALOP_BIT 0
/*
* R53 (0x35) - Line Mixer2
*/
#define WM8990_RROPGARON 0x0040 /* RROPGARON */
#define WM8990_RROPGARON_BIT 6
#define WM8990_RLOPGARON 0x0020 /* RLOPGARON */
#define WM8990_RLOPGARON_BIT 5
#define WM8990_ROPRON 0x0010 /* ROPRON */
#define WM8990_ROPRON_BIT 4
#define WM8990_RL12ROP 0x0004 /* RL12ROP */
#define WM8990_RL12ROP_BIT 2
#define WM8990_RR12ROP 0x0002 /* RR12ROP */
#define WM8990_RR12ROP_BIT 1
#define WM8990_RROPGAROP 0x0001 /* RROPGAROP */
#define WM8990_RROPGAROP_BIT 0
/*
* R54 (0x36) - Speaker Mixer
*/
#define WM8990_LB2SPK 0x0080 /* LB2SPK */
#define WM8990_LB2SPK_BIT 7
#define WM8990_RB2SPK 0x0040 /* RB2SPK */
#define WM8990_RB2SPK_BIT 6
#define WM8990_LI2SPK 0x0020 /* LI2SPK */
#define WM8990_LI2SPK_BIT 5
#define WM8990_RI2SPK 0x0010 /* RI2SPK */
#define WM8990_RI2SPK_BIT 4
#define WM8990_LOPGASPK 0x0008 /* LOPGASPK */
#define WM8990_LOPGASPK_BIT 3
#define WM8990_ROPGASPK 0x0004 /* ROPGASPK */
#define WM8990_ROPGASPK_BIT 2
#define WM8990_LDSPK 0x0002 /* LDSPK */
#define WM8990_LDSPK_BIT 1
#define WM8990_RDSPK 0x0001 /* RDSPK */
#define WM8990_RDSPK_BIT 0
/*
* R55 (0x37) - Additional Control
*/
#define WM8990_VROI 0x0001 /* VROI */
/*
* R56 (0x38) - AntiPOP1
*/
#define WM8990_DIS_LLINE 0x0020 /* DIS_LLINE */
#define WM8990_DIS_RLINE 0x0010 /* DIS_RLINE */
#define WM8990_DIS_OUT3 0x0008 /* DIS_OUT3 */
#define WM8990_DIS_OUT4 0x0004 /* DIS_OUT4 */
#define WM8990_DIS_LOUT 0x0002 /* DIS_LOUT */
#define WM8990_DIS_ROUT 0x0001 /* DIS_ROUT */
/*
* R57 (0x39) - AntiPOP2
*/
#define WM8990_SOFTST 0x0040 /* SOFTST */
#define WM8990_BUFIOEN 0x0008 /* BUFIOEN */
#define WM8990_BUFDCOPEN 0x0004 /* BUFDCOPEN */
#define WM8990_POBCTRL 0x0002 /* POBCTRL */
#define WM8990_VMIDTOG 0x0001 /* VMIDTOG */
/*
* R58 (0x3A) - MICBIAS
*/
#define WM8990_MCDSCTH_MASK 0x00C0 /* MCDSCTH - [7:6] */
#define WM8990_MCDTHR_MASK 0x0038 /* MCDTHR - [5:3] */
#define WM8990_MCD 0x0004 /* MCD */
#define WM8990_MBSEL 0x0001 /* MBSEL */
/*
* R60 (0x3C) - PLL1
*/
#define WM8990_SDM 0x0080 /* SDM */
#define WM8990_PRESCALE 0x0040 /* PRESCALE */
#define WM8990_PLLN_MASK 0x000F /* PLLN - [3:0] */
/*
* R61 (0x3D) - PLL2
*/
#define WM8990_PLLK1_MASK 0x00FF /* PLLK1 - [7:0] */
/*
* R62 (0x3E) - PLL3
*/
#define WM8990_PLLK2_MASK 0x00FF /* PLLK2 - [7:0] */
/*
* R63 (0x3F) - Internal Driver Bits
*/
#define WM8990_INMIXL_PWR_BIT 0
#define WM8990_AINLMUX_PWR_BIT 1
#define WM8990_INMIXR_PWR_BIT 2
#define WM8990_AINRMUX_PWR_BIT 3
struct wm8990_setup_data {
unsigned i2c_bus;
unsigned short i2c_address;
};
#define WM8990_MCLK_DIV 0
#define WM8990_DACCLK_DIV 1
#define WM8990_ADCCLK_DIV 2
#define WM8990_BCLK_DIV 3
extern struct snd_soc_dai wm8990_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm8990;
#endif /* __WM8990REGISTERDEFS_H__ */
/*------------------------------ END OF FILE ---------------------------------*/

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#ifndef WM9081_H
#define WM9081_H
/*
* wm9081.c -- WM9081 ALSA SoC Audio driver
*
* Author: Mark Brown
*
* Copyright 2009 Wolfson Microelectronics plc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <sound/soc.h>
extern struct snd_soc_dai wm9081_dai;
extern struct snd_soc_codec_device soc_codec_dev_wm9081;
/*
* SYSCLK sources
*/
#define WM9081_SYSCLK_MCLK 1 /* Use MCLK without FLL */
#define WM9081_SYSCLK_FLL_MCLK 2 /* Use MCLK, enabling FLL if required */
/*
* Register values.
*/
#define WM9081_SOFTWARE_RESET 0x00
#define WM9081_ANALOGUE_LINEOUT 0x02
#define WM9081_ANALOGUE_SPEAKER_PGA 0x03
#define WM9081_VMID_CONTROL 0x04
#define WM9081_BIAS_CONTROL_1 0x05
#define WM9081_ANALOGUE_MIXER 0x07
#define WM9081_ANTI_POP_CONTROL 0x08
#define WM9081_ANALOGUE_SPEAKER_1 0x09
#define WM9081_ANALOGUE_SPEAKER_2 0x0A
#define WM9081_POWER_MANAGEMENT 0x0B
#define WM9081_CLOCK_CONTROL_1 0x0C
#define WM9081_CLOCK_CONTROL_2 0x0D
#define WM9081_CLOCK_CONTROL_3 0x0E
#define WM9081_FLL_CONTROL_1 0x10
#define WM9081_FLL_CONTROL_2 0x11
#define WM9081_FLL_CONTROL_3 0x12
#define WM9081_FLL_CONTROL_4 0x13
#define WM9081_FLL_CONTROL_5 0x14
#define WM9081_AUDIO_INTERFACE_1 0x16
#define WM9081_AUDIO_INTERFACE_2 0x17
#define WM9081_AUDIO_INTERFACE_3 0x18
#define WM9081_AUDIO_INTERFACE_4 0x19
#define WM9081_INTERRUPT_STATUS 0x1A
#define WM9081_INTERRUPT_STATUS_MASK 0x1B
#define WM9081_INTERRUPT_POLARITY 0x1C
#define WM9081_INTERRUPT_CONTROL 0x1D
#define WM9081_DAC_DIGITAL_1 0x1E
#define WM9081_DAC_DIGITAL_2 0x1F
#define WM9081_DRC_1 0x20
#define WM9081_DRC_2 0x21
#define WM9081_DRC_3 0x22
#define WM9081_DRC_4 0x23
#define WM9081_WRITE_SEQUENCER_1 0x26
#define WM9081_WRITE_SEQUENCER_2 0x27
#define WM9081_MW_SLAVE_1 0x28
#define WM9081_EQ_1 0x2A
#define WM9081_EQ_2 0x2B
#define WM9081_EQ_3 0x2C
#define WM9081_EQ_4 0x2D
#define WM9081_EQ_5 0x2E
#define WM9081_EQ_6 0x2F
#define WM9081_EQ_7 0x30
#define WM9081_EQ_8 0x31
#define WM9081_EQ_9 0x32
#define WM9081_EQ_10 0x33
#define WM9081_EQ_11 0x34
#define WM9081_EQ_12 0x35
#define WM9081_EQ_13 0x36
#define WM9081_EQ_14 0x37
#define WM9081_EQ_15 0x38
#define WM9081_EQ_16 0x39
#define WM9081_EQ_17 0x3A
#define WM9081_EQ_18 0x3B
#define WM9081_EQ_19 0x3C
#define WM9081_EQ_20 0x3D
#define WM9081_REGISTER_COUNT 55
#define WM9081_MAX_REGISTER 0x3D
/*
* Field Definitions.
*/
/*
* R0 (0x00) - Software Reset
*/
#define WM9081_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
#define WM9081_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
#define WM9081_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
/*
* R2 (0x02) - Analogue Lineout
*/
#define WM9081_LINEOUT_MUTE 0x0080 /* LINEOUT_MUTE */
#define WM9081_LINEOUT_MUTE_MASK 0x0080 /* LINEOUT_MUTE */
#define WM9081_LINEOUT_MUTE_SHIFT 7 /* LINEOUT_MUTE */
#define WM9081_LINEOUT_MUTE_WIDTH 1 /* LINEOUT_MUTE */
#define WM9081_LINEOUTZC 0x0040 /* LINEOUTZC */
#define WM9081_LINEOUTZC_MASK 0x0040 /* LINEOUTZC */
#define WM9081_LINEOUTZC_SHIFT 6 /* LINEOUTZC */
#define WM9081_LINEOUTZC_WIDTH 1 /* LINEOUTZC */
#define WM9081_LINEOUT_VOL_MASK 0x003F /* LINEOUT_VOL - [5:0] */
#define WM9081_LINEOUT_VOL_SHIFT 0 /* LINEOUT_VOL - [5:0] */
#define WM9081_LINEOUT_VOL_WIDTH 6 /* LINEOUT_VOL - [5:0] */
/*
* R3 (0x03) - Analogue Speaker PGA
*/
#define WM9081_SPKPGA_MUTE 0x0080 /* SPKPGA_MUTE */
#define WM9081_SPKPGA_MUTE_MASK 0x0080 /* SPKPGA_MUTE */
#define WM9081_SPKPGA_MUTE_SHIFT 7 /* SPKPGA_MUTE */
#define WM9081_SPKPGA_MUTE_WIDTH 1 /* SPKPGA_MUTE */
#define WM9081_SPKPGAZC 0x0040 /* SPKPGAZC */
#define WM9081_SPKPGAZC_MASK 0x0040 /* SPKPGAZC */
#define WM9081_SPKPGAZC_SHIFT 6 /* SPKPGAZC */
#define WM9081_SPKPGAZC_WIDTH 1 /* SPKPGAZC */
#define WM9081_SPKPGA_VOL_MASK 0x003F /* SPKPGA_VOL - [5:0] */
#define WM9081_SPKPGA_VOL_SHIFT 0 /* SPKPGA_VOL - [5:0] */
#define WM9081_SPKPGA_VOL_WIDTH 6 /* SPKPGA_VOL - [5:0] */
/*
* R4 (0x04) - VMID Control
*/
#define WM9081_VMID_BUF_ENA 0x0020 /* VMID_BUF_ENA */
#define WM9081_VMID_BUF_ENA_MASK 0x0020 /* VMID_BUF_ENA */
#define WM9081_VMID_BUF_ENA_SHIFT 5 /* VMID_BUF_ENA */
#define WM9081_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
#define WM9081_VMID_RAMP 0x0008 /* VMID_RAMP */
#define WM9081_VMID_RAMP_MASK 0x0008 /* VMID_RAMP */
#define WM9081_VMID_RAMP_SHIFT 3 /* VMID_RAMP */
#define WM9081_VMID_RAMP_WIDTH 1 /* VMID_RAMP */
#define WM9081_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */
#define WM9081_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */
#define WM9081_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */
#define WM9081_VMID_FAST_ST 0x0001 /* VMID_FAST_ST */
#define WM9081_VMID_FAST_ST_MASK 0x0001 /* VMID_FAST_ST */
#define WM9081_VMID_FAST_ST_SHIFT 0 /* VMID_FAST_ST */
#define WM9081_VMID_FAST_ST_WIDTH 1 /* VMID_FAST_ST */
/*
* R5 (0x05) - Bias Control 1
*/
#define WM9081_BIAS_SRC 0x0040 /* BIAS_SRC */
#define WM9081_BIAS_SRC_MASK 0x0040 /* BIAS_SRC */
#define WM9081_BIAS_SRC_SHIFT 6 /* BIAS_SRC */
#define WM9081_BIAS_SRC_WIDTH 1 /* BIAS_SRC */
#define WM9081_STBY_BIAS_LVL 0x0020 /* STBY_BIAS_LVL */
#define WM9081_STBY_BIAS_LVL_MASK 0x0020 /* STBY_BIAS_LVL */
#define WM9081_STBY_BIAS_LVL_SHIFT 5 /* STBY_BIAS_LVL */
#define WM9081_STBY_BIAS_LVL_WIDTH 1 /* STBY_BIAS_LVL */
#define WM9081_STBY_BIAS_ENA 0x0010 /* STBY_BIAS_ENA */
#define WM9081_STBY_BIAS_ENA_MASK 0x0010 /* STBY_BIAS_ENA */
#define WM9081_STBY_BIAS_ENA_SHIFT 4 /* STBY_BIAS_ENA */
#define WM9081_STBY_BIAS_ENA_WIDTH 1 /* STBY_BIAS_ENA */
#define WM9081_BIAS_LVL_MASK 0x000C /* BIAS_LVL - [3:2] */
#define WM9081_BIAS_LVL_SHIFT 2 /* BIAS_LVL - [3:2] */
#define WM9081_BIAS_LVL_WIDTH 2 /* BIAS_LVL - [3:2] */
#define WM9081_BIAS_ENA 0x0002 /* BIAS_ENA */
#define WM9081_BIAS_ENA_MASK 0x0002 /* BIAS_ENA */
#define WM9081_BIAS_ENA_SHIFT 1 /* BIAS_ENA */
#define WM9081_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
#define WM9081_STARTUP_BIAS_ENA 0x0001 /* STARTUP_BIAS_ENA */
#define WM9081_STARTUP_BIAS_ENA_MASK 0x0001 /* STARTUP_BIAS_ENA */
#define WM9081_STARTUP_BIAS_ENA_SHIFT 0 /* STARTUP_BIAS_ENA */
#define WM9081_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */
/*
* R7 (0x07) - Analogue Mixer
*/
#define WM9081_DAC_SEL 0x0010 /* DAC_SEL */
#define WM9081_DAC_SEL_MASK 0x0010 /* DAC_SEL */
#define WM9081_DAC_SEL_SHIFT 4 /* DAC_SEL */
#define WM9081_DAC_SEL_WIDTH 1 /* DAC_SEL */
#define WM9081_IN2_VOL 0x0008 /* IN2_VOL */
#define WM9081_IN2_VOL_MASK 0x0008 /* IN2_VOL */
#define WM9081_IN2_VOL_SHIFT 3 /* IN2_VOL */
#define WM9081_IN2_VOL_WIDTH 1 /* IN2_VOL */
#define WM9081_IN2_ENA 0x0004 /* IN2_ENA */
#define WM9081_IN2_ENA_MASK 0x0004 /* IN2_ENA */
#define WM9081_IN2_ENA_SHIFT 2 /* IN2_ENA */
#define WM9081_IN2_ENA_WIDTH 1 /* IN2_ENA */
#define WM9081_IN1_VOL 0x0002 /* IN1_VOL */
#define WM9081_IN1_VOL_MASK 0x0002 /* IN1_VOL */
#define WM9081_IN1_VOL_SHIFT 1 /* IN1_VOL */
#define WM9081_IN1_VOL_WIDTH 1 /* IN1_VOL */
#define WM9081_IN1_ENA 0x0001 /* IN1_ENA */
#define WM9081_IN1_ENA_MASK 0x0001 /* IN1_ENA */
#define WM9081_IN1_ENA_SHIFT 0 /* IN1_ENA */
#define WM9081_IN1_ENA_WIDTH 1 /* IN1_ENA */
/*
* R8 (0x08) - Anti Pop Control
*/
#define WM9081_LINEOUT_DISCH 0x0004 /* LINEOUT_DISCH */
#define WM9081_LINEOUT_DISCH_MASK 0x0004 /* LINEOUT_DISCH */
#define WM9081_LINEOUT_DISCH_SHIFT 2 /* LINEOUT_DISCH */
#define WM9081_LINEOUT_DISCH_WIDTH 1 /* LINEOUT_DISCH */
#define WM9081_LINEOUT_VROI 0x0002 /* LINEOUT_VROI */
#define WM9081_LINEOUT_VROI_MASK 0x0002 /* LINEOUT_VROI */
#define WM9081_LINEOUT_VROI_SHIFT 1 /* LINEOUT_VROI */
#define WM9081_LINEOUT_VROI_WIDTH 1 /* LINEOUT_VROI */
#define WM9081_LINEOUT_CLAMP 0x0001 /* LINEOUT_CLAMP */
#define WM9081_LINEOUT_CLAMP_MASK 0x0001 /* LINEOUT_CLAMP */
#define WM9081_LINEOUT_CLAMP_SHIFT 0 /* LINEOUT_CLAMP */
#define WM9081_LINEOUT_CLAMP_WIDTH 1 /* LINEOUT_CLAMP */
/*
* R9 (0x09) - Analogue Speaker 1
*/
#define WM9081_SPK_DCGAIN_MASK 0x0038 /* SPK_DCGAIN - [5:3] */
#define WM9081_SPK_DCGAIN_SHIFT 3 /* SPK_DCGAIN - [5:3] */
#define WM9081_SPK_DCGAIN_WIDTH 3 /* SPK_DCGAIN - [5:3] */
#define WM9081_SPK_ACGAIN_MASK 0x0007 /* SPK_ACGAIN - [2:0] */
#define WM9081_SPK_ACGAIN_SHIFT 0 /* SPK_ACGAIN - [2:0] */
#define WM9081_SPK_ACGAIN_WIDTH 3 /* SPK_ACGAIN - [2:0] */
/*
* R10 (0x0A) - Analogue Speaker 2
*/
#define WM9081_SPK_MODE 0x0040 /* SPK_MODE */
#define WM9081_SPK_MODE_MASK 0x0040 /* SPK_MODE */
#define WM9081_SPK_MODE_SHIFT 6 /* SPK_MODE */
#define WM9081_SPK_MODE_WIDTH 1 /* SPK_MODE */
#define WM9081_SPK_INV_MUTE 0x0010 /* SPK_INV_MUTE */
#define WM9081_SPK_INV_MUTE_MASK 0x0010 /* SPK_INV_MUTE */
#define WM9081_SPK_INV_MUTE_SHIFT 4 /* SPK_INV_MUTE */
#define WM9081_SPK_INV_MUTE_WIDTH 1 /* SPK_INV_MUTE */
#define WM9081_OUT_SPK_CTRL 0x0008 /* OUT_SPK_CTRL */
#define WM9081_OUT_SPK_CTRL_MASK 0x0008 /* OUT_SPK_CTRL */
#define WM9081_OUT_SPK_CTRL_SHIFT 3 /* OUT_SPK_CTRL */
#define WM9081_OUT_SPK_CTRL_WIDTH 1 /* OUT_SPK_CTRL */
/*
* R11 (0x0B) - Power Management
*/
#define WM9081_TSHUT_ENA 0x0100 /* TSHUT_ENA */
#define WM9081_TSHUT_ENA_MASK 0x0100 /* TSHUT_ENA */
#define WM9081_TSHUT_ENA_SHIFT 8 /* TSHUT_ENA */
#define WM9081_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
#define WM9081_TSENSE_ENA 0x0080 /* TSENSE_ENA */
#define WM9081_TSENSE_ENA_MASK 0x0080 /* TSENSE_ENA */
#define WM9081_TSENSE_ENA_SHIFT 7 /* TSENSE_ENA */
#define WM9081_TSENSE_ENA_WIDTH 1 /* TSENSE_ENA */
#define WM9081_TEMP_SHUT 0x0040 /* TEMP_SHUT */
#define WM9081_TEMP_SHUT_MASK 0x0040 /* TEMP_SHUT */
#define WM9081_TEMP_SHUT_SHIFT 6 /* TEMP_SHUT */
#define WM9081_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */
#define WM9081_LINEOUT_ENA 0x0010 /* LINEOUT_ENA */
#define WM9081_LINEOUT_ENA_MASK 0x0010 /* LINEOUT_ENA */
#define WM9081_LINEOUT_ENA_SHIFT 4 /* LINEOUT_ENA */
#define WM9081_LINEOUT_ENA_WIDTH 1 /* LINEOUT_ENA */
#define WM9081_SPKPGA_ENA 0x0004 /* SPKPGA_ENA */
#define WM9081_SPKPGA_ENA_MASK 0x0004 /* SPKPGA_ENA */
#define WM9081_SPKPGA_ENA_SHIFT 2 /* SPKPGA_ENA */
#define WM9081_SPKPGA_ENA_WIDTH 1 /* SPKPGA_ENA */
#define WM9081_SPK_ENA 0x0002 /* SPK_ENA */
#define WM9081_SPK_ENA_MASK 0x0002 /* SPK_ENA */
#define WM9081_SPK_ENA_SHIFT 1 /* SPK_ENA */
#define WM9081_SPK_ENA_WIDTH 1 /* SPK_ENA */
#define WM9081_DAC_ENA 0x0001 /* DAC_ENA */
#define WM9081_DAC_ENA_MASK 0x0001 /* DAC_ENA */
#define WM9081_DAC_ENA_SHIFT 0 /* DAC_ENA */
#define WM9081_DAC_ENA_WIDTH 1 /* DAC_ENA */
/*
* R12 (0x0C) - Clock Control 1
*/
#define WM9081_CLK_OP_DIV_MASK 0x1C00 /* CLK_OP_DIV - [12:10] */
#define WM9081_CLK_OP_DIV_SHIFT 10 /* CLK_OP_DIV - [12:10] */
#define WM9081_CLK_OP_DIV_WIDTH 3 /* CLK_OP_DIV - [12:10] */
#define WM9081_CLK_TO_DIV_MASK 0x0300 /* CLK_TO_DIV - [9:8] */
#define WM9081_CLK_TO_DIV_SHIFT 8 /* CLK_TO_DIV - [9:8] */
#define WM9081_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [9:8] */
#define WM9081_MCLKDIV2 0x0080 /* MCLKDIV2 */
#define WM9081_MCLKDIV2_MASK 0x0080 /* MCLKDIV2 */
#define WM9081_MCLKDIV2_SHIFT 7 /* MCLKDIV2 */
#define WM9081_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */
/*
* R13 (0x0D) - Clock Control 2
*/
#define WM9081_CLK_SYS_RATE_MASK 0x00F0 /* CLK_SYS_RATE - [7:4] */
#define WM9081_CLK_SYS_RATE_SHIFT 4 /* CLK_SYS_RATE - [7:4] */
#define WM9081_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [7:4] */
#define WM9081_SAMPLE_RATE_MASK 0x000F /* SAMPLE_RATE - [3:0] */
#define WM9081_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [3:0] */
#define WM9081_SAMPLE_RATE_WIDTH 4 /* SAMPLE_RATE - [3:0] */
/*
* R14 (0x0E) - Clock Control 3
*/
#define WM9081_CLK_SRC_SEL 0x2000 /* CLK_SRC_SEL */
#define WM9081_CLK_SRC_SEL_MASK 0x2000 /* CLK_SRC_SEL */
#define WM9081_CLK_SRC_SEL_SHIFT 13 /* CLK_SRC_SEL */
#define WM9081_CLK_SRC_SEL_WIDTH 1 /* CLK_SRC_SEL */
#define WM9081_CLK_OP_ENA 0x0020 /* CLK_OP_ENA */
#define WM9081_CLK_OP_ENA_MASK 0x0020 /* CLK_OP_ENA */
#define WM9081_CLK_OP_ENA_SHIFT 5 /* CLK_OP_ENA */
#define WM9081_CLK_OP_ENA_WIDTH 1 /* CLK_OP_ENA */
#define WM9081_CLK_TO_ENA 0x0004 /* CLK_TO_ENA */
#define WM9081_CLK_TO_ENA_MASK 0x0004 /* CLK_TO_ENA */
#define WM9081_CLK_TO_ENA_SHIFT 2 /* CLK_TO_ENA */
#define WM9081_CLK_TO_ENA_WIDTH 1 /* CLK_TO_ENA */
#define WM9081_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */
#define WM9081_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */
#define WM9081_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */
#define WM9081_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */
#define WM9081_CLK_SYS_ENA 0x0001 /* CLK_SYS_ENA */
#define WM9081_CLK_SYS_ENA_MASK 0x0001 /* CLK_SYS_ENA */
#define WM9081_CLK_SYS_ENA_SHIFT 0 /* CLK_SYS_ENA */
#define WM9081_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */
/*
* R16 (0x10) - FLL Control 1
*/
#define WM9081_FLL_HOLD 0x0008 /* FLL_HOLD */
#define WM9081_FLL_HOLD_MASK 0x0008 /* FLL_HOLD */
#define WM9081_FLL_HOLD_SHIFT 3 /* FLL_HOLD */
#define WM9081_FLL_HOLD_WIDTH 1 /* FLL_HOLD */
#define WM9081_FLL_FRAC 0x0004 /* FLL_FRAC */
#define WM9081_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */
#define WM9081_FLL_FRAC_SHIFT 2 /* FLL_FRAC */
#define WM9081_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
#define WM9081_FLL_ENA 0x0001 /* FLL_ENA */
#define WM9081_FLL_ENA_MASK 0x0001 /* FLL_ENA */
#define WM9081_FLL_ENA_SHIFT 0 /* FLL_ENA */
#define WM9081_FLL_ENA_WIDTH 1 /* FLL_ENA */
/*
* R17 (0x11) - FLL Control 2
*/
#define WM9081_FLL_OUTDIV_MASK 0x0700 /* FLL_OUTDIV - [10:8] */
#define WM9081_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [10:8] */
#define WM9081_FLL_OUTDIV_WIDTH 3 /* FLL_OUTDIV - [10:8] */
#define WM9081_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
#define WM9081_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
#define WM9081_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
#define WM9081_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
#define WM9081_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
#define WM9081_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
/*
* R18 (0x12) - FLL Control 3
*/
#define WM9081_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
#define WM9081_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
#define WM9081_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
/*
* R19 (0x13) - FLL Control 4
*/
#define WM9081_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
#define WM9081_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
#define WM9081_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
#define WM9081_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
#define WM9081_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
#define WM9081_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
/*
* R20 (0x14) - FLL Control 5
*/
#define WM9081_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
#define WM9081_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
#define WM9081_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
#define WM9081_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
#define WM9081_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
#define WM9081_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
/*
* R22 (0x16) - Audio Interface 1
*/
#define WM9081_AIFDAC_CHAN 0x0040 /* AIFDAC_CHAN */
#define WM9081_AIFDAC_CHAN_MASK 0x0040 /* AIFDAC_CHAN */
#define WM9081_AIFDAC_CHAN_SHIFT 6 /* AIFDAC_CHAN */
#define WM9081_AIFDAC_CHAN_WIDTH 1 /* AIFDAC_CHAN */
#define WM9081_AIFDAC_TDM_SLOT_MASK 0x0030 /* AIFDAC_TDM_SLOT - [5:4] */
#define WM9081_AIFDAC_TDM_SLOT_SHIFT 4 /* AIFDAC_TDM_SLOT - [5:4] */
#define WM9081_AIFDAC_TDM_SLOT_WIDTH 2 /* AIFDAC_TDM_SLOT - [5:4] */
#define WM9081_AIFDAC_TDM_MODE_MASK 0x000C /* AIFDAC_TDM_MODE - [3:2] */
#define WM9081_AIFDAC_TDM_MODE_SHIFT 2 /* AIFDAC_TDM_MODE - [3:2] */
#define WM9081_AIFDAC_TDM_MODE_WIDTH 2 /* AIFDAC_TDM_MODE - [3:2] */
#define WM9081_DAC_COMP 0x0002 /* DAC_COMP */
#define WM9081_DAC_COMP_MASK 0x0002 /* DAC_COMP */
#define WM9081_DAC_COMP_SHIFT 1 /* DAC_COMP */
#define WM9081_DAC_COMP_WIDTH 1 /* DAC_COMP */
#define WM9081_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */
#define WM9081_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */
#define WM9081_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */
#define WM9081_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
/*
* R23 (0x17) - Audio Interface 2
*/
#define WM9081_AIF_TRIS 0x0200 /* AIF_TRIS */
#define WM9081_AIF_TRIS_MASK 0x0200 /* AIF_TRIS */
#define WM9081_AIF_TRIS_SHIFT 9 /* AIF_TRIS */
#define WM9081_AIF_TRIS_WIDTH 1 /* AIF_TRIS */
#define WM9081_DAC_DAT_INV 0x0100 /* DAC_DAT_INV */
#define WM9081_DAC_DAT_INV_MASK 0x0100 /* DAC_DAT_INV */
#define WM9081_DAC_DAT_INV_SHIFT 8 /* DAC_DAT_INV */
#define WM9081_DAC_DAT_INV_WIDTH 1 /* DAC_DAT_INV */
#define WM9081_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */
#define WM9081_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */
#define WM9081_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */
#define WM9081_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */
#define WM9081_BCLK_DIR 0x0040 /* BCLK_DIR */
#define WM9081_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */
#define WM9081_BCLK_DIR_SHIFT 6 /* BCLK_DIR */
#define WM9081_BCLK_DIR_WIDTH 1 /* BCLK_DIR */
#define WM9081_LRCLK_DIR 0x0020 /* LRCLK_DIR */
#define WM9081_LRCLK_DIR_MASK 0x0020 /* LRCLK_DIR */
#define WM9081_LRCLK_DIR_SHIFT 5 /* LRCLK_DIR */
#define WM9081_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */
#define WM9081_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */
#define WM9081_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */
#define WM9081_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */
#define WM9081_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */
#define WM9081_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */
#define WM9081_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */
#define WM9081_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */
#define WM9081_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */
#define WM9081_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */
#define WM9081_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */
/*
* R24 (0x18) - Audio Interface 3
*/
#define WM9081_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */
#define WM9081_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */
#define WM9081_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */
/*
* R25 (0x19) - Audio Interface 4
*/
#define WM9081_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */
#define WM9081_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */
#define WM9081_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */
/*
* R26 (0x1A) - Interrupt Status
*/
#define WM9081_WSEQ_BUSY_EINT 0x0004 /* WSEQ_BUSY_EINT */
#define WM9081_WSEQ_BUSY_EINT_MASK 0x0004 /* WSEQ_BUSY_EINT */
#define WM9081_WSEQ_BUSY_EINT_SHIFT 2 /* WSEQ_BUSY_EINT */
#define WM9081_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */
#define WM9081_TSHUT_EINT 0x0001 /* TSHUT_EINT */
#define WM9081_TSHUT_EINT_MASK 0x0001 /* TSHUT_EINT */
#define WM9081_TSHUT_EINT_SHIFT 0 /* TSHUT_EINT */
#define WM9081_TSHUT_EINT_WIDTH 1 /* TSHUT_EINT */
/*
* R27 (0x1B) - Interrupt Status Mask
*/
#define WM9081_IM_WSEQ_BUSY_EINT 0x0004 /* IM_WSEQ_BUSY_EINT */
#define WM9081_IM_WSEQ_BUSY_EINT_MASK 0x0004 /* IM_WSEQ_BUSY_EINT */
#define WM9081_IM_WSEQ_BUSY_EINT_SHIFT 2 /* IM_WSEQ_BUSY_EINT */
#define WM9081_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */
#define WM9081_IM_TSHUT_EINT 0x0001 /* IM_TSHUT_EINT */
#define WM9081_IM_TSHUT_EINT_MASK 0x0001 /* IM_TSHUT_EINT */
#define WM9081_IM_TSHUT_EINT_SHIFT 0 /* IM_TSHUT_EINT */
#define WM9081_IM_TSHUT_EINT_WIDTH 1 /* IM_TSHUT_EINT */
/*
* R28 (0x1C) - Interrupt Polarity
*/
#define WM9081_TSHUT_INV 0x0001 /* TSHUT_INV */
#define WM9081_TSHUT_INV_MASK 0x0001 /* TSHUT_INV */
#define WM9081_TSHUT_INV_SHIFT 0 /* TSHUT_INV */
#define WM9081_TSHUT_INV_WIDTH 1 /* TSHUT_INV */
/*
* R29 (0x1D) - Interrupt Control
*/
#define WM9081_IRQ_POL 0x8000 /* IRQ_POL */
#define WM9081_IRQ_POL_MASK 0x8000 /* IRQ_POL */
#define WM9081_IRQ_POL_SHIFT 15 /* IRQ_POL */
#define WM9081_IRQ_POL_WIDTH 1 /* IRQ_POL */
#define WM9081_IRQ_OP_CTRL 0x0001 /* IRQ_OP_CTRL */
#define WM9081_IRQ_OP_CTRL_MASK 0x0001 /* IRQ_OP_CTRL */
#define WM9081_IRQ_OP_CTRL_SHIFT 0 /* IRQ_OP_CTRL */
#define WM9081_IRQ_OP_CTRL_WIDTH 1 /* IRQ_OP_CTRL */
/*
* R30 (0x1E) - DAC Digital 1
*/
#define WM9081_DAC_VOL_MASK 0x00FF /* DAC_VOL - [7:0] */
#define WM9081_DAC_VOL_SHIFT 0 /* DAC_VOL - [7:0] */
#define WM9081_DAC_VOL_WIDTH 8 /* DAC_VOL - [7:0] */
/*
* R31 (0x1F) - DAC Digital 2
*/
#define WM9081_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */
#define WM9081_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */
#define WM9081_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */
#define WM9081_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
#define WM9081_DAC_MUTEMODE 0x0200 /* DAC_MUTEMODE */
#define WM9081_DAC_MUTEMODE_MASK 0x0200 /* DAC_MUTEMODE */
#define WM9081_DAC_MUTEMODE_SHIFT 9 /* DAC_MUTEMODE */
#define WM9081_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */
#define WM9081_DAC_MUTE 0x0008 /* DAC_MUTE */
#define WM9081_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */
#define WM9081_DAC_MUTE_SHIFT 3 /* DAC_MUTE */
#define WM9081_DAC_MUTE_WIDTH 1 /* DAC_MUTE */
#define WM9081_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */
#define WM9081_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */
#define WM9081_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */
/*
* R32 (0x20) - DRC 1
*/
#define WM9081_DRC_ENA 0x8000 /* DRC_ENA */
#define WM9081_DRC_ENA_MASK 0x8000 /* DRC_ENA */
#define WM9081_DRC_ENA_SHIFT 15 /* DRC_ENA */
#define WM9081_DRC_ENA_WIDTH 1 /* DRC_ENA */
#define WM9081_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */
#define WM9081_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */
#define WM9081_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */
#define WM9081_DRC_FF_DLY 0x0020 /* DRC_FF_DLY */
#define WM9081_DRC_FF_DLY_MASK 0x0020 /* DRC_FF_DLY */
#define WM9081_DRC_FF_DLY_SHIFT 5 /* DRC_FF_DLY */
#define WM9081_DRC_FF_DLY_WIDTH 1 /* DRC_FF_DLY */
#define WM9081_DRC_QR 0x0004 /* DRC_QR */
#define WM9081_DRC_QR_MASK 0x0004 /* DRC_QR */
#define WM9081_DRC_QR_SHIFT 2 /* DRC_QR */
#define WM9081_DRC_QR_WIDTH 1 /* DRC_QR */
#define WM9081_DRC_ANTICLIP 0x0002 /* DRC_ANTICLIP */
#define WM9081_DRC_ANTICLIP_MASK 0x0002 /* DRC_ANTICLIP */
#define WM9081_DRC_ANTICLIP_SHIFT 1 /* DRC_ANTICLIP */
#define WM9081_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */
/*
* R33 (0x21) - DRC 2
*/
#define WM9081_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */
#define WM9081_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */
#define WM9081_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */
#define WM9081_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */
#define WM9081_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */
#define WM9081_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */
#define WM9081_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */
#define WM9081_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */
#define WM9081_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */
#define WM9081_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */
#define WM9081_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */
#define WM9081_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */
#define WM9081_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */
#define WM9081_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */
#define WM9081_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */
#define WM9081_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */
#define WM9081_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */
#define WM9081_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */
/*
* R34 (0x22) - DRC 3
*/
#define WM9081_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */
#define WM9081_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */
#define WM9081_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */
#define WM9081_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */
#define WM9081_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */
#define WM9081_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */
/*
* R35 (0x23) - DRC 4
*/
#define WM9081_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */
#define WM9081_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */
#define WM9081_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */
#define WM9081_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */
#define WM9081_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */
#define WM9081_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */
/*
* R38 (0x26) - Write Sequencer 1
*/
#define WM9081_WSEQ_ENA 0x8000 /* WSEQ_ENA */
#define WM9081_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
#define WM9081_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
#define WM9081_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
#define WM9081_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
#define WM9081_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
#define WM9081_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
#define WM9081_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
#define WM9081_WSEQ_START 0x0100 /* WSEQ_START */
#define WM9081_WSEQ_START_MASK 0x0100 /* WSEQ_START */
#define WM9081_WSEQ_START_SHIFT 8 /* WSEQ_START */
#define WM9081_WSEQ_START_WIDTH 1 /* WSEQ_START */
#define WM9081_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
#define WM9081_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
#define WM9081_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
/*
* R39 (0x27) - Write Sequencer 2
*/
#define WM9081_WSEQ_CURRENT_INDEX_MASK 0x07F0 /* WSEQ_CURRENT_INDEX - [10:4] */
#define WM9081_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [10:4] */
#define WM9081_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [10:4] */
#define WM9081_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
#define WM9081_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
#define WM9081_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */
#define WM9081_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
/*
* R40 (0x28) - MW Slave 1
*/
#define WM9081_SPI_CFG 0x0020 /* SPI_CFG */
#define WM9081_SPI_CFG_MASK 0x0020 /* SPI_CFG */
#define WM9081_SPI_CFG_SHIFT 5 /* SPI_CFG */
#define WM9081_SPI_CFG_WIDTH 1 /* SPI_CFG */
#define WM9081_SPI_4WIRE 0x0010 /* SPI_4WIRE */
#define WM9081_SPI_4WIRE_MASK 0x0010 /* SPI_4WIRE */
#define WM9081_SPI_4WIRE_SHIFT 4 /* SPI_4WIRE */
#define WM9081_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
#define WM9081_ARA_ENA 0x0008 /* ARA_ENA */
#define WM9081_ARA_ENA_MASK 0x0008 /* ARA_ENA */
#define WM9081_ARA_ENA_SHIFT 3 /* ARA_ENA */
#define WM9081_ARA_ENA_WIDTH 1 /* ARA_ENA */
#define WM9081_AUTO_INC 0x0002 /* AUTO_INC */
#define WM9081_AUTO_INC_MASK 0x0002 /* AUTO_INC */
#define WM9081_AUTO_INC_SHIFT 1 /* AUTO_INC */
#define WM9081_AUTO_INC_WIDTH 1 /* AUTO_INC */
/*
* R42 (0x2A) - EQ 1
*/
#define WM9081_EQ_B1_GAIN_MASK 0xF800 /* EQ_B1_GAIN - [15:11] */
#define WM9081_EQ_B1_GAIN_SHIFT 11 /* EQ_B1_GAIN - [15:11] */
#define WM9081_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [15:11] */
#define WM9081_EQ_B2_GAIN_MASK 0x07C0 /* EQ_B2_GAIN - [10:6] */
#define WM9081_EQ_B2_GAIN_SHIFT 6 /* EQ_B2_GAIN - [10:6] */
#define WM9081_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [10:6] */
#define WM9081_EQ_B4_GAIN_MASK 0x003E /* EQ_B4_GAIN - [5:1] */
#define WM9081_EQ_B4_GAIN_SHIFT 1 /* EQ_B4_GAIN - [5:1] */
#define WM9081_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [5:1] */
#define WM9081_EQ_ENA 0x0001 /* EQ_ENA */
#define WM9081_EQ_ENA_MASK 0x0001 /* EQ_ENA */
#define WM9081_EQ_ENA_SHIFT 0 /* EQ_ENA */
#define WM9081_EQ_ENA_WIDTH 1 /* EQ_ENA */
/*
* R43 (0x2B) - EQ 2
*/
#define WM9081_EQ_B3_GAIN_MASK 0xF800 /* EQ_B3_GAIN - [15:11] */
#define WM9081_EQ_B3_GAIN_SHIFT 11 /* EQ_B3_GAIN - [15:11] */
#define WM9081_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [15:11] */
#define WM9081_EQ_B5_GAIN_MASK 0x07C0 /* EQ_B5_GAIN - [10:6] */
#define WM9081_EQ_B5_GAIN_SHIFT 6 /* EQ_B5_GAIN - [10:6] */
#define WM9081_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [10:6] */
/*
* R44 (0x2C) - EQ 3
*/
#define WM9081_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */
#define WM9081_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */
#define WM9081_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */
/*
* R45 (0x2D) - EQ 4
*/
#define WM9081_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */
#define WM9081_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */
#define WM9081_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */
/*
* R46 (0x2E) - EQ 5
*/
#define WM9081_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */
#define WM9081_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */
#define WM9081_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */
/*
* R47 (0x2F) - EQ 6
*/
#define WM9081_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */
#define WM9081_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */
#define WM9081_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */
/*
* R48 (0x30) - EQ 7
*/
#define WM9081_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */
#define WM9081_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */
#define WM9081_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */
/*
* R49 (0x31) - EQ 8
*/
#define WM9081_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */
#define WM9081_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */
#define WM9081_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */
/*
* R50 (0x32) - EQ 9
*/
#define WM9081_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */
#define WM9081_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */
#define WM9081_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */
/*
* R51 (0x33) - EQ 10
*/
#define WM9081_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */
#define WM9081_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */
#define WM9081_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */
/*
* R52 (0x34) - EQ 11
*/
#define WM9081_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */
#define WM9081_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */
#define WM9081_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */
/*
* R53 (0x35) - EQ 12
*/
#define WM9081_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */
#define WM9081_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */
#define WM9081_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */
/*
* R54 (0x36) - EQ 13
*/
#define WM9081_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */
#define WM9081_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */
#define WM9081_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */
/*
* R55 (0x37) - EQ 14
*/
#define WM9081_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */
#define WM9081_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */
#define WM9081_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */
/*
* R56 (0x38) - EQ 15
*/
#define WM9081_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */
#define WM9081_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */
#define WM9081_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */
/*
* R57 (0x39) - EQ 16
*/
#define WM9081_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */
#define WM9081_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */
#define WM9081_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */
/*
* R58 (0x3A) - EQ 17
*/
#define WM9081_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */
#define WM9081_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */
#define WM9081_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */
/*
* R59 (0x3B) - EQ 18
*/
#define WM9081_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */
#define WM9081_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */
#define WM9081_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */
/*
* R60 (0x3C) - EQ 19
*/
#define WM9081_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */
#define WM9081_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */
#define WM9081_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */
/*
* R61 (0x3D) - EQ 20
*/
#define WM9081_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */
#define WM9081_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */
#define WM9081_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */
#endif

452
kernel/sound/soc/codecs/wm9705.c Normal file
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/*
* wm9705.c -- ALSA Soc WM9705 codec support
*
* Copyright 2008 Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; Version 2 of the License only.
*
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "wm9705.h"
/*
* WM9705 register cache
*/
static const u16 wm9705_reg[] = {
0x6150, 0x8000, 0x8000, 0x8000, /* 0x0 */
0x0000, 0x8000, 0x8008, 0x8008, /* 0x8 */
0x8808, 0x8808, 0x8808, 0x8808, /* 0x10 */
0x8808, 0x0000, 0x8000, 0x0000, /* 0x18 */
0x0000, 0x0000, 0x0000, 0x000f, /* 0x20 */
0x0605, 0x0000, 0xbb80, 0x0000, /* 0x28 */
0x0000, 0xbb80, 0x0000, 0x0000, /* 0x30 */
0x0000, 0x2000, 0x0000, 0x0000, /* 0x38 */
0x0000, 0x0000, 0x0000, 0x0000, /* 0x40 */
0x0000, 0x0000, 0x0000, 0x0000, /* 0x48 */
0x0000, 0x0000, 0x0000, 0x0000, /* 0x50 */
0x0000, 0x0000, 0x0000, 0x0000, /* 0x58 */
0x0000, 0x0000, 0x0000, 0x0000, /* 0x60 */
0x0000, 0x0000, 0x0000, 0x0000, /* 0x68 */
0x0000, 0x0808, 0x0000, 0x0006, /* 0x70 */
0x0000, 0x0000, 0x574d, 0x4c05, /* 0x78 */
};
static const struct snd_kcontrol_new wm9705_snd_ac97_controls[] = {
SOC_DOUBLE("Master Playback Volume", AC97_MASTER, 8, 0, 31, 1),
SOC_SINGLE("Master Playback Switch", AC97_MASTER, 15, 1, 1),
SOC_DOUBLE("Headphone Playback Volume", AC97_HEADPHONE, 8, 0, 31, 1),
SOC_SINGLE("Headphone Playback Switch", AC97_HEADPHONE, 15, 1, 1),
SOC_DOUBLE("PCM Playback Volume", AC97_PCM, 8, 0, 31, 1),
SOC_SINGLE("PCM Playback Switch", AC97_PCM, 15, 1, 1),
SOC_SINGLE("Mono Playback Volume", AC97_MASTER_MONO, 0, 31, 1),
SOC_SINGLE("Mono Playback Switch", AC97_MASTER_MONO, 15, 1, 1),
SOC_SINGLE("PCBeep Playback Volume", AC97_PC_BEEP, 1, 15, 1),
SOC_SINGLE("Phone Playback Volume", AC97_PHONE, 0, 31, 1),
SOC_DOUBLE("Line Playback Volume", AC97_LINE, 8, 0, 31, 1),
SOC_DOUBLE("CD Playback Volume", AC97_CD, 8, 0, 31, 1),
SOC_SINGLE("Mic Playback Volume", AC97_MIC, 0, 31, 1),
SOC_SINGLE("Mic 20dB Boost Switch", AC97_MIC, 6, 1, 0),
SOC_DOUBLE("Capture Volume", AC97_REC_GAIN, 8, 0, 15, 0),
SOC_SINGLE("Capture Switch", AC97_REC_GAIN, 15, 1, 1),
};
static const char *wm9705_mic[] = {"Mic 1", "Mic 2"};
static const char *wm9705_rec_sel[] = {"Mic", "CD", "NC", "NC",
"Line", "Stereo Mix", "Mono Mix", "Phone"};
static const struct soc_enum wm9705_enum_mic =
SOC_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 8, 2, wm9705_mic);
static const struct soc_enum wm9705_enum_rec_l =
SOC_ENUM_SINGLE(AC97_REC_SEL, 8, 8, wm9705_rec_sel);
static const struct soc_enum wm9705_enum_rec_r =
SOC_ENUM_SINGLE(AC97_REC_SEL, 0, 8, wm9705_rec_sel);
/* Headphone Mixer */
static const struct snd_kcontrol_new wm9705_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("PCBeep Playback Switch", AC97_PC_BEEP, 15, 1, 1),
SOC_DAPM_SINGLE("CD Playback Switch", AC97_CD, 15, 1, 1),
SOC_DAPM_SINGLE("Mic Playback Switch", AC97_MIC, 15, 1, 1),
SOC_DAPM_SINGLE("Phone Playback Switch", AC97_PHONE, 15, 1, 1),
SOC_DAPM_SINGLE("Line Playback Switch", AC97_LINE, 15, 1, 1),
};
/* Mic source */
static const struct snd_kcontrol_new wm9705_mic_src_controls =
SOC_DAPM_ENUM("Route", wm9705_enum_mic);
/* Capture source */
static const struct snd_kcontrol_new wm9705_capture_selectl_controls =
SOC_DAPM_ENUM("Route", wm9705_enum_rec_l);
static const struct snd_kcontrol_new wm9705_capture_selectr_controls =
SOC_DAPM_ENUM("Route", wm9705_enum_rec_r);
/* DAPM widgets */
static const struct snd_soc_dapm_widget wm9705_dapm_widgets[] = {
SND_SOC_DAPM_MUX("Mic Source", SND_SOC_NOPM, 0, 0,
&wm9705_mic_src_controls),
SND_SOC_DAPM_MUX("Left Capture Source", SND_SOC_NOPM, 0, 0,
&wm9705_capture_selectl_controls),
SND_SOC_DAPM_MUX("Right Capture Source", SND_SOC_NOPM, 0, 0,
&wm9705_capture_selectr_controls),
SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_MIXER_NAMED_CTL("HP Mixer", SND_SOC_NOPM, 0, 0,
&wm9705_hp_mixer_controls[0],
ARRAY_SIZE(wm9705_hp_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_PGA("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Speaker PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Line PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Line out PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mono PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Phone PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Mic PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("PCBEEP PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("CD PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
SND_SOC_DAPM_OUTPUT("LOUT"),
SND_SOC_DAPM_OUTPUT("ROUT"),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_INPUT("PHONE"),
SND_SOC_DAPM_INPUT("LINEINL"),
SND_SOC_DAPM_INPUT("LINEINR"),
SND_SOC_DAPM_INPUT("CDINL"),
SND_SOC_DAPM_INPUT("CDINR"),
SND_SOC_DAPM_INPUT("PCBEEP"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
};
/* Audio map
* WM9705 has no switches to disable the route from the inputs to the HP mixer
* so in order to prevent active inputs from forcing the audio outputs to be
* constantly enabled, we use the mutes on those inputs to simulate such
* controls.
*/
static const struct snd_soc_dapm_route audio_map[] = {
/* HP mixer */
{"HP Mixer", "PCBeep Playback Switch", "PCBEEP PGA"},
{"HP Mixer", "CD Playback Switch", "CD PGA"},
{"HP Mixer", "Mic Playback Switch", "Mic PGA"},
{"HP Mixer", "Phone Playback Switch", "Phone PGA"},
{"HP Mixer", "Line Playback Switch", "Line PGA"},
{"HP Mixer", NULL, "Left DAC"},
{"HP Mixer", NULL, "Right DAC"},
/* mono mixer */
{"Mono Mixer", NULL, "HP Mixer"},
/* outputs */
{"Headphone PGA", NULL, "HP Mixer"},
{"HPOUTL", NULL, "Headphone PGA"},
{"HPOUTR", NULL, "Headphone PGA"},
{"Line out PGA", NULL, "HP Mixer"},
{"LOUT", NULL, "Line out PGA"},
{"ROUT", NULL, "Line out PGA"},
{"Mono PGA", NULL, "Mono Mixer"},
{"MONOOUT", NULL, "Mono PGA"},
/* inputs */
{"CD PGA", NULL, "CDINL"},
{"CD PGA", NULL, "CDINR"},
{"Line PGA", NULL, "LINEINL"},
{"Line PGA", NULL, "LINEINR"},
{"Phone PGA", NULL, "PHONE"},
{"Mic Source", "Mic 1", "MIC1"},
{"Mic Source", "Mic 2", "MIC2"},
{"Mic PGA", NULL, "Mic Source"},
{"PCBEEP PGA", NULL, "PCBEEP"},
/* Left capture selector */
{"Left Capture Source", "Mic", "Mic Source"},
{"Left Capture Source", "CD", "CDINL"},
{"Left Capture Source", "Line", "LINEINL"},
{"Left Capture Source", "Stereo Mix", "HP Mixer"},
{"Left Capture Source", "Mono Mix", "HP Mixer"},
{"Left Capture Source", "Phone", "PHONE"},
/* Right capture source */
{"Right Capture Source", "Mic", "Mic Source"},
{"Right Capture Source", "CD", "CDINR"},
{"Right Capture Source", "Line", "LINEINR"},
{"Right Capture Source", "Stereo Mix", "HP Mixer"},
{"Right Capture Source", "Mono Mix", "HP Mixer"},
{"Right Capture Source", "Phone", "PHONE"},
{"ADC PGA", NULL, "Left Capture Source"},
{"ADC PGA", NULL, "Right Capture Source"},
/* ADC's */
{"Left ADC", NULL, "ADC PGA"},
{"Right ADC", NULL, "ADC PGA"},
};
static int wm9705_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, wm9705_dapm_widgets,
ARRAY_SIZE(wm9705_dapm_widgets));
snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
snd_soc_dapm_new_widgets(codec);
return 0;
}
/* We use a register cache to enhance read performance. */
static unsigned int ac97_read(struct snd_soc_codec *codec, unsigned int reg)
{
u16 *cache = codec->reg_cache;
switch (reg) {
case AC97_RESET:
case AC97_VENDOR_ID1:
case AC97_VENDOR_ID2:
return soc_ac97_ops.read(codec->ac97, reg);
default:
reg = reg >> 1;
if (reg >= (ARRAY_SIZE(wm9705_reg)))
return -EIO;
return cache[reg];
}
}
static int ac97_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int val)
{
u16 *cache = codec->reg_cache;
soc_ac97_ops.write(codec->ac97, reg, val);
reg = reg >> 1;
if (reg < (ARRAY_SIZE(wm9705_reg)))
cache[reg] = val;
return 0;
}
static int ac97_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
int reg;
u16 vra;
vra = ac97_read(codec, AC97_EXTENDED_STATUS);
ac97_write(codec, AC97_EXTENDED_STATUS, vra | 0x1);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = AC97_PCM_FRONT_DAC_RATE;
else
reg = AC97_PCM_LR_ADC_RATE;
return ac97_write(codec, reg, runtime->rate);
}
#define WM9705_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | \
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000)
static struct snd_soc_dai_ops wm9705_dai_ops = {
.prepare = ac97_prepare,
};
struct snd_soc_dai wm9705_dai[] = {
{
.name = "AC97 HiFi",
.ac97_control = 1,
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM9705_AC97_RATES,
.formats = SND_SOC_STD_AC97_FMTS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM9705_AC97_RATES,
.formats = SND_SOC_STD_AC97_FMTS,
},
.ops = &wm9705_dai_ops,
},
{
.name = "AC97 Aux",
.playback = {
.stream_name = "Aux Playback",
.channels_min = 1,
.channels_max = 1,
.rates = WM9705_AC97_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
}
};
EXPORT_SYMBOL_GPL(wm9705_dai);
static int wm9705_reset(struct snd_soc_codec *codec)
{
if (soc_ac97_ops.reset) {
soc_ac97_ops.reset(codec->ac97);
if (ac97_read(codec, 0) == wm9705_reg[0])
return 0; /* Success */
}
return -EIO;
}
#ifdef CONFIG_PM
static int wm9705_soc_suspend(struct platform_device *pdev, pm_message_t msg)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
soc_ac97_ops.write(codec->ac97, AC97_POWERDOWN, 0xffff);
return 0;
}
static int wm9705_soc_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
int i, ret;
u16 *cache = codec->reg_cache;
ret = wm9705_reset(codec);
if (ret < 0) {
printk(KERN_ERR "could not reset AC97 codec\n");
return ret;
}
for (i = 2; i < ARRAY_SIZE(wm9705_reg) << 1; i += 2) {
soc_ac97_ops.write(codec->ac97, i, cache[i>>1]);
}
return 0;
}
#else
#define wm9705_soc_suspend NULL
#define wm9705_soc_resume NULL
#endif
static int wm9705_soc_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
printk(KERN_INFO "WM9705 SoC Audio Codec\n");
socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec),
GFP_KERNEL);
if (socdev->card->codec == NULL)
return -ENOMEM;
codec = socdev->card->codec;
mutex_init(&codec->mutex);
codec->reg_cache = kmemdup(wm9705_reg, sizeof(wm9705_reg), GFP_KERNEL);
if (codec->reg_cache == NULL) {
ret = -ENOMEM;
goto cache_err;
}
codec->reg_cache_size = sizeof(wm9705_reg);
codec->reg_cache_step = 2;
codec->name = "WM9705";
codec->owner = THIS_MODULE;
codec->dai = wm9705_dai;
codec->num_dai = ARRAY_SIZE(wm9705_dai);
codec->write = ac97_write;
codec->read = ac97_read;
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
ret = snd_soc_new_ac97_codec(codec, &soc_ac97_ops, 0);
if (ret < 0) {
printk(KERN_ERR "wm9705: failed to register AC97 codec\n");
goto codec_err;
}
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0)
goto pcm_err;
ret = wm9705_reset(codec);
if (ret)
goto reset_err;
snd_soc_add_controls(codec, wm9705_snd_ac97_controls,
ARRAY_SIZE(wm9705_snd_ac97_controls));
wm9705_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
printk(KERN_ERR "wm9705: failed to register card\n");
goto reset_err;
}
return 0;
reset_err:
snd_soc_free_pcms(socdev);
pcm_err:
snd_soc_free_ac97_codec(codec);
codec_err:
kfree(codec->reg_cache);
cache_err:
kfree(socdev->card->codec);
socdev->card->codec = NULL;
return ret;
}
static int wm9705_soc_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
if (codec == NULL)
return 0;
snd_soc_dapm_free(socdev);
snd_soc_free_pcms(socdev);
snd_soc_free_ac97_codec(codec);
kfree(codec->reg_cache);
kfree(codec);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_wm9705 = {
.probe = wm9705_soc_probe,
.remove = wm9705_soc_remove,
.suspend = wm9705_soc_suspend,
.resume = wm9705_soc_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm9705);
MODULE_DESCRIPTION("ASoC WM9705 driver");
MODULE_AUTHOR("Ian Molton");
MODULE_LICENSE("GPL v2");

14
kernel/sound/soc/codecs/wm9705.h Normal file
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/*
* wm9705.h -- WM9705 Soc Audio driver
*/
#ifndef _WM9705_H
#define _WM9705_H
#define WM9705_DAI_AC97_HIFI 0
#define WM9705_DAI_AC97_AUX 1
extern struct snd_soc_dai wm9705_dai[2];
extern struct snd_soc_codec_device soc_codec_dev_wm9705;
#endif

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kernel/sound/soc/codecs/wm9712.c Normal file
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/*
* wm9712.c -- ALSA Soc WM9712 codec support
*
* Copyright 2006 Wolfson Microelectronics PLC.
* Author: Liam Girdwood <lrg@slimlogic.co.uk>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "wm9712.h"
#define WM9712_VERSION "0.4"
static unsigned int ac97_read(struct snd_soc_codec *codec,
unsigned int reg);
static int ac97_write(struct snd_soc_codec *codec,
unsigned int reg, unsigned int val);
/*
* WM9712 register cache
*/
static const u16 wm9712_reg[] = {
0x6174, 0x8000, 0x8000, 0x8000, /* 6 */
0x0f0f, 0xaaa0, 0xc008, 0x6808, /* e */
0xe808, 0xaaa0, 0xad00, 0x8000, /* 16 */
0xe808, 0x3000, 0x8000, 0x0000, /* 1e */
0x0000, 0x0000, 0x0000, 0x000f, /* 26 */
0x0405, 0x0410, 0xbb80, 0xbb80, /* 2e */
0x0000, 0xbb80, 0x0000, 0x0000, /* 36 */
0x0000, 0x2000, 0x0000, 0x0000, /* 3e */
0x0000, 0x0000, 0x0000, 0x0000, /* 46 */
0x0000, 0x0000, 0xf83e, 0xffff, /* 4e */
0x0000, 0x0000, 0x0000, 0xf83e, /* 56 */
0x0008, 0x0000, 0x0000, 0x0000, /* 5e */
0xb032, 0x3e00, 0x0000, 0x0000, /* 66 */
0x0000, 0x0000, 0x0000, 0x0000, /* 6e */
0x0000, 0x0000, 0x0000, 0x0006, /* 76 */
0x0001, 0x0000, 0x574d, 0x4c12, /* 7e */
0x0000, 0x0000 /* virtual hp mixers */
};
/* virtual HP mixers regs */
#define HPL_MIXER 0x80
#define HPR_MIXER 0x82
static const char *wm9712_alc_select[] = {"None", "Left", "Right", "Stereo"};
static const char *wm9712_alc_mux[] = {"Stereo", "Left", "Right", "None"};
static const char *wm9712_out3_src[] = {"Left", "VREF", "Left + Right",
"Mono"};
static const char *wm9712_spk_src[] = {"Speaker Mix", "Headphone Mix"};
static const char *wm9712_rec_adc[] = {"Stereo", "Left", "Right", "Mute"};
static const char *wm9712_base[] = {"Linear Control", "Adaptive Boost"};
static const char *wm9712_rec_gain[] = {"+1.5dB Steps", "+0.75dB Steps"};
static const char *wm9712_mic[] = {"Mic 1", "Differential", "Mic 2",
"Stereo"};
static const char *wm9712_rec_sel[] = {"Mic", "NC", "NC", "Speaker Mixer",
"Line", "Headphone Mixer", "Phone Mixer", "Phone"};
static const char *wm9712_ng_type[] = {"Constant Gain", "Mute"};
static const char *wm9712_diff_sel[] = {"Mic", "Line"};
static const struct soc_enum wm9712_enum[] = {
SOC_ENUM_SINGLE(AC97_PCI_SVID, 14, 4, wm9712_alc_select),
SOC_ENUM_SINGLE(AC97_VIDEO, 12, 4, wm9712_alc_mux),
SOC_ENUM_SINGLE(AC97_AUX, 9, 4, wm9712_out3_src),
SOC_ENUM_SINGLE(AC97_AUX, 8, 2, wm9712_spk_src),
SOC_ENUM_SINGLE(AC97_REC_SEL, 12, 4, wm9712_rec_adc),
SOC_ENUM_SINGLE(AC97_MASTER_TONE, 15, 2, wm9712_base),
SOC_ENUM_DOUBLE(AC97_REC_GAIN, 14, 6, 2, wm9712_rec_gain),
SOC_ENUM_SINGLE(AC97_MIC, 5, 4, wm9712_mic),
SOC_ENUM_SINGLE(AC97_REC_SEL, 8, 8, wm9712_rec_sel),
SOC_ENUM_SINGLE(AC97_REC_SEL, 0, 8, wm9712_rec_sel),
SOC_ENUM_SINGLE(AC97_PCI_SVID, 5, 2, wm9712_ng_type),
SOC_ENUM_SINGLE(0x5c, 8, 2, wm9712_diff_sel),
};
static const struct snd_kcontrol_new wm9712_snd_ac97_controls[] = {
SOC_DOUBLE("Speaker Playback Volume", AC97_MASTER, 8, 0, 31, 1),
SOC_SINGLE("Speaker Playback Switch", AC97_MASTER, 15, 1, 1),
SOC_DOUBLE("Headphone Playback Volume", AC97_HEADPHONE, 8, 0, 31, 1),
SOC_SINGLE("Headphone Playback Switch", AC97_HEADPHONE, 15, 1, 1),
SOC_DOUBLE("PCM Playback Volume", AC97_PCM, 8, 0, 31, 1),
SOC_SINGLE("Speaker Playback ZC Switch", AC97_MASTER, 7, 1, 0),
SOC_SINGLE("Speaker Playback Invert Switch", AC97_MASTER, 6, 1, 0),
SOC_SINGLE("Headphone Playback ZC Switch", AC97_HEADPHONE, 7, 1, 0),
SOC_SINGLE("Mono Playback ZC Switch", AC97_MASTER_MONO, 7, 1, 0),
SOC_SINGLE("Mono Playback Volume", AC97_MASTER_MONO, 0, 31, 1),
SOC_SINGLE("Mono Playback Switch", AC97_MASTER_MONO, 15, 1, 1),
SOC_SINGLE("ALC Target Volume", AC97_CODEC_CLASS_REV, 12, 15, 0),
SOC_SINGLE("ALC Hold Time", AC97_CODEC_CLASS_REV, 8, 15, 0),
SOC_SINGLE("ALC Decay Time", AC97_CODEC_CLASS_REV, 4, 15, 0),
SOC_SINGLE("ALC Attack Time", AC97_CODEC_CLASS_REV, 0, 15, 0),
SOC_ENUM("ALC Function", wm9712_enum[0]),
SOC_SINGLE("ALC Max Volume", AC97_PCI_SVID, 11, 7, 0),
SOC_SINGLE("ALC ZC Timeout", AC97_PCI_SVID, 9, 3, 1),
SOC_SINGLE("ALC ZC Switch", AC97_PCI_SVID, 8, 1, 0),
SOC_SINGLE("ALC NG Switch", AC97_PCI_SVID, 7, 1, 0),
SOC_ENUM("ALC NG Type", wm9712_enum[10]),
SOC_SINGLE("ALC NG Threshold", AC97_PCI_SVID, 0, 31, 1),
SOC_SINGLE("Mic Headphone Volume", AC97_VIDEO, 12, 7, 1),
SOC_SINGLE("ALC Headphone Volume", AC97_VIDEO, 7, 7, 1),
SOC_SINGLE("Out3 Switch", AC97_AUX, 15, 1, 1),
SOC_SINGLE("Out3 ZC Switch", AC97_AUX, 7, 1, 1),
SOC_SINGLE("Out3 Volume", AC97_AUX, 0, 31, 1),
SOC_SINGLE("PCBeep Bypass Headphone Volume", AC97_PC_BEEP, 12, 7, 1),
SOC_SINGLE("PCBeep Bypass Speaker Volume", AC97_PC_BEEP, 8, 7, 1),
SOC_SINGLE("PCBeep Bypass Phone Volume", AC97_PC_BEEP, 4, 7, 1),
SOC_SINGLE("Aux Playback Headphone Volume", AC97_CD, 12, 7, 1),
SOC_SINGLE("Aux Playback Speaker Volume", AC97_CD, 8, 7, 1),
SOC_SINGLE("Aux Playback Phone Volume", AC97_CD, 4, 7, 1),
SOC_SINGLE("Phone Volume", AC97_PHONE, 0, 15, 1),
SOC_DOUBLE("Line Capture Volume", AC97_LINE, 8, 0, 31, 1),
SOC_SINGLE("Capture 20dB Boost Switch", AC97_REC_SEL, 14, 1, 0),
SOC_SINGLE("Capture to Phone 20dB Boost Switch", AC97_REC_SEL, 11, 1, 1),
SOC_SINGLE("3D Upper Cut-off Switch", AC97_3D_CONTROL, 5, 1, 1),
SOC_SINGLE("3D Lower Cut-off Switch", AC97_3D_CONTROL, 4, 1, 1),
SOC_SINGLE("3D Playback Volume", AC97_3D_CONTROL, 0, 15, 0),
SOC_ENUM("Bass Control", wm9712_enum[5]),
SOC_SINGLE("Bass Cut-off Switch", AC97_MASTER_TONE, 12, 1, 1),
SOC_SINGLE("Tone Cut-off Switch", AC97_MASTER_TONE, 4, 1, 1),
SOC_SINGLE("Playback Attenuate (-6dB) Switch", AC97_MASTER_TONE, 6, 1, 0),
SOC_SINGLE("Bass Volume", AC97_MASTER_TONE, 8, 15, 1),
SOC_SINGLE("Treble Volume", AC97_MASTER_TONE, 0, 15, 1),
SOC_SINGLE("Capture ADC Switch", AC97_REC_GAIN, 15, 1, 1),
SOC_ENUM("Capture Volume Steps", wm9712_enum[6]),
SOC_DOUBLE("Capture Volume", AC97_REC_GAIN, 8, 0, 63, 1),
SOC_SINGLE("Capture ZC Switch", AC97_REC_GAIN, 7, 1, 0),
SOC_SINGLE("Mic 1 Volume", AC97_MIC, 8, 31, 1),
SOC_SINGLE("Mic 2 Volume", AC97_MIC, 0, 31, 1),
SOC_SINGLE("Mic 20dB Boost Switch", AC97_MIC, 7, 1, 0),
};
/* We have to create a fake left and right HP mixers because
* the codec only has a single control that is shared by both channels.
* This makes it impossible to determine the audio path.
*/
static int mixer_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
u16 l, r, beep, line, phone, mic, pcm, aux;
l = ac97_read(w->codec, HPL_MIXER);
r = ac97_read(w->codec, HPR_MIXER);
beep = ac97_read(w->codec, AC97_PC_BEEP);
mic = ac97_read(w->codec, AC97_VIDEO);
phone = ac97_read(w->codec, AC97_PHONE);
line = ac97_read(w->codec, AC97_LINE);
pcm = ac97_read(w->codec, AC97_PCM);
aux = ac97_read(w->codec, AC97_CD);
if (l & 0x1 || r & 0x1)
ac97_write(w->codec, AC97_VIDEO, mic & 0x7fff);
else
ac97_write(w->codec, AC97_VIDEO, mic | 0x8000);
if (l & 0x2 || r & 0x2)
ac97_write(w->codec, AC97_PCM, pcm & 0x7fff);
else
ac97_write(w->codec, AC97_PCM, pcm | 0x8000);
if (l & 0x4 || r & 0x4)
ac97_write(w->codec, AC97_LINE, line & 0x7fff);
else
ac97_write(w->codec, AC97_LINE, line | 0x8000);
if (l & 0x8 || r & 0x8)
ac97_write(w->codec, AC97_PHONE, phone & 0x7fff);
else
ac97_write(w->codec, AC97_PHONE, phone | 0x8000);
if (l & 0x10 || r & 0x10)
ac97_write(w->codec, AC97_CD, aux & 0x7fff);
else
ac97_write(w->codec, AC97_CD, aux | 0x8000);
if (l & 0x20 || r & 0x20)
ac97_write(w->codec, AC97_PC_BEEP, beep & 0x7fff);
else
ac97_write(w->codec, AC97_PC_BEEP, beep | 0x8000);
return 0;
}
/* Left Headphone Mixers */
static const struct snd_kcontrol_new wm9712_hpl_mixer_controls[] = {
SOC_DAPM_SINGLE("PCBeep Bypass Switch", HPL_MIXER, 5, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", HPL_MIXER, 4, 1, 0),
SOC_DAPM_SINGLE("Phone Bypass Switch", HPL_MIXER, 3, 1, 0),
SOC_DAPM_SINGLE("Line Bypass Switch", HPL_MIXER, 2, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", HPL_MIXER, 1, 1, 0),
SOC_DAPM_SINGLE("Mic Sidetone Switch", HPL_MIXER, 0, 1, 0),
};
/* Right Headphone Mixers */
static const struct snd_kcontrol_new wm9712_hpr_mixer_controls[] = {
SOC_DAPM_SINGLE("PCBeep Bypass Switch", HPR_MIXER, 5, 1, 0),
SOC_DAPM_SINGLE("Aux Playback Switch", HPR_MIXER, 4, 1, 0),
SOC_DAPM_SINGLE("Phone Bypass Switch", HPR_MIXER, 3, 1, 0),
SOC_DAPM_SINGLE("Line Bypass Switch", HPR_MIXER, 2, 1, 0),
SOC_DAPM_SINGLE("PCM Playback Switch", HPR_MIXER, 1, 1, 0),
SOC_DAPM_SINGLE("Mic Sidetone Switch", HPR_MIXER, 0, 1, 0),
};
/* Speaker Mixer */
static const struct snd_kcontrol_new wm9712_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("PCBeep Bypass Switch", AC97_PC_BEEP, 11, 1, 1),
SOC_DAPM_SINGLE("Aux Playback Switch", AC97_CD, 11, 1, 1),
SOC_DAPM_SINGLE("Phone Bypass Switch", AC97_PHONE, 14, 1, 1),
SOC_DAPM_SINGLE("Line Bypass Switch", AC97_LINE, 14, 1, 1),
SOC_DAPM_SINGLE("PCM Playback Switch", AC97_PCM, 14, 1, 1),
};
/* Phone Mixer */
static const struct snd_kcontrol_new wm9712_phone_mixer_controls[] = {
SOC_DAPM_SINGLE("PCBeep Bypass Switch", AC97_PC_BEEP, 7, 1, 1),
SOC_DAPM_SINGLE("Aux Playback Switch", AC97_CD, 7, 1, 1),
SOC_DAPM_SINGLE("Line Bypass Switch", AC97_LINE, 13, 1, 1),
SOC_DAPM_SINGLE("PCM Playback Switch", AC97_PCM, 13, 1, 1),
SOC_DAPM_SINGLE("Mic 1 Sidetone Switch", AC97_MIC, 14, 1, 1),
SOC_DAPM_SINGLE("Mic 2 Sidetone Switch", AC97_MIC, 13, 1, 1),
};
/* ALC headphone mux */
static const struct snd_kcontrol_new wm9712_alc_mux_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[1]);
/* out 3 mux */
static const struct snd_kcontrol_new wm9712_out3_mux_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[2]);
/* spk mux */
static const struct snd_kcontrol_new wm9712_spk_mux_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[3]);
/* Capture to Phone mux */
static const struct snd_kcontrol_new wm9712_capture_phone_mux_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[4]);
/* Capture left select */
static const struct snd_kcontrol_new wm9712_capture_selectl_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[8]);
/* Capture right select */
static const struct snd_kcontrol_new wm9712_capture_selectr_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[9]);
/* Mic select */
static const struct snd_kcontrol_new wm9712_mic_src_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[7]);
/* diff select */
static const struct snd_kcontrol_new wm9712_diff_sel_controls =
SOC_DAPM_ENUM("Route", wm9712_enum[11]);
static const struct snd_soc_dapm_widget wm9712_dapm_widgets[] = {
SND_SOC_DAPM_MUX("ALC Sidetone Mux", SND_SOC_NOPM, 0, 0,
&wm9712_alc_mux_controls),
SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0,
&wm9712_out3_mux_controls),
SND_SOC_DAPM_MUX("Speaker Mux", SND_SOC_NOPM, 0, 0,
&wm9712_spk_mux_controls),
SND_SOC_DAPM_MUX("Capture Phone Mux", SND_SOC_NOPM, 0, 0,
&wm9712_capture_phone_mux_controls),
SND_SOC_DAPM_MUX("Left Capture Select", SND_SOC_NOPM, 0, 0,
&wm9712_capture_selectl_controls),
SND_SOC_DAPM_MUX("Right Capture Select", SND_SOC_NOPM, 0, 0,
&wm9712_capture_selectr_controls),
SND_SOC_DAPM_MUX("Mic Select Source", SND_SOC_NOPM, 0, 0,
&wm9712_mic_src_controls),
SND_SOC_DAPM_MUX("Differential Source", SND_SOC_NOPM, 0, 0,
&wm9712_diff_sel_controls),
SND_SOC_DAPM_MIXER("AC97 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER_E("Left HP Mixer", AC97_INT_PAGING, 9, 1,
&wm9712_hpl_mixer_controls[0], ARRAY_SIZE(wm9712_hpl_mixer_controls),
mixer_event, SND_SOC_DAPM_POST_REG),
SND_SOC_DAPM_MIXER_E("Right HP Mixer", AC97_INT_PAGING, 8, 1,
&wm9712_hpr_mixer_controls[0], ARRAY_SIZE(wm9712_hpr_mixer_controls),
mixer_event, SND_SOC_DAPM_POST_REG),
SND_SOC_DAPM_MIXER("Phone Mixer", AC97_INT_PAGING, 6, 1,
&wm9712_phone_mixer_controls[0], ARRAY_SIZE(wm9712_phone_mixer_controls)),
SND_SOC_DAPM_MIXER("Speaker Mixer", AC97_INT_PAGING, 7, 1,
&wm9712_speaker_mixer_controls[0],
ARRAY_SIZE(wm9712_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", AC97_INT_PAGING, 14, 1),
SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", AC97_INT_PAGING, 13, 1),
SND_SOC_DAPM_DAC("Aux DAC", "Aux Playback", SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture", AC97_INT_PAGING, 12, 1),
SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture", AC97_INT_PAGING, 11, 1),
SND_SOC_DAPM_PGA("Headphone PGA", AC97_INT_PAGING, 4, 1, NULL, 0),
SND_SOC_DAPM_PGA("Speaker PGA", AC97_INT_PAGING, 3, 1, NULL, 0),
SND_SOC_DAPM_PGA("Out 3 PGA", AC97_INT_PAGING, 5, 1, NULL, 0),
SND_SOC_DAPM_PGA("Line PGA", AC97_INT_PAGING, 2, 1, NULL, 0),
SND_SOC_DAPM_PGA("Phone PGA", AC97_INT_PAGING, 1, 1, NULL, 0),
SND_SOC_DAPM_PGA("Mic PGA", AC97_INT_PAGING, 0, 1, NULL, 0),
SND_SOC_DAPM_MICBIAS("Mic Bias", AC97_INT_PAGING, 10, 1),
SND_SOC_DAPM_OUTPUT("MONOOUT"),
SND_SOC_DAPM_OUTPUT("HPOUTL"),
SND_SOC_DAPM_OUTPUT("HPOUTR"),
SND_SOC_DAPM_OUTPUT("LOUT2"),
SND_SOC_DAPM_OUTPUT("ROUT2"),
SND_SOC_DAPM_OUTPUT("OUT3"),
SND_SOC_DAPM_INPUT("LINEINL"),
SND_SOC_DAPM_INPUT("LINEINR"),
SND_SOC_DAPM_INPUT("PHONE"),
SND_SOC_DAPM_INPUT("PCBEEP"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
};
static const struct snd_soc_dapm_route audio_map[] = {
/* virtual mixer - mixes left & right channels for spk and mono */
{"AC97 Mixer", NULL, "Left DAC"},
{"AC97 Mixer", NULL, "Right DAC"},
/* Left HP mixer */
{"Left HP Mixer", "PCBeep Bypass Switch", "PCBEEP"},
{"Left HP Mixer", "Aux Playback Switch", "Aux DAC"},
{"Left HP Mixer", "Phone Bypass Switch", "Phone PGA"},
{"Left HP Mixer", "Line Bypass Switch", "Line PGA"},
{"Left HP Mixer", "PCM Playback Switch", "Left DAC"},
{"Left HP Mixer", "Mic Sidetone Switch", "Mic PGA"},
{"Left HP Mixer", NULL, "ALC Sidetone Mux"},
/* Right HP mixer */
{"Right HP Mixer", "PCBeep Bypass Switch", "PCBEEP"},
{"Right HP Mixer", "Aux Playback Switch", "Aux DAC"},
{"Right HP Mixer", "Phone Bypass Switch", "Phone PGA"},
{"Right HP Mixer", "Line Bypass Switch", "Line PGA"},
{"Right HP Mixer", "PCM Playback Switch", "Right DAC"},
{"Right HP Mixer", "Mic Sidetone Switch", "Mic PGA"},
{"Right HP Mixer", NULL, "ALC Sidetone Mux"},
/* speaker mixer */
{"Speaker Mixer", "PCBeep Bypass Switch", "PCBEEP"},
{"Speaker Mixer", "Line Bypass Switch", "Line PGA"},
{"Speaker Mixer", "PCM Playback Switch", "AC97 Mixer"},
{"Speaker Mixer", "Phone Bypass Switch", "Phone PGA"},
{"Speaker Mixer", "Aux Playback Switch", "Aux DAC"},
/* Phone mixer */
{"Phone Mixer", "PCBeep Bypass Switch", "PCBEEP"},
{"Phone Mixer", "Line Bypass Switch", "Line PGA"},
{"Phone Mixer", "Aux Playback Switch", "Aux DAC"},
{"Phone Mixer", "PCM Playback Switch", "AC97 Mixer"},
{"Phone Mixer", "Mic 1 Sidetone Switch", "Mic PGA"},
{"Phone Mixer", "Mic 2 Sidetone Switch", "Mic PGA"},
/* inputs */
{"Line PGA", NULL, "LINEINL"},
{"Line PGA", NULL, "LINEINR"},
{"Phone PGA", NULL, "PHONE"},
{"Mic PGA", NULL, "MIC1"},
{"Mic PGA", NULL, "MIC2"},
/* left capture selector */
{"Left Capture Select", "Mic", "MIC1"},
{"Left Capture Select", "Speaker Mixer", "Speaker Mixer"},
{"Left Capture Select", "Line", "LINEINL"},
{"Left Capture Select", "Headphone Mixer", "Left HP Mixer"},
{"Left Capture Select", "Phone Mixer", "Phone Mixer"},
{"Left Capture Select", "Phone", "PHONE"},
/* right capture selector */
{"Right Capture Select", "Mic", "MIC2"},
{"Right Capture Select", "Speaker Mixer", "Speaker Mixer"},
{"Right Capture Select", "Line", "LINEINR"},
{"Right Capture Select", "Headphone Mixer", "Right HP Mixer"},
{"Right Capture Select", "Phone Mixer", "Phone Mixer"},
{"Right Capture Select", "Phone", "PHONE"},
/* ALC Sidetone */
{"ALC Sidetone Mux", "Stereo", "Left Capture Select"},
{"ALC Sidetone Mux", "Stereo", "Right Capture Select"},
{"ALC Sidetone Mux", "Left", "Left Capture Select"},
{"ALC Sidetone Mux", "Right", "Right Capture Select"},
/* ADC's */
{"Left ADC", NULL, "Left Capture Select"},
{"Right ADC", NULL, "Right Capture Select"},
/* outputs */
{"MONOOUT", NULL, "Phone Mixer"},
{"HPOUTL", NULL, "Headphone PGA"},
{"Headphone PGA", NULL, "Left HP Mixer"},
{"HPOUTR", NULL, "Headphone PGA"},
{"Headphone PGA", NULL, "Right HP Mixer"},
/* mono mixer */
{"Mono Mixer", NULL, "Left HP Mixer"},
{"Mono Mixer", NULL, "Right HP Mixer"},
/* Out3 Mux */
{"Out3 Mux", "Left", "Left HP Mixer"},
{"Out3 Mux", "Mono", "Phone Mixer"},
{"Out3 Mux", "Left + Right", "Mono Mixer"},
{"Out 3 PGA", NULL, "Out3 Mux"},
{"OUT3", NULL, "Out 3 PGA"},
/* speaker Mux */
{"Speaker Mux", "Speaker Mix", "Speaker Mixer"},
{"Speaker Mux", "Headphone Mix", "Mono Mixer"},
{"Speaker PGA", NULL, "Speaker Mux"},
{"LOUT2", NULL, "Speaker PGA"},
{"ROUT2", NULL, "Speaker PGA"},
};
static int wm9712_add_widgets(struct snd_soc_codec *codec)
{
snd_soc_dapm_new_controls(codec, wm9712_dapm_widgets,
ARRAY_SIZE(wm9712_dapm_widgets));
snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
snd_soc_dapm_new_widgets(codec);
return 0;
}
static unsigned int ac97_read(struct snd_soc_codec *codec,
unsigned int reg)
{
u16 *cache = codec->reg_cache;
if (reg == AC97_RESET || reg == AC97_GPIO_STATUS ||
reg == AC97_VENDOR_ID1 || reg == AC97_VENDOR_ID2 ||
reg == AC97_REC_GAIN)
return soc_ac97_ops.read(codec->ac97, reg);
else {
reg = reg >> 1;
if (reg >= (ARRAY_SIZE(wm9712_reg)))
return -EIO;
return cache[reg];
}
}
static int ac97_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int val)
{
u16 *cache = codec->reg_cache;
if (reg < 0x7c)
soc_ac97_ops.write(codec->ac97, reg, val);
reg = reg >> 1;
if (reg < (ARRAY_SIZE(wm9712_reg)))
cache[reg] = val;
return 0;
}
static int ac97_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
int reg;
u16 vra;
vra = ac97_read(codec, AC97_EXTENDED_STATUS);
ac97_write(codec, AC97_EXTENDED_STATUS, vra | 0x1);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = AC97_PCM_FRONT_DAC_RATE;
else
reg = AC97_PCM_LR_ADC_RATE;
return ac97_write(codec, reg, runtime->rate);
}
static int ac97_aux_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_device *socdev = rtd->socdev;
struct snd_soc_codec *codec = socdev->card->codec;
u16 vra, xsle;
vra = ac97_read(codec, AC97_EXTENDED_STATUS);
ac97_write(codec, AC97_EXTENDED_STATUS, vra | 0x1);
xsle = ac97_read(codec, AC97_PCI_SID);
ac97_write(codec, AC97_PCI_SID, xsle | 0x8000);
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
return -ENODEV;
return ac97_write(codec, AC97_PCM_SURR_DAC_RATE, runtime->rate);
}
#define WM9712_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 |\
SNDRV_PCM_RATE_48000)
static struct snd_soc_dai_ops wm9712_dai_ops_hifi = {
.prepare = ac97_prepare,
};
static struct snd_soc_dai_ops wm9712_dai_ops_aux = {
.prepare = ac97_aux_prepare,
};
struct snd_soc_dai wm9712_dai[] = {
{
.name = "AC97 HiFi",
.ac97_control = 1,
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = WM9712_AC97_RATES,
.formats = SND_SOC_STD_AC97_FMTS,},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = WM9712_AC97_RATES,
.formats = SND_SOC_STD_AC97_FMTS,},
.ops = &wm9712_dai_ops_hifi,
},
{
.name = "AC97 Aux",
.playback = {
.stream_name = "Aux Playback",
.channels_min = 1,
.channels_max = 1,
.rates = WM9712_AC97_RATES,
.formats = SND_SOC_STD_AC97_FMTS,},
.ops = &wm9712_dai_ops_aux,
}
};
EXPORT_SYMBOL_GPL(wm9712_dai);
static int wm9712_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
ac97_write(codec, AC97_POWERDOWN, 0x0000);
break;
case SND_SOC_BIAS_OFF:
/* disable everything including AC link */
ac97_write(codec, AC97_EXTENDED_MSTATUS, 0xffff);
ac97_write(codec, AC97_POWERDOWN, 0xffff);
break;
}
codec->bias_level = level;
return 0;
}
static int wm9712_reset(struct snd_soc_codec *codec, int try_warm)
{
if (try_warm && soc_ac97_ops.warm_reset) {
soc_ac97_ops.warm_reset(codec->ac97);
if (ac97_read(codec, 0) == wm9712_reg[0])
return 1;
}
soc_ac97_ops.reset(codec->ac97);
if (soc_ac97_ops.warm_reset)
soc_ac97_ops.warm_reset(codec->ac97);
if (ac97_read(codec, 0) != wm9712_reg[0])
goto err;
return 0;
err:
printk(KERN_ERR "WM9712 AC97 reset failed\n");
return -EIO;
}
static int wm9712_soc_suspend(struct platform_device *pdev,
pm_message_t state)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
wm9712_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int wm9712_soc_resume(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
int i, ret;
u16 *cache = codec->reg_cache;
ret = wm9712_reset(codec, 1);
if (ret < 0) {
printk(KERN_ERR "could not reset AC97 codec\n");
return ret;
}
wm9712_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
if (ret == 0) {
/* Sync reg_cache with the hardware after cold reset */
for (i = 2; i < ARRAY_SIZE(wm9712_reg) << 1; i += 2) {
if (i == AC97_INT_PAGING || i == AC97_POWERDOWN ||
(i > 0x58 && i != 0x5c))
continue;
soc_ac97_ops.write(codec->ac97, i, cache[i>>1]);
}
}
if (codec->suspend_bias_level == SND_SOC_BIAS_ON)
wm9712_set_bias_level(codec, SND_SOC_BIAS_ON);
return ret;
}
static int wm9712_soc_probe(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec;
int ret = 0;
printk(KERN_INFO "WM9711/WM9712 SoC Audio Codec %s\n", WM9712_VERSION);
socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec),
GFP_KERNEL);
if (socdev->card->codec == NULL)
return -ENOMEM;
codec = socdev->card->codec;
mutex_init(&codec->mutex);
codec->reg_cache = kmemdup(wm9712_reg, sizeof(wm9712_reg), GFP_KERNEL);
if (codec->reg_cache == NULL) {
ret = -ENOMEM;
goto cache_err;
}
codec->reg_cache_size = sizeof(wm9712_reg);
codec->reg_cache_step = 2;
codec->name = "WM9712";
codec->owner = THIS_MODULE;
codec->dai = wm9712_dai;
codec->num_dai = ARRAY_SIZE(wm9712_dai);
codec->write = ac97_write;
codec->read = ac97_read;
codec->set_bias_level = wm9712_set_bias_level;
INIT_LIST_HEAD(&codec->dapm_widgets);
INIT_LIST_HEAD(&codec->dapm_paths);
ret = snd_soc_new_ac97_codec(codec, &soc_ac97_ops, 0);
if (ret < 0) {
printk(KERN_ERR "wm9712: failed to register AC97 codec\n");
goto codec_err;
}
/* register pcms */
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
if (ret < 0)
goto pcm_err;
ret = wm9712_reset(codec, 0);
if (ret < 0) {
printk(KERN_ERR "Failed to reset WM9712: AC97 link error\n");
goto reset_err;
}
/* set alc mux to none */
ac97_write(codec, AC97_VIDEO, ac97_read(codec, AC97_VIDEO) | 0x3000);
wm9712_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
snd_soc_add_controls(codec, wm9712_snd_ac97_controls,
ARRAY_SIZE(wm9712_snd_ac97_controls));
wm9712_add_widgets(codec);
ret = snd_soc_init_card(socdev);
if (ret < 0) {
printk(KERN_ERR "wm9712: failed to register card\n");
goto reset_err;
}
return 0;
reset_err:
snd_soc_free_pcms(socdev);
pcm_err:
snd_soc_free_ac97_codec(codec);
codec_err:
kfree(codec->reg_cache);
cache_err:
kfree(socdev->card->codec);
socdev->card->codec = NULL;
return ret;
}
static int wm9712_soc_remove(struct platform_device *pdev)
{
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
struct snd_soc_codec *codec = socdev->card->codec;
if (codec == NULL)
return 0;
snd_soc_dapm_free(socdev);
snd_soc_free_pcms(socdev);
snd_soc_free_ac97_codec(codec);
kfree(codec->reg_cache);
kfree(codec);
return 0;
}
struct snd_soc_codec_device soc_codec_dev_wm9712 = {
.probe = wm9712_soc_probe,
.remove = wm9712_soc_remove,
.suspend = wm9712_soc_suspend,
.resume = wm9712_soc_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_wm9712);
MODULE_DESCRIPTION("ASoC WM9711/WM9712 driver");
MODULE_AUTHOR("Liam Girdwood");
MODULE_LICENSE("GPL");

14
kernel/sound/soc/codecs/wm9712.h Normal file
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/*
* wm9712.h -- WM9712 Soc Audio driver
*/
#ifndef _WM9712_H
#define _WM9712_H
#define WM9712_DAI_AC97_HIFI 0
#define WM9712_DAI_AC97_AUX 1
extern struct snd_soc_dai wm9712_dai[2];
extern struct snd_soc_codec_device soc_codec_dev_wm9712;
#endif

1300
kernel/sound/soc/codecs/wm9713.c Normal file
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File diff suppressed because it is too large Load Diff

53
kernel/sound/soc/codecs/wm9713.h Normal file
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@@ -0,0 +1,53 @@
/*
* wm9713.h -- WM9713 Soc Audio driver
*/
#ifndef _WM9713_H
#define _WM9713_H
/* clock inputs */
#define WM9713_CLKA_PIN 0
#define WM9713_CLKB_PIN 1
/* clock divider ID's */
#define WM9713_PCMCLK_DIV 0
#define WM9713_CLKA_MULT 1
#define WM9713_CLKB_MULT 2
#define WM9713_HIFI_DIV 3
#define WM9713_PCMBCLK_DIV 4
#define WM9713_PCMCLK_PLL_DIV 5
#define WM9713_HIFI_PLL_DIV 6
/* Calculate the appropriate bit mask for the external PCM clock divider */
#define WM9713_PCMDIV(x) ((x - 1) << 8)
/* Calculate the appropriate bit mask for the external HiFi clock divider */
#define WM9713_HIFIDIV(x) ((x - 1) << 12)
/* MCLK clock mulitipliers */
#define WM9713_CLKA_X1 (0 << 1)
#define WM9713_CLKA_X2 (1 << 1)
#define WM9713_CLKB_X1 (0 << 2)
#define WM9713_CLKB_X2 (1 << 2)
/* MCLK clock MUX */
#define WM9713_CLK_MUX_A (0 << 0)
#define WM9713_CLK_MUX_B (1 << 0)
/* Voice DAI BCLK divider */
#define WM9713_PCMBCLK_DIV_1 (0 << 9)
#define WM9713_PCMBCLK_DIV_2 (1 << 9)
#define WM9713_PCMBCLK_DIV_4 (2 << 9)
#define WM9713_PCMBCLK_DIV_8 (3 << 9)
#define WM9713_PCMBCLK_DIV_16 (4 << 9)
#define WM9713_DAI_AC97_HIFI 0
#define WM9713_DAI_AC97_AUX 1
#define WM9713_DAI_PCM_VOICE 2
extern struct snd_soc_codec_device soc_codec_dev_wm9713;
extern struct snd_soc_dai wm9713_dai[3];
int wm9713_reset(struct snd_soc_codec *codec, int try_warm);
#endif

747
kernel/sound/soc/codecs/wm_hubs.c Normal file
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/*
* wm_hubs.c -- WM8993/4 common code
*
* Copyright 2009 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8993.h"
#include "wm_hubs.h"
const DECLARE_TLV_DB_SCALE(wm_hubs_spkmix_tlv, -300, 300, 0);
EXPORT_SYMBOL_GPL(wm_hubs_spkmix_tlv);
static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1650, 150, 0);
static const DECLARE_TLV_DB_SCALE(inmix_sw_tlv, 0, 3000, 0);
static const DECLARE_TLV_DB_SCALE(inmix_tlv, -1500, 300, 1);
static const DECLARE_TLV_DB_SCALE(earpiece_tlv, -600, 600, 0);
static const DECLARE_TLV_DB_SCALE(outmix_tlv, -2100, 300, 0);
static const DECLARE_TLV_DB_SCALE(spkmixout_tlv, -1800, 600, 1);
static const DECLARE_TLV_DB_SCALE(outpga_tlv, -5700, 100, 0);
static const unsigned int spkboost_tlv[] = {
TLV_DB_RANGE_HEAD(7),
0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
};
static const DECLARE_TLV_DB_SCALE(line_tlv, -600, 600, 0);
static const char *speaker_ref_text[] = {
"SPKVDD/2",
"VMID",
};
static const struct soc_enum speaker_ref =
SOC_ENUM_SINGLE(WM8993_SPEAKER_MIXER, 8, 2, speaker_ref_text);
static const char *speaker_mode_text[] = {
"Class D",
"Class AB",
};
static const struct soc_enum speaker_mode =
SOC_ENUM_SINGLE(WM8993_SPKMIXR_ATTENUATION, 8, 2, speaker_mode_text);
static void wait_for_dc_servo(struct snd_soc_codec *codec)
{
unsigned int reg;
int count = 0;
dev_dbg(codec->dev, "Waiting for DC servo...\n");
do {
count++;
msleep(1);
reg = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_0);
dev_dbg(codec->dev, "DC servo status: %x\n", reg);
} while ((reg & WM8993_DCS_CAL_COMPLETE_MASK)
!= WM8993_DCS_CAL_COMPLETE_MASK && count < 1000);
if ((reg & WM8993_DCS_CAL_COMPLETE_MASK)
!= WM8993_DCS_CAL_COMPLETE_MASK)
dev_err(codec->dev, "Timed out waiting for DC Servo\n");
}
/*
* Update the DC servo calibration on gain changes
*/
static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
int ret;
ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
/* Only need to do this if the outputs are active */
if (snd_soc_read(codec, WM8993_POWER_MANAGEMENT_1)
& (WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA))
snd_soc_update_bits(codec,
WM8993_DC_SERVO_0,
WM8993_DCS_TRIG_SINGLE_0 |
WM8993_DCS_TRIG_SINGLE_1,
WM8993_DCS_TRIG_SINGLE_0 |
WM8993_DCS_TRIG_SINGLE_1);
return ret;
}
static const struct snd_kcontrol_new analogue_snd_controls[] = {
SOC_SINGLE_TLV("IN1L Volume", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
inpga_tlv),
SOC_SINGLE("IN1L Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
SOC_SINGLE("IN1L ZC Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 0),
SOC_SINGLE_TLV("IN1R Volume", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
inpga_tlv),
SOC_SINGLE("IN1R Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
SOC_SINGLE("IN1R ZC Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 0),
SOC_SINGLE_TLV("IN2L Volume", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
inpga_tlv),
SOC_SINGLE("IN2L Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
SOC_SINGLE("IN2L ZC Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 0),
SOC_SINGLE_TLV("IN2R Volume", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
inpga_tlv),
SOC_SINGLE("IN2R Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
SOC_SINGLE("IN2R ZC Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 0),
SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8993_INPUT_MIXER3, 7, 1, 0,
inmix_sw_tlv),
SOC_SINGLE_TLV("MIXINL IN1L Volume", WM8993_INPUT_MIXER3, 4, 1, 0,
inmix_sw_tlv),
SOC_SINGLE_TLV("MIXINL Output Record Volume", WM8993_INPUT_MIXER3, 0, 7, 0,
inmix_tlv),
SOC_SINGLE_TLV("MIXINL IN1LP Volume", WM8993_INPUT_MIXER5, 6, 7, 0, inmix_tlv),
SOC_SINGLE_TLV("MIXINL Direct Voice Volume", WM8993_INPUT_MIXER5, 0, 6, 0,
inmix_tlv),
SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8993_INPUT_MIXER4, 7, 1, 0,
inmix_sw_tlv),
SOC_SINGLE_TLV("MIXINR IN1R Volume", WM8993_INPUT_MIXER4, 4, 1, 0,
inmix_sw_tlv),
SOC_SINGLE_TLV("MIXINR Output Record Volume", WM8993_INPUT_MIXER4, 0, 7, 0,
inmix_tlv),
SOC_SINGLE_TLV("MIXINR IN1RP Volume", WM8993_INPUT_MIXER6, 6, 7, 0, inmix_tlv),
SOC_SINGLE_TLV("MIXINR Direct Voice Volume", WM8993_INPUT_MIXER6, 0, 6, 0,
inmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer IN2RN Volume", WM8993_OUTPUT_MIXER5, 6, 7, 1,
outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer IN2LN Volume", WM8993_OUTPUT_MIXER3, 6, 7, 1,
outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer IN2LP Volume", WM8993_OUTPUT_MIXER3, 9, 7, 1,
outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer IN1L Volume", WM8993_OUTPUT_MIXER3, 0, 7, 1,
outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer IN1R Volume", WM8993_OUTPUT_MIXER3, 3, 7, 1,
outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer Right Input Volume",
WM8993_OUTPUT_MIXER5, 3, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer Left Input Volume",
WM8993_OUTPUT_MIXER5, 0, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Left Output Mixer DAC Volume", WM8993_OUTPUT_MIXER5, 9, 7, 1,
outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer IN2LN Volume",
WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer IN2RN Volume",
WM8993_OUTPUT_MIXER4, 6, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer IN1L Volume",
WM8993_OUTPUT_MIXER4, 3, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer IN1R Volume",
WM8993_OUTPUT_MIXER4, 0, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer IN2RP Volume",
WM8993_OUTPUT_MIXER4, 9, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer Left Input Volume",
WM8993_OUTPUT_MIXER6, 3, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer Right Input Volume",
WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
SOC_SINGLE_TLV("Right Output Mixer DAC Volume",
WM8993_OUTPUT_MIXER6, 9, 7, 1, outmix_tlv),
SOC_DOUBLE_R_TLV("Output Volume", WM8993_LEFT_OPGA_VOLUME,
WM8993_RIGHT_OPGA_VOLUME, 0, 63, 0, outpga_tlv),
SOC_DOUBLE_R("Output Switch", WM8993_LEFT_OPGA_VOLUME,
WM8993_RIGHT_OPGA_VOLUME, 6, 1, 0),
SOC_DOUBLE_R("Output ZC Switch", WM8993_LEFT_OPGA_VOLUME,
WM8993_RIGHT_OPGA_VOLUME, 7, 1, 0),
SOC_SINGLE("Earpiece Switch", WM8993_HPOUT2_VOLUME, 5, 1, 1),
SOC_SINGLE_TLV("Earpiece Volume", WM8993_HPOUT2_VOLUME, 4, 1, 1, earpiece_tlv),
SOC_SINGLE_TLV("SPKL Input Volume", WM8993_SPKMIXL_ATTENUATION,
5, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKL IN1LP Volume", WM8993_SPKMIXL_ATTENUATION,
4, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKL Output Volume", WM8993_SPKMIXL_ATTENUATION,
3, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKR Input Volume", WM8993_SPKMIXR_ATTENUATION,
5, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKR IN1RP Volume", WM8993_SPKMIXR_ATTENUATION,
4, 1, 1, wm_hubs_spkmix_tlv),
SOC_SINGLE_TLV("SPKR Output Volume", WM8993_SPKMIXR_ATTENUATION,
3, 1, 1, wm_hubs_spkmix_tlv),
SOC_DOUBLE_R_TLV("Speaker Mixer Volume",
WM8993_SPKMIXL_ATTENUATION, WM8993_SPKMIXR_ATTENUATION,
0, 3, 1, spkmixout_tlv),
SOC_DOUBLE_R_TLV("Speaker Volume",
WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
0, 63, 0, outpga_tlv),
SOC_DOUBLE_R("Speaker Switch",
WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
6, 1, 0),
SOC_DOUBLE_R("Speaker ZC Switch",
WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
7, 1, 0),
SOC_DOUBLE_TLV("Speaker Boost Volume", WM8993_SPKOUT_BOOST, 0, 3, 7, 0,
spkboost_tlv),
SOC_ENUM("Speaker Reference", speaker_ref),
SOC_ENUM("Speaker Mode", speaker_mode),
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Headphone Volume",
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
SNDRV_CTL_ELEM_ACCESS_READWRITE,
.tlv.p = outpga_tlv,
.info = snd_soc_info_volsw_2r,
.get = snd_soc_get_volsw_2r, .put = wm8993_put_dc_servo,
.private_value = (unsigned long)&(struct soc_mixer_control) {
.reg = WM8993_LEFT_OUTPUT_VOLUME,
.rreg = WM8993_RIGHT_OUTPUT_VOLUME,
.shift = 0, .max = 63
},
},
SOC_DOUBLE_R("Headphone Switch", WM8993_LEFT_OUTPUT_VOLUME,
WM8993_RIGHT_OUTPUT_VOLUME, 6, 1, 0),
SOC_DOUBLE_R("Headphone ZC Switch", WM8993_LEFT_OUTPUT_VOLUME,
WM8993_RIGHT_OUTPUT_VOLUME, 7, 1, 0),
SOC_SINGLE("LINEOUT1N Switch", WM8993_LINE_OUTPUTS_VOLUME, 6, 1, 1),
SOC_SINGLE("LINEOUT1P Switch", WM8993_LINE_OUTPUTS_VOLUME, 5, 1, 1),
SOC_SINGLE_TLV("LINEOUT1 Volume", WM8993_LINE_OUTPUTS_VOLUME, 4, 1, 1,
line_tlv),
SOC_SINGLE("LINEOUT2N Switch", WM8993_LINE_OUTPUTS_VOLUME, 2, 1, 1),
SOC_SINGLE("LINEOUT2P Switch", WM8993_LINE_OUTPUTS_VOLUME, 1, 1, 1),
SOC_SINGLE_TLV("LINEOUT2 Volume", WM8993_LINE_OUTPUTS_VOLUME, 0, 1, 1,
line_tlv),
};
static int hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
unsigned int reg = snd_soc_read(codec, WM8993_ANALOGUE_HP_0);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
WM8993_CP_ENA, WM8993_CP_ENA);
msleep(5);
snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA);
reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY;
snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
/* Start the DC servo */
snd_soc_update_bits(codec, WM8993_DC_SERVO_0,
0xFFFF,
WM8993_DCS_ENA_CHAN_0 |
WM8993_DCS_ENA_CHAN_1 |
WM8993_DCS_TRIG_STARTUP_1 |
WM8993_DCS_TRIG_STARTUP_0);
wait_for_dc_servo(codec);
reg |= WM8993_HPOUT1R_OUTP | WM8993_HPOUT1R_RMV_SHORT |
WM8993_HPOUT1L_OUTP | WM8993_HPOUT1L_RMV_SHORT;
snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
break;
case SND_SOC_DAPM_PRE_PMD:
reg &= ~(WM8993_HPOUT1L_RMV_SHORT |
WM8993_HPOUT1L_DLY |
WM8993_HPOUT1L_OUTP |
WM8993_HPOUT1R_RMV_SHORT |
WM8993_HPOUT1R_DLY |
WM8993_HPOUT1R_OUTP);
snd_soc_update_bits(codec, WM8993_DC_SERVO_0,
0xffff, 0);
snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
0);
snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
WM8993_CP_ENA, 0);
break;
}
return 0;
}
static int earpiece_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *control, int event)
{
struct snd_soc_codec *codec = w->codec;
u16 reg = snd_soc_read(codec, WM8993_ANTIPOP1) & ~WM8993_HPOUT2_IN_ENA;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
reg |= WM8993_HPOUT2_IN_ENA;
snd_soc_write(codec, WM8993_ANTIPOP1, reg);
udelay(50);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_write(codec, WM8993_ANTIPOP1, reg);
break;
default:
BUG();
break;
}
return 0;
}
static const struct snd_kcontrol_new in1l_pga[] = {
SOC_DAPM_SINGLE("IN1LP Switch", WM8993_INPUT_MIXER2, 5, 1, 0),
SOC_DAPM_SINGLE("IN1LN Switch", WM8993_INPUT_MIXER2, 4, 1, 0),
};
static const struct snd_kcontrol_new in1r_pga[] = {
SOC_DAPM_SINGLE("IN1RP Switch", WM8993_INPUT_MIXER2, 1, 1, 0),
SOC_DAPM_SINGLE("IN1RN Switch", WM8993_INPUT_MIXER2, 0, 1, 0),
};
static const struct snd_kcontrol_new in2l_pga[] = {
SOC_DAPM_SINGLE("IN2LP Switch", WM8993_INPUT_MIXER2, 7, 1, 0),
SOC_DAPM_SINGLE("IN2LN Switch", WM8993_INPUT_MIXER2, 6, 1, 0),
};
static const struct snd_kcontrol_new in2r_pga[] = {
SOC_DAPM_SINGLE("IN2RP Switch", WM8993_INPUT_MIXER2, 3, 1, 0),
SOC_DAPM_SINGLE("IN2RN Switch", WM8993_INPUT_MIXER2, 2, 1, 0),
};
static const struct snd_kcontrol_new mixinl[] = {
SOC_DAPM_SINGLE("IN2L Switch", WM8993_INPUT_MIXER3, 8, 1, 0),
SOC_DAPM_SINGLE("IN1L Switch", WM8993_INPUT_MIXER3, 5, 1, 0),
};
static const struct snd_kcontrol_new mixinr[] = {
SOC_DAPM_SINGLE("IN2R Switch", WM8993_INPUT_MIXER4, 8, 1, 0),
SOC_DAPM_SINGLE("IN1R Switch", WM8993_INPUT_MIXER4, 5, 1, 0),
};
static const struct snd_kcontrol_new left_output_mixer[] = {
SOC_DAPM_SINGLE("Right Input Switch", WM8993_OUTPUT_MIXER1, 7, 1, 0),
SOC_DAPM_SINGLE("Left Input Switch", WM8993_OUTPUT_MIXER1, 6, 1, 0),
SOC_DAPM_SINGLE("IN2RN Switch", WM8993_OUTPUT_MIXER1, 5, 1, 0),
SOC_DAPM_SINGLE("IN2LN Switch", WM8993_OUTPUT_MIXER1, 4, 1, 0),
SOC_DAPM_SINGLE("IN2LP Switch", WM8993_OUTPUT_MIXER1, 1, 1, 0),
SOC_DAPM_SINGLE("IN1R Switch", WM8993_OUTPUT_MIXER1, 3, 1, 0),
SOC_DAPM_SINGLE("IN1L Switch", WM8993_OUTPUT_MIXER1, 2, 1, 0),
SOC_DAPM_SINGLE("DAC Switch", WM8993_OUTPUT_MIXER1, 0, 1, 0),
};
static const struct snd_kcontrol_new right_output_mixer[] = {
SOC_DAPM_SINGLE("Left Input Switch", WM8993_OUTPUT_MIXER2, 7, 1, 0),
SOC_DAPM_SINGLE("Right Input Switch", WM8993_OUTPUT_MIXER2, 6, 1, 0),
SOC_DAPM_SINGLE("IN2LN Switch", WM8993_OUTPUT_MIXER2, 5, 1, 0),
SOC_DAPM_SINGLE("IN2RN Switch", WM8993_OUTPUT_MIXER2, 4, 1, 0),
SOC_DAPM_SINGLE("IN1L Switch", WM8993_OUTPUT_MIXER2, 3, 1, 0),
SOC_DAPM_SINGLE("IN1R Switch", WM8993_OUTPUT_MIXER2, 2, 1, 0),
SOC_DAPM_SINGLE("IN2RP Switch", WM8993_OUTPUT_MIXER2, 1, 1, 0),
SOC_DAPM_SINGLE("DAC Switch", WM8993_OUTPUT_MIXER2, 0, 1, 0),
};
static const struct snd_kcontrol_new earpiece_mixer[] = {
SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_HPOUT2_MIXER, 5, 1, 0),
SOC_DAPM_SINGLE("Left Output Switch", WM8993_HPOUT2_MIXER, 4, 1, 0),
SOC_DAPM_SINGLE("Right Output Switch", WM8993_HPOUT2_MIXER, 3, 1, 0),
};
static const struct snd_kcontrol_new left_speaker_boost[] = {
SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 5, 1, 0),
SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 4, 1, 0),
SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 3, 1, 0),
};
static const struct snd_kcontrol_new right_speaker_boost[] = {
SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 2, 1, 0),
SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 1, 1, 0),
SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 0, 1, 0),
};
static const struct snd_kcontrol_new line1_mix[] = {
SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER1, 2, 1, 0),
SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER1, 1, 1, 0),
SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
};
static const struct snd_kcontrol_new line1n_mix[] = {
SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 6, 1, 0),
SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER1, 5, 1, 0),
};
static const struct snd_kcontrol_new line1p_mix[] = {
SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
};
static const struct snd_kcontrol_new line2_mix[] = {
SOC_DAPM_SINGLE("IN2R Switch", WM8993_LINE_MIXER2, 2, 1, 0),
SOC_DAPM_SINGLE("IN2L Switch", WM8993_LINE_MIXER2, 1, 1, 0),
SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
};
static const struct snd_kcontrol_new line2n_mix[] = {
SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER2, 6, 1, 0),
SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 5, 1, 0),
};
static const struct snd_kcontrol_new line2p_mix[] = {
SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
};
static const struct snd_soc_dapm_widget analogue_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("IN1LN"),
SND_SOC_DAPM_INPUT("IN1LP"),
SND_SOC_DAPM_INPUT("IN2LN"),
SND_SOC_DAPM_INPUT("IN2LP/VXRN"),
SND_SOC_DAPM_INPUT("IN1RN"),
SND_SOC_DAPM_INPUT("IN1RP"),
SND_SOC_DAPM_INPUT("IN2RN"),
SND_SOC_DAPM_INPUT("IN2RP/VXRP"),
SND_SOC_DAPM_MICBIAS("MICBIAS2", WM8993_POWER_MANAGEMENT_1, 5, 0),
SND_SOC_DAPM_MICBIAS("MICBIAS1", WM8993_POWER_MANAGEMENT_1, 4, 0),
SND_SOC_DAPM_MIXER("IN1L PGA", WM8993_POWER_MANAGEMENT_2, 6, 0,
in1l_pga, ARRAY_SIZE(in1l_pga)),
SND_SOC_DAPM_MIXER("IN1R PGA", WM8993_POWER_MANAGEMENT_2, 4, 0,
in1r_pga, ARRAY_SIZE(in1r_pga)),
SND_SOC_DAPM_MIXER("IN2L PGA", WM8993_POWER_MANAGEMENT_2, 7, 0,
in2l_pga, ARRAY_SIZE(in2l_pga)),
SND_SOC_DAPM_MIXER("IN2R PGA", WM8993_POWER_MANAGEMENT_2, 5, 0,
in2r_pga, ARRAY_SIZE(in2r_pga)),
/* Dummy widgets to represent differential paths */
SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("MIXINL", WM8993_POWER_MANAGEMENT_2, 9, 0,
mixinl, ARRAY_SIZE(mixinl)),
SND_SOC_DAPM_MIXER("MIXINR", WM8993_POWER_MANAGEMENT_2, 8, 0,
mixinr, ARRAY_SIZE(mixinr)),
SND_SOC_DAPM_MIXER("Left Output Mixer", WM8993_POWER_MANAGEMENT_3, 5, 0,
left_output_mixer, ARRAY_SIZE(left_output_mixer)),
SND_SOC_DAPM_MIXER("Right Output Mixer", WM8993_POWER_MANAGEMENT_3, 4, 0,
right_output_mixer, ARRAY_SIZE(right_output_mixer)),
SND_SOC_DAPM_PGA("Left Output PGA", WM8993_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Output PGA", WM8993_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0,
NULL, 0,
hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
earpiece_mixer, ARRAY_SIZE(earpiece_mixer)),
SND_SOC_DAPM_PGA_E("Earpiece Driver", WM8993_POWER_MANAGEMENT_1, 11, 0,
NULL, 0, earpiece_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("SPKL Boost", SND_SOC_NOPM, 0, 0,
left_speaker_boost, ARRAY_SIZE(left_speaker_boost)),
SND_SOC_DAPM_MIXER("SPKR Boost", SND_SOC_NOPM, 0, 0,
right_speaker_boost, ARRAY_SIZE(right_speaker_boost)),
SND_SOC_DAPM_PGA("SPKL Driver", WM8993_POWER_MANAGEMENT_1, 12, 0,
NULL, 0),
SND_SOC_DAPM_PGA("SPKR Driver", WM8993_POWER_MANAGEMENT_1, 13, 0,
NULL, 0),
SND_SOC_DAPM_MIXER("LINEOUT1 Mixer", SND_SOC_NOPM, 0, 0,
line1_mix, ARRAY_SIZE(line1_mix)),
SND_SOC_DAPM_MIXER("LINEOUT2 Mixer", SND_SOC_NOPM, 0, 0,
line2_mix, ARRAY_SIZE(line2_mix)),
SND_SOC_DAPM_MIXER("LINEOUT1N Mixer", SND_SOC_NOPM, 0, 0,
line1n_mix, ARRAY_SIZE(line1n_mix)),
SND_SOC_DAPM_MIXER("LINEOUT1P Mixer", SND_SOC_NOPM, 0, 0,
line1p_mix, ARRAY_SIZE(line1p_mix)),
SND_SOC_DAPM_MIXER("LINEOUT2N Mixer", SND_SOC_NOPM, 0, 0,
line2n_mix, ARRAY_SIZE(line2n_mix)),
SND_SOC_DAPM_MIXER("LINEOUT2P Mixer", SND_SOC_NOPM, 0, 0,
line2p_mix, ARRAY_SIZE(line2p_mix)),
SND_SOC_DAPM_PGA("LINEOUT1N Driver", WM8993_POWER_MANAGEMENT_3, 13, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LINEOUT1P Driver", WM8993_POWER_MANAGEMENT_3, 12, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LINEOUT2N Driver", WM8993_POWER_MANAGEMENT_3, 11, 0,
NULL, 0),
SND_SOC_DAPM_PGA("LINEOUT2P Driver", WM8993_POWER_MANAGEMENT_3, 10, 0,
NULL, 0),
SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
SND_SOC_DAPM_OUTPUT("HPOUT1L"),
SND_SOC_DAPM_OUTPUT("HPOUT1R"),
SND_SOC_DAPM_OUTPUT("HPOUT2P"),
SND_SOC_DAPM_OUTPUT("HPOUT2N"),
SND_SOC_DAPM_OUTPUT("LINEOUT1P"),
SND_SOC_DAPM_OUTPUT("LINEOUT1N"),
SND_SOC_DAPM_OUTPUT("LINEOUT2P"),
SND_SOC_DAPM_OUTPUT("LINEOUT2N"),
};
static const struct snd_soc_dapm_route analogue_routes[] = {
{ "IN1L PGA", "IN1LP Switch", "IN1LP" },
{ "IN1L PGA", "IN1LN Switch", "IN1LN" },
{ "IN1R PGA", "IN1RP Switch", "IN1RP" },
{ "IN1R PGA", "IN1RN Switch", "IN1RN" },
{ "IN2L PGA", "IN2LP Switch", "IN2LP/VXRN" },
{ "IN2L PGA", "IN2LN Switch", "IN2LN" },
{ "IN2R PGA", "IN2RP Switch", "IN2RP/VXRP" },
{ "IN2R PGA", "IN2RN Switch", "IN2RN" },
{ "Direct Voice", NULL, "IN2LP/VXRN" },
{ "Direct Voice", NULL, "IN2RP/VXRP" },
{ "MIXINL", "IN1L Switch", "IN1L PGA" },
{ "MIXINL", "IN2L Switch", "IN2L PGA" },
{ "MIXINL", NULL, "Direct Voice" },
{ "MIXINL", NULL, "IN1LP" },
{ "MIXINL", NULL, "Left Output Mixer" },
{ "MIXINR", "IN1R Switch", "IN1R PGA" },
{ "MIXINR", "IN2R Switch", "IN2R PGA" },
{ "MIXINR", NULL, "Direct Voice" },
{ "MIXINR", NULL, "IN1RP" },
{ "MIXINR", NULL, "Right Output Mixer" },
{ "ADCL", NULL, "MIXINL" },
{ "ADCR", NULL, "MIXINR" },
{ "Left Output Mixer", "Left Input Switch", "MIXINL" },
{ "Left Output Mixer", "Right Input Switch", "MIXINR" },
{ "Left Output Mixer", "IN2RN Switch", "IN2RN" },
{ "Left Output Mixer", "IN2LN Switch", "IN2LN" },
{ "Left Output Mixer", "IN2LP Switch", "IN2LP/VXRN" },
{ "Left Output Mixer", "IN1L Switch", "IN1L PGA" },
{ "Left Output Mixer", "IN1R Switch", "IN1R PGA" },
{ "Right Output Mixer", "Left Input Switch", "MIXINL" },
{ "Right Output Mixer", "Right Input Switch", "MIXINR" },
{ "Right Output Mixer", "IN2LN Switch", "IN2LN" },
{ "Right Output Mixer", "IN2RN Switch", "IN2RN" },
{ "Right Output Mixer", "IN2RP Switch", "IN2RP/VXRP" },
{ "Right Output Mixer", "IN1L Switch", "IN1L PGA" },
{ "Right Output Mixer", "IN1R Switch", "IN1R PGA" },
{ "Left Output PGA", NULL, "Left Output Mixer" },
{ "Left Output PGA", NULL, "TOCLK" },
{ "Right Output PGA", NULL, "Right Output Mixer" },
{ "Right Output PGA", NULL, "TOCLK" },
{ "Earpiece Mixer", "Direct Voice Switch", "Direct Voice" },
{ "Earpiece Mixer", "Left Output Switch", "Left Output PGA" },
{ "Earpiece Mixer", "Right Output Switch", "Right Output PGA" },
{ "Earpiece Driver", NULL, "Earpiece Mixer" },
{ "HPOUT2N", NULL, "Earpiece Driver" },
{ "HPOUT2P", NULL, "Earpiece Driver" },
{ "SPKL", "Input Switch", "MIXINL" },
{ "SPKL", "IN1LP Switch", "IN1LP" },
{ "SPKL", "Output Switch", "Left Output PGA" },
{ "SPKL", NULL, "TOCLK" },
{ "SPKR", "Input Switch", "MIXINR" },
{ "SPKR", "IN1RP Switch", "IN1RP" },
{ "SPKR", "Output Switch", "Right Output PGA" },
{ "SPKR", NULL, "TOCLK" },
{ "SPKL Boost", "Direct Voice Switch", "Direct Voice" },
{ "SPKL Boost", "SPKL Switch", "SPKL" },
{ "SPKL Boost", "SPKR Switch", "SPKR" },
{ "SPKR Boost", "Direct Voice Switch", "Direct Voice" },
{ "SPKR Boost", "SPKR Switch", "SPKR" },
{ "SPKR Boost", "SPKL Switch", "SPKL" },
{ "SPKL Driver", NULL, "SPKL Boost" },
{ "SPKL Driver", NULL, "CLK_SYS" },
{ "SPKR Driver", NULL, "SPKR Boost" },
{ "SPKR Driver", NULL, "CLK_SYS" },
{ "SPKOUTLP", NULL, "SPKL Driver" },
{ "SPKOUTLN", NULL, "SPKL Driver" },
{ "SPKOUTRP", NULL, "SPKR Driver" },
{ "SPKOUTRN", NULL, "SPKR Driver" },
{ "Left Headphone Mux", "Mixer", "Left Output PGA" },
{ "Right Headphone Mux", "Mixer", "Right Output PGA" },
{ "Headphone PGA", NULL, "Left Headphone Mux" },
{ "Headphone PGA", NULL, "Right Headphone Mux" },
{ "Headphone PGA", NULL, "CLK_SYS" },
{ "HPOUT1L", NULL, "Headphone PGA" },
{ "HPOUT1R", NULL, "Headphone PGA" },
{ "LINEOUT1N", NULL, "LINEOUT1N Driver" },
{ "LINEOUT1P", NULL, "LINEOUT1P Driver" },
{ "LINEOUT2N", NULL, "LINEOUT2N Driver" },
{ "LINEOUT2P", NULL, "LINEOUT2P Driver" },
};
static const struct snd_soc_dapm_route lineout1_diff_routes[] = {
{ "LINEOUT1 Mixer", "IN1L Switch", "IN1L PGA" },
{ "LINEOUT1 Mixer", "IN1R Switch", "IN1R PGA" },
{ "LINEOUT1 Mixer", "Output Switch", "Left Output PGA" },
{ "LINEOUT1N Driver", NULL, "LINEOUT1 Mixer" },
{ "LINEOUT1P Driver", NULL, "LINEOUT1 Mixer" },
};
static const struct snd_soc_dapm_route lineout1_se_routes[] = {
{ "LINEOUT1N Mixer", "Left Output Switch", "Left Output PGA" },
{ "LINEOUT1N Mixer", "Right Output Switch", "Right Output PGA" },
{ "LINEOUT1P Mixer", "Left Output Switch", "Left Output PGA" },
{ "LINEOUT1N Driver", NULL, "LINEOUT1N Mixer" },
{ "LINEOUT1P Driver", NULL, "LINEOUT1P Mixer" },
};
static const struct snd_soc_dapm_route lineout2_diff_routes[] = {
{ "LINEOUT2 Mixer", "IN2L Switch", "IN2L PGA" },
{ "LINEOUT2 Mixer", "IN2R Switch", "IN2R PGA" },
{ "LINEOUT2 Mixer", "Output Switch", "Right Output PGA" },
{ "LINEOUT2N Driver", NULL, "LINEOUT2 Mixer" },
{ "LINEOUT2P Driver", NULL, "LINEOUT2 Mixer" },
};
static const struct snd_soc_dapm_route lineout2_se_routes[] = {
{ "LINEOUT2N Mixer", "Left Output Switch", "Left Output PGA" },
{ "LINEOUT2N Mixer", "Right Output Switch", "Right Output PGA" },
{ "LINEOUT2P Mixer", "Right Output Switch", "Right Output PGA" },
{ "LINEOUT2N Driver", NULL, "LINEOUT2N Mixer" },
{ "LINEOUT2P Driver", NULL, "LINEOUT2P Mixer" },
};
int wm_hubs_add_analogue_controls(struct snd_soc_codec *codec)
{
/* Latch volume update bits & default ZC on */
snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_1_2_VOLUME,
WM8993_IN1_VU, WM8993_IN1_VU);
snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_1_2_VOLUME,
WM8993_IN1_VU, WM8993_IN1_VU);
snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_3_4_VOLUME,
WM8993_IN2_VU, WM8993_IN2_VU);
snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_3_4_VOLUME,
WM8993_IN2_VU, WM8993_IN2_VU);
snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_LEFT,
WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_RIGHT,
WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
snd_soc_update_bits(codec, WM8993_LEFT_OUTPUT_VOLUME,
WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC,
WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC);
snd_soc_update_bits(codec, WM8993_RIGHT_OUTPUT_VOLUME,
WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC,
WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC);
snd_soc_update_bits(codec, WM8993_LEFT_OPGA_VOLUME,
WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU,
WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU);
snd_soc_update_bits(codec, WM8993_RIGHT_OPGA_VOLUME,
WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU,
WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU);
snd_soc_add_controls(codec, analogue_snd_controls,
ARRAY_SIZE(analogue_snd_controls));
snd_soc_dapm_new_controls(codec, analogue_dapm_widgets,
ARRAY_SIZE(analogue_dapm_widgets));
return 0;
}
EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_controls);
int wm_hubs_add_analogue_routes(struct snd_soc_codec *codec,
int lineout1_diff, int lineout2_diff)
{
snd_soc_dapm_add_routes(codec, analogue_routes,
ARRAY_SIZE(analogue_routes));
if (lineout1_diff)
snd_soc_dapm_add_routes(codec,
lineout1_diff_routes,
ARRAY_SIZE(lineout1_diff_routes));
else
snd_soc_dapm_add_routes(codec,
lineout1_se_routes,
ARRAY_SIZE(lineout1_se_routes));
if (lineout2_diff)
snd_soc_dapm_add_routes(codec,
lineout2_diff_routes,
ARRAY_SIZE(lineout2_diff_routes));
else
snd_soc_dapm_add_routes(codec,
lineout2_se_routes,
ARRAY_SIZE(lineout2_se_routes));
return 0;
}
EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_routes);
MODULE_DESCRIPTION("Shared support for Wolfson hubs products");
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
MODULE_LICENSE("GPL");

24
kernel/sound/soc/codecs/wm_hubs.h Normal file
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@@ -0,0 +1,24 @@
/*
* wm_hubs.h -- WM899x common code
*
* Copyright 2009 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM_HUBS_H
#define _WM_HUBS_H
struct snd_soc_codec;
extern const unsigned int wm_hubs_spkmix_tlv[];
extern int wm_hubs_add_analogue_controls(struct snd_soc_codec *);
extern int wm_hubs_add_analogue_routes(struct snd_soc_codec *, int, int);
#endif