779 lines
19 KiB
Plaintext
779 lines
19 KiB
Plaintext
comment "Processor Type"
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config CPU_32
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bool
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default y
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# Select CPU types depending on the architecture selected. This selects
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# which CPUs we support in the kernel image, and the compiler instruction
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# optimiser behaviour.
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# ARM610
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config CPU_ARM610
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bool "Support ARM610 processor" if ARCH_RPC
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select CPU_32v3
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select CPU_CACHE_V3
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V3 if MMU
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select CPU_TLB_V3 if MMU
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select CPU_PABRT_LEGACY
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help
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The ARM610 is the successor to the ARM3 processor
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and was produced by VLSI Technology Inc.
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Say Y if you want support for the ARM610 processor.
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Otherwise, say N.
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# ARM7TDMI
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config CPU_ARM7TDMI
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bool "Support ARM7TDMI processor"
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depends on !MMU
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select CPU_32v4T
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select CPU_ABRT_LV4T
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select CPU_PABRT_LEGACY
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select CPU_CACHE_V4
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help
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A 32-bit RISC microprocessor based on the ARM7 processor core
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which has no memory control unit and cache.
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Say Y if you want support for the ARM7TDMI processor.
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Otherwise, say N.
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# ARM710
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config CPU_ARM710
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bool "Support ARM710 processor" if ARCH_RPC
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select CPU_32v3
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select CPU_CACHE_V3
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V3 if MMU
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select CPU_TLB_V3 if MMU
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select CPU_PABRT_LEGACY
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help
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A 32-bit RISC microprocessor based on the ARM7 processor core
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designed by Advanced RISC Machines Ltd. The ARM710 is the
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successor to the ARM610 processor. It was released in
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July 1994 by VLSI Technology Inc.
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Say Y if you want support for the ARM710 processor.
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Otherwise, say N.
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# ARM720T
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config CPU_ARM720T
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bool "Support ARM720T processor" if ARCH_INTEGRATOR
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select CPU_32v4T
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select CPU_ABRT_LV4T
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select CPU_PABRT_LEGACY
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select CPU_CACHE_V4
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WT if MMU
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select CPU_TLB_V4WT if MMU
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help
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A 32-bit RISC processor with 8kByte Cache, Write Buffer and
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MMU built around an ARM7TDMI core.
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Say Y if you want support for the ARM720T processor.
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Otherwise, say N.
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# ARM740T
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config CPU_ARM740T
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bool "Support ARM740T processor" if ARCH_INTEGRATOR
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depends on !MMU
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select CPU_32v4T
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select CPU_ABRT_LV4T
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select CPU_PABRT_LEGACY
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select CPU_CACHE_V3 # although the core is v4t
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select CPU_CP15_MPU
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help
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A 32-bit RISC processor with 8KB cache or 4KB variants,
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write buffer and MPU(Protection Unit) built around
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an ARM7TDMI core.
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Say Y if you want support for the ARM740T processor.
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Otherwise, say N.
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# ARM9TDMI
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config CPU_ARM9TDMI
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bool "Support ARM9TDMI processor"
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depends on !MMU
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select CPU_32v4T
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select CPU_ABRT_NOMMU
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select CPU_PABRT_LEGACY
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select CPU_CACHE_V4
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help
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A 32-bit RISC microprocessor based on the ARM9 processor core
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which has no memory control unit and cache.
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Say Y if you want support for the ARM9TDMI processor.
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Otherwise, say N.
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# ARM920T
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config CPU_ARM920T
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bool "Support ARM920T processor" if ARCH_INTEGRATOR
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select CPU_32v4T
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select CPU_ABRT_EV4T
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select CPU_PABRT_LEGACY
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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The ARM920T is licensed to be produced by numerous vendors,
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and is used in the Cirrus EP93xx and the Samsung S3C2410.
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Say Y if you want support for the ARM920T processor.
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Otherwise, say N.
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# ARM922T
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config CPU_ARM922T
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bool "Support ARM922T processor" if ARCH_INTEGRATOR
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select CPU_32v4T
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select CPU_ABRT_EV4T
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select CPU_PABRT_LEGACY
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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The ARM922T is a version of the ARM920T, but with smaller
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instruction and data caches. It is used in Altera's
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Excalibur XA device family and Micrel's KS8695 Centaur.
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Say Y if you want support for the ARM922T processor.
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Otherwise, say N.
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# ARM925T
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config CPU_ARM925T
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bool "Support ARM925T processor" if ARCH_OMAP1
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select CPU_32v4T
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select CPU_ABRT_EV4T
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select CPU_PABRT_LEGACY
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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The ARM925T is a mix between the ARM920T and ARM926T, but with
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different instruction and data caches. It is used in TI's OMAP
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device family.
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Say Y if you want support for the ARM925T processor.
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Otherwise, say N.
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# ARM926T
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config CPU_ARM926T
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bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
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select CPU_32v5
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select CPU_ABRT_EV5TJ
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select CPU_PABRT_LEGACY
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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This is a variant of the ARM920. It has slightly different
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instruction sequences for cache and TLB operations. Curiously,
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there is no documentation on it at the ARM corporate website.
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Say Y if you want support for the ARM926T processor.
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Otherwise, say N.
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# FA526
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config CPU_FA526
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bool
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select CPU_32v4
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select CPU_ABRT_EV4
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select CPU_PABRT_LEGACY
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_CACHE_FA
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select CPU_COPY_FA if MMU
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select CPU_TLB_FA if MMU
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help
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The FA526 is a version of the ARMv4 compatible processor with
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Branch Target Buffer, Unified TLB and cache line size 16.
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Say Y if you want support for the FA526 processor.
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Otherwise, say N.
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# ARM940T
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config CPU_ARM940T
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bool "Support ARM940T processor" if ARCH_INTEGRATOR
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depends on !MMU
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select CPU_32v4T
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select CPU_ABRT_NOMMU
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select CPU_PABRT_LEGACY
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select CPU_CACHE_VIVT
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select CPU_CP15_MPU
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help
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ARM940T is a member of the ARM9TDMI family of general-
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purpose microprocessors with MPU and separate 4KB
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instruction and 4KB data cases, each with a 4-word line
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length.
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Say Y if you want support for the ARM940T processor.
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Otherwise, say N.
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# ARM946E-S
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config CPU_ARM946E
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bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
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depends on !MMU
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select CPU_32v5
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select CPU_ABRT_NOMMU
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select CPU_PABRT_LEGACY
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select CPU_CACHE_VIVT
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select CPU_CP15_MPU
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help
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ARM946E-S is a member of the ARM9E-S family of high-
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performance, 32-bit system-on-chip processor solutions.
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The TCM and ARMv5TE 32-bit instruction set is supported.
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Say Y if you want support for the ARM946E-S processor.
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Otherwise, say N.
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# ARM1020 - needs validating
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config CPU_ARM1020
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bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV4T
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select CPU_PABRT_LEGACY
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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The ARM1020 is the 32K cached version of the ARM10 processor,
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with an addition of a floating-point unit.
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Say Y if you want support for the ARM1020 processor.
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Otherwise, say N.
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# ARM1020E - needs validating
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config CPU_ARM1020E
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bool "Support ARM1020E processor" if ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV4T
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select CPU_PABRT_LEGACY
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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depends on n
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# ARM1022E
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config CPU_ARM1022
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bool "Support ARM1022E processor" if ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV4T
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select CPU_PABRT_LEGACY
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU # can probably do better
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select CPU_TLB_V4WBI if MMU
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help
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The ARM1022E is an implementation of the ARMv5TE architecture
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based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
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embedded trace macrocell, and a floating-point unit.
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Say Y if you want support for the ARM1022E processor.
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Otherwise, say N.
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# ARM1026EJ-S
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config CPU_ARM1026
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bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
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select CPU_PABRT_LEGACY
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU # can probably do better
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select CPU_TLB_V4WBI if MMU
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help
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The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
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based upon the ARM10 integer core.
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Say Y if you want support for the ARM1026EJ-S processor.
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Otherwise, say N.
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# SA110
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config CPU_SA110
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bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
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select CPU_32v3 if ARCH_RPC
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select CPU_32v4 if !ARCH_RPC
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select CPU_ABRT_EV4
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select CPU_PABRT_LEGACY
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select CPU_CACHE_V4WB
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WB if MMU
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help
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The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
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is available at five speeds ranging from 100 MHz to 233 MHz.
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More information is available at
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<http://developer.intel.com/design/strong/sa110.htm>.
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Say Y if you want support for the SA-110 processor.
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Otherwise, say N.
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# SA1100
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config CPU_SA1100
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bool
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select CPU_32v4
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select CPU_ABRT_EV4
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select CPU_PABRT_LEGACY
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select CPU_CACHE_V4WB
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_TLB_V4WB if MMU
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# XScale
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config CPU_XSCALE
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bool
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_PABRT_LEGACY
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_TLB_V4WBI if MMU
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# XScale Core Version 3
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config CPU_XSC3
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bool
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_PABRT_LEGACY
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_TLB_V4WBI if MMU
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select IO_36
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# Marvell PJ1 (Mohawk)
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config CPU_MOHAWK
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bool
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_PABRT_LEGACY
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_TLB_V4WBI if MMU
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select CPU_COPY_V4WB if MMU
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# Feroceon
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config CPU_FEROCEON
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bool
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_PABRT_LEGACY
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_FEROCEON if MMU
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select CPU_TLB_FEROCEON if MMU
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config CPU_FEROCEON_OLD_ID
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bool "Accept early Feroceon cores with an ARM926 ID"
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depends on CPU_FEROCEON && !CPU_ARM926T
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default y
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help
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This enables the usage of some old Feroceon cores
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for which the CPU ID is equal to the ARM926 ID.
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Relevant for Feroceon-1850 and early Feroceon-2850.
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# ARMv6
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config CPU_V6
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bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
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select CPU_32v6
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select CPU_ABRT_EV6
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select CPU_PABRT_V6
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select CPU_CACHE_V6
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select CPU_CACHE_VIPT
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select CPU_CP15_MMU
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select CPU_HAS_ASID if MMU
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select CPU_COPY_V6 if MMU
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select CPU_TLB_V6 if MMU
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# ARMv6k
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config CPU_32v6K
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bool "Support ARM V6K processor extensions" if !SMP
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depends on CPU_V6
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default y if SMP && !ARCH_MX3
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help
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Say Y here if your ARMv6 processor supports the 'K' extension.
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This enables the kernel to use some instructions not present
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on previous processors, and as such a kernel build with this
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enabled will not boot on processors with do not support these
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instructions.
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# ARMv7
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config CPU_V7
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bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
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select CPU_32v6K
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select CPU_32v7
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select CPU_ABRT_EV7
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select CPU_PABRT_V7
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select CPU_CACHE_V7
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select CPU_CACHE_VIPT
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select CPU_CP15_MMU
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select CPU_HAS_ASID if MMU
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select CPU_COPY_V6 if MMU
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select CPU_TLB_V7 if MMU
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# Figure out what processor architecture version we should be using.
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# This defines the compiler instruction set which depends on the machine type.
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config CPU_32v3
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bool
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select TLS_REG_EMUL if SMP || !MMU
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select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
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config CPU_32v4
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bool
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select TLS_REG_EMUL if SMP || !MMU
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select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
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config CPU_32v4T
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bool
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select TLS_REG_EMUL if SMP || !MMU
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select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
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config CPU_32v5
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bool
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select TLS_REG_EMUL if SMP || !MMU
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select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
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config CPU_32v6
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bool
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select TLS_REG_EMUL if !CPU_32v6K && !MMU
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config CPU_32v7
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bool
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# The abort model
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config CPU_ABRT_NOMMU
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bool
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config CPU_ABRT_EV4
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bool
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config CPU_ABRT_EV4T
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bool
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config CPU_ABRT_LV4T
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bool
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config CPU_ABRT_EV5T
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bool
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config CPU_ABRT_EV5TJ
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bool
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config CPU_ABRT_EV6
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bool
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config CPU_ABRT_EV7
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bool
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config CPU_PABRT_LEGACY
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bool
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config CPU_PABRT_V6
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bool
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config CPU_PABRT_V7
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bool
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# The cache model
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config CPU_CACHE_V3
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bool
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config CPU_CACHE_V4
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bool
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config CPU_CACHE_V4WT
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bool
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config CPU_CACHE_V4WB
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bool
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config CPU_CACHE_V6
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bool
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config CPU_CACHE_V7
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bool
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config CPU_CACHE_VIVT
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bool
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config CPU_CACHE_VIPT
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bool
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config CPU_CACHE_FA
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bool
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if MMU
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# The copy-page model
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config CPU_COPY_V3
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bool
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config CPU_COPY_V4WT
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bool
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config CPU_COPY_V4WB
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bool
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config CPU_COPY_FEROCEON
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bool
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config CPU_COPY_FA
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bool
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config CPU_COPY_V6
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bool
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# This selects the TLB model
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config CPU_TLB_V3
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bool
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help
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ARM Architecture Version 3 TLB.
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config CPU_TLB_V4WT
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bool
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help
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ARM Architecture Version 4 TLB with writethrough cache.
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config CPU_TLB_V4WB
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bool
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help
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ARM Architecture Version 4 TLB with writeback cache.
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config CPU_TLB_V4WBI
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bool
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help
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ARM Architecture Version 4 TLB with writeback cache and invalidate
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instruction cache entry.
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config CPU_TLB_FEROCEON
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bool
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help
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Feroceon TLB (v4wbi with non-outer-cachable page table walks).
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config CPU_TLB_FA
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bool
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help
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Faraday ARM FA526 architecture, unified TLB with writeback cache
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and invalidate instruction cache entry. Branch target buffer is
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also supported.
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config CPU_TLB_V6
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bool
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config CPU_TLB_V7
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bool
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endif
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config CPU_HAS_ASID
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bool
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help
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This indicates whether the CPU has the ASID register; used to
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tag TLB and possibly cache entries.
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config CPU_CP15
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bool
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help
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Processor has the CP15 register.
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config CPU_CP15_MMU
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bool
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select CPU_CP15
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help
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Processor has the CP15 register, which has MMU related registers.
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config CPU_CP15_MPU
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bool
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select CPU_CP15
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help
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Processor has the CP15 register, which has MPU related registers.
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#
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# CPU supports 36-bit I/O
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#
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config IO_36
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bool
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comment "Processor Features"
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config ARM_THUMB
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bool "Support Thumb user binaries"
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depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON
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default y
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help
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Say Y if you want to include kernel support for running user space
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Thumb binaries.
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The Thumb instruction set is a compressed form of the standard ARM
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instruction set resulting in smaller binaries at the expense of
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slightly less efficient code.
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If you don't know what this all is, saying Y is a safe choice.
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config ARM_THUMBEE
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bool "Enable ThumbEE CPU extension"
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depends on CPU_V7
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help
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Say Y here if you have a CPU with the ThumbEE extension and code to
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make use of it. Say N for code that can run on CPUs without ThumbEE.
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config CPU_BIG_ENDIAN
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bool "Build big-endian kernel"
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depends on ARCH_SUPPORTS_BIG_ENDIAN
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help
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Say Y if you plan on running a kernel in big-endian mode.
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Note that your board must be properly built and your board
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port must properly enable any big-endian related features
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of your chipset/board/processor.
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config CPU_ENDIAN_BE8
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bool
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depends on CPU_BIG_ENDIAN
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default CPU_V6 || CPU_V7
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help
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Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
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config CPU_ENDIAN_BE32
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bool
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depends on CPU_BIG_ENDIAN
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default !CPU_ENDIAN_BE8
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help
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Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
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config CPU_HIGH_VECTOR
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depends on !MMU && CPU_CP15 && !CPU_ARM740T
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bool "Select the High exception vector"
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help
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Say Y here to select high exception vector(0xFFFF0000~).
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The exception vector can be vary depending on the platform
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design in nommu mode. If your platform needs to select
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high exception vector, say Y.
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Otherwise or if you are unsure, say N, and the low exception
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vector (0x00000000~) will be used.
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config CPU_ICACHE_DISABLE
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bool "Disable I-Cache (I-bit)"
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depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
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help
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Say Y here to disable the processor instruction cache. Unless
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you have a reason not to or are unsure, say N.
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config CPU_DCACHE_DISABLE
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bool "Disable D-Cache (C-bit)"
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depends on CPU_CP15
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help
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Say Y here to disable the processor data cache. Unless
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you have a reason not to or are unsure, say N.
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config CPU_DCACHE_SIZE
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hex
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depends on CPU_ARM740T || CPU_ARM946E
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default 0x00001000 if CPU_ARM740T
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default 0x00002000 # default size for ARM946E-S
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help
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Some cores are synthesizable to have various sized cache. For
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ARM946E-S case, it can vary from 0KB to 1MB.
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To support such cache operations, it is efficient to know the size
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before compile time.
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If your SoC is configured to have a different size, define the value
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here with proper conditions.
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config CPU_DCACHE_WRITETHROUGH
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bool "Force write through D-cache"
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depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
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default y if CPU_ARM925T
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help
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Say Y here to use the data cache in writethrough mode. Unless you
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specifically require this or are unsure, say N.
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config CPU_CACHE_ROUND_ROBIN
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bool "Round robin I and D cache replacement algorithm"
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depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
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help
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Say Y here to use the predictable round-robin cache replacement
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policy. Unless you specifically require this or are unsure, say N.
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config CPU_BPREDICT_DISABLE
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bool "Disable branch prediction"
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depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
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help
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Say Y here to disable branch prediction. If unsure, say N.
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config TLS_REG_EMUL
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bool
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help
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An SMP system using a pre-ARMv6 processor (there are apparently
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a few prototypes like that in existence) and therefore access to
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that required register must be emulated.
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config HAS_TLS_REG
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bool
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depends on !TLS_REG_EMUL
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default y if SMP || CPU_32v7
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help
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This selects support for the CP15 thread register.
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It is defined to be available on some ARMv6 processors (including
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all SMP capable ARMv6's) or later processors. User space may
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assume directly accessing that register and always obtain the
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expected value only on ARMv7 and above.
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config NEEDS_SYSCALL_FOR_CMPXCHG
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bool
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help
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SMP on a pre-ARMv6 processor? Well OK then.
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Forget about fast user space cmpxchg support.
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It is just not possible.
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config OUTER_CACHE
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bool
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config CACHE_FEROCEON_L2
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bool "Enable the Feroceon L2 cache controller"
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depends on ARCH_KIRKWOOD || ARCH_MV78XX0
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default y
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select OUTER_CACHE
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help
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This option enables the Feroceon L2 cache controller.
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config CACHE_FEROCEON_L2_WRITETHROUGH
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bool "Force Feroceon L2 cache write through"
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depends on CACHE_FEROCEON_L2
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help
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Say Y here to use the Feroceon L2 cache in writethrough mode.
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Unless you specifically require this, say N for writeback mode.
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config CACHE_L2X0
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bool "Enable the L2x0 outer cache controller"
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depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
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REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK
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default y
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select OUTER_CACHE
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help
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This option enables the L2x0 PrimeCell.
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config CACHE_XSC3L2
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bool "Enable the L2 cache on XScale3"
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depends on CPU_XSC3
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default y
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select OUTER_CACHE
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help
|
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This option enables the L2 cache on XScale3.
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config ARM_L1_CACHE_SHIFT
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int
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default 6 if ARCH_OMAP3
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default 5
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