128 lines
4.1 KiB
C
Executable File
128 lines
4.1 KiB
C
Executable File
/*
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* Copyright (C) 2011 STMicroelectronics
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* Author: Francesco M. Virlinzi <francesco.virlinzi@st.com>
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*
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* May be copied or modified under the terms of the GNU General Public
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* License V.2 ONLY. See linux/COPYING for more information.
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*/
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#ifndef __stm_synopsys_dwc_ddr32_h__
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#define __stm_synopsys_dwc_ddr32_h__
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#include <linux/stm/poke_table.h>
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/*
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* Synopsys DWC SDram Protocol Controller
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* For registers description see:
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* 'DesignWare Cores DDR3/2 SDRAM Protocol - Controller -
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* Databook - Version 2.10a - February 4, 2009'
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*/
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#define DDR_SCTL 0x4
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# define DDR_SCTL_CFG 0x1
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# define DDR_SCTL_GO 0x2
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# define DDR_SCTL_SLEEP 0x3
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# define DDR_SCTL_WAKEUP 0x4
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#define DDR_STAT 0x8
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# define DDR_STAT_CONFIG 0x1
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# define DDR_STAT_ACCESS 0x3
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# define DDR_STAT_LOW_POWER 0x5
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#define DDR_DTU_CFG 0x208
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# define DDR_DTU_CFG_ENABLE 0x1
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#define DDR_PHY_IOCRV1 0x31C
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/*
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* Synopsys DWC SDram Phy Controller
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* For registers description see:
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* 'DesignWare Cores DDR3/2 SDRAM PHY -
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* Databook - February 5, 2009'
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*
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* - Table 5.1: PHY Control Register Mapping
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* and
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* - Table 5.30: PUB Control Register Mapping
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*/
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#define DDR_PHY_REG(idx) (0x400 + (idx) * 4)
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#define DDR_PHY_PIR DDR_PHY_REG(1) /* 0x04 */
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# define DDR_PHY_PIR_PLL_RESET (1 << 7)
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# define DDR_PHY_PIR_PLL_PD (1 << 8)
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#define DDR_PHY_PGCR0 DDR_PHY_REG(2) /* 0x08 */
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#define DDR_PHY_PGCR1 DDR_PHY_REG(3) /* 0x0c */
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#define DDR_PHY_ACIOCR DDR_PHY_REG(12) /* 0x30 */
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# define DDR_PHY_ACIOCR_OUTPUT_ENABLE (1 << 1)
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# define DDR_PHY_ACIOCR_PDD (1 << 3)
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# define DDR_PHY_ACIOCR_PDR (1 << 4)
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#define DDR_PHY_DXCCR DDR_PHY_REG(13) /* 0x34 */
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# define DDR_PHY_DXCCR_DXODT (1 << 0)
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# define DDR_PHY_DXCCR_PDR (1 << 4)
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/*
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* Synopsys DDR32: in Self-Refresh
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*/
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#define synopsys_ddr32_in_self_refresh(_ddr_base) \
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/* Enable the DDR self refresh mode */ \
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/* from ACCESS to LowPower (based on paraghaph. 7.1.4) */ \
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POKE32((_ddr_base) + DDR_SCTL, DDR_SCTL_SLEEP), \
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WHILE_NE32((_ddr_base) + DDR_STAT, DDR_STAT_LOW_POWER, DDR_STAT_LOW_POWER)
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/*
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* Synopsys DDR: out of Self-Refresh
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*/
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#define synopsys_ddr32_out_of_self_refresh(_ddr_base) \
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/* Disables the DDR self refresh mode */ \
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/* from LowPower to Access (based on paraghaph 7.1.3) */ \
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POKE32((_ddr_base) + DDR_SCTL, DDR_SCTL_WAKEUP), \
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WHILE_NE32((_ddr_base) + DDR_STAT, DDR_STAT_ACCESS, DDR_STAT_ACCESS), \
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\
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POKE32((_ddr_base) + DDR_SCTL, DDR_SCTL_CFG), \
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WHILE_NE32((_ddr_base) + DDR_STAT, DDR_STAT_CONFIG, DDR_STAT_CONFIG), \
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\
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POKE32((_ddr_base) + DDR_SCTL, DDR_SCTL_GO), \
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WHILE_NE32((_ddr_base) + DDR_STAT, DDR_STAT_ACCESS, DDR_STAT_ACCESS)
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/*
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* Synopsys DDR Phy: moving in Standby
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*/
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#define synopsys_ddr32_phy_standby_enter(_ddr_base) \
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OR32((_ddr_base) + DDR_PHY_DXCCR, DDR_PHY_DXCCR_DXODT), \
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/* DDR_Phy Pll in reset */ \
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OR32((_ddr_base) + DDR_PHY_PIR, DDR_PHY_PIR_PLL_RESET)
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/*
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* Synopsys DDR Phy: moving out Standby
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*/
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#define synopsys_ddr32_phy_standby_exit(_ddr_base) \
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/* DDR_Phy Pll out of reset */ \
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UPDATE32((_ddr_base) + DDR_PHY_PIR, ~DDR_PHY_PIR_PLL_RESET, 0), \
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UPDATE32((_ddr_base) + DDR_PHY_DXCCR, ~DDR_PHY_DXCCR_DXODT, 0)
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/*
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* Synopsys DDR Phy: moving in HoM
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*/
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#define synopsys_ddr32_phy_hom_enter(_ddr_base) \
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/* 2. Turn in LowPower the DDR-Phy */ \
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OR32((_ddr_base) + DDR_PHY_PIR, DDR_PHY_PIR_PLL_RESET), \
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OR32((_ddr_base) + DDR_PHY_PIR, DDR_PHY_PIR_PLL_PD), \
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\
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POKE32((_ddr_base) + DDR_PHY_ACIOCR, -1), \
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UPDATE32((_ddr_base) + DDR_PHY_ACIOCR, ~1, 0), \
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\
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OR32((_ddr_base) + DDR_PHY_DXCCR, DDR_PHY_DXCCR_PDR), \
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\
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/* Disable CK going to the SDRAM */ \
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UPDATE32((_ddr_base) + DDR_PHY_PGCR0, ~(0x3f << 26), 0), \
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UPDATE32((_ddr_base) + DDR_PHY_PGCR1, ~(5 << 12), 0)
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#define synopsys_ddr32_in_hom(_ddr_base) \
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/* Enable DTU */ \
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OR32((_ddr_base) + DDR_DTU_CFG, DDR_DTU_CFG_ENABLE), \
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synopsys_ddr32_in_self_refresh(_ddr_base), \
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synopsys_ddr32_phy_hom_enter(_ddr_base)
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#endif
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