538 lines
15 KiB
C
538 lines
15 KiB
C
/* ZD1211 USB-WLAN driver for Linux
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*
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* Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
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* Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include "zd_rf.h"
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#include "zd_usb.h"
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#include "zd_chip.h"
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/* This RF programming code is based upon the code found in v2.16.0.0 of the
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* ZyDAS vendor driver. Unlike other RF's, Ubec publish full technical specs
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* for this RF on their website, so we're able to understand more than
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* usual as to what is going on. Thumbs up for Ubec for doing that. */
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/* The 3-wire serial interface provides access to 8 write-only registers.
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* The data format is a 4 bit register address followed by a 20 bit value. */
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#define UW2453_REGWRITE(reg, val) ((((reg) & 0xf) << 20) | ((val) & 0xfffff))
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/* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth
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* fractional divide ratio) and 3 (VCO config).
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*
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* We configure the RF to produce an interrupt when the PLL is locked onto
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* the configured frequency. During initialization, we run through a variety
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* of different VCO configurations on channel 1 until we detect a PLL lock.
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* When this happens, we remember which VCO configuration produced the lock
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* and use it later. Actually, we use the configuration *after* the one that
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* produced the lock, which seems odd, but it works.
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*
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* If we do not see a PLL lock on any standard VCO config, we fall back on an
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* autocal configuration, which has a fixed (as opposed to per-channel) VCO
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* config and different synth values from the standard set (divide ratio
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* is still shared with the standard set). */
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/* The per-channel synth values for all standard VCO configurations. These get
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* written to register 1. */
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static const u8 uw2453_std_synth[] = {
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RF_CHANNEL( 1) = 0x47,
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RF_CHANNEL( 2) = 0x47,
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RF_CHANNEL( 3) = 0x67,
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RF_CHANNEL( 4) = 0x67,
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RF_CHANNEL( 5) = 0x67,
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RF_CHANNEL( 6) = 0x67,
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RF_CHANNEL( 7) = 0x57,
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RF_CHANNEL( 8) = 0x57,
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RF_CHANNEL( 9) = 0x57,
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RF_CHANNEL(10) = 0x57,
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RF_CHANNEL(11) = 0x77,
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RF_CHANNEL(12) = 0x77,
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RF_CHANNEL(13) = 0x77,
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RF_CHANNEL(14) = 0x4f,
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};
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/* This table stores the synthesizer fractional divide ratio for *all* VCO
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* configurations (both standard and autocal). These get written to register 2.
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*/
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static const u16 uw2453_synth_divide[] = {
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RF_CHANNEL( 1) = 0x999,
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RF_CHANNEL( 2) = 0x99b,
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RF_CHANNEL( 3) = 0x998,
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RF_CHANNEL( 4) = 0x99a,
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RF_CHANNEL( 5) = 0x999,
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RF_CHANNEL( 6) = 0x99b,
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RF_CHANNEL( 7) = 0x998,
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RF_CHANNEL( 8) = 0x99a,
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RF_CHANNEL( 9) = 0x999,
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RF_CHANNEL(10) = 0x99b,
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RF_CHANNEL(11) = 0x998,
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RF_CHANNEL(12) = 0x99a,
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RF_CHANNEL(13) = 0x999,
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RF_CHANNEL(14) = 0xccc,
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};
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/* Here is the data for all the standard VCO configurations. We shrink our
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* table a little by observing that both channels in a consecutive pair share
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* the same value. We also observe that the high 4 bits ([0:3] in the specs)
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* are all 'Reserved' and are always set to 0x4 - we chop them off in the data
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* below. */
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#define CHAN_TO_PAIRIDX(a) ((a - 1) / 2)
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#define RF_CHANPAIR(a,b) [CHAN_TO_PAIRIDX(a)]
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static const u16 uw2453_std_vco_cfg[][7] = {
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{ /* table 1 */
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RF_CHANPAIR( 1, 2) = 0x664d,
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RF_CHANPAIR( 3, 4) = 0x604d,
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RF_CHANPAIR( 5, 6) = 0x6675,
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RF_CHANPAIR( 7, 8) = 0x6475,
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RF_CHANPAIR( 9, 10) = 0x6655,
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RF_CHANPAIR(11, 12) = 0x6455,
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RF_CHANPAIR(13, 14) = 0x6665,
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},
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{ /* table 2 */
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RF_CHANPAIR( 1, 2) = 0x666d,
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RF_CHANPAIR( 3, 4) = 0x606d,
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RF_CHANPAIR( 5, 6) = 0x664d,
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RF_CHANPAIR( 7, 8) = 0x644d,
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RF_CHANPAIR( 9, 10) = 0x6675,
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RF_CHANPAIR(11, 12) = 0x6475,
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RF_CHANPAIR(13, 14) = 0x6655,
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},
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{ /* table 3 */
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RF_CHANPAIR( 1, 2) = 0x665d,
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RF_CHANPAIR( 3, 4) = 0x605d,
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RF_CHANPAIR( 5, 6) = 0x666d,
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RF_CHANPAIR( 7, 8) = 0x646d,
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RF_CHANPAIR( 9, 10) = 0x664d,
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RF_CHANPAIR(11, 12) = 0x644d,
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RF_CHANPAIR(13, 14) = 0x6675,
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},
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{ /* table 4 */
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RF_CHANPAIR( 1, 2) = 0x667d,
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RF_CHANPAIR( 3, 4) = 0x607d,
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RF_CHANPAIR( 5, 6) = 0x665d,
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RF_CHANPAIR( 7, 8) = 0x645d,
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RF_CHANPAIR( 9, 10) = 0x666d,
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RF_CHANPAIR(11, 12) = 0x646d,
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RF_CHANPAIR(13, 14) = 0x664d,
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},
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{ /* table 5 */
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RF_CHANPAIR( 1, 2) = 0x6643,
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RF_CHANPAIR( 3, 4) = 0x6043,
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RF_CHANPAIR( 5, 6) = 0x667d,
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RF_CHANPAIR( 7, 8) = 0x647d,
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RF_CHANPAIR( 9, 10) = 0x665d,
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RF_CHANPAIR(11, 12) = 0x645d,
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RF_CHANPAIR(13, 14) = 0x666d,
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},
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{ /* table 6 */
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RF_CHANPAIR( 1, 2) = 0x6663,
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RF_CHANPAIR( 3, 4) = 0x6063,
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RF_CHANPAIR( 5, 6) = 0x6643,
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RF_CHANPAIR( 7, 8) = 0x6443,
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RF_CHANPAIR( 9, 10) = 0x667d,
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RF_CHANPAIR(11, 12) = 0x647d,
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RF_CHANPAIR(13, 14) = 0x665d,
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},
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{ /* table 7 */
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RF_CHANPAIR( 1, 2) = 0x6653,
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RF_CHANPAIR( 3, 4) = 0x6053,
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RF_CHANPAIR( 5, 6) = 0x6663,
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RF_CHANPAIR( 7, 8) = 0x6463,
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RF_CHANPAIR( 9, 10) = 0x6643,
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RF_CHANPAIR(11, 12) = 0x6443,
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RF_CHANPAIR(13, 14) = 0x667d,
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},
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{ /* table 8 */
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RF_CHANPAIR( 1, 2) = 0x6673,
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RF_CHANPAIR( 3, 4) = 0x6073,
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RF_CHANPAIR( 5, 6) = 0x6653,
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RF_CHANPAIR( 7, 8) = 0x6453,
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RF_CHANPAIR( 9, 10) = 0x6663,
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RF_CHANPAIR(11, 12) = 0x6463,
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RF_CHANPAIR(13, 14) = 0x6643,
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},
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{ /* table 9 */
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RF_CHANPAIR( 1, 2) = 0x664b,
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RF_CHANPAIR( 3, 4) = 0x604b,
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RF_CHANPAIR( 5, 6) = 0x6673,
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RF_CHANPAIR( 7, 8) = 0x6473,
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RF_CHANPAIR( 9, 10) = 0x6653,
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RF_CHANPAIR(11, 12) = 0x6453,
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RF_CHANPAIR(13, 14) = 0x6663,
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},
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{ /* table 10 */
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RF_CHANPAIR( 1, 2) = 0x666b,
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RF_CHANPAIR( 3, 4) = 0x606b,
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RF_CHANPAIR( 5, 6) = 0x664b,
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RF_CHANPAIR( 7, 8) = 0x644b,
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RF_CHANPAIR( 9, 10) = 0x6673,
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RF_CHANPAIR(11, 12) = 0x6473,
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RF_CHANPAIR(13, 14) = 0x6653,
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},
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{ /* table 11 */
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RF_CHANPAIR( 1, 2) = 0x665b,
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RF_CHANPAIR( 3, 4) = 0x605b,
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RF_CHANPAIR( 5, 6) = 0x666b,
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RF_CHANPAIR( 7, 8) = 0x646b,
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RF_CHANPAIR( 9, 10) = 0x664b,
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RF_CHANPAIR(11, 12) = 0x644b,
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RF_CHANPAIR(13, 14) = 0x6673,
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},
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};
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/* The per-channel synth values for autocal. These get written to register 1. */
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static const u16 uw2453_autocal_synth[] = {
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RF_CHANNEL( 1) = 0x6847,
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RF_CHANNEL( 2) = 0x6847,
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RF_CHANNEL( 3) = 0x6867,
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RF_CHANNEL( 4) = 0x6867,
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RF_CHANNEL( 5) = 0x6867,
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RF_CHANNEL( 6) = 0x6867,
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RF_CHANNEL( 7) = 0x6857,
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RF_CHANNEL( 8) = 0x6857,
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RF_CHANNEL( 9) = 0x6857,
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RF_CHANNEL(10) = 0x6857,
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RF_CHANNEL(11) = 0x6877,
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RF_CHANNEL(12) = 0x6877,
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RF_CHANNEL(13) = 0x6877,
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RF_CHANNEL(14) = 0x684f,
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};
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/* The VCO configuration for autocal (all channels) */
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static const u16 UW2453_AUTOCAL_VCO_CFG = 0x6662;
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/* TX gain settings. The array index corresponds to the TX power integration
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* values found in the EEPROM. The values get written to register 7. */
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static u32 uw2453_txgain[] = {
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[0x00] = 0x0e313,
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[0x01] = 0x0fb13,
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[0x02] = 0x0e093,
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[0x03] = 0x0f893,
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[0x04] = 0x0ea93,
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[0x05] = 0x1f093,
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[0x06] = 0x1f493,
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[0x07] = 0x1f693,
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[0x08] = 0x1f393,
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[0x09] = 0x1f35b,
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[0x0a] = 0x1e6db,
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[0x0b] = 0x1ff3f,
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[0x0c] = 0x1ffff,
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[0x0d] = 0x361d7,
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[0x0e] = 0x37fbf,
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[0x0f] = 0x3ff8b,
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[0x10] = 0x3ff33,
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[0x11] = 0x3fb3f,
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[0x12] = 0x3ffff,
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};
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/* RF-specific structure */
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struct uw2453_priv {
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/* index into synth/VCO config tables where PLL lock was found
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* -1 means autocal */
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int config;
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};
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#define UW2453_PRIV(rf) ((struct uw2453_priv *) (rf)->priv)
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static int uw2453_synth_set_channel(struct zd_chip *chip, int channel,
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bool autocal)
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{
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int r;
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int idx = channel - 1;
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u32 val;
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if (autocal)
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val = UW2453_REGWRITE(1, uw2453_autocal_synth[idx]);
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else
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val = UW2453_REGWRITE(1, uw2453_std_synth[idx]);
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r = zd_rfwrite_locked(chip, val, RF_RV_BITS);
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if (r)
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return r;
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return zd_rfwrite_locked(chip,
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UW2453_REGWRITE(2, uw2453_synth_divide[idx]), RF_RV_BITS);
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}
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static int uw2453_write_vco_cfg(struct zd_chip *chip, u16 value)
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{
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/* vendor driver always sets these upper bits even though the specs say
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* they are reserved */
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u32 val = 0x40000 | value;
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return zd_rfwrite_locked(chip, UW2453_REGWRITE(3, val), RF_RV_BITS);
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}
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static int uw2453_init_mode(struct zd_chip *chip)
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{
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static const u32 rv[] = {
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UW2453_REGWRITE(0, 0x25f98), /* enter IDLE mode */
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UW2453_REGWRITE(0, 0x25f9a), /* enter CAL_VCO mode */
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UW2453_REGWRITE(0, 0x25f94), /* enter RX/TX mode */
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UW2453_REGWRITE(0, 0x27fd4), /* power down RSSI circuit */
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};
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return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
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}
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static int uw2453_set_tx_gain_level(struct zd_chip *chip, int channel)
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{
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u8 int_value = chip->pwr_int_values[channel - 1];
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if (int_value >= ARRAY_SIZE(uw2453_txgain)) {
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dev_dbg_f(zd_chip_dev(chip), "can't configure TX gain for "
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"int value %x on channel %d\n", int_value, channel);
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return 0;
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}
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return zd_rfwrite_locked(chip,
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UW2453_REGWRITE(7, uw2453_txgain[int_value]), RF_RV_BITS);
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}
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static int uw2453_init_hw(struct zd_rf *rf)
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{
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int i, r;
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int found_config = -1;
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u16 intr_status;
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struct zd_chip *chip = zd_rf_to_chip(rf);
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static const struct zd_ioreq16 ioreqs[] = {
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{ CR10, 0x89 }, { CR15, 0x20 },
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{ CR17, 0x28 }, /* 6112 no change */
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{ CR23, 0x38 }, { CR24, 0x20 }, { CR26, 0x93 },
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{ CR27, 0x15 }, { CR28, 0x3e }, { CR29, 0x00 },
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{ CR33, 0x28 }, { CR34, 0x30 },
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{ CR35, 0x43 }, /* 6112 3e->43 */
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{ CR41, 0x24 }, { CR44, 0x32 },
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{ CR46, 0x92 }, /* 6112 96->92 */
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{ CR47, 0x1e },
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{ CR48, 0x04 }, /* 5602 Roger */
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{ CR49, 0xfa }, { CR79, 0x58 }, { CR80, 0x30 },
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{ CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 },
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{ CR91, 0x00 }, { CR92, 0x0a }, { CR98, 0x8d },
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{ CR99, 0x28 }, { CR100, 0x02 },
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{ CR101, 0x09 }, /* 6112 13->1f 6220 1f->13 6407 13->9 */
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{ CR102, 0x27 },
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{ CR106, 0x1c }, /* 5d07 5112 1f->1c 6220 1c->1f 6221 1f->1c */
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{ CR107, 0x1c }, /* 6220 1c->1a 5221 1a->1c */
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{ CR109, 0x13 },
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{ CR110, 0x1f }, /* 6112 13->1f 6221 1f->13 6407 13->0x09 */
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{ CR111, 0x13 }, { CR112, 0x1f }, { CR113, 0x27 },
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{ CR114, 0x23 }, /* 6221 27->23 */
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{ CR115, 0x24 }, /* 6112 24->1c 6220 1c->24 */
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{ CR116, 0x24 }, /* 6220 1c->24 */
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{ CR117, 0xfa }, /* 6112 fa->f8 6220 f8->f4 6220 f4->fa */
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{ CR118, 0xf0 }, /* 5d07 6112 f0->f2 6220 f2->f0 */
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{ CR119, 0x1a }, /* 6112 1a->10 6220 10->14 6220 14->1a */
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{ CR120, 0x4f },
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{ CR121, 0x1f }, /* 6220 4f->1f */
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{ CR122, 0xf0 }, { CR123, 0x57 }, { CR125, 0xad },
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{ CR126, 0x6c }, { CR127, 0x03 },
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{ CR128, 0x14 }, /* 6302 12->11 */
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{ CR129, 0x12 }, /* 6301 10->0f */
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{ CR130, 0x10 }, { CR137, 0x50 }, { CR138, 0xa8 },
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{ CR144, 0xac }, { CR146, 0x20 }, { CR252, 0xff },
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{ CR253, 0xff },
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};
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static const u32 rv[] = {
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UW2453_REGWRITE(4, 0x2b), /* configure reciever gain */
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UW2453_REGWRITE(5, 0x19e4f), /* configure transmitter gain */
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UW2453_REGWRITE(6, 0xf81ad), /* enable RX/TX filter tuning */
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UW2453_REGWRITE(7, 0x3fffe), /* disable TX gain in test mode */
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/* enter CAL_FIL mode, TX gain set by registers, RX gain set by pins,
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* RSSI circuit powered down, reduced RSSI range */
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UW2453_REGWRITE(0, 0x25f9c), /* 5d01 cal_fil */
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/* synthesizer configuration for channel 1 */
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UW2453_REGWRITE(1, 0x47),
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UW2453_REGWRITE(2, 0x999),
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/* disable manual VCO band selection */
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UW2453_REGWRITE(3, 0x7602),
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/* enable manual VCO band selection, configure current level */
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UW2453_REGWRITE(3, 0x46063),
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};
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r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
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if (r)
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return r;
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r = zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
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if (r)
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return r;
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r = uw2453_init_mode(chip);
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if (r)
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return r;
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/* Try all standard VCO configuration settings on channel 1 */
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for (i = 0; i < ARRAY_SIZE(uw2453_std_vco_cfg) - 1; i++) {
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/* Configure synthesizer for channel 1 */
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r = uw2453_synth_set_channel(chip, 1, false);
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if (r)
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return r;
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/* Write VCO config */
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r = uw2453_write_vco_cfg(chip, uw2453_std_vco_cfg[i][0]);
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if (r)
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return r;
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/* ack interrupt event */
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r = zd_iowrite16_locked(chip, 0x0f, UW2453_INTR_REG);
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if (r)
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return r;
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/* check interrupt status */
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r = zd_ioread16_locked(chip, &intr_status, UW2453_INTR_REG);
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if (r)
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return r;
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if (!(intr_status & 0xf)) {
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dev_dbg_f(zd_chip_dev(chip),
|
|
"PLL locked on configuration %d\n", i);
|
|
found_config = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (found_config == -1) {
|
|
/* autocal */
|
|
dev_dbg_f(zd_chip_dev(chip),
|
|
"PLL did not lock, using autocal\n");
|
|
|
|
r = uw2453_synth_set_channel(chip, 1, true);
|
|
if (r)
|
|
return r;
|
|
|
|
r = uw2453_write_vco_cfg(chip, UW2453_AUTOCAL_VCO_CFG);
|
|
if (r)
|
|
return r;
|
|
}
|
|
|
|
/* To match the vendor driver behaviour, we use the configuration after
|
|
* the one that produced a lock. */
|
|
UW2453_PRIV(rf)->config = found_config + 1;
|
|
|
|
return zd_iowrite16_locked(chip, 0x06, CR203);
|
|
}
|
|
|
|
static int uw2453_set_channel(struct zd_rf *rf, u8 channel)
|
|
{
|
|
int r;
|
|
u16 vco_cfg;
|
|
int config = UW2453_PRIV(rf)->config;
|
|
bool autocal = (config == -1);
|
|
struct zd_chip *chip = zd_rf_to_chip(rf);
|
|
|
|
static const struct zd_ioreq16 ioreqs[] = {
|
|
{ CR80, 0x30 }, { CR81, 0x30 }, { CR79, 0x58 },
|
|
{ CR12, 0xf0 }, { CR77, 0x1b }, { CR78, 0x58 },
|
|
};
|
|
|
|
r = uw2453_synth_set_channel(chip, channel, autocal);
|
|
if (r)
|
|
return r;
|
|
|
|
if (autocal)
|
|
vco_cfg = UW2453_AUTOCAL_VCO_CFG;
|
|
else
|
|
vco_cfg = uw2453_std_vco_cfg[config][CHAN_TO_PAIRIDX(channel)];
|
|
|
|
r = uw2453_write_vco_cfg(chip, vco_cfg);
|
|
if (r)
|
|
return r;
|
|
|
|
r = uw2453_init_mode(chip);
|
|
if (r)
|
|
return r;
|
|
|
|
r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
|
|
if (r)
|
|
return r;
|
|
|
|
r = uw2453_set_tx_gain_level(chip, channel);
|
|
if (r)
|
|
return r;
|
|
|
|
return zd_iowrite16_locked(chip, 0x06, CR203);
|
|
}
|
|
|
|
static int uw2453_switch_radio_on(struct zd_rf *rf)
|
|
{
|
|
int r;
|
|
struct zd_chip *chip = zd_rf_to_chip(rf);
|
|
struct zd_ioreq16 ioreqs[] = {
|
|
{ CR11, 0x00 }, { CR251, 0x3f },
|
|
};
|
|
|
|
/* enter RXTX mode */
|
|
r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f94), RF_RV_BITS);
|
|
if (r)
|
|
return r;
|
|
|
|
if (zd_chip_is_zd1211b(chip))
|
|
ioreqs[1].value = 0x7f;
|
|
|
|
return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
|
|
}
|
|
|
|
static int uw2453_switch_radio_off(struct zd_rf *rf)
|
|
{
|
|
int r;
|
|
struct zd_chip *chip = zd_rf_to_chip(rf);
|
|
static const struct zd_ioreq16 ioreqs[] = {
|
|
{ CR11, 0x04 }, { CR251, 0x2f },
|
|
};
|
|
|
|
/* enter IDLE mode */
|
|
/* FIXME: shouldn't we go to SLEEP? sent email to zydas */
|
|
r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f90), RF_RV_BITS);
|
|
if (r)
|
|
return r;
|
|
|
|
return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
|
|
}
|
|
|
|
static void uw2453_clear(struct zd_rf *rf)
|
|
{
|
|
kfree(rf->priv);
|
|
}
|
|
|
|
int zd_rf_init_uw2453(struct zd_rf *rf)
|
|
{
|
|
rf->init_hw = uw2453_init_hw;
|
|
rf->set_channel = uw2453_set_channel;
|
|
rf->switch_radio_on = uw2453_switch_radio_on;
|
|
rf->switch_radio_off = uw2453_switch_radio_off;
|
|
rf->patch_6m_band_edge = zd_rf_generic_patch_6m;
|
|
rf->clear = uw2453_clear;
|
|
/* we have our own TX integration code */
|
|
rf->update_channel_int = 0;
|
|
|
|
rf->priv = kmalloc(sizeof(struct uw2453_priv), GFP_KERNEL);
|
|
if (rf->priv == NULL)
|
|
return -ENOMEM;
|
|
|
|
return 0;
|
|
}
|
|
|