88 lines
2.8 KiB
C
88 lines
2.8 KiB
C
/*****************************************************************************
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*
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* File name : clock-regs-stx7141.h
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* Description : Low Level API - Base addresses & register definitions.
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*
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* COPYRIGHT (C) 2009 STMicroelectronics - All Rights Reserved
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* May be copied or modified under the terms of the GNU General Public
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* License v2. See linux/COPYING for more information.
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*
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*****************************************************************************/
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#ifndef __CLOCK_LLA_REGS_H
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#define __CLOCK_LLA_REGS_H
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/* --- Base addresses ---------------------------------------- */
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#define CKGA_BASE_ADDRESS 0xfe213000
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#define CKGB_BASE_ADDRESS 0xfe000000
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#define CKGC_BASE_ADDRESS 0xfe210000
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/* --- CKGA registers ( hardware specific ) --------------------------------- */
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#define CKGA_PLL0_CFG 0x000
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#define CKGA_PLL1_CFG 0x004
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#define CKGA_POWER_CFG 0x010
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#define CKGA_CLKOPSRC_SWITCH_CFG 0x014
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#define CKGA_OSC_ENABLE_FB 0x018
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#define CKGA_PLL0_ENABLE_FB 0x01c
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#define CKGA_PLL1_ENABLE_FB 0x020
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#define CKGA_CLKOPSRC_SWITCH_CFG2 0x024
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#define CKGA_CLKOBS_MUX1_CFG 0x030
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#define CKGA_CLKOBS_MASTER_MAXCOUNT 0x034
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#define CKGA_CLKOBS_CMD 0x038
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#define CKGA_CLKOBS_STATUS 0x03c
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#define CKGA_CLKOBS_SLAVE0_COUNT 0x040
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#define CKGA_OSCMUX_DEBUG 0x044
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#define CKGA_LOW_POWER_CTRL 0x04C
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/*
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* The CKGA_SOURCE_CFG(..) replaces the
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* - CKGA_OSC_DIV0_CFG
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* - CKGA_PLL0HS_DIV0_CFG
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* - CKGA_PLL0LS_DIV0_CFG
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* - CKGA_PLL1_DIV0_CFG
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* macros.
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* The _parent_id identifies the parent as:
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* - 0: OSC
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* - 1: PLL0_HS
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* - 2: PLL0_LS
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* - 3: PLL1
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*/
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#define CKGA_SOURCE_CFG(_parent_id) (0x800 + (_parent_id) * 0x100)
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/* Clockgen B registers */
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#define CKGB_LOCK 0x010
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#define CKGB_FS0_CTRL 0x014
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#define CKGB_FS1_CTRL 0x05c
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#define CKGB_FS0_CLKOUT_CTRL 0x058
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#define CKGB_FS1_CLKOUT_CTRL 0x0a0
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#define CKGB_DISPLAY_CFG 0x0a4
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#define CKGB_FS_SELECT 0x0a8
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#define CKGB_POWER_DOWN 0x0ac
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#define CKGB_POWER_ENABLE 0x0b0
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#define CKGB_OUT_CTRL 0x0b4
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#define CKGB_CRISTAL_SEL 0x0b8
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#define CKGB_FS_MD(_bk, _chan) \
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((_bk) * 0x48 + 0x18 + (_chan) * 0x10)
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#define CKGB_FS_PE(_bk, _chan) (0x4 + CKGB_FS_MD(_bk, _chan))
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#define CKGB_FS_EN_PRG(_bk, _chan) (0x8 + CKGB_FS_MD(_bk, _chan))
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#define CKGB_FS_SDIV(_bk, _chan) (0xc + CKGB_FS_MD(_bk, _chan))
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/* Clock recovery registers */
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#define CKGB_RECOV_REF_MAX 0x000
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#define CKGB_RECOV_CMD 0x004
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#define CKGB_RECOV_CPT_PCM 0x008
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#define CKGB_RECOV_CPT_HD 0x00c
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/* --- Audio config registers --- */
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#define CKGC_FS_CFG(_bk) (0x100 * (_bk))
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#define CKGC_FS_MD(_bk, _chan) \
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(0x100 * (_bk) + 0x10 + 0x10 * (_chan))
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#define CKGC_FS_PE(_bk, _chan) (0x4 + CKGC_FS_MD(_bk, _chan))
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#define CKGC_FS_SDIV(_bk, _chan) (0x8 + CKGC_FS_MD(_bk, _chan))
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#define CKGC_FS_EN_PRG(_bk, _chan) (0xc + CKGC_FS_MD(_bk, _chan))
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#endif /* End __CLOCK_LLA_REGS_H */
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