425 lines
12 KiB
C
425 lines
12 KiB
C
/*
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* (c) 2010 STMicroelectronics Limited
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*
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* Author: Pawel Moll <pawel.moll@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/stm/pad.h>
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#include <linux/stm/sysconf.h>
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#include <linux/stm/emi.h>
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#include <linux/stm/device.h>
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#include <linux/stm/fli7510.h>
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#include <linux/pci.h>
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#include <asm/irq-ilc.h>
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/* PCI Resources ---------------------------------------------------------- */
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/* You may pass one of the PCI_PIN_* constants to use dedicated pin or
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* just pass interrupt number generated with gpio_to_irq() when PIO pads
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* are used as interrupts or IRLx_IRQ when using external interrupts inputs */
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int fli7510_pcibios_map_platform_irq(struct stm_plat_pci_config *pci_config,
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u8 pin)
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{
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int result;
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int type;
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BUG_ON(cpu_data->type != CPU_FLI7510);
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if (pin < 1 || pin > 4)
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return -1;
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type = pci_config->pci_irq[pin - 1];
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switch (type) {
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case PCI_PIN_ALTERNATIVE:
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/* Actually there are no alternative pins... */
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BUG();
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result = -1;
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break;
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case PCI_PIN_DEFAULT:
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/* Only INTA/INTB are described as "dedicated" PCI
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* interrupts and even if these two are described as that,
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* they are actually just "normal" external interrupt
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* inputs (INT2 & INT3)... Additionally, depending
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* on the spec version, the number below may seem wrong,
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* but believe me - they are correct :-) */
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switch (pin) {
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case 1 ... 2:
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result = ILC_IRQ(119 - (pin - 1));
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/* Configure the ILC input to be active low,
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* which is the PCI way... */
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set_irq_type(result, IRQ_TYPE_LEVEL_LOW);
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break;
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default:
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/* Other should be passed just as interrupt number
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* (eg. result of the ILC_IRQ() macro) */
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BUG();
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result = -1;
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break;
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}
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break;
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case PCI_PIN_UNUSED:
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result = -1; /* Not used */
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break;
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default:
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/* Take whatever interrupt you are told */
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result = type;
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break;
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}
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return result;
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}
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static void fli7510_pci_power(struct stm_device_state *device_state,
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enum stm_device_power_state power)
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{
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int i;
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int value = (power == stm_device_power_on) ? 0 : 1;
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stm_device_sysconf_write(device_state, "PCI_PWR", value);
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for (i = 5; i; --i) {
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if (stm_device_sysconf_read(device_state, "PCI_ACK")
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== value)
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break;
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mdelay(10);
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}
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return;
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}
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static struct platform_device fli7510_pci_device = {
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.name = "pci_stm",
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.id = -1,
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.num_resources = 7,
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.resource = (struct resource[]) {
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/* 512 MB */
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STM_PLAT_RESOURCE_MEM_NAMED("pci memory",
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0xc0000000, 0x20000000),
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{
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.name = "pci io",
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.start = 0x0400,
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.end = 0xffff,
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.flags = IORESOURCE_IO,
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},
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STM_PLAT_RESOURCE_MEM_NAMED("pci emiss", 0xfd200000, 0x17fc),
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STM_PLAT_RESOURCE_MEM_NAMED("pci ahb", 0xfd080000, 0xff),
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STM_PLAT_RESOURCE_IRQ_NAMED("pci dma", ILC_IRQ(47), -1),
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STM_PLAT_RESOURCE_IRQ_NAMED("pci err", ILC_IRQ(48), -1),
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/* SERR interrupt set in fli7510_configure_pci() */
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STM_PLAT_RESOURCE_IRQ_NAMED("pci serr", -1, -1),
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},
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.dev.platform_data = &(struct stm_device_config){
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.sysconfs_num = 2,
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.sysconfs = (struct stm_device_sysconf []){
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STM_DEVICE_SYSCONF(CFG_PWR_DWN_CTL, 2, 2,
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"PCI_PWR"),
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STM_DEVICE_SYSCONF(CFG_PCI_ROPC_STATUS,
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18, 18, "PCI_ACK"),
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},
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.power = fli7510_pci_power,
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}
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};
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#define FLI7510_PIO_PCI_REQ(i) stm_gpio(15, (i - 1) * 2)
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#define FLI7510_PIO_PCI_GNT(i) stm_gpio(15, ((i - 1) * 2) + 1)
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#define FLI7510_PIO_PCI_INT(i) stm_gpio(25, i)
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#define FLI7510_PIO_PCI_SERR stm_gpio(16, 6)
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void __init fli7510_configure_pci(struct stm_plat_pci_config *pci_conf)
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{
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struct sysconf_field *sc;
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int i;
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/* PCI is available in FLI7510 only! */
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if (cpu_data->type != CPU_FLI7510) {
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BUG();
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return;
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}
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/* Fill in the default values */
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if (!pci_conf->ad_override_default) {
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pci_conf->ad_threshold = 5;
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pci_conf->ad_read_ahead = 1;
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pci_conf->ad_chunks_in_msg = 0;
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pci_conf->ad_pcks_in_chunk = 0;
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pci_conf->ad_trigger_mode = 1;
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pci_conf->ad_max_opcode = 5;
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pci_conf->ad_posted = 1;
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}
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/* The EMI_BUS_REQ[0] pin (also know just as EmiBusReq) is
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* internally wired to the arbiter's PCI request 3 line.
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* And the answer to the obvious question is: That's right,
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* the EMI_BUSREQ[3] is not wired at all... */
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pci_conf->req0_to_req3 = 1;
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BUG_ON(pci_conf->req_gnt[3] != PCI_PIN_UNUSED);
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/* Copy over platform specific data to driver */
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fli7510_pci_device.dev.platform_data = pci_conf;
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/* REQ/GNT[1..2] PIOs setup */
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for (i = 1; i <= 2; i++) {
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switch (pci_conf->req_gnt[i]) {
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case PCI_PIN_DEFAULT:
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/* emiss_bus_req_enable */
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sc = sysconf_claim(CFG_COMMS_CONFIG_1,
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24 + (i - 1), 24 + (i - 1), "PCI");
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sysconf_write(sc, 1);
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if (gpio_request(FLI7510_PIO_PCI_REQ(i),
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"PCI_REQ") == 0)
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stm_gpio_direction(FLI7510_PIO_PCI_REQ(i),
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STM_GPIO_DIRECTION_IN);
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else
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printk(KERN_ERR "Unable to configure PIO for "
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"PCI_REQ%d\n", i);
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if (gpio_request(FLI7510_PIO_PCI_GNT(i),
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"PCI_GNT") == 0)
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stm_gpio_direction(FLI7510_PIO_PCI_GNT(i),
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STM_GPIO_DIRECTION_ALT_OUT);
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else
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printk(KERN_ERR "Unable to configure PIO for "
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"PCI_GNT%d\n", i);
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break;
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case PCI_PIN_UNUSED:
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/* Unused is unused - nothing to do */
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break;
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default:
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/* No alternative here... */
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BUG();
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break;
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}
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}
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/* Claim "dedicated" interrupt pins... */
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for (i = 0; i < 4; i++) {
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static const char *int_name[] = {
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"PCI INTA",
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"PCI INTB",
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};
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switch (pci_conf->pci_irq[i]) {
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case PCI_PIN_DEFAULT:
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if (i > 1) {
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BUG();
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break;
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}
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if (gpio_request(FLI7510_PIO_PCI_INT(i),
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int_name[i]) != 0)
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printk(KERN_ERR "Unable to claim PIO for "
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"%s\n", int_name[0]);
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break;
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case PCI_PIN_ALTERNATIVE:
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/* No alternative here... */
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BUG();
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break;
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default:
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/* Unused or interrupt number passed, nothing to do */
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break;
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}
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}
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/* Configure the SERR interrupt (if wired up) */
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switch (pci_conf->serr_irq) {
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case PCI_PIN_DEFAULT:
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if (gpio_request(FLI7510_PIO_PCI_SERR, "PCI SERR#") == 0) {
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stm_gpio_direction(FLI7510_PIO_PCI_SERR,
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STM_GPIO_DIRECTION_IN);
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pci_conf->serr_irq = gpio_to_irq(FLI7510_PIO_PCI_SERR);
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set_irq_type(pci_conf->serr_irq, IRQ_TYPE_LEVEL_LOW);
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} else {
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printk(KERN_WARNING "%s(): Failed to claim PCI SERR# "
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"PIO!\n", __func__);
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pci_conf->serr_irq = PCI_PIN_UNUSED;
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}
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break;
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case PCI_PIN_ALTERNATIVE:
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/* No alternative here */
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BUG();
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pci_conf->serr_irq = PCI_PIN_UNUSED;
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break;
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}
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if (pci_conf->serr_irq == PCI_PIN_UNUSED) {
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/* "Disable" the SERR IRQ resource (it's last on the list) */
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fli7510_pci_device.num_resources--;
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} else {
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struct resource *res = platform_get_resource_byname(
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&fli7510_pci_device, IORESOURCE_IRQ,
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"pci serr");
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res->start = pci_conf->serr_irq;
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res->end = pci_conf->serr_irq;
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}
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fli7510_pci_device.dev.parent =
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bus_find_device_by_name(&platform_bus_type, NULL, "emi");
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platform_device_register(&fli7510_pci_device);
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}
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static struct pcie_sysconfs {
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struct sysconf_field *reg1;
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struct sysconf_field *reg3;
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struct sysconf_field *reg4;
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} fli7540_pcie_sysconfs;
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/* REG1_PCIE_CORE_MIPHY_INIT */
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#define MIPHY_OSC_MODE_GM (1<<0)
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#define MIPHY_OSC_MODE_MILLER (1<<1)
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#define MIPHY_PLL_REF_DIV_BY_2 (1<<2)
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#define MIPHY_P1_TX_LSPD (1<<3)
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#define MIPHY_P1_RX_LSPD (1<<4)
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#define MIPHY_P1_SSC_EN (1<<5)
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#define MIPHY_P1_NEARAFELB (1<<6)
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#define MIPHY_P1_FARAFELB (1<<7)
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#define MIPHY_PCIE_SOFT_RST_N (1<<8)
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#define MIPHY_P1_SERDES_IDDQ (1<<9)
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#define DFT_DEBUG_SEL (1<<10)
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#define PCIE_PREFETCH_BRIDGE_EN (1<<11)
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/* REG3_MIPHY_INIT */
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#define MIPHY_P1_OSC_BYPASS (1<<0)
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#define PCIE_DEVICE_TYPE_RC (1<<1)
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#define MIPHY_P1_OSC_FORCE_EXT (1<<2)
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#define MIPHY_OSC_EXT_SEL (1<<3)
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/* REG4_PCIE_CORE_LINK_CTRL */
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#define PCIE_APP_LTSSM_ENABLE (1<<0)
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#define PCIE_APP_REQ_RETRY_EN (1<<1)
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#define PCIE_CFG_LANE_EN (1<<2)
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#define PCIE_DEBUG_ADD_MASK 0x7f8
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#define PCIE_DEBUG_ADD(x) (((x) << 3) & PCIE_DEBUG_ADD_MASK)
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#define PCIE_DEBUG_MODE (1<<11)
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#define PCIE_APP_INIT_RST (1<<12)
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#define PCIE_SYS_INT (1<<13)
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static void fli7540_pcie_init(void *handle)
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{
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struct pcie_sysconfs *sys = handle;
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u32 data;
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/* Force external clock to be used */
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sysconf_write(sys->reg3, MIPHY_P1_OSC_BYPASS |
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PCIE_DEVICE_TYPE_RC);
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/* Soft reset the PCIE core. This then selects if you
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* are in root complex or endpoint mode
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*/
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data = sysconf_read(sys->reg1);
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sysconf_write(sys->reg1, data | MIPHY_PCIE_SOFT_RST_N);
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}
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static void fli7540_pcie_ltssm_disable(void *handle)
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{
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struct pcie_sysconfs *sys = handle;
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sysconf_write(sys->reg4, 0);
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}
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static void fli7540_pcie_ltssm_enable(void *handle)
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{
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struct pcie_sysconfs *sys = handle;
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sysconf_write(sys->reg4, PCIE_APP_LTSSM_ENABLE);
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}
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/* Ops to drive the platform specific bits of the interface */
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static struct stm_plat_pcie_ops fli7540_pcie_ops = {
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.init = fli7540_pcie_init,
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.enable_ltssm = fli7540_pcie_ltssm_enable,
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.disable_ltssm = fli7540_pcie_ltssm_disable,
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};
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static struct stm_plat_pcie_config fli7540_plat_pcie_config = {
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.ahb_val = 0x264207,
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.ops_handle = &fli7540_pcie_sysconfs,
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.ops = &fli7540_pcie_ops,
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};
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#define PCIE_MEM_START 0xc0000000
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#define PCIE_MEM_SIZE 0x3c00000
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#define PCIE_CNTRL_REG_SIZE 0x1000
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#define PCIE_AHB_REG_SIZE 0x8
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#define MSI_FIRST_IRQ (NR_IRQS - 33)
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#define MSI_LAST_IRQ (NR_IRQS - 1)
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static struct platform_device fli7540_pcie_device = {
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.name = "pcie_stm",
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.id = -1,
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.num_resources = 8,
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.resource = (struct resource[]) {
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/* Main PCI window, 960 MB */
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STM_PLAT_RESOURCE_MEM_NAMED("pcie memory",
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PCIE_MEM_START, PCIE_MEM_SIZE),
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/* There actually is no IO for the PCI express cell, so this
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* is a dummy really. Must be disjoint from PCI
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*/
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{
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.name = "pcie io",
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.start = 0x10000,
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.end = 0x1ffff,
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.flags = IORESOURCE_IO,
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},
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STM_PLAT_RESOURCE_MEM_NAMED("pcie cntrl", 0xfe100000,
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PCIE_CNTRL_REG_SIZE),
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/* Cut 1 moves where this is, probed dynamically */
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STM_PLAT_RESOURCE_MEM_NAMED("pcie ahb", 0xfe180000,
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PCIE_AHB_REG_SIZE),
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STM_PLAT_RESOURCE_IRQ_NAMED("pcie inta", ILC_IRQ(133), -1),
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STM_PLAT_RESOURCE_IRQ_NAMED("pcie syserr", ILC_IRQ(135), -1),
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STM_PLAT_RESOURCE_IRQ_NAMED("msi mux", ILC_IRQ(134), -1),
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{
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.start = MSI_FIRST_IRQ,
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.end = MSI_LAST_IRQ,
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.name = "msi range",
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.flags = IORESOURCE_IRQ,
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}
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},
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.dev.platform_data = &fli7540_plat_pcie_config,
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};
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void __init fli7540_configure_pcie(struct fli7540_pcie_config *config)
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{
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struct resource *res;
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/* Cut1 of the Freeman ultra moves where the spare regs and the ahb
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* bridge are. We adjust them accordingly here. Strangely the spare
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* registers appear to be replicated at the old address as well.
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*/
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if (cpu_data->cut_major >= 1) {
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res = platform_get_resource_byname(&fli7540_pcie_device,
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IORESOURCE_MEM, "pcie ahb");
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BUG_ON(!res);
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res->start = 0xfe108000;
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res->end = res->start + PCIE_AHB_REG_SIZE - 1;
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}
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/* Claim the sysconfs in the PCIE spare block */
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fli7540_pcie_sysconfs.reg1 = sysconf_claim(
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CFG_REG1_PCIE_CORE_MIPHY_INIT, 0, 11, "pcie");
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fli7540_pcie_sysconfs.reg3 = sysconf_claim(
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CFG_REG3_MIPHY_INIT, 0, 3, "pcie");
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fli7540_pcie_sysconfs.reg4 = sysconf_claim(
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CFG_REG4_PCIE_CORE_LINK_CTRL, 0, 13, "pcie");
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fli7540_plat_pcie_config.reset_gpio = config->reset_gpio;
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fli7540_plat_pcie_config.reset = config->reset;
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/* Freeman only has one miphy */
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fli7540_plat_pcie_config.miphy_num = 0;
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platform_device_register(&fli7540_pcie_device);
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}
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