389 lines
11 KiB
C
389 lines
11 KiB
C
/*
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* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained from Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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/**
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* @file mali_platform.c
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* Platform specific Mali driver functions for Mali 400 PMU hardware
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*/
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#include "mali_kernel_common.h"
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#include "mali_osk.h"
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#include "mali_platform.h"
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#if USING_MALI_PMM
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#include "mali_pmm.h"
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/* Internal test on/off */
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#define PMU_TEST 0
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/** @brief PMU hardware info
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*/
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typedef struct platform_pmu
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{
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u32 reg_base_addr; /**< PMU registers base address */
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u32 reg_size; /**< PMU registers size */
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const char *name; /**< PMU name */
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u32 irq_num; /**< PMU irq number */
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mali_io_address reg_mapped; /**< IO-mapped pointer to registers */
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} platform_pmu_t;
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static platform_pmu_t *pmu_info = NULL;
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/** @brief Register layout for hardware PMU
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*/
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typedef enum {
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PMU_REG_ADDR_MGMT_POWER_UP = 0x00, /*< Power up register */
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PMU_REG_ADDR_MGMT_POWER_DOWN = 0x04, /*< Power down register */
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PMU_REG_ADDR_MGMT_STATUS = 0x08, /*< Core sleep status register */
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PMU_REG_ADDR_MGMT_INT_MASK = 0x0C, /*< Interrupt mask register */
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PMU_REG_ADDR_MGMT_INT_RAWSTAT = 0x10, /*< Interrupt raw status register */
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PMU_REG_ADDR_MGMT_INT_STAT = 0x14, /*< Interrupt status register */
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PMU_REG_ADDR_MGMT_INT_CLEAR = 0x18, /*< Interrupt clear register */
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PMU_REG_ADDR_MGMT_SW_DELAY = 0x1C, /*< Software delay register */
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PMU_REG_ADDR_MGMT_MASTER_PWR_UP = 0x24, /*< Master power up register */
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PMU_REGISTER_ADDRESS_SPACE_SIZE = 0x28, /*< Size of register space */
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} pmu_reg_addr_mgmt_addr;
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/* Internal functions */
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u32 pmu_reg_read(platform_pmu_t *pmu, u32 relative_address);
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void pmu_reg_write(platform_pmu_t *pmu, u32 relative_address, u32 new_val);
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mali_pmm_core_mask pmu_translate_cores_to_pmu(mali_pmm_core_mask cores);
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#if PMU_TEST
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void pmm_pmu_dump_regs( platform_pmu_t *pmu );
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void pmm_pmu_test( platform_pmu_t *pmu, u32 cores );
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#endif
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#endif /* USING_MALI_PMM */
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_mali_osk_errcode_t mali_platform_init(_mali_osk_resource_t *resource)
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{
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#if USING_MALI_PMM
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if( resource == NULL )
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{
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/* Nothing to set up for the system */
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}
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else if( resource->type == PMU )
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{
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if( (resource->base == 0) ||
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(resource->description == NULL) )
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{
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/* NOTE: We currently don't care about any other resource settings */
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MALI_PRINT_ERROR(("PLATFORM mali400-pmu: Missing PMU set up information\n"));
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MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
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}
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MALI_DEBUG_ASSERT( pmu_info == NULL );
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pmu_info = (platform_pmu_t *)_mali_osk_malloc(sizeof(*pmu_info));
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MALI_CHECK_NON_NULL( pmu_info, _MALI_OSK_ERR_NOMEM );
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/* All values get 0 as default */
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_mali_osk_memset(pmu_info, 0, sizeof(*pmu_info));
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pmu_info->reg_base_addr = resource->base;
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pmu_info->reg_size = (u32)PMU_REGISTER_ADDRESS_SPACE_SIZE;
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pmu_info->name = resource->description;
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pmu_info->irq_num = resource->irq;
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if( _MALI_OSK_ERR_OK != _mali_osk_mem_reqregion(pmu_info->reg_base_addr, pmu_info->reg_size, pmu_info->name) )
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{
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MALI_PRINT_ERROR(("PLATFORM mali400-pmu: Could not request register region (0x%08X - 0x%08X) for %s\n",
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pmu_info->reg_base_addr, pmu_info->reg_base_addr + pmu_info->reg_size - 1, pmu_info->name));
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goto cleanup;
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}
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else
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{
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MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Success: request_mem_region: (0x%08X - 0x%08X) for %s\n",
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pmu_info->reg_base_addr, pmu_info->reg_base_addr + pmu_info->reg_size - 1, pmu_info->name));
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}
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pmu_info->reg_mapped = _mali_osk_mem_mapioregion( pmu_info->reg_base_addr, pmu_info->reg_size, pmu_info->name );
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if( 0 == pmu_info->reg_mapped )
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{
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MALI_PRINT_ERROR(("PLATFORM mali400-pmu: Could not ioremap registers for %s .\n", pmu_info->name));
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_mali_osk_mem_unreqregion( pmu_info->reg_base_addr, pmu_info->reg_size );
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goto cleanup;
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}
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else
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{
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MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Success: ioremap_nocache: Internal ptr: (0x%08X - 0x%08X) for %s\n",
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(u32) pmu_info->reg_mapped,
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((u32)pmu_info->reg_mapped)+ pmu_info->reg_size - 1,
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pmu_info->name));
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}
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MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Success: Mapping registers to %s\n", pmu_info->name));
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#if PMU_TEST
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pmu_test(pmu_info, (MALI_PMM_CORE_GP));
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pmu_test(pmu_info, (MALI_PMM_CORE_GP|MALI_PMM_CORE_L2|MALI_PMM_CORE_PP0));
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#endif
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MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Initialized - %s\n", pmu_info->name) );
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}
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else
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{
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/* Didn't expect a different resource */
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MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
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}
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MALI_SUCCESS;
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cleanup:
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_mali_osk_free(pmu_info);
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pmu_info = NULL;
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MALI_ERROR(_MALI_OSK_ERR_NOMEM);
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#else
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/* Nothing to do when not using PMM - as mali already on */
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MALI_SUCCESS;
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#endif
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}
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_mali_osk_errcode_t mali_platform_deinit(_mali_osk_resource_type_t *type)
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{
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#if USING_MALI_PMM
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if( type == NULL )
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{
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/* Nothing to tear down for the system */
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}
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else if (*type == PMU)
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{
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if( pmu_info )
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{
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_mali_osk_mem_unmapioregion(pmu_info->reg_base_addr, pmu_info->reg_size, pmu_info->reg_mapped);
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_mali_osk_mem_unreqregion(pmu_info->reg_base_addr, pmu_info->reg_size);
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_mali_osk_free(pmu_info);
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pmu_info = NULL;
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MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Terminated PMU\n") );
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}
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}
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else
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{
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/* Didn't expect a different resource */
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MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
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}
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MALI_SUCCESS;
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#else
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/* Nothing to do when not using PMM */
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MALI_SUCCESS;
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#endif
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}
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_mali_osk_errcode_t mali_platform_powerdown(u32 cores)
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{
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#if USING_MALI_PMM
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u32 stat;
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u32 timeout;
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u32 cores_pmu;
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MALI_DEBUG_ASSERT_POINTER(pmu_info);
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MALI_DEBUG_ASSERT( cores != 0 ); /* Shouldn't receive zero from PMM */
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MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: power down (0x%x)\n", cores) );
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cores_pmu = pmu_translate_cores_to_pmu(cores);
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pmu_reg_write( pmu_info, (u32)PMU_REG_ADDR_MGMT_POWER_DOWN, cores_pmu );
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/* Wait for cores to be powered down */
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timeout = 10; /* 10ms */
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do
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{
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/* Get status of sleeping cores */
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stat = pmu_reg_read( pmu_info, (u32)PMU_REG_ADDR_MGMT_STATUS );
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stat &= cores_pmu;
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if( stat == cores_pmu ) break; /* All cores we wanted are now asleep */
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_mali_osk_time_ubusydelay(1000); /* 1ms */
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timeout--;
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} while( timeout > 0 );
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if( timeout == 0 ) MALI_ERROR(_MALI_OSK_ERR_TIMEOUT);
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MALI_SUCCESS;
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#else
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/* Nothing to do when not using PMM */
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MALI_SUCCESS;
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#endif
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}
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_mali_osk_errcode_t mali_platform_powerup(u32 cores)
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{
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#if USING_MALI_PMM
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u32 cores_pmu;
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u32 stat;
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u32 timeout;
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MALI_DEBUG_ASSERT_POINTER(pmu_info);
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MALI_DEBUG_ASSERT( cores != 0 ); /* Shouldn't receive zero from PMM */
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MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: power up (0x%x)\n", cores) );
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/* Don't use interrupts - just poll status */
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pmu_reg_write( pmu_info, (u32)PMU_REG_ADDR_MGMT_INT_MASK, 0 );
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cores_pmu = pmu_translate_cores_to_pmu(cores);
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pmu_reg_write( pmu_info, (u32)PMU_REG_ADDR_MGMT_POWER_UP, cores_pmu );
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timeout = 10; /* 10ms */
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do
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{
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/* Get status of sleeping cores */
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stat = pmu_reg_read( pmu_info, (u32)PMU_REG_ADDR_MGMT_STATUS );
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stat &= cores_pmu;
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if( stat == 0 ) break; /* All cores we wanted are now awake */
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_mali_osk_time_ubusydelay(1000); /* 1ms */
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timeout--;
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} while( timeout > 0 );
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if( timeout == 0 ) MALI_ERROR(_MALI_OSK_ERR_TIMEOUT);
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MALI_SUCCESS;
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#else
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/* Nothing to do when not using PMM */
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MALI_SUCCESS;
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#endif
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}
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void mali_gpu_utilization_handler(u32 utilization)
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{
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}
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#if USING_MALI_PMM
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/***** INTERNAL *****/
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/** @brief Internal PMU function to translate the cores bit mask
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* into something the hardware PMU understands
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*
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* @param cores PMM cores bitmask
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* @return PMU hardware cores bitmask
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*/
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u32 pmu_translate_cores_to_pmu(mali_pmm_core_mask cores)
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{
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/* For Mali 400 PMU the cores mask is already the same as what
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* the hardware PMU expects.
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* For other hardware, some translation can be done here, by
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* translating the MALI_PMM_CORE_* bits into specific hardware
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* bits
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*/
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return cores;
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}
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/** @brief Internal PMU function to read a PMU register
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*
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* @param pmu handle that identifies the PMU hardware
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* @param relative_address relative PMU hardware address to read from
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* @return 32-bit value that was read from the address
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*/
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u32 pmu_reg_read(platform_pmu_t *pmu, u32 relative_address)
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{
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u32 read_val;
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MALI_DEBUG_ASSERT_POINTER(pmu);
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MALI_DEBUG_ASSERT((relative_address & 0x03) == 0);
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MALI_DEBUG_ASSERT(relative_address < pmu->reg_size);
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read_val = _mali_osk_mem_ioread32(pmu->reg_mapped, relative_address);
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MALI_DEBUG_PRINT( 5, ("PMU: reg_read: %s Addr:0x%04X Val:0x%08x\n",
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pmu->name, relative_address, read_val));
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return read_val;
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}
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/** @brief Internal PMU function to write to a PMU register
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*
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* @param pmu handle that identifies the PMU hardware
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* @param relative_address relative PMU hardware address to write to
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* @param new_val new 32-bit value to write into the address
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*/
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void pmu_reg_write(platform_pmu_t *pmu, u32 relative_address, u32 new_val)
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{
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MALI_DEBUG_ASSERT_POINTER(pmu);
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MALI_DEBUG_ASSERT((relative_address & 0x03) == 0);
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MALI_DEBUG_ASSERT(relative_address < pmu->reg_size);
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MALI_DEBUG_PRINT( 5, ("PMU: reg_write: %s Addr:0x%04X Val:0x%08x\n",
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pmu->name, relative_address, new_val));
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_mali_osk_mem_iowrite32(pmu->reg_mapped, relative_address, new_val);
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}
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#if MALI_POWER_MGMT_TEST_SUITE
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u32 pmu_get_power_up_down_info(void)
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{
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return pmu_reg_read(pmu_info, (u32)PMU_REG_ADDR_MGMT_STATUS);
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}
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#endif /* MALI_POWER_MGMT_TEST_SUITE */
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#endif /* USING_MALI_PMM */
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#if USING_MALI_PMM && PMU_TEST
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/***** TEST *****/
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void pmu_dump_regs( platform_pmu_t *pmu )
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{
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u32 addr;
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for( addr = 0x0; addr < PMU_REGISTER_ADDRESS_SPACE_SIZE; addr += 0x4 )
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{
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MALI_PRINT( ("PMU_REG: 0x%08x: 0x%04x\n", (addr + pmu->reg_base_addr), pmu_reg_read( pmu, addr ) ) );
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}
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}
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/* This function is an internal test for the PMU without any Mali h/w interaction */
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void pmu_test( platform_pmu_t *pmu, u32 cores )
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{
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u32 stat;
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u32 timeout;
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MALI_PRINT( ("PMU_TEST: Start\n") );
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pmu_dump_regs( pmu );
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MALI_PRINT( ("PMU_TEST: Power down cores: 0x%x\n", cores) );
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_mali_pmm_pmu_power_down( pmu, cores, MALI_TRUE );
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stat = pmu_reg_read( pmu, (u32)PMU_REG_ADDR_MGMT_STATUS );
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MALI_PRINT( ("PMU_TEST: %s\n", (stat & cores) == cores ? "SUCCESS" : "FAIL" ) );
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pmu_dump_regs( pmu );
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MALI_PRINT( ("PMU_TEST: Power up cores: 0x%x\n", cores) );
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_mali_pmm_pmu_power_up( pmu, cores, MALI_FALSE );
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MALI_PRINT( ("PMU_TEST: Waiting for power up...\n") );
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timeout = 1000; /* 1 sec */
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while( !_mali_pmm_pmu_irq_power_up(pmu) && timeout > 0 )
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{
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_mali_osk_time_ubusydelay(1000); /* 1ms */
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timeout--;
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}
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MALI_PRINT( ("PMU_TEST: Waited %dms for interrupt\n", (1000-timeout)) );
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stat = pmu_reg_read( pmu, (u32)PMU_REG_ADDR_MGMT_STATUS );
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MALI_PRINT( ("PMU_TEST: %s\n", (stat & cores) == 0 ? "SUCCESS" : "FAIL" ) );
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_mali_pmm_pmu_irq_power_up_clear(pmu);
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pmu_dump_regs( pmu );
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MALI_PRINT( ("PMU_TEST: Finish\n") );
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}
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#endif /* USING_MALI_PMM && PMU_TEST */
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