479 lines
14 KiB
C
479 lines
14 KiB
C
/* sun4m_irq.c
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* arch/sparc/kernel/sun4m_irq.c:
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*
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* djhr: Hacked out of irq.c into a CPU dependent version.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
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* Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
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* Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
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*/
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/psr.h>
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#include <asm/vaddrs.h>
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#include <asm/timer.h>
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#include <asm/openprom.h>
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#include <asm/oplib.h>
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#include <asm/traps.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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#include <asm/smp.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/cacheflush.h>
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#include "irq.h"
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struct sun4m_irq_percpu {
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u32 pending;
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u32 clear;
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u32 set;
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};
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struct sun4m_irq_global {
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u32 pending;
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u32 mask;
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u32 mask_clear;
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u32 mask_set;
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u32 interrupt_target;
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};
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/* Code in entry.S needs to get at these register mappings. */
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struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
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struct sun4m_irq_global __iomem *sun4m_irq_global;
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/* Dave Redman (djhr@tadpole.co.uk)
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* The sun4m interrupt registers.
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*/
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#define SUN4M_INT_ENABLE 0x80000000
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#define SUN4M_INT_E14 0x00000080
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#define SUN4M_INT_E10 0x00080000
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#define SUN4M_HARD_INT(x) (0x000000001 << (x))
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#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
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#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
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#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
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#define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */
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#define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */
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#define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */
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#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
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#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
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#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
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#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
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#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
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#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
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#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
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#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
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#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
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#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
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#define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */
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#define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR | \
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SUN4M_INT_M2S_WRITE_ERR | \
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SUN4M_INT_ECC_ERR | \
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SUN4M_INT_VME_ERR)
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#define SUN4M_INT_SBUS(x) (1 << (x+7))
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#define SUN4M_INT_VME(x) (1 << (x))
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/* Interrupt levels used by OBP */
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#define OBP_INT_LEVEL_SOFT 0x10
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#define OBP_INT_LEVEL_ONBOARD 0x20
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#define OBP_INT_LEVEL_SBUS 0x30
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#define OBP_INT_LEVEL_VME 0x40
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/* Interrupt level assignment on sun4m:
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*
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* level source
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* ------------------------------------------------------------
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* 1 softint-1
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* 2 softint-2, VME/SBUS level 1
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* 3 softint-3, VME/SBUS level 2
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* 4 softint-4, onboard SCSI
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* 5 softint-5, VME/SBUS level 3
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* 6 softint-6, onboard ETHERNET
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* 7 softint-7, VME/SBUS level 4
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* 8 softint-8, onboard VIDEO
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* 9 softint-9, VME/SBUS level 5, Module Interrupt
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* 10 softint-10, system counter/timer
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* 11 softint-11, VME/SBUS level 6, Floppy
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* 12 softint-12, Keyboard/Mouse, Serial
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* 13 softint-13, VME/SBUS level 7, ISDN Audio
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* 14 softint-14, per-processor counter/timer
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* 15 softint-15, Asynchronous Errors (broadcast)
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*
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* Each interrupt source is masked distinctly in the sun4m interrupt
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* registers. The PIL level alone is therefore ambiguous, since multiple
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* interrupt sources map to a single PIL.
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*
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* This ambiguity is resolved in the 'intr' property for device nodes
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* in the OF device tree. Each 'intr' property entry is composed of
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* two 32-bit words. The first word is the IRQ priority value, which
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* is what we're intersted in. The second word is the IRQ vector, which
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* is unused.
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*
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* The low 4 bits of the IRQ priority indicate the PIL, and the upper
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* 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20
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* means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled.
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*
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* For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
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* whereas a value of 0x33 is SBUS level 2. Here are some sample
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* 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
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* Tadpole S3 GX systems.
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*
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* esp: 0x24 onboard ESP SCSI
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* le: 0x26 onboard Lance ETHERNET
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* p9100: 0x32 SBUS level 1 P9100 video
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* bpp: 0x33 SBUS level 2 BPP parallel port device
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* DBRI: 0x39 SBUS level 5 DBRI ISDN audio
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* SUNW,leo: 0x39 SBUS level 5 LEO video
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* pcmcia: 0x3b SBUS level 6 PCMCIA controller
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* uctrl: 0x3b SBUS level 6 UCTRL device
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* modem: 0x3d SBUS level 7 MODEM
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* zs: 0x2c onboard keyboard/mouse/serial
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* floppy: 0x2b onboard Floppy
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* power: 0x22 onboard power device (XXX unknown mask bit XXX)
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*/
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static unsigned long irq_mask[0x50] = {
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/* SMP */
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0, SUN4M_SOFT_INT(1),
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SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
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SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
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SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
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SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
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SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
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SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
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SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
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/* soft */
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0, SUN4M_SOFT_INT(1),
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SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
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SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
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SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
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SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
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SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
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SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
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SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
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/* onboard */
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0, 0, 0, 0,
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SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0,
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SUN4M_INT_VIDEO, SUN4M_INT_MODULE,
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SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY,
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(SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),
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SUN4M_INT_AUDIO, 0, SUN4M_INT_MODULE_ERR,
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/* sbus */
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0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1),
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0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3),
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0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5),
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0, SUN4M_INT_SBUS(6), 0, 0,
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/* vme */
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0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1),
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0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3),
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0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5),
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0, SUN4M_INT_VME(6), 0, 0
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};
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static unsigned long sun4m_get_irqmask(unsigned int irq)
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{
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unsigned long mask;
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if (irq < 0x50)
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mask = irq_mask[irq];
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else
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mask = 0;
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if (!mask)
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printk(KERN_ERR "sun4m_get_irqmask: IRQ%d has no valid mask!\n",
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irq);
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return mask;
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}
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static void sun4m_disable_irq(unsigned int irq_nr)
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{
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unsigned long mask, flags;
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int cpu = smp_processor_id();
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mask = sun4m_get_irqmask(irq_nr);
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local_irq_save(flags);
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if (irq_nr > 15)
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sbus_writel(mask, &sun4m_irq_global->mask_set);
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else
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sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
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local_irq_restore(flags);
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}
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static void sun4m_enable_irq(unsigned int irq_nr)
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{
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unsigned long mask, flags;
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int cpu = smp_processor_id();
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/* Dreadful floppy hack. When we use 0x2b instead of
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* 0x0b the system blows (it starts to whistle!).
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* So we continue to use 0x0b. Fixme ASAP. --P3
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*/
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if (irq_nr != 0x0b) {
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mask = sun4m_get_irqmask(irq_nr);
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local_irq_save(flags);
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if (irq_nr > 15)
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sbus_writel(mask, &sun4m_irq_global->mask_clear);
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else
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sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
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local_irq_restore(flags);
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} else {
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local_irq_save(flags);
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sbus_writel(SUN4M_INT_FLOPPY, &sun4m_irq_global->mask_clear);
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local_irq_restore(flags);
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}
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}
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static unsigned long cpu_pil_to_imask[16] = {
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/*0*/ 0x00000000,
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/*1*/ 0x00000000,
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/*2*/ SUN4M_INT_SBUS(0) | SUN4M_INT_VME(0),
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/*3*/ SUN4M_INT_SBUS(1) | SUN4M_INT_VME(1),
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/*4*/ SUN4M_INT_SCSI,
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/*5*/ SUN4M_INT_SBUS(2) | SUN4M_INT_VME(2),
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/*6*/ SUN4M_INT_ETHERNET,
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/*7*/ SUN4M_INT_SBUS(3) | SUN4M_INT_VME(3),
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/*8*/ SUN4M_INT_VIDEO,
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/*9*/ SUN4M_INT_SBUS(4) | SUN4M_INT_VME(4) | SUN4M_INT_MODULE_ERR,
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/*10*/ SUN4M_INT_REALTIME,
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/*11*/ SUN4M_INT_SBUS(5) | SUN4M_INT_VME(5) | SUN4M_INT_FLOPPY,
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/*12*/ SUN4M_INT_SERIAL | SUN4M_INT_KBDMS,
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/*13*/ SUN4M_INT_SBUS(6) | SUN4M_INT_VME(6) | SUN4M_INT_AUDIO,
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/*14*/ SUN4M_INT_E14,
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/*15*/ SUN4M_INT_ERROR
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};
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/* We assume the caller has disabled local interrupts when these are called,
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* or else very bizarre behavior will result.
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*/
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static void sun4m_disable_pil_irq(unsigned int pil)
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{
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sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_set);
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}
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static void sun4m_enable_pil_irq(unsigned int pil)
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{
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sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_clear);
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}
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#ifdef CONFIG_SMP
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static void sun4m_send_ipi(int cpu, int level)
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{
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unsigned long mask = sun4m_get_irqmask(level);
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sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
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}
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static void sun4m_clear_ipi(int cpu, int level)
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{
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unsigned long mask = sun4m_get_irqmask(level);
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sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
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}
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static void sun4m_set_udt(int cpu)
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{
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sbus_writel(cpu, &sun4m_irq_global->interrupt_target);
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}
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#endif
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struct sun4m_timer_percpu {
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u32 l14_limit;
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u32 l14_count;
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u32 l14_limit_noclear;
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u32 user_timer_start_stop;
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};
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static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
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struct sun4m_timer_global {
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u32 l10_limit;
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u32 l10_count;
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u32 l10_limit_noclear;
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u32 reserved;
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u32 timer_config;
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};
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static struct sun4m_timer_global __iomem *timers_global;
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#define TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10)
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unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
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static void sun4m_clear_clock_irq(void)
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{
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sbus_readl(&timers_global->l10_limit);
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}
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void sun4m_nmi(struct pt_regs *regs)
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{
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unsigned long afsr, afar, si;
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printk(KERN_ERR "Aieee: sun4m NMI received!\n");
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/* XXX HyperSparc hack XXX */
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__asm__ __volatile__("mov 0x500, %%g1\n\t"
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"lda [%%g1] 0x4, %0\n\t"
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"mov 0x600, %%g1\n\t"
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"lda [%%g1] 0x4, %1\n\t" :
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"=r" (afsr), "=r" (afar));
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printk(KERN_ERR "afsr=%08lx afar=%08lx\n", afsr, afar);
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si = sbus_readl(&sun4m_irq_global->pending);
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printk(KERN_ERR "si=%08lx\n", si);
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if (si & SUN4M_INT_MODULE_ERR)
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printk(KERN_ERR "Module async error\n");
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if (si & SUN4M_INT_M2S_WRITE_ERR)
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printk(KERN_ERR "MBus/SBus async error\n");
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if (si & SUN4M_INT_ECC_ERR)
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printk(KERN_ERR "ECC memory error\n");
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if (si & SUN4M_INT_VME_ERR)
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printk(KERN_ERR "VME async error\n");
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printk(KERN_ERR "you lose buddy boy...\n");
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show_regs(regs);
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prom_halt();
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}
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/* Exported for sun4m_smp.c */
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void sun4m_clear_profile_irq(int cpu)
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{
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sbus_readl(&timers_percpu[cpu]->l14_limit);
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}
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static void sun4m_load_profile_irq(int cpu, unsigned int limit)
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{
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sbus_writel(limit, &timers_percpu[cpu]->l14_limit);
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}
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static void __init sun4m_init_timers(irq_handler_t counter_fn)
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{
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struct device_node *dp = of_find_node_by_name(NULL, "counter");
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int i, err, len, num_cpu_timers;
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const u32 *addr;
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if (!dp) {
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printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
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return;
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}
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addr = of_get_property(dp, "address", &len);
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of_node_put(dp);
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if (!addr) {
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printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
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return;
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}
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num_cpu_timers = (len / sizeof(u32)) - 1;
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for (i = 0; i < num_cpu_timers; i++) {
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timers_percpu[i] = (void __iomem *)
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(unsigned long) addr[i];
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}
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timers_global = (void __iomem *)
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(unsigned long) addr[num_cpu_timers];
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sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit);
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master_l10_counter = &timers_global->l10_count;
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err = request_irq(TIMER_IRQ, counter_fn,
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(IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL);
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if (err) {
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printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
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err);
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return;
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}
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for (i = 0; i < num_cpu_timers; i++)
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sbus_writel(0, &timers_percpu[i]->l14_limit);
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if (num_cpu_timers == 4)
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sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);
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#ifdef CONFIG_SMP
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{
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unsigned long flags;
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extern unsigned long lvl14_save[4];
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struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
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/* For SMP we use the level 14 ticker, however the bootup code
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* has copied the firmware's level 14 vector into the boot cpu's
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* trap table, we must fix this now or we get squashed.
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*/
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local_irq_save(flags);
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trap_table->inst_one = lvl14_save[0];
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trap_table->inst_two = lvl14_save[1];
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trap_table->inst_three = lvl14_save[2];
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trap_table->inst_four = lvl14_save[3];
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local_flush_cache_all();
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local_irq_restore(flags);
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}
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#endif
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}
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void __init sun4m_init_IRQ(void)
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{
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struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
|
|
int len, i, mid, num_cpu_iregs;
|
|
const u32 *addr;
|
|
|
|
if (!dp) {
|
|
printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
|
|
return;
|
|
}
|
|
|
|
addr = of_get_property(dp, "address", &len);
|
|
of_node_put(dp);
|
|
if (!addr) {
|
|
printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
|
|
return;
|
|
}
|
|
|
|
num_cpu_iregs = (len / sizeof(u32)) - 1;
|
|
for (i = 0; i < num_cpu_iregs; i++) {
|
|
sun4m_irq_percpu[i] = (void __iomem *)
|
|
(unsigned long) addr[i];
|
|
}
|
|
sun4m_irq_global = (void __iomem *)
|
|
(unsigned long) addr[num_cpu_iregs];
|
|
|
|
local_irq_disable();
|
|
|
|
sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
|
|
for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
|
|
sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);
|
|
|
|
if (num_cpu_iregs == 4)
|
|
sbus_writel(0, &sun4m_irq_global->interrupt_target);
|
|
|
|
BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
|
|
BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
|
|
BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
|
|
BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
|
|
BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
|
|
BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
|
|
sparc_init_timers = sun4m_init_timers;
|
|
#ifdef CONFIG_SMP
|
|
BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
|
|
BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
|
|
BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
|
|
#endif
|
|
|
|
/* Cannot enable interrupts until OBP ticker is disabled. */
|
|
}
|