241 lines
5.0 KiB
C
241 lines
5.0 KiB
C
/*
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* iop13xx IRQ handling / support functions
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* Copyright (c) 2005-2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/sysctl.h>
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#include <asm/uaccess.h>
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#include <asm/mach/irq.h>
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <mach/msi.h>
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/* INTCTL0 CP6 R0 Page 4
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*/
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static u32 read_intctl_0(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
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return val;
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}
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static void write_intctl_0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
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}
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/* INTCTL1 CP6 R1 Page 4
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*/
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static u32 read_intctl_1(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
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return val;
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}
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static void write_intctl_1(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
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}
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/* INTCTL2 CP6 R2 Page 4
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*/
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static u32 read_intctl_2(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
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return val;
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}
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static void write_intctl_2(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
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}
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/* INTCTL3 CP6 R3 Page 4
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*/
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static u32 read_intctl_3(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
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return val;
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}
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static void write_intctl_3(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
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}
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/* INTSTR0 CP6 R0 Page 5
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*/
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static void write_intstr_0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
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}
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/* INTSTR1 CP6 R1 Page 5
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*/
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static void write_intstr_1(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
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}
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/* INTSTR2 CP6 R2 Page 5
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*/
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static void write_intstr_2(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
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}
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/* INTSTR3 CP6 R3 Page 5
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*/
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static void write_intstr_3(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
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}
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/* INTBASE CP6 R0 Page 2
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*/
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static void write_intbase(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
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}
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/* INTSIZE CP6 R2 Page 2
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*/
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static void write_intsize(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
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}
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/* 0 = Interrupt Masked and 1 = Interrupt not masked */
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static void
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iop13xx_irq_mask0 (unsigned int irq)
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{
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write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
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}
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static void
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iop13xx_irq_mask1 (unsigned int irq)
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{
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write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
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}
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static void
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iop13xx_irq_mask2 (unsigned int irq)
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{
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write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
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}
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static void
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iop13xx_irq_mask3 (unsigned int irq)
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{
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write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
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}
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static void
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iop13xx_irq_unmask0(unsigned int irq)
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{
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write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
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}
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static void
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iop13xx_irq_unmask1(unsigned int irq)
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{
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write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
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}
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static void
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iop13xx_irq_unmask2(unsigned int irq)
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{
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write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
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}
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static void
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iop13xx_irq_unmask3(unsigned int irq)
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{
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write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
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}
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static struct irq_chip iop13xx_irqchip1 = {
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.name = "IOP13xx-1",
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.ack = iop13xx_irq_mask0,
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.mask = iop13xx_irq_mask0,
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.unmask = iop13xx_irq_unmask0,
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};
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static struct irq_chip iop13xx_irqchip2 = {
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.name = "IOP13xx-2",
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.ack = iop13xx_irq_mask1,
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.mask = iop13xx_irq_mask1,
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.unmask = iop13xx_irq_unmask1,
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};
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static struct irq_chip iop13xx_irqchip3 = {
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.name = "IOP13xx-3",
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.ack = iop13xx_irq_mask2,
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.mask = iop13xx_irq_mask2,
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.unmask = iop13xx_irq_unmask2,
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};
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static struct irq_chip iop13xx_irqchip4 = {
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.name = "IOP13xx-4",
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.ack = iop13xx_irq_mask3,
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.mask = iop13xx_irq_mask3,
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.unmask = iop13xx_irq_unmask3,
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};
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extern void iop_init_cp6_handler(void);
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void __init iop13xx_init_irq(void)
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{
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unsigned int i;
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iop_init_cp6_handler();
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/* disable all interrupts */
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write_intctl_0(0);
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write_intctl_1(0);
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write_intctl_2(0);
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write_intctl_3(0);
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/* treat all as IRQ */
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write_intstr_0(0);
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write_intstr_1(0);
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write_intstr_2(0);
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write_intstr_3(0);
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/* initialize the interrupt vector generator */
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write_intbase(INTBASE);
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write_intsize(INTSIZE_4);
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for(i = 0; i <= IRQ_IOP13XX_HPI; i++) {
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if (i < 32)
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set_irq_chip(i, &iop13xx_irqchip1);
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else if (i < 64)
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set_irq_chip(i, &iop13xx_irqchip2);
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else if (i < 96)
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set_irq_chip(i, &iop13xx_irqchip3);
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else
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set_irq_chip(i, &iop13xx_irqchip4);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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iop13xx_msi_init();
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}
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