570 lines
16 KiB
C
570 lines
16 KiB
C
/*
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* arch/sh/boards/st/mb628/setup.c
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*
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* Copyright (C) 2008 STMicroelectronics Limited
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* Author: Stuart Menefy (stuart.menefy@st.com)
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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* STMicroelectronics STx7141 Mboard support.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/phy.h>
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#include <linux/lirc.h>
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#include <linux/gpio.h>
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#include <linux/gpio_keys.h>
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#include <linux/input.h>
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#include <linux/stm/emi.h>
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#include <linux/stm/platform.h>
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#include <linux/stm/stx7141.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/partitions.h>
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#include <asm/irq-ilc.h>
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#include <asm/irl.h>
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#include <mach/epld.h>
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#include <sound/stm.h>
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#include <mach/common.h>
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/*
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* Flash setup depends on boot-device:
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*
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* boot-from-XXX
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* NOR NAND
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* ---------------------------------------------------------------------
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* J70 (CS routing) 2-3 (EMIA->NOR_CS) 1-2 (EMIA->NAND_CS)
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* SW8-4 (mode 14:bus width) ON (16bit) OFF (8bit)
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* SW9-1 (mode 16,17) ON (boot NOR) OFF (boot NAND)
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* SW9-2 ON ON
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* ---------------------------------------------------------------------
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*
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* Notes: SW8-4 was found not to work correctly on early rev A boards.
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* J69 must be in position 2-3 to enable the on-board Flash devices (both
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* NOR and NAND) rather than STEM).
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* J89 and J84 must be both in position 1-2 to avoid shorting A15.
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* Board modifications are required to achieve boot from SPI (not
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* supported here).
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* Jumper settings based on board rev A
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*/
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static struct platform_device mb628_epld_device;
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static void __init mb628_setup(char **cmdline_p)
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{
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u8 test;
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printk(KERN_INFO "STMicroelectronics STx7141 Mboard initialisation\n");
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stx7141_early_device_init();
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#ifndef CONFIG_SH_ST_MB628_STMMAC0
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/* Cannot use the ASC 1 when configure the GMAC0
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* due to a PIO conflict */
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stx7141_configure_asc(1, &(struct stx7141_asc_config) {
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.routing.asc1 = stx7141_asc1_pio10,
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.hw_flow_control = 1,
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.is_console = 1, });
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#endif
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stx7141_configure_asc(2, &(struct stx7141_asc_config) {
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.routing.asc2 = stx7141_asc2_pio6,
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.hw_flow_control = 1,
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.is_console = 0, });
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epld_early_init(&mb628_epld_device);
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epld_write(0xab, EPLD_TEST);
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test = epld_read(EPLD_TEST);
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printk(KERN_INFO "mb628 EPLD version %ld, test %s\n",
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epld_read(EPLD_IDENT),
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(test == (u8)(~0xab)) ? "passed" : "failed");
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}
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/* Serial Flash Chip Select
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*
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* SPI_CS is controlled via an EPLD register. Here we create a virtual GPIO
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* device which maps onto the register. This allows the default SPI chip select
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* function to be used.
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*/
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#define EPLD_SPI_CHIPSELECT_GPIO_BASE 200 /* Avoid clash with real PIOs */
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static void epld_spi_chipselect_set(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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u8 reg;
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reg = epld_read(EPLD_ENABLE);
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if (value)
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reg |= EPLD_ENABLE_SPI_NOTCS;
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else
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reg &= ~EPLD_ENABLE_SPI_NOTCS;
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epld_write(reg, EPLD_ENABLE);
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}
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static int epld_spi_chipselect_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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epld_spi_chipselect_set(chip, offset, value);
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return 0;
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}
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static struct gpio_chip epld_spi_chipselect = {
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.set = epld_spi_chipselect_set,
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.direction_output = epld_spi_chipselect_output,
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.base = EPLD_SPI_CHIPSELECT_GPIO_BASE,
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.ngpio = 1,
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};
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/* Serial Flash */
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static struct spi_board_info mb628_serial_flash = {
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.modalias = "m25p80",
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.bus_num = 0,
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.chip_select = EPLD_SPI_CHIPSELECT_GPIO_BASE,
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.max_speed_hz = 7000000,
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.mode = SPI_MODE_3,
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.platform_data = &(struct flash_platform_data) {
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.name = "m25p80",
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.type = "m25p32",
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.nr_parts = 2,
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.parts = (struct mtd_partition []) {
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{
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.name = "Serial Flash 1",
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.size = 0x00080000,
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.offset = 0,
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}, {
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.name = "Serial Flash 2",
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_NXTBLK,
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},
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},
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}
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};
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/* NOR Flash */
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static void mb628_nor_set_vpp(struct map_info *info, int enable)
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{
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epld_write((enable ? EPLD_FLASH_NOTWP : 0) | EPLD_FLASH_NOTRESET,
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EPLD_FLASH);
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}
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static struct platform_device mb628_nor_flash = {
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.name = "physmap-flash",
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.id = -1,
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.num_resources = 1,
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.resource = (struct resource[]) {
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/* updated in mb628_device_init() */
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STM_PLAT_RESOURCE_MEM(0, 32*1024*1024),
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},
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.dev.platform_data = &(struct physmap_flash_data) {
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.width = 2,
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.set_vpp = mb628_nor_set_vpp,
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.nr_parts = 3,
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.parts = (struct mtd_partition []) {
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{
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.name = "NOR Flash 1",
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.size = 0x00080000,
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.offset = 0x00000000,
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}, {
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.name = "NOR Flash 2",
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.size = 0x00200000,
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.offset = MTDPART_OFS_NXTBLK,
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}, {
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.name = "NOR Flash 3",
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_NXTBLK,
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},
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},
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},
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};
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/* NAND Flash */
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static struct stm_nand_bank_data mb628_nand_flash = {
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.csn = 0, /* updated in mb628_device_init() */
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.options = NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT,
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.nr_partitions = 2,
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.partitions = (struct mtd_partition []) {
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{
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.name = "NAND Flash 1",
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.offset = 0,
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.size = 0x00800000
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}, {
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.name = "NAND Flash 2",
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.offset = MTDPART_OFS_NXTBLK,
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.size = MTDPART_SIZ_FULL
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},
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},
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.timing_data = &(struct stm_nand_timing_data) {
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.sig_setup = 10, /* times in ns */
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.sig_hold = 10,
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.CE_deassert = 0,
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.WE_to_RBn = 100,
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.wr_on = 10,
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.wr_off = 40,
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.rd_on = 10,
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.rd_off = 40,
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.chip_delay = 30, /* in us */
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},
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.emi_withinbankoffset = 0,
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};
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static int mb628_phy_reset(void *bus)
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{
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u8 reg;
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static int first = 1;
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/* Both PHYs share the same reset signal, only act on the first. */
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if (!first)
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return 1;
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first = 0;
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reg = epld_read(EPLD_RESET);
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reg &= ~EPLD_RESET_MII;
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epld_write(reg, EPLD_RESET);
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udelay(150);
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reg |= EPLD_RESET_MII;
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epld_write(reg, EPLD_RESET);
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/* DP83865 (PHY chip) has a looong initialization
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* procedure... Let's give him some time to settle down... */
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udelay(1000);
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/*
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* The SMSC LAN8700 requires a 21mS delay after reset. This
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* matches the power on reset signal period, which should only
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* be applied after power on, but experimentally appears to be
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* applied post reset as well.
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*/
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mdelay(25);
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return 1;
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}
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/*
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* Several things need to be configured to use the GMAC0 with the
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* mb539 - SMSC LAN8700 PHY board:
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*
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* - normally the PHY's internal 1V8 regulator is used, which is
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* is enabled at PHY power up (not reset) by sampling RXCLK/REGOFF.
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* It appears that the STx7141's internal pull up resistor on this
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* signal is enabled at power on, defeating the internal pull down
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* in the SMSC device. Thus it is necessary to fix an external
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* pull down resistor to RXCLK/REGOFF. 10K appears to be sufficient.
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*
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* Alternativly fitting J2 on the mb539 supplies power from an
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* off-chip regulator, working around this problem.
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*
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* - various signals are muxed with the MII pins (as well as DVO_DATA).
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* + ASC1_RXD and ASC1_RTS, so make sure J101 is set to 2-3. This
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* allows the EPLD to disable the level converter.
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* + PCIREQ1 and PCIREQ2 need to be disabled by removing J104 and J98
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* (near the PCI slot).
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* + SYSITRQ1 needs to be disabled, which requires removing R232
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* (near CN17). See DDTS INSbl29196 for details.
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* + PCIGNT2 needs to be disabled. This can be done either by removing
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* R241, or by ensuring that jumper J89 is not in position 1-2 (by
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* either removing it completely or putting it in position 2-3).
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*
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* - other jumper and switch settings for the mb539:
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* + J1 fit 1-2 (use on board crystal)
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* + SW1: 1:on, 2:off, 3:off, 4:off
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* + SW2: 1:off, 2:off, 3:off, 4:off
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*
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* - For reliable SMI signalling it is necessary to have a
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* pull up resistor on the MDIO signal. This can be done by
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* installing R3 on the mb539 which is normally a DNF.
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*
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* - to use the MDINT signal, R148 needs to be in position 1-2.
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* To disable this, replace the irq with -1 in the data below.
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*/
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#ifdef CONFIG_SH_ST_MB628_STMMAC0
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static struct stmmac_mdio_bus_data stmmac0_mdio_bus = {
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.bus_id = 0,
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.phy_reset = mb628_phy_reset,
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.phy_mask = 0,
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.probed_phy_irq = ILC_IRQ(43),
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};
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#endif
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static struct stmmac_mdio_bus_data stmmac1_mdio_bus = {
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.bus_id = 1,
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.phy_reset = mb628_phy_reset,
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.phy_mask = 0,
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};
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static struct platform_device mb628_epld_device = {
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.name = "epld",
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.id = -1,
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.num_resources = 1,
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.resource = (struct resource[]) {
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{
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.start = 0x05000000,
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/* Minimum size to ensure mapped by PMB */
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.end = 0x05000000+(8*1024*1024)-1,
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.flags = IORESOURCE_MEM,
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}
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},
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.dev.platform_data = &(struct plat_epld_data) {
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.opsize = 8,
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},
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};
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#ifdef CONFIG_SND
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/* CS8416 SPDIF to I2S converter (IC14) */
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static struct platform_device mb628_snd_spdif_input = {
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.name = "snd_conv_dummy",
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.id = -1,
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.dev.platform_data = &(struct snd_stm_conv_dummy_info) {
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.group = "SPDIF Input",
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.source_bus_id = "snd_pcm_reader.0",
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.channel_from = 0,
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.channel_to = 1,
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.format = SND_STM_FORMAT__I2S |
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SND_STM_FORMAT__SUBFRAME_32_BITS,
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},
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};
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static struct platform_device mb628_snd_external_dacs = {
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.name = "snd_conv_epld",
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.id = -1,
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.dev.platform_data = &(struct snd_stm_conv_epld_info) {
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.group = "External DACs",
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.source_bus_id = "snd_pcm_player.0",
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.channel_from = 0,
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.channel_to = 9,
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.format = SND_STM_FORMAT__I2S |
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SND_STM_FORMAT__SUBFRAME_32_BITS,
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.oversampling = 256,
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.mute_supported = 1,
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.mute_offset = EPLD_AUDIO,
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.mute_mask = EPLD_AUDIO_PCMDAC1_SMUTE |
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EPLD_AUDIO_PCMDAC2_SMUTE,
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.mute_value = EPLD_AUDIO_PCMDAC1_SMUTE |
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EPLD_AUDIO_PCMDAC2_SMUTE,
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.unmute_value = 0,
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},
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};
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#endif
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static struct platform_device *mb628_devices[] __initdata = {
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&mb628_epld_device,
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#ifdef CONFIG_SND
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&mb628_snd_spdif_input,
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&mb628_snd_external_dacs,
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#endif
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};
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static int __init mb628_device_init(void)
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{
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struct sysconf_field *sc;
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/* Configure FLASH devices */
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sc = sysconf_claim(SYS_STA, 1, 16, 17, "boot_mode");
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switch (sysconf_read(sc)) {
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case 0x0:
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/* Boot-from-NOR: */
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pr_info("Configuring FLASH for boot-from-NOR\n");
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mb628_nor_flash.resource[0].start = 0x00000000;
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mb628_nor_flash.resource[0].end = emi_bank_base(1) - 1;
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platform_device_register(&mb628_nor_flash);
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break;
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case 0x1:
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/* Boot-from-NAND */
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pr_info("Configuring FLASH for boot-from-NAND\n");
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mb628_nand_flash.csn = 0;
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stx7141_configure_nand(&(struct stm_nand_config) {
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.driver = stm_nand_flex,
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.nr_banks = 1,
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.banks = &mb628_nand_flash,
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.rbn.flex_connected = 1,});
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/* The MTD NAND code doesn't understand the concept of VPP, (or
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* hardware write protect) so permanently enable it.
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*/
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epld_write(EPLD_FLASH_NOTWP | EPLD_FLASH_NOTRESET, EPLD_FLASH);
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break;
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default:
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BUG();
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break;
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}
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/*
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* Can't enable PWM output without conflicting with either
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* SSC6 (audio) or USB1A OC (which is disabled in cut 1 because it
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* has the wrong OC polarity but would still result in contention).
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*
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* stx7141_configure_pwm(0, 1);
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*/
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stx7141_configure_ssc_spi(0, NULL);
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stx7141_configure_ssc_spi(1, NULL);
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stx7141_configure_ssc_i2c(2);
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stx7141_configure_ssc_i2c(3);
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stx7141_configure_ssc_i2c(4);
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stx7141_configure_ssc_i2c(5);
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stx7141_configure_ssc_i2c(6);
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stx7141_configure_usb(0, &(struct stx7141_usb_config) {
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.ovrcur_mode = stx7141_usb_ovrcur_active_low,
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.pwr_enabled = 1 });
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/* This requires fitting jumpers J52A 1-2 and J52B 4-5 */
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stx7141_configure_usb(1, &(struct stx7141_usb_config) {
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.ovrcur_mode = stx7141_usb_ovrcur_active_low,
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.pwr_enabled = 1 });
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/*
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* USB1.1 ports on mb628 rev A are missing the series
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* resistors, which can make them unreliable, and also the
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* pull down resistors, which causes them to report spurious
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* device connection. Unfortunately we can't determine board
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* revision, but most boards are now rev B, so make the ports
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* available here. Boards with cut 1 Si will have these ports
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* disabled anyway, becuase the OC polarity is wrong. Users
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* with rev A boards and cut 2 Si will need to remove these
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* lines.
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*/
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stx7141_configure_usb(2, &(struct stx7141_usb_config) {
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.ovrcur_mode = stx7141_usb_ovrcur_active_low,
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.pwr_enabled = 1 });
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stx7141_configure_usb(3, &(struct stx7141_usb_config) {
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.ovrcur_mode = stx7141_usb_ovrcur_active_low,
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.pwr_enabled = 1 });
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stx7141_configure_sata();
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/* Note R253 must be removed for Ethernet MDIO signal to work. */
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#ifdef CONFIG_SH_ST_MB628_STMMAC0
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/* Must disable ASC1 if using GMII0 */
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epld_write(epld_read(EPLD_ENABLE) | EPLD_ASC1_EN | EPLD_ENABLE_MII0,
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EPLD_ENABLE);
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/* Configure GMII0 MDINT for active low */
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set_irq_type(ILC_IRQ(43), IRQ_TYPE_LEVEL_LOW);
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stx7141_configure_ethernet(0, &(struct stx7141_ethernet_config) {
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.mode = stx7141_ethernet_mode_mii,
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.phy_bus = 0,
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.phy_addr = -1,
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.mdio_bus_data = &stmmac0_mdio_bus,
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});
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#endif
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epld_write(epld_read(EPLD_ENABLE) | EPLD_ENABLE_MII1, EPLD_ENABLE);
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stx7141_configure_ethernet(1, &(struct stx7141_ethernet_config) {
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.mode = stx7141_ethernet_mode_gmii,
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.phy_bus = 1,
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.phy_addr = -1,
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.mdio_bus_data = &stmmac1_mdio_bus,
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});
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stx7141_configure_lirc(&(struct stx7141_lirc_config) {
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.rx_mode = stx7141_lirc_rx_disabled,
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.tx_enabled = 1,
|
|
.tx_od_enabled = 1 });
|
|
|
|
/* Audio peripherals
|
|
*
|
|
* WARNING! Board rev. A has swapped silkscreen labels of J16 & J32!
|
|
*
|
|
* The recommended audio setup of MB628 is as follows:
|
|
* SW2[1..4] - [ON, OFF, OFF, ON]
|
|
* SW5[1..4] - [OFF, OFF, OFF, OFF]
|
|
* SW3[1..4] - [OFF, OFF, ON, OFF]
|
|
* SW12[1..4] - [OFF, OFF, OFF, OFF]
|
|
* SW13[1..4] - [OFF, OFF, OFF, OFF]
|
|
* J2 - 2-3
|
|
* J3 - 1-2
|
|
* J6 - 1-2
|
|
* J7 - 1-2
|
|
* J8 - 1-2
|
|
* J12 - 1-2
|
|
* J16-A - 1-2, J16-B - 1-2
|
|
* J23-A - 2-3, J23-B - 2-3
|
|
* J26-A - 1-2, J26-B - 2-3
|
|
* J34-A - 1-2, J34-B - 2-3
|
|
* J41-A - 3-2, J41-B - 3-2
|
|
*
|
|
* Additionally the audio EPLD should be updated to the latest
|
|
* available release.
|
|
*
|
|
* With such settings the audio outputs layout presents as follows:
|
|
*
|
|
* +--------------------------------------+
|
|
* | |
|
|
* | (S.I) (1.R) (1.L) (0.4) (0.3) | TOP
|
|
* | |
|
|
* | (---) (0.2) (0.1) (0.10) (0.9) |
|
|
* | |
|
|
* | (S.O) (0.6) (0.5) (0.8) (0.7) | BOTTOM
|
|
* | |
|
|
* +--------------------------------------+
|
|
* CN6 CN5 CN4 CN3 CN2
|
|
*
|
|
* where:
|
|
* - S.I - SPDIF input - PCM Reader #0
|
|
* - S.O - SPDIF output - SPDIF Player (HDMI)
|
|
* - 1.R, 1.L - audio outputs - PCM Player #1, channel L(1)/R(2)
|
|
* - 0.1-10 - audio outputs - PCM Player #0, channels 1 to 10
|
|
*/
|
|
|
|
/* As digital audio outputs are now GPIOs, we have to claim them... */
|
|
stx7141_configure_audio(&(struct stx7141_audio_config) {
|
|
.pcm_player_0_output =
|
|
stx7141_pcm_player_0_output_10_channels,
|
|
.pcm_player_1_output_enabled = 0,
|
|
.spdif_player_output_enabled = 1,
|
|
.pcm_reader_0_input_enabled = 1,
|
|
.pcm_reader_1_input_enabled = 1 });
|
|
|
|
/* We use both DACs to get full 10-channels output from
|
|
* PCM Player #0 (EPLD muxing mode #1) */
|
|
{
|
|
unsigned int value = epld_read(EPLD_AUDIO);
|
|
|
|
value &= ~(EPLD_AUDIO_AUD_SW_CTRL_MASK <<
|
|
EPLD_AUDIO_AUD_SW_CTRL_SHIFT);
|
|
value |= 0x1 << EPLD_AUDIO_AUD_SW_CTRL_SHIFT;
|
|
|
|
epld_write(value, EPLD_AUDIO);
|
|
}
|
|
|
|
gpiochip_add(&epld_spi_chipselect);
|
|
spi_register_board_info(&mb628_serial_flash, 1);
|
|
|
|
return platform_add_devices(mb628_devices, ARRAY_SIZE(mb628_devices));
|
|
}
|
|
arch_initcall(mb628_device_init);
|
|
|
|
static void __iomem *mb628_ioport_map(unsigned long port, unsigned int size)
|
|
{
|
|
/*
|
|
* No IO ports on this device, but to allow safe probing pick
|
|
* somewhere safe to redirect all reads and writes.
|
|
*/
|
|
return (void __iomem *)CCN_PVR;
|
|
}
|
|
|
|
static void __init mb628_init_irq(void)
|
|
{
|
|
}
|
|
|
|
struct sh_machine_vector mv_mb628 __initmv = {
|
|
.mv_name = "mb628",
|
|
.mv_setup = mb628_setup,
|
|
.mv_nr_irqs = NR_IRQS,
|
|
.mv_init_irq = mb628_init_irq,
|
|
.mv_ioport_map = mb628_ioport_map,
|
|
};
|