918 lines
28 KiB
C
918 lines
28 KiB
C
/*****************************************************************************
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* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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/****************************************************************************/
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/**
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* @file dmacHw.c
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*
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* @brief Low level DMA controller driver routines
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*
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* @note
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*
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* These routines provide basic DMA functionality only.
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*/
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/****************************************************************************/
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/* ---- Include Files ---------------------------------------------------- */
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#include <csp/stdint.h>
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#include <csp/string.h>
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#include <stddef.h>
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#include <csp/dmacHw.h>
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#include <mach/csp/dmacHw_reg.h>
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#include <mach/csp/dmacHw_priv.h>
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#include <mach/csp/chipcHw_inline.h>
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/* ---- External Function Prototypes ------------------------------------- */
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/* Allocate DMA control blocks */
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dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];
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uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2;
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uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2;
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/****************************************************************************/
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/**
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* @brief Get maximum FIFO for a DMA channel
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*
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* @return Maximum allowable FIFO size
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*
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*
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*/
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/****************************************************************************/
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static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
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) {
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uint32_t val = 0;
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dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
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dmacHw_MISC_t *pMiscReg =
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(dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
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switch (pCblk->channel) {
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case 0:
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val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
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break;
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case 1:
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val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
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break;
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case 2:
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val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
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break;
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case 3:
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val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
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break;
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case 4:
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val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
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break;
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case 5:
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val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
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break;
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case 6:
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val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
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break;
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case 7:
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val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
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break;
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}
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if (val <= 0x4) {
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return 8 << val;
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} else {
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dmacHw_ASSERT(0);
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}
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return 0;
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}
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/****************************************************************************/
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/**
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* @brief Program channel register to initiate transfer
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*
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* @return void
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*
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*
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* @note
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* - Descriptor buffer MUST ALWAYS be flushed before calling this function
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* - This function should also be called from ISR to program the channel with
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* pending descriptors
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*/
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/****************************************************************************/
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void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
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dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
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void *pDescriptor /* [ IN ] Descriptor buffer */
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) {
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dmacHw_DESC_RING_t *pRing;
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dmacHw_DESC_t *pProg;
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dmacHw_CBLK_t *pCblk;
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pCblk = dmacHw_HANDLE_TO_CBLK(handle);
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pRing = dmacHw_GET_DESC_RING(pDescriptor);
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if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
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/* Not safe yet to program the channel */
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return;
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}
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if (pCblk->varDataStarted) {
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if (pCblk->descUpdated) {
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pCblk->descUpdated = 0;
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pProg =
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(dmacHw_DESC_t *) ((uint32_t)
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dmacHw_REG_LLP(pCblk->module,
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pCblk->channel) +
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pRing->virt2PhyOffset);
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/* Load descriptor if not loaded */
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if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) {
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dmacHw_SET_SAR(pCblk->module, pCblk->channel,
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pProg->sar);
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dmacHw_SET_DAR(pCblk->module, pCblk->channel,
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pProg->dar);
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dmacHw_REG_CTL_LO(pCblk->module,
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pCblk->channel) =
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pProg->ctl.lo;
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dmacHw_REG_CTL_HI(pCblk->module,
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pCblk->channel) =
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pProg->ctl.hi;
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} else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) {
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/* Return as end descriptor is processed */
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return;
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} else {
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dmacHw_ASSERT(0);
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}
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} else {
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return;
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}
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} else {
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if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) {
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/* Do not make a single chain, rather process one descriptor at a time */
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pProg = pRing->pHead;
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/* Point to the next descriptor for next iteration */
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dmacHw_NEXT_DESC(pRing, pHead);
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} else {
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/* Return if no more pending descriptor */
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if (pRing->pEnd == NULL) {
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return;
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}
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pProg = pRing->pProg;
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if (pConfig->transferMode ==
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dmacHw_TRANSFER_MODE_CONTINUOUS) {
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/* Make sure a complete ring can be formed */
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dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd->
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llp == pRing->pProg);
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/* Make sure pProg pointing to the pHead */
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dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg ==
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pRing->pHead);
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/* Make a complete ring */
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do {
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pRing->pProg->ctl.lo |=
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(dmacHw_REG_CTL_LLP_DST_EN |
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dmacHw_REG_CTL_LLP_SRC_EN);
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pRing->pProg =
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(dmacHw_DESC_t *) pRing->pProg->llp;
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} while (pRing->pProg != pRing->pHead);
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} else {
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/* Make a single long chain */
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while (pRing->pProg != pRing->pEnd) {
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pRing->pProg->ctl.lo |=
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(dmacHw_REG_CTL_LLP_DST_EN |
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dmacHw_REG_CTL_LLP_SRC_EN);
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pRing->pProg =
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(dmacHw_DESC_t *) pRing->pProg->llp;
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}
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}
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}
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/* Program the channel registers */
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dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar);
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dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar);
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dmacHw_SET_LLP(pCblk->module, pCblk->channel,
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(uint32_t) pProg - pRing->virt2PhyOffset);
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dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) =
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pProg->ctl.lo;
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dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) =
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pProg->ctl.hi;
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if (pRing->pEnd) {
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/* Remember the descriptor to use next */
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pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp;
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}
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/* Indicate no more pending descriptor */
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pRing->pEnd = (dmacHw_DESC_t *) NULL;
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}
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/* Start DMA operation */
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dmacHw_DMA_START(pCblk->module, pCblk->channel);
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}
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/****************************************************************************/
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/**
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* @brief Initializes DMA
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*
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* This function initializes DMA CSP driver
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*
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* @note
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* Must be called before using any DMA channel
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*/
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/****************************************************************************/
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void dmacHw_initDma(void)
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{
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uint32_t i = 0;
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dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0);
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dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1);
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/* Enable access to the DMA block */
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chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0);
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chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1);
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if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) {
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dmacHw_ASSERT(0);
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}
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memset((void *)dmacHw_gCblk, 0,
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sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1));
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for (i = 0; i < dmaChannelCount_0; i++) {
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dmacHw_gCblk[i].module = 0;
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dmacHw_gCblk[i].channel = i;
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}
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for (i = 0; i < dmaChannelCount_1; i++) {
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dmacHw_gCblk[i + dmaChannelCount_0].module = 1;
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dmacHw_gCblk[i + dmaChannelCount_0].channel = i;
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}
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}
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/****************************************************************************/
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/**
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* @brief Exit function for DMA
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*
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* This function isolates DMA from the system
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*
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*/
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/****************************************************************************/
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void dmacHw_exitDma(void)
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{
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/* Disable access to the DMA block */
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chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0);
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chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1);
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}
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/****************************************************************************/
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/**
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* @brief Gets a handle to a DMA channel
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*
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* This function returns a handle, representing a control block of a particular DMA channel
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*
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* @return -1 - On Failure
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* handle - On Success, representing a channel control block
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*
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* @note
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* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
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*/
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/****************************************************************************/
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dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */
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) {
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int idx;
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switch ((channelId >> 8)) {
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case 0:
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dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0);
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idx = (channelId & 0xff);
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break;
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case 1:
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dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1);
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idx = dmaChannelCount_0 + (channelId & 0xff);
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break;
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default:
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dmacHw_ASSERT(0);
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return (dmacHw_HANDLE_t) -1;
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}
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return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]);
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}
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/****************************************************************************/
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/**
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* @brief Initializes a DMA channel for use
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*
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* This function initializes and resets a DMA channel for use
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*
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* @return -1 - On Failure
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* 0 - On Success
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*
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* @note
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* None
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*/
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/****************************************************************************/
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int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
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) {
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dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
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int module = pCblk->module;
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int channel = pCblk->channel;
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/* Reinitialize the control block */
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memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
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pCblk->module = module;
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pCblk->channel = channel;
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/* Enable DMA controller */
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dmacHw_DMA_ENABLE(pCblk->module);
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/* Reset DMA channel */
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dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
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dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
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dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
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dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
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/* Clear all raw interrupt status */
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dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
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dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
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dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
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/* Mask event specific interrupts */
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dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
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dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
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dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
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dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
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dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
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return 0;
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}
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/****************************************************************************/
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/**
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* @brief Finds amount of memory required to form a descriptor ring
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*
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*
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* @return Number of bytes required to form a descriptor ring
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*
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*
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*/
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/****************************************************************************/
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uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */
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) {
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/* Need extra 4 byte to ensure 32 bit alignment */
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return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) +
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sizeof(uint32_t);
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}
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/****************************************************************************/
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/**
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* @brief Initializes descriptor ring
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*
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* This function will initializes the descriptor ring of a DMA channel
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*
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*
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* @return -1 - On failure
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* 0 - On success
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* @note
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* - "len" parameter should be obtained from "dmacHw_descriptorLen"
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* - Descriptor buffer MUST be 32 bit aligned and uncached as it is
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* accessed by ARM and DMA
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*/
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/****************************************************************************/
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int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
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uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
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uint32_t len, /* [ IN ] Size of the pBuf */
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uint32_t num /* [ IN ] Number of descriptor in the ring */
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) {
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uint32_t i;
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dmacHw_DESC_RING_t *pRing;
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dmacHw_DESC_t *pDesc;
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/* Check the alignment of the descriptor */
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if ((uint32_t) pDescriptorVirt & 0x00000003) {
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dmacHw_ASSERT(0);
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return -1;
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}
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/* Check if enough space has been allocated for descriptor ring */
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if (len < dmacHw_descriptorLen(num)) {
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return -1;
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}
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pRing = dmacHw_GET_DESC_RING(pDescriptorVirt);
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pRing->pHead =
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(dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t));
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pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
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pRing->pProg = dmacHw_DESC_INIT;
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/* Initialize link item chain, starting from the head */
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pDesc = pRing->pHead;
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/* Find the offset between virtual to physical address */
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pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr;
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/* Form the descriptor ring */
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for (i = 0; i < num - 1; i++) {
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/* Clear link list item */
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memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
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/* Point to the next item in the physical address */
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pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset;
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/* Point to the next item in the virtual address */
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pDesc->llp = (uint32_t) (pDesc + 1);
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/* Mark descriptor is ready to use */
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pDesc->ctl.hi = dmacHw_DESC_FREE;
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/* Look into next link list item */
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pDesc++;
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}
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/* Clear last link list item */
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memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
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/* Last item pointing to the first item in the
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physical address to complete the ring */
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pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset;
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/* Last item pointing to the first item in the
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virtual address to complete the ring
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*/
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pDesc->llp = (uint32_t) pRing->pHead;
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/* Mark descriptor is ready to use */
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pDesc->ctl.hi = dmacHw_DESC_FREE;
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/* Set the number of descriptors in the ring */
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pRing->num = num;
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return 0;
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}
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|
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/****************************************************************************/
|
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/**
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* @brief Configure DMA channel
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*
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* @return 0 : On success
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* -1 : On failure
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*/
|
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/****************************************************************************/
|
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int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
|
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dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */
|
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) {
|
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dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
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uint32_t cfgHigh = 0;
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int srcTrSize;
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int dstTrSize;
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|
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pCblk->varDataStarted = 0;
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pCblk->userData = NULL;
|
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|
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/* Configure
|
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- Burst transaction when enough data in available in FIFO
|
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- AHB Access protection 1
|
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- Source and destination peripheral ports
|
|
*/
|
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cfgHigh =
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dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
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dmacHw_SRC_PERI_INTF(pConfig->
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srcPeripheralPort) |
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dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
|
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/* Set priority */
|
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dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
|
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pConfig->channelPriority);
|
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|
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if (pConfig->dstStatusRegisterAddress != 0) {
|
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/* Destination status update enable */
|
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cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
|
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/* Configure status registers */
|
|
dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
|
|
pConfig->dstStatusRegisterAddress);
|
|
}
|
|
|
|
if (pConfig->srcStatusRegisterAddress != 0) {
|
|
/* Source status update enable */
|
|
cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
|
|
/* Source status update enable */
|
|
dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
|
|
pConfig->srcStatusRegisterAddress);
|
|
}
|
|
/* Configure the config high register */
|
|
dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
|
|
|
|
/* Clear all raw interrupt status */
|
|
dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
|
|
dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
|
|
dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
|
|
|
|
/* Configure block interrupt */
|
|
if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
|
|
dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
|
|
} else {
|
|
dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
|
|
}
|
|
/* Configure complete transfer interrupt */
|
|
if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
|
|
dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
|
|
} else {
|
|
dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
|
|
}
|
|
/* Configure error interrupt */
|
|
if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
|
|
dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
|
|
} else {
|
|
dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
|
|
}
|
|
/* Configure gather register */
|
|
if (pConfig->srcGatherWidth) {
|
|
srcTrSize =
|
|
dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
|
|
if (!
|
|
((pConfig->srcGatherWidth % srcTrSize)
|
|
&& (pConfig->srcGatherJump % srcTrSize))) {
|
|
dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
|
|
((pConfig->srcGatherWidth /
|
|
srcTrSize) << 20) | (pConfig->srcGatherJump /
|
|
srcTrSize);
|
|
} else {
|
|
return -1;
|
|
}
|
|
}
|
|
/* Configure scatter register */
|
|
if (pConfig->dstScatterWidth) {
|
|
dstTrSize =
|
|
dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
|
|
if (!
|
|
((pConfig->dstScatterWidth % dstTrSize)
|
|
&& (pConfig->dstScatterJump % dstTrSize))) {
|
|
dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
|
|
((pConfig->dstScatterWidth /
|
|
dstTrSize) << 20) | (pConfig->dstScatterJump /
|
|
dstTrSize);
|
|
} else {
|
|
return -1;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Indicates whether DMA transfer is in progress or completed
|
|
*
|
|
* @return DMA transfer status
|
|
* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing
|
|
* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed
|
|
* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error
|
|
*
|
|
*/
|
|
/****************************************************************************/
|
|
dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
|
|
) {
|
|
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
|
|
|
|
if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
|
|
return dmacHw_TRANSFER_STATUS_BUSY;
|
|
} else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) &
|
|
(0x00000001 << pCblk->channel)) {
|
|
return dmacHw_TRANSFER_STATUS_ERROR;
|
|
}
|
|
|
|
return dmacHw_TRANSFER_STATUS_DONE;
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Set descriptors for known data length
|
|
*
|
|
* When DMA has to work as a flow controller, this function prepares the
|
|
* descriptor chain to transfer data
|
|
*
|
|
* from:
|
|
* - Memory to memory
|
|
* - Peripheral to memory
|
|
* - Memory to Peripheral
|
|
* - Peripheral to Peripheral
|
|
*
|
|
* @return -1 - On failure
|
|
* 0 - On success
|
|
*
|
|
*/
|
|
/****************************************************************************/
|
|
int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
|
|
void *pDescriptor, /* [ IN ] Descriptor buffer */
|
|
void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
|
|
void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
|
|
size_t dataLen /* [ IN ] Data length in bytes */
|
|
) {
|
|
dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
|
|
dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
|
|
dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
|
|
dmacHw_DESC_t *pStart;
|
|
dmacHw_DESC_t *pProg;
|
|
int srcTs = 0;
|
|
int blkTs = 0;
|
|
int oddSize = 0;
|
|
int descCount = 0;
|
|
int count = 0;
|
|
int dstTrSize = 0;
|
|
int srcTrSize = 0;
|
|
uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
|
|
|
|
dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
|
|
srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
|
|
|
|
/* Skip Tx if buffer is NULL or length is unknown */
|
|
if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
|
|
/* Do not initiate transfer */
|
|
return -1;
|
|
}
|
|
|
|
/* Ensure scatter and gather are transaction aligned */
|
|
if ((pConfig->srcGatherWidth % srcTrSize)
|
|
|| (pConfig->dstScatterWidth % dstTrSize)) {
|
|
return -2;
|
|
}
|
|
|
|
/*
|
|
Background 1: DMAC can not perform DMA if source and destination addresses are
|
|
not properly aligned with the channel's transaction width. So, for successful
|
|
DMA transfer, transaction width must be set according to the alignment of the
|
|
source and destination address.
|
|
*/
|
|
|
|
/* Adjust destination transaction width if destination address is not aligned properly */
|
|
dstTrWidth = pConfig->dstMaxTransactionWidth;
|
|
while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
|
|
dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
|
|
dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
|
|
}
|
|
|
|
/* Adjust source transaction width if source address is not aligned properly */
|
|
srcTrWidth = pConfig->srcMaxTransactionWidth;
|
|
while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
|
|
srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
|
|
srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
|
|
}
|
|
|
|
/* Find the maximum transaction per descriptor */
|
|
if (pConfig->maxDataPerBlock
|
|
&& ((pConfig->maxDataPerBlock / srcTrSize) <
|
|
dmacHw_MAX_BLOCKSIZE)) {
|
|
maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
|
|
}
|
|
|
|
/* Find number of source transactions needed to complete the DMA transfer */
|
|
srcTs = dataLen / srcTrSize;
|
|
/* Find the odd number of bytes that need to be transferred as single byte transaction width */
|
|
if (srcTs && (dstTrSize > srcTrSize)) {
|
|
oddSize = dataLen % dstTrSize;
|
|
/* Adjust source transaction count due to "oddSize" */
|
|
srcTs = srcTs - (oddSize / srcTrSize);
|
|
} else {
|
|
oddSize = dataLen % srcTrSize;
|
|
}
|
|
/* Adjust "descCount" due to "oddSize" */
|
|
if (oddSize) {
|
|
descCount++;
|
|
}
|
|
/* Find the number of descriptor needed for total "srcTs" */
|
|
if (srcTs) {
|
|
descCount += ((srcTs - 1) / maxBlockSize) + 1;
|
|
}
|
|
|
|
/* Check the availability of "descCount" discriptors in the ring */
|
|
pProg = pRing->pHead;
|
|
for (count = 0; (descCount <= pRing->num) && (count < descCount);
|
|
count++) {
|
|
if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) {
|
|
/* Sufficient descriptors are not available */
|
|
return -3;
|
|
}
|
|
pProg = (dmacHw_DESC_t *) pProg->llp;
|
|
}
|
|
|
|
/* Remember the link list item to program the channel registers */
|
|
pStart = pProg = pRing->pHead;
|
|
/* Make a link list with "descCount(=count)" number of descriptors */
|
|
while (count) {
|
|
/* Reset channel control information */
|
|
pProg->ctl.lo = 0;
|
|
/* Enable source gather if configured */
|
|
if (pConfig->srcGatherWidth) {
|
|
pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE;
|
|
}
|
|
/* Enable destination scatter if configured */
|
|
if (pConfig->dstScatterWidth) {
|
|
pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE;
|
|
}
|
|
/* Set source and destination address */
|
|
pProg->sar = (uint32_t) pSrcAddr;
|
|
pProg->dar = (uint32_t) pDstAddr;
|
|
/* Use "devCtl" to mark that user memory need to be freed later if needed */
|
|
if (pProg == pRing->pHead) {
|
|
pProg->devCtl = dmacHw_FREE_USER_MEMORY;
|
|
} else {
|
|
pProg->devCtl = 0;
|
|
}
|
|
|
|
blkTs = srcTs;
|
|
|
|
/* Special treatmeant for last descriptor */
|
|
if (count == 1) {
|
|
/* Mark the last descriptor */
|
|
pProg->ctl.lo &=
|
|
~(dmacHw_REG_CTL_LLP_DST_EN |
|
|
dmacHw_REG_CTL_LLP_SRC_EN);
|
|
/* Treatment for odd data bytes */
|
|
if (oddSize) {
|
|
/* Adjust for single byte transaction width */
|
|
switch (pConfig->transferType) {
|
|
case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
|
|
dstTrWidth =
|
|
dmacHw_DST_TRANSACTION_WIDTH_8;
|
|
blkTs =
|
|
(oddSize / srcTrSize) +
|
|
((oddSize % srcTrSize) ? 1 : 0);
|
|
break;
|
|
case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
|
|
srcTrWidth =
|
|
dmacHw_SRC_TRANSACTION_WIDTH_8;
|
|
blkTs = oddSize;
|
|
break;
|
|
case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
|
|
srcTrWidth =
|
|
dmacHw_SRC_TRANSACTION_WIDTH_8;
|
|
dstTrWidth =
|
|
dmacHw_DST_TRANSACTION_WIDTH_8;
|
|
blkTs = oddSize;
|
|
break;
|
|
case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
|
|
/* Do not adjust the transaction width */
|
|
break;
|
|
}
|
|
} else {
|
|
srcTs -= blkTs;
|
|
}
|
|
} else {
|
|
if (srcTs / maxBlockSize) {
|
|
blkTs = maxBlockSize;
|
|
}
|
|
/* Remaining source transactions for next iteration */
|
|
srcTs -= blkTs;
|
|
}
|
|
/* Must have a valid source transactions */
|
|
dmacHw_ASSERT(blkTs > 0);
|
|
/* Set control information */
|
|
if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
|
|
pProg->ctl.lo |= pConfig->transferType |
|
|
pConfig->srcUpdate |
|
|
pConfig->dstUpdate |
|
|
srcTrWidth |
|
|
dstTrWidth |
|
|
pConfig->srcMaxBurstWidth |
|
|
pConfig->dstMaxBurstWidth |
|
|
pConfig->srcMasterInterface |
|
|
pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
|
|
} else {
|
|
uint32_t transferType = 0;
|
|
switch (pConfig->transferType) {
|
|
case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
|
|
transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
|
|
break;
|
|
case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
|
|
transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
|
|
break;
|
|
default:
|
|
dmacHw_ASSERT(0);
|
|
}
|
|
pProg->ctl.lo |= transferType |
|
|
pConfig->srcUpdate |
|
|
pConfig->dstUpdate |
|
|
srcTrWidth |
|
|
dstTrWidth |
|
|
pConfig->srcMaxBurstWidth |
|
|
pConfig->dstMaxBurstWidth |
|
|
pConfig->srcMasterInterface |
|
|
pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
|
|
}
|
|
|
|
/* Set block transaction size */
|
|
pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
|
|
/* Look for next descriptor */
|
|
if (count > 1) {
|
|
/* Point to the next descriptor */
|
|
pProg = (dmacHw_DESC_t *) pProg->llp;
|
|
|
|
/* Update source and destination address for next iteration */
|
|
switch (pConfig->transferType) {
|
|
case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
|
|
if (pConfig->dstScatterWidth) {
|
|
pDstAddr =
|
|
(char *)pDstAddr +
|
|
blkTs * srcTrSize +
|
|
(((blkTs * srcTrSize) /
|
|
pConfig->dstScatterWidth) *
|
|
pConfig->dstScatterJump);
|
|
} else {
|
|
pDstAddr =
|
|
(char *)pDstAddr +
|
|
blkTs * srcTrSize;
|
|
}
|
|
break;
|
|
case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
|
|
if (pConfig->srcGatherWidth) {
|
|
pSrcAddr =
|
|
(char *)pDstAddr +
|
|
blkTs * srcTrSize +
|
|
(((blkTs * srcTrSize) /
|
|
pConfig->srcGatherWidth) *
|
|
pConfig->srcGatherJump);
|
|
} else {
|
|
pSrcAddr =
|
|
(char *)pSrcAddr +
|
|
blkTs * srcTrSize;
|
|
}
|
|
break;
|
|
case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
|
|
if (pConfig->dstScatterWidth) {
|
|
pDstAddr =
|
|
(char *)pDstAddr +
|
|
blkTs * srcTrSize +
|
|
(((blkTs * srcTrSize) /
|
|
pConfig->dstScatterWidth) *
|
|
pConfig->dstScatterJump);
|
|
} else {
|
|
pDstAddr =
|
|
(char *)pDstAddr +
|
|
blkTs * srcTrSize;
|
|
}
|
|
|
|
if (pConfig->srcGatherWidth) {
|
|
pSrcAddr =
|
|
(char *)pDstAddr +
|
|
blkTs * srcTrSize +
|
|
(((blkTs * srcTrSize) /
|
|
pConfig->srcGatherWidth) *
|
|
pConfig->srcGatherJump);
|
|
} else {
|
|
pSrcAddr =
|
|
(char *)pSrcAddr +
|
|
blkTs * srcTrSize;
|
|
}
|
|
break;
|
|
case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
|
|
/* Do not adjust the address */
|
|
break;
|
|
default:
|
|
dmacHw_ASSERT(0);
|
|
}
|
|
} else {
|
|
/* At the end of transfer "srcTs" must be zero */
|
|
dmacHw_ASSERT(srcTs == 0);
|
|
}
|
|
count--;
|
|
}
|
|
|
|
/* Remember the descriptor to initialize the registers */
|
|
if (pRing->pProg == dmacHw_DESC_INIT) {
|
|
pRing->pProg = pStart;
|
|
}
|
|
/* Indicate that the descriptor is updated */
|
|
pRing->pEnd = pProg;
|
|
/* Head pointing to the next descriptor */
|
|
pRing->pHead = (dmacHw_DESC_t *) pProg->llp;
|
|
/* Update Tail pointer if destination is a peripheral,
|
|
because no one is going to read from the pTail
|
|
*/
|
|
if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
|
|
pRing->pTail = pRing->pHead;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Provides DMA controller attributes
|
|
*
|
|
*
|
|
* @return DMA controller attributes
|
|
*
|
|
* @note
|
|
* None
|
|
*/
|
|
/****************************************************************************/
|
|
uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
|
|
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */
|
|
) {
|
|
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
|
|
|
|
switch (attr) {
|
|
case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM:
|
|
return dmacHw_GET_NUM_CHANNEL(pCblk->module);
|
|
case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE:
|
|
return (1 <<
|
|
(dmacHw_GET_MAX_BLOCK_SIZE
|
|
(pCblk->module, pCblk->module) + 2)) - 8;
|
|
case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM:
|
|
return dmacHw_GET_NUM_INTERFACE(pCblk->module);
|
|
case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH:
|
|
return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module,
|
|
pCblk->channel);
|
|
case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE:
|
|
return GetFifoSize(handle);
|
|
}
|
|
dmacHw_ASSERT(0);
|
|
return 0;
|
|
}
|