56 lines
1.7 KiB
C
56 lines
1.7 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*
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* This file may be distributed under the terms of the GNU General
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* Public License, version 2.
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*/
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#ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__
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#define __ARCH_ARM_MACH_MX1_CRM_REGS_H__
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#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR)
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#define SCM_BASE IO_ADDRESS(SCM_BASE_ADDR)
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/* CCM register addresses */
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#define CCM_CSCR (CCM_BASE + 0x0)
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#define CCM_MPCTL0 (CCM_BASE + 0x4)
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#define CCM_MPCTL1 (CCM_BASE + 0x8)
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#define CCM_SPCTL0 (CCM_BASE + 0xC)
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#define CCM_SPCTL1 (CCM_BASE + 0x10)
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#define CCM_PCDR (CCM_BASE + 0x20)
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#define CCM_CSCR_CLKO_OFFSET 29
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#define CCM_CSCR_CLKO_MASK (0x7 << 29)
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#define CCM_CSCR_USB_OFFSET 26
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#define CCM_CSCR_USB_MASK (0x7 << 26)
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#define CCM_CSCR_SPLL_RESTART (1 << 22)
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#define CCM_CSCR_MPLL_RESTART (1 << 21)
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#define CCM_CSCR_OSC_EN_SHIFT 17
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#define CCM_CSCR_SYSTEM_SEL (1 << 16)
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#define CCM_CSCR_BCLK_OFFSET 10
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#define CCM_CSCR_BCLK_MASK (0xF << 10)
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#define CCM_CSCR_PRESC (1 << 15)
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#define CCM_CSCR_SPEN (1 << 1)
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#define CCM_CSCR_MPEN (1 << 0)
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#define CCM_PCDR_PCLK3_OFFSET 16
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#define CCM_PCDR_PCLK3_MASK (0x7F << 16)
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#define CCM_PCDR_PCLK2_OFFSET 4
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#define CCM_PCDR_PCLK2_MASK (0xF << 4)
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#define CCM_PCDR_PCLK1_OFFSET 0
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#define CCM_PCDR_PCLK1_MASK 0xF
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/* SCM register addresses */
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#define SCM_SIDR (SCM_BASE + 0x0)
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#define SCM_FMCR (SCM_BASE + 0x4)
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#define SCM_GPCR (SCM_BASE + 0x8)
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#define SCM_GCCR (SCM_BASE + 0xC)
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#define SCM_GCCR_DMA_CLK_EN_OFFSET 3
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#define SCM_GCCR_CSI_CLK_EN_OFFSET 2
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#define SCM_GCCR_MMA_CLK_EN_OFFSET 1
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#define SCM_GCCR_USBD_CLK_EN_OFFSET 0
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#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */
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