1442 lines
39 KiB
C
1442 lines
39 KiB
C
/*******************************************************************************
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Intel(R) Gigabit Ethernet Linux driver
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Copyright(c) 2007-2009 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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/* e1000_82575
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* e1000_82576
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*/
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/if_ether.h>
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#include "e1000_mac.h"
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#include "e1000_82575.h"
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static s32 igb_get_invariants_82575(struct e1000_hw *);
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static s32 igb_acquire_phy_82575(struct e1000_hw *);
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static void igb_release_phy_82575(struct e1000_hw *);
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static s32 igb_acquire_nvm_82575(struct e1000_hw *);
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static void igb_release_nvm_82575(struct e1000_hw *);
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static s32 igb_check_for_link_82575(struct e1000_hw *);
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static s32 igb_get_cfg_done_82575(struct e1000_hw *);
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static s32 igb_init_hw_82575(struct e1000_hw *);
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static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
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static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
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static s32 igb_reset_hw_82575(struct e1000_hw *);
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static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
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static s32 igb_setup_copper_link_82575(struct e1000_hw *);
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static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
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static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
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static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
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static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
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static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
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u16 *);
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static s32 igb_get_phy_id_82575(struct e1000_hw *);
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static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
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static bool igb_sgmii_active_82575(struct e1000_hw *);
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static s32 igb_reset_init_script_82575(struct e1000_hw *);
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static s32 igb_read_mac_addr_82575(struct e1000_hw *);
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static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
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static s32 igb_get_invariants_82575(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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struct e1000_nvm_info *nvm = &hw->nvm;
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struct e1000_mac_info *mac = &hw->mac;
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struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
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u32 eecd;
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s32 ret_val;
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u16 size;
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u32 ctrl_ext = 0;
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switch (hw->device_id) {
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case E1000_DEV_ID_82575EB_COPPER:
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case E1000_DEV_ID_82575EB_FIBER_SERDES:
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case E1000_DEV_ID_82575GB_QUAD_COPPER:
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mac->type = e1000_82575;
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break;
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case E1000_DEV_ID_82576:
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case E1000_DEV_ID_82576_NS:
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case E1000_DEV_ID_82576_NS_SERDES:
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case E1000_DEV_ID_82576_FIBER:
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case E1000_DEV_ID_82576_SERDES:
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case E1000_DEV_ID_82576_QUAD_COPPER:
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case E1000_DEV_ID_82576_SERDES_QUAD:
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mac->type = e1000_82576;
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break;
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default:
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return -E1000_ERR_MAC_INIT;
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break;
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}
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/* Set media type */
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/*
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* The 82575 uses bits 22:23 for link mode. The mode can be changed
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* based on the EEPROM. We cannot rely upon device ID. There
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* is no distinguishable difference between fiber and internal
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* SerDes mode on the 82575. There can be an external PHY attached
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* on the SGMII interface. For this, we'll set sgmii_active to true.
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*/
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phy->media_type = e1000_media_type_copper;
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dev_spec->sgmii_active = false;
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ctrl_ext = rd32(E1000_CTRL_EXT);
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switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
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case E1000_CTRL_EXT_LINK_MODE_SGMII:
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dev_spec->sgmii_active = true;
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ctrl_ext |= E1000_CTRL_I2C_ENA;
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break;
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case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
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hw->phy.media_type = e1000_media_type_internal_serdes;
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ctrl_ext |= E1000_CTRL_I2C_ENA;
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break;
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default:
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ctrl_ext &= ~E1000_CTRL_I2C_ENA;
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break;
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}
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wr32(E1000_CTRL_EXT, ctrl_ext);
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/* Set mta register count */
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mac->mta_reg_count = 128;
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/* Set rar entry count */
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mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
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if (mac->type == e1000_82576)
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mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
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/* Set if part includes ASF firmware */
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mac->asf_firmware_present = true;
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/* Set if manageability features are enabled. */
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mac->arc_subsystem_valid =
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(rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
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? true : false;
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/* physical interface link setup */
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mac->ops.setup_physical_interface =
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(hw->phy.media_type == e1000_media_type_copper)
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? igb_setup_copper_link_82575
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: igb_setup_serdes_link_82575;
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/* NVM initialization */
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eecd = rd32(E1000_EECD);
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nvm->opcode_bits = 8;
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nvm->delay_usec = 1;
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switch (nvm->override) {
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case e1000_nvm_override_spi_large:
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nvm->page_size = 32;
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nvm->address_bits = 16;
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break;
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case e1000_nvm_override_spi_small:
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nvm->page_size = 8;
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nvm->address_bits = 8;
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break;
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default:
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nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
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nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
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break;
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}
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nvm->type = e1000_nvm_eeprom_spi;
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size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
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E1000_EECD_SIZE_EX_SHIFT);
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/*
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* Added to a constant, "size" becomes the left-shift value
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* for setting word_size.
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*/
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size += NVM_WORD_SIZE_BASE_SHIFT;
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/* EEPROM access above 16k is unsupported */
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if (size > 14)
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size = 14;
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nvm->word_size = 1 << size;
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/* if 82576 then initialize mailbox parameters */
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if (mac->type == e1000_82576)
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igb_init_mbx_params_pf(hw);
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/* setup PHY parameters */
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if (phy->media_type != e1000_media_type_copper) {
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phy->type = e1000_phy_none;
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return 0;
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}
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phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
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phy->reset_delay_us = 100;
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/* PHY function pointers */
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if (igb_sgmii_active_82575(hw)) {
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phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
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phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
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phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
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} else {
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phy->ops.reset = igb_phy_hw_reset;
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phy->ops.read_reg = igb_read_phy_reg_igp;
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phy->ops.write_reg = igb_write_phy_reg_igp;
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}
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/* set lan id */
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hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
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E1000_STATUS_FUNC_SHIFT;
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/* Set phy->phy_addr and phy->id. */
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ret_val = igb_get_phy_id_82575(hw);
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if (ret_val)
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return ret_val;
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/* Verify phy id and set remaining function pointers */
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switch (phy->id) {
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case M88E1111_I_PHY_ID:
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phy->type = e1000_phy_m88;
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phy->ops.get_phy_info = igb_get_phy_info_m88;
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phy->ops.get_cable_length = igb_get_cable_length_m88;
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phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
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break;
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case IGP03E1000_E_PHY_ID:
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phy->type = e1000_phy_igp_3;
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phy->ops.get_phy_info = igb_get_phy_info_igp;
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phy->ops.get_cable_length = igb_get_cable_length_igp_2;
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phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
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phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
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phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
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break;
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default:
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return -E1000_ERR_PHY;
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}
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return 0;
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}
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/**
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* igb_acquire_phy_82575 - Acquire rights to access PHY
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* @hw: pointer to the HW structure
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*
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* Acquire access rights to the correct PHY. This is a
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* function pointer entry point called by the api module.
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**/
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static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
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{
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u16 mask;
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mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
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return igb_acquire_swfw_sync_82575(hw, mask);
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}
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/**
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* igb_release_phy_82575 - Release rights to access PHY
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* @hw: pointer to the HW structure
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*
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* A wrapper to release access rights to the correct PHY. This is a
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* function pointer entry point called by the api module.
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**/
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static void igb_release_phy_82575(struct e1000_hw *hw)
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{
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u16 mask;
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mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
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igb_release_swfw_sync_82575(hw, mask);
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}
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/**
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* igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
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* @hw: pointer to the HW structure
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* @offset: register offset to be read
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* @data: pointer to the read data
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*
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* Reads the PHY register at offset using the serial gigabit media independent
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* interface and stores the retrieved information in data.
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**/
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static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
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u16 *data)
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{
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struct e1000_phy_info *phy = &hw->phy;
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u32 i, i2ccmd = 0;
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if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
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hw_dbg("PHY Address %u is out of range\n", offset);
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return -E1000_ERR_PARAM;
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}
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/*
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* Set up Op-code, Phy Address, and register address in the I2CCMD
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* register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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*/
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i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
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(phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
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(E1000_I2CCMD_OPCODE_READ));
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wr32(E1000_I2CCMD, i2ccmd);
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/* Poll the ready bit to see if the I2C read completed */
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for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
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udelay(50);
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i2ccmd = rd32(E1000_I2CCMD);
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if (i2ccmd & E1000_I2CCMD_READY)
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break;
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}
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if (!(i2ccmd & E1000_I2CCMD_READY)) {
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hw_dbg("I2CCMD Read did not complete\n");
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return -E1000_ERR_PHY;
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}
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if (i2ccmd & E1000_I2CCMD_ERROR) {
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hw_dbg("I2CCMD Error bit set\n");
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return -E1000_ERR_PHY;
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}
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/* Need to byte-swap the 16-bit value. */
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*data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
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return 0;
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}
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/**
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* igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
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* @hw: pointer to the HW structure
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* @offset: register offset to write to
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* @data: data to write at register offset
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*
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* Writes the data to PHY register at the offset using the serial gigabit
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* media independent interface.
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**/
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static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
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u16 data)
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{
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struct e1000_phy_info *phy = &hw->phy;
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u32 i, i2ccmd = 0;
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u16 phy_data_swapped;
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if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
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hw_dbg("PHY Address %d is out of range\n", offset);
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return -E1000_ERR_PARAM;
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}
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/* Swap the data bytes for the I2C interface */
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phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
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/*
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* Set up Op-code, Phy Address, and register address in the I2CCMD
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* register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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*/
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i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
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(phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
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E1000_I2CCMD_OPCODE_WRITE |
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phy_data_swapped);
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wr32(E1000_I2CCMD, i2ccmd);
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/* Poll the ready bit to see if the I2C read completed */
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for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
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udelay(50);
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i2ccmd = rd32(E1000_I2CCMD);
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if (i2ccmd & E1000_I2CCMD_READY)
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break;
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}
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if (!(i2ccmd & E1000_I2CCMD_READY)) {
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hw_dbg("I2CCMD Write did not complete\n");
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return -E1000_ERR_PHY;
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}
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if (i2ccmd & E1000_I2CCMD_ERROR) {
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hw_dbg("I2CCMD Error bit set\n");
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return -E1000_ERR_PHY;
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}
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return 0;
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}
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/**
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* igb_get_phy_id_82575 - Retrieve PHY addr and id
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* @hw: pointer to the HW structure
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*
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* Retrieves the PHY address and ID for both PHY's which do and do not use
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* sgmi interface.
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**/
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static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val = 0;
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u16 phy_id;
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u32 ctrl_ext;
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/*
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* For SGMII PHYs, we try the list of possible addresses until
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* we find one that works. For non-SGMII PHYs
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* (e.g. integrated copper PHYs), an address of 1 should
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* work. The result of this function should mean phy->phy_addr
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* and phy->id are set correctly.
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*/
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if (!(igb_sgmii_active_82575(hw))) {
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phy->addr = 1;
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ret_val = igb_get_phy_id(hw);
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goto out;
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}
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/* Power on sgmii phy if it is disabled */
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ctrl_ext = rd32(E1000_CTRL_EXT);
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wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
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wrfl();
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msleep(300);
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/*
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* The address field in the I2CCMD register is 3 bits and 0 is invalid.
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* Therefore, we need to test 1-7
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*/
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for (phy->addr = 1; phy->addr < 8; phy->addr++) {
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ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
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if (ret_val == 0) {
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hw_dbg("Vendor ID 0x%08X read at address %u\n",
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phy_id, phy->addr);
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/*
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* At the time of this writing, The M88 part is
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* the only supported SGMII PHY product.
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*/
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if (phy_id == M88_VENDOR)
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break;
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} else {
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hw_dbg("PHY address %u was unreadable\n", phy->addr);
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}
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}
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/* A valid PHY type couldn't be found. */
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if (phy->addr == 8) {
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phy->addr = 0;
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ret_val = -E1000_ERR_PHY;
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goto out;
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} else {
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ret_val = igb_get_phy_id(hw);
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}
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/* restore previous sfp cage power state */
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wr32(E1000_CTRL_EXT, ctrl_ext);
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out:
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return ret_val;
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}
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/**
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* igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
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* @hw: pointer to the HW structure
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*
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* Resets the PHY using the serial gigabit media independent interface.
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**/
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static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
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{
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s32 ret_val;
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/*
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* This isn't a true "hard" reset, but is the only reset
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* available to us at this time.
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*/
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hw_dbg("Soft resetting SGMII attached PHY...\n");
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/*
|
|
* SFP documentation requires the following to configure the SPF module
|
|
* to work on SGMII. No further documentation is given.
|
|
*/
|
|
ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
ret_val = igb_phy_sw_reset(hw);
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
|
|
* @hw: pointer to the HW structure
|
|
* @active: true to enable LPLU, false to disable
|
|
*
|
|
* Sets the LPLU D0 state according to the active flag. When
|
|
* activating LPLU this function also disables smart speed
|
|
* and vice versa. LPLU will not be activated unless the
|
|
* device autonegotiation advertisement meets standards of
|
|
* either 10 or 10/100 or 10/100/1000 at all duplexes.
|
|
* This is a function pointer entry point only called by
|
|
* PHY setup routines.
|
|
**/
|
|
static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
|
|
{
|
|
struct e1000_phy_info *phy = &hw->phy;
|
|
s32 ret_val;
|
|
u16 data;
|
|
|
|
ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
if (active) {
|
|
data |= IGP02E1000_PM_D0_LPLU;
|
|
ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
|
|
data);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
/* When LPLU is enabled, we should disable SmartSpeed */
|
|
ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
|
|
&data);
|
|
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
|
|
ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
|
|
data);
|
|
if (ret_val)
|
|
goto out;
|
|
} else {
|
|
data &= ~IGP02E1000_PM_D0_LPLU;
|
|
ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
|
|
data);
|
|
/*
|
|
* LPLU and SmartSpeed are mutually exclusive. LPLU is used
|
|
* during Dx states where the power conservation is most
|
|
* important. During driver activity we should enable
|
|
* SmartSpeed, so performance is maintained.
|
|
*/
|
|
if (phy->smart_speed == e1000_smart_speed_on) {
|
|
ret_val = phy->ops.read_reg(hw,
|
|
IGP01E1000_PHY_PORT_CONFIG, &data);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
data |= IGP01E1000_PSCFR_SMART_SPEED;
|
|
ret_val = phy->ops.write_reg(hw,
|
|
IGP01E1000_PHY_PORT_CONFIG, data);
|
|
if (ret_val)
|
|
goto out;
|
|
} else if (phy->smart_speed == e1000_smart_speed_off) {
|
|
ret_val = phy->ops.read_reg(hw,
|
|
IGP01E1000_PHY_PORT_CONFIG, &data);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
|
|
ret_val = phy->ops.write_reg(hw,
|
|
IGP01E1000_PHY_PORT_CONFIG, data);
|
|
if (ret_val)
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* igb_acquire_nvm_82575 - Request for access to EEPROM
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Acquire the necessary semaphores for exclusive access to the EEPROM.
|
|
* Set the EEPROM access request bit and wait for EEPROM access grant bit.
|
|
* Return successful if access grant bit set, else clear the request for
|
|
* EEPROM access and return -E1000_ERR_NVM (-1).
|
|
**/
|
|
static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
|
|
{
|
|
s32 ret_val;
|
|
|
|
ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
ret_val = igb_acquire_nvm(hw);
|
|
|
|
if (ret_val)
|
|
igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* igb_release_nvm_82575 - Release exclusive access to EEPROM
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Stop any current commands to the EEPROM and clear the EEPROM request bit,
|
|
* then release the semaphores acquired.
|
|
**/
|
|
static void igb_release_nvm_82575(struct e1000_hw *hw)
|
|
{
|
|
igb_release_nvm(hw);
|
|
igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
|
|
}
|
|
|
|
/**
|
|
* igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
|
|
* @hw: pointer to the HW structure
|
|
* @mask: specifies which semaphore to acquire
|
|
*
|
|
* Acquire the SW/FW semaphore to access the PHY or NVM. The mask
|
|
* will also specify which port we're acquiring the lock for.
|
|
**/
|
|
static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
|
|
{
|
|
u32 swfw_sync;
|
|
u32 swmask = mask;
|
|
u32 fwmask = mask << 16;
|
|
s32 ret_val = 0;
|
|
s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
|
|
|
|
while (i < timeout) {
|
|
if (igb_get_hw_semaphore(hw)) {
|
|
ret_val = -E1000_ERR_SWFW_SYNC;
|
|
goto out;
|
|
}
|
|
|
|
swfw_sync = rd32(E1000_SW_FW_SYNC);
|
|
if (!(swfw_sync & (fwmask | swmask)))
|
|
break;
|
|
|
|
/*
|
|
* Firmware currently using resource (fwmask)
|
|
* or other software thread using resource (swmask)
|
|
*/
|
|
igb_put_hw_semaphore(hw);
|
|
mdelay(5);
|
|
i++;
|
|
}
|
|
|
|
if (i == timeout) {
|
|
hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
|
|
ret_val = -E1000_ERR_SWFW_SYNC;
|
|
goto out;
|
|
}
|
|
|
|
swfw_sync |= swmask;
|
|
wr32(E1000_SW_FW_SYNC, swfw_sync);
|
|
|
|
igb_put_hw_semaphore(hw);
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* igb_release_swfw_sync_82575 - Release SW/FW semaphore
|
|
* @hw: pointer to the HW structure
|
|
* @mask: specifies which semaphore to acquire
|
|
*
|
|
* Release the SW/FW semaphore used to access the PHY or NVM. The mask
|
|
* will also specify which port we're releasing the lock for.
|
|
**/
|
|
static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
|
|
{
|
|
u32 swfw_sync;
|
|
|
|
while (igb_get_hw_semaphore(hw) != 0);
|
|
/* Empty */
|
|
|
|
swfw_sync = rd32(E1000_SW_FW_SYNC);
|
|
swfw_sync &= ~mask;
|
|
wr32(E1000_SW_FW_SYNC, swfw_sync);
|
|
|
|
igb_put_hw_semaphore(hw);
|
|
}
|
|
|
|
/**
|
|
* igb_get_cfg_done_82575 - Read config done bit
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Read the management control register for the config done bit for
|
|
* completion status. NOTE: silicon which is EEPROM-less will fail trying
|
|
* to read the config done bit, so an error is *ONLY* logged and returns
|
|
* 0. If we were to return with error, EEPROM-less silicon
|
|
* would not be able to be reset or change link.
|
|
**/
|
|
static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
|
|
{
|
|
s32 timeout = PHY_CFG_TIMEOUT;
|
|
s32 ret_val = 0;
|
|
u32 mask = E1000_NVM_CFG_DONE_PORT_0;
|
|
|
|
if (hw->bus.func == 1)
|
|
mask = E1000_NVM_CFG_DONE_PORT_1;
|
|
|
|
while (timeout) {
|
|
if (rd32(E1000_EEMNGCTL) & mask)
|
|
break;
|
|
msleep(1);
|
|
timeout--;
|
|
}
|
|
if (!timeout)
|
|
hw_dbg("MNG configuration cycle has not completed.\n");
|
|
|
|
/* If EEPROM is not marked present, init the PHY manually */
|
|
if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
|
|
(hw->phy.type == e1000_phy_igp_3))
|
|
igb_phy_init_script_igp3(hw);
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* igb_check_for_link_82575 - Check for link
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* If sgmii is enabled, then use the pcs register to determine link, otherwise
|
|
* use the generic interface for determining link.
|
|
**/
|
|
static s32 igb_check_for_link_82575(struct e1000_hw *hw)
|
|
{
|
|
s32 ret_val;
|
|
u16 speed, duplex;
|
|
|
|
/* SGMII link check is done through the PCS register. */
|
|
if ((hw->phy.media_type != e1000_media_type_copper) ||
|
|
(igb_sgmii_active_82575(hw))) {
|
|
ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
|
|
&duplex);
|
|
/*
|
|
* Use this flag to determine if link needs to be checked or
|
|
* not. If we have link clear the flag so that we do not
|
|
* continue to check for link.
|
|
*/
|
|
hw->mac.get_link_status = !hw->mac.serdes_has_link;
|
|
} else {
|
|
ret_val = igb_check_for_copper_link(hw);
|
|
}
|
|
|
|
return ret_val;
|
|
}
|
|
/**
|
|
* igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
|
|
* @hw: pointer to the HW structure
|
|
* @speed: stores the current speed
|
|
* @duplex: stores the current duplex
|
|
*
|
|
* Using the physical coding sub-layer (PCS), retrieve the current speed and
|
|
* duplex, then store the values in the pointers provided.
|
|
**/
|
|
static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
|
|
u16 *duplex)
|
|
{
|
|
struct e1000_mac_info *mac = &hw->mac;
|
|
u32 pcs;
|
|
|
|
/* Set up defaults for the return values of this function */
|
|
mac->serdes_has_link = false;
|
|
*speed = 0;
|
|
*duplex = 0;
|
|
|
|
/*
|
|
* Read the PCS Status register for link state. For non-copper mode,
|
|
* the status register is not accurate. The PCS status register is
|
|
* used instead.
|
|
*/
|
|
pcs = rd32(E1000_PCS_LSTAT);
|
|
|
|
/*
|
|
* The link up bit determines when link is up on autoneg. The sync ok
|
|
* gets set once both sides sync up and agree upon link. Stable link
|
|
* can be determined by checking for both link up and link sync ok
|
|
*/
|
|
if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
|
|
mac->serdes_has_link = true;
|
|
|
|
/* Detect and store PCS speed */
|
|
if (pcs & E1000_PCS_LSTS_SPEED_1000) {
|
|
*speed = SPEED_1000;
|
|
} else if (pcs & E1000_PCS_LSTS_SPEED_100) {
|
|
*speed = SPEED_100;
|
|
} else {
|
|
*speed = SPEED_10;
|
|
}
|
|
|
|
/* Detect and store PCS duplex */
|
|
if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
|
|
*duplex = FULL_DUPLEX;
|
|
} else {
|
|
*duplex = HALF_DUPLEX;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* igb_shutdown_serdes_link_82575 - Remove link during power down
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* In the case of fiber serdes, shut down optics and PCS on driver unload
|
|
* when management pass thru is not enabled.
|
|
**/
|
|
void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
|
|
{
|
|
u32 reg;
|
|
|
|
if (hw->phy.media_type != e1000_media_type_internal_serdes ||
|
|
igb_sgmii_active_82575(hw))
|
|
return;
|
|
|
|
/* if the management interface is not enabled, then power down */
|
|
if (!igb_enable_mng_pass_thru(hw)) {
|
|
/* Disable PCS to turn off link */
|
|
reg = rd32(E1000_PCS_CFG0);
|
|
reg &= ~E1000_PCS_CFG_PCS_EN;
|
|
wr32(E1000_PCS_CFG0, reg);
|
|
|
|
/* shutdown the laser */
|
|
reg = rd32(E1000_CTRL_EXT);
|
|
reg |= E1000_CTRL_EXT_SDP3_DATA;
|
|
wr32(E1000_CTRL_EXT, reg);
|
|
|
|
/* flush the write to verify completion */
|
|
wrfl();
|
|
msleep(1);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
/**
|
|
* igb_reset_hw_82575 - Reset hardware
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* This resets the hardware into a known state. This is a
|
|
* function pointer entry point called by the api module.
|
|
**/
|
|
static s32 igb_reset_hw_82575(struct e1000_hw *hw)
|
|
{
|
|
u32 ctrl, icr;
|
|
s32 ret_val;
|
|
|
|
/*
|
|
* Prevent the PCI-E bus from sticking if there is no TLP connection
|
|
* on the last TLP read/write transaction when MAC is reset.
|
|
*/
|
|
ret_val = igb_disable_pcie_master(hw);
|
|
if (ret_val)
|
|
hw_dbg("PCI-E Master disable polling has failed.\n");
|
|
|
|
/* set the completion timeout for interface */
|
|
ret_val = igb_set_pcie_completion_timeout(hw);
|
|
if (ret_val) {
|
|
hw_dbg("PCI-E Set completion timeout has failed.\n");
|
|
}
|
|
|
|
hw_dbg("Masking off all interrupts\n");
|
|
wr32(E1000_IMC, 0xffffffff);
|
|
|
|
wr32(E1000_RCTL, 0);
|
|
wr32(E1000_TCTL, E1000_TCTL_PSP);
|
|
wrfl();
|
|
|
|
msleep(10);
|
|
|
|
ctrl = rd32(E1000_CTRL);
|
|
|
|
hw_dbg("Issuing a global reset to MAC\n");
|
|
wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
|
|
|
|
ret_val = igb_get_auto_rd_done(hw);
|
|
if (ret_val) {
|
|
/*
|
|
* When auto config read does not complete, do not
|
|
* return with an error. This can happen in situations
|
|
* where there is no eeprom and prevents getting link.
|
|
*/
|
|
hw_dbg("Auto Read Done did not complete\n");
|
|
}
|
|
|
|
/* If EEPROM is not present, run manual init scripts */
|
|
if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
|
|
igb_reset_init_script_82575(hw);
|
|
|
|
/* Clear any pending interrupt events. */
|
|
wr32(E1000_IMC, 0xffffffff);
|
|
icr = rd32(E1000_ICR);
|
|
|
|
/* Install any alternate MAC address into RAR0 */
|
|
ret_val = igb_check_alt_mac_addr(hw);
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* igb_init_hw_82575 - Initialize hardware
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* This inits the hardware readying it for operation.
|
|
**/
|
|
static s32 igb_init_hw_82575(struct e1000_hw *hw)
|
|
{
|
|
struct e1000_mac_info *mac = &hw->mac;
|
|
s32 ret_val;
|
|
u16 i, rar_count = mac->rar_entry_count;
|
|
|
|
/* Initialize identification LED */
|
|
ret_val = igb_id_led_init(hw);
|
|
if (ret_val) {
|
|
hw_dbg("Error initializing identification LED\n");
|
|
/* This is not fatal and we should not stop init due to this */
|
|
}
|
|
|
|
/* Disabling VLAN filtering */
|
|
hw_dbg("Initializing the IEEE VLAN\n");
|
|
igb_clear_vfta(hw);
|
|
|
|
/* Setup the receive address */
|
|
igb_init_rx_addrs(hw, rar_count);
|
|
|
|
/* Zero out the Multicast HASH table */
|
|
hw_dbg("Zeroing the MTA\n");
|
|
for (i = 0; i < mac->mta_reg_count; i++)
|
|
array_wr32(E1000_MTA, i, 0);
|
|
|
|
/* Setup link and flow control */
|
|
ret_val = igb_setup_link(hw);
|
|
|
|
/*
|
|
* Clear all of the statistics registers (clear on read). It is
|
|
* important that we do this after we have tried to establish link
|
|
* because the symbol error count will increment wildly if there
|
|
* is no link.
|
|
*/
|
|
igb_clear_hw_cntrs_82575(hw);
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* igb_setup_copper_link_82575 - Configure copper link settings
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Configures the link for auto-neg or forced speed and duplex. Then we check
|
|
* for link, once link is established calls to configure collision distance
|
|
* and flow control are called.
|
|
**/
|
|
static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
|
|
{
|
|
u32 ctrl;
|
|
s32 ret_val;
|
|
bool link;
|
|
|
|
ctrl = rd32(E1000_CTRL);
|
|
ctrl |= E1000_CTRL_SLU;
|
|
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
|
|
wr32(E1000_CTRL, ctrl);
|
|
|
|
ret_val = igb_setup_serdes_link_82575(hw);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
|
|
ret_val = hw->phy.ops.reset(hw);
|
|
if (ret_val) {
|
|
hw_dbg("Error resetting the PHY.\n");
|
|
goto out;
|
|
}
|
|
}
|
|
switch (hw->phy.type) {
|
|
case e1000_phy_m88:
|
|
ret_val = igb_copper_link_setup_m88(hw);
|
|
break;
|
|
case e1000_phy_igp_3:
|
|
ret_val = igb_copper_link_setup_igp(hw);
|
|
break;
|
|
default:
|
|
ret_val = -E1000_ERR_PHY;
|
|
break;
|
|
}
|
|
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
if (hw->mac.autoneg) {
|
|
/*
|
|
* Setup autoneg and flow control advertisement
|
|
* and perform autonegotiation.
|
|
*/
|
|
ret_val = igb_copper_link_autoneg(hw);
|
|
if (ret_val)
|
|
goto out;
|
|
} else {
|
|
/*
|
|
* PHY will be set to 10H, 10F, 100H or 100F
|
|
* depending on user settings.
|
|
*/
|
|
hw_dbg("Forcing Speed and Duplex\n");
|
|
ret_val = hw->phy.ops.force_speed_duplex(hw);
|
|
if (ret_val) {
|
|
hw_dbg("Error Forcing Speed and Duplex\n");
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Check link status. Wait up to 100 microseconds for link to become
|
|
* valid.
|
|
*/
|
|
ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
if (link) {
|
|
hw_dbg("Valid link established!!!\n");
|
|
/* Config the MAC and PHY after link is up */
|
|
igb_config_collision_dist(hw);
|
|
ret_val = igb_config_fc_after_link_up(hw);
|
|
} else {
|
|
hw_dbg("Unable to establish link!!!\n");
|
|
}
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* igb_setup_serdes_link_82575 - Setup link for fiber/serdes
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Configures speed and duplex for fiber and serdes links.
|
|
**/
|
|
static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
|
|
{
|
|
u32 ctrl_reg, reg;
|
|
|
|
if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
|
|
!igb_sgmii_active_82575(hw))
|
|
return 0;
|
|
|
|
/*
|
|
* On the 82575, SerDes loopback mode persists until it is
|
|
* explicitly turned off or a power cycle is performed. A read to
|
|
* the register does not indicate its status. Therefore, we ensure
|
|
* loopback mode is disabled during initialization.
|
|
*/
|
|
wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
|
|
|
|
/* power on the sfp cage if present */
|
|
reg = rd32(E1000_CTRL_EXT);
|
|
reg &= ~E1000_CTRL_EXT_SDP3_DATA;
|
|
wr32(E1000_CTRL_EXT, reg);
|
|
|
|
ctrl_reg = rd32(E1000_CTRL);
|
|
ctrl_reg |= E1000_CTRL_SLU;
|
|
|
|
if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
|
|
/* set both sw defined pins */
|
|
ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
|
|
|
|
/* Set switch control to serdes energy detect */
|
|
reg = rd32(E1000_CONNSW);
|
|
reg |= E1000_CONNSW_ENRGSRC;
|
|
wr32(E1000_CONNSW, reg);
|
|
}
|
|
|
|
reg = rd32(E1000_PCS_LCTL);
|
|
|
|
if (igb_sgmii_active_82575(hw)) {
|
|
/* allow time for SFP cage to power up phy */
|
|
msleep(300);
|
|
|
|
/* AN time out should be disabled for SGMII mode */
|
|
reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
|
|
} else {
|
|
ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
|
|
E1000_CTRL_FD | E1000_CTRL_FRCDPX;
|
|
}
|
|
|
|
wr32(E1000_CTRL, ctrl_reg);
|
|
|
|
/*
|
|
* New SerDes mode allows for forcing speed or autonegotiating speed
|
|
* at 1gb. Autoneg should be default set by most drivers. This is the
|
|
* mode that will be compatible with older link partners and switches.
|
|
* However, both are supported by the hardware and some drivers/tools.
|
|
*/
|
|
|
|
reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
|
|
E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
|
|
|
|
/*
|
|
* We force flow control to prevent the CTRL register values from being
|
|
* overwritten by the autonegotiated flow control values
|
|
*/
|
|
reg |= E1000_PCS_LCTL_FORCE_FCTRL;
|
|
|
|
/*
|
|
* we always set sgmii to autoneg since it is the phy that will be
|
|
* forcing the link and the serdes is just a go-between
|
|
*/
|
|
if (hw->mac.autoneg || igb_sgmii_active_82575(hw)) {
|
|
/* Set PCS register for autoneg */
|
|
reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
|
|
E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
|
|
E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
|
|
E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
|
|
hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
|
|
} else {
|
|
/* Set PCS register for forced speed */
|
|
reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
|
|
E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
|
|
E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
|
|
E1000_PCS_LCTL_FSD | /* Force Speed */
|
|
E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
|
|
hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
|
|
}
|
|
|
|
wr32(E1000_PCS_LCTL, reg);
|
|
|
|
if (!igb_sgmii_active_82575(hw))
|
|
igb_force_mac_fc(hw);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* igb_sgmii_active_82575 - Return sgmii state
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* 82575 silicon has a serialized gigabit media independent interface (sgmii)
|
|
* which can be enabled for use in the embedded applications. Simply
|
|
* return the current state of the sgmii interface.
|
|
**/
|
|
static bool igb_sgmii_active_82575(struct e1000_hw *hw)
|
|
{
|
|
struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
|
|
return dev_spec->sgmii_active;
|
|
}
|
|
|
|
/**
|
|
* igb_reset_init_script_82575 - Inits HW defaults after reset
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Inits recommended HW defaults after a reset when there is no EEPROM
|
|
* detected. This is only for the 82575.
|
|
**/
|
|
static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
|
|
{
|
|
if (hw->mac.type == e1000_82575) {
|
|
hw_dbg("Running reset init script for 82575\n");
|
|
/* SerDes configuration via SERDESCTRL */
|
|
igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
|
|
igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
|
|
igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
|
|
igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
|
|
|
|
/* CCM configuration via CCMCTL register */
|
|
igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
|
|
igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
|
|
|
|
/* PCIe lanes configuration */
|
|
igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
|
|
igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
|
|
igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
|
|
igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
|
|
|
|
/* PCIe PLL Configuration */
|
|
igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
|
|
igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
|
|
igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* igb_read_mac_addr_82575 - Read device MAC address
|
|
* @hw: pointer to the HW structure
|
|
**/
|
|
static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
|
|
{
|
|
s32 ret_val = 0;
|
|
|
|
/*
|
|
* If there's an alternate MAC address place it in RAR0
|
|
* so that it will override the Si installed default perm
|
|
* address.
|
|
*/
|
|
ret_val = igb_check_alt_mac_addr(hw);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
ret_val = igb_read_mac_addr(hw);
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Clears the hardware counters by reading the counter registers.
|
|
**/
|
|
static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
|
|
{
|
|
u32 temp;
|
|
|
|
igb_clear_hw_cntrs_base(hw);
|
|
|
|
temp = rd32(E1000_PRC64);
|
|
temp = rd32(E1000_PRC127);
|
|
temp = rd32(E1000_PRC255);
|
|
temp = rd32(E1000_PRC511);
|
|
temp = rd32(E1000_PRC1023);
|
|
temp = rd32(E1000_PRC1522);
|
|
temp = rd32(E1000_PTC64);
|
|
temp = rd32(E1000_PTC127);
|
|
temp = rd32(E1000_PTC255);
|
|
temp = rd32(E1000_PTC511);
|
|
temp = rd32(E1000_PTC1023);
|
|
temp = rd32(E1000_PTC1522);
|
|
|
|
temp = rd32(E1000_ALGNERRC);
|
|
temp = rd32(E1000_RXERRC);
|
|
temp = rd32(E1000_TNCRS);
|
|
temp = rd32(E1000_CEXTERR);
|
|
temp = rd32(E1000_TSCTC);
|
|
temp = rd32(E1000_TSCTFC);
|
|
|
|
temp = rd32(E1000_MGTPRC);
|
|
temp = rd32(E1000_MGTPDC);
|
|
temp = rd32(E1000_MGTPTC);
|
|
|
|
temp = rd32(E1000_IAC);
|
|
temp = rd32(E1000_ICRXOC);
|
|
|
|
temp = rd32(E1000_ICRXPTC);
|
|
temp = rd32(E1000_ICRXATC);
|
|
temp = rd32(E1000_ICTXPTC);
|
|
temp = rd32(E1000_ICTXATC);
|
|
temp = rd32(E1000_ICTXQEC);
|
|
temp = rd32(E1000_ICTXQMTC);
|
|
temp = rd32(E1000_ICRXDMTC);
|
|
|
|
temp = rd32(E1000_CBTMPC);
|
|
temp = rd32(E1000_HTDPMC);
|
|
temp = rd32(E1000_CBRMPC);
|
|
temp = rd32(E1000_RPTHC);
|
|
temp = rd32(E1000_HGPTC);
|
|
temp = rd32(E1000_HTCBDPC);
|
|
temp = rd32(E1000_HGORCL);
|
|
temp = rd32(E1000_HGORCH);
|
|
temp = rd32(E1000_HGOTCL);
|
|
temp = rd32(E1000_HGOTCH);
|
|
temp = rd32(E1000_LENERRS);
|
|
|
|
/* This register should not be read in copper configurations */
|
|
if (hw->phy.media_type == e1000_media_type_internal_serdes ||
|
|
igb_sgmii_active_82575(hw))
|
|
temp = rd32(E1000_SCVPC);
|
|
}
|
|
|
|
/**
|
|
* igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* After rx enable if managability is enabled then there is likely some
|
|
* bad data at the start of the fifo and possibly in the DMA fifo. This
|
|
* function clears the fifos and flushes any packets that came in as rx was
|
|
* being enabled.
|
|
**/
|
|
void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
|
|
{
|
|
u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
|
|
int i, ms_wait;
|
|
|
|
if (hw->mac.type != e1000_82575 ||
|
|
!(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
|
|
return;
|
|
|
|
/* Disable all RX queues */
|
|
for (i = 0; i < 4; i++) {
|
|
rxdctl[i] = rd32(E1000_RXDCTL(i));
|
|
wr32(E1000_RXDCTL(i),
|
|
rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
|
|
}
|
|
/* Poll all queues to verify they have shut down */
|
|
for (ms_wait = 0; ms_wait < 10; ms_wait++) {
|
|
msleep(1);
|
|
rx_enabled = 0;
|
|
for (i = 0; i < 4; i++)
|
|
rx_enabled |= rd32(E1000_RXDCTL(i));
|
|
if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
|
|
break;
|
|
}
|
|
|
|
if (ms_wait == 10)
|
|
hw_dbg("Queue disable timed out after 10ms\n");
|
|
|
|
/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
|
|
* incoming packets are rejected. Set enable and wait 2ms so that
|
|
* any packet that was coming in as RCTL.EN was set is flushed
|
|
*/
|
|
rfctl = rd32(E1000_RFCTL);
|
|
wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
|
|
|
|
rlpml = rd32(E1000_RLPML);
|
|
wr32(E1000_RLPML, 0);
|
|
|
|
rctl = rd32(E1000_RCTL);
|
|
temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
|
|
temp_rctl |= E1000_RCTL_LPE;
|
|
|
|
wr32(E1000_RCTL, temp_rctl);
|
|
wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
|
|
wrfl();
|
|
msleep(2);
|
|
|
|
/* Enable RX queues that were previously enabled and restore our
|
|
* previous state
|
|
*/
|
|
for (i = 0; i < 4; i++)
|
|
wr32(E1000_RXDCTL(i), rxdctl[i]);
|
|
wr32(E1000_RCTL, rctl);
|
|
wrfl();
|
|
|
|
wr32(E1000_RLPML, rlpml);
|
|
wr32(E1000_RFCTL, rfctl);
|
|
|
|
/* Flush receive errors generated by workaround */
|
|
rd32(E1000_ROC);
|
|
rd32(E1000_RNBC);
|
|
rd32(E1000_MPC);
|
|
}
|
|
|
|
/**
|
|
* igb_set_pcie_completion_timeout - set pci-e completion timeout
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
|
|
* however the hardware default for these parts is 500us to 1ms which is less
|
|
* than the 10ms recommended by the pci-e spec. To address this we need to
|
|
* increase the value to either 10ms to 200ms for capability version 1 config,
|
|
* or 16ms to 55ms for version 2.
|
|
**/
|
|
static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
|
|
{
|
|
u32 gcr = rd32(E1000_GCR);
|
|
s32 ret_val = 0;
|
|
u16 pcie_devctl2;
|
|
|
|
/* only take action if timeout value is defaulted to 0 */
|
|
if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
|
|
goto out;
|
|
|
|
/*
|
|
* if capababilities version is type 1 we can write the
|
|
* timeout of 10ms to 200ms through the GCR register
|
|
*/
|
|
if (!(gcr & E1000_GCR_CAP_VER2)) {
|
|
gcr |= E1000_GCR_CMPL_TMOUT_10ms;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* for version 2 capabilities we need to write the config space
|
|
* directly in order to set the completion timeout value for
|
|
* 16ms to 55ms
|
|
*/
|
|
ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
|
|
&pcie_devctl2);
|
|
if (ret_val)
|
|
goto out;
|
|
|
|
pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
|
|
|
|
ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
|
|
&pcie_devctl2);
|
|
out:
|
|
/* disable completion timeout resend */
|
|
gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
|
|
|
|
wr32(E1000_GCR, gcr);
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
|
|
* @hw: pointer to the hardware struct
|
|
* @enable: state to enter, either enabled or disabled
|
|
*
|
|
* enables/disables L2 switch loopback functionality.
|
|
**/
|
|
void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
|
|
{
|
|
u32 dtxswc = rd32(E1000_DTXSWC);
|
|
|
|
if (enable)
|
|
dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
|
|
else
|
|
dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
|
|
|
|
wr32(E1000_DTXSWC, dtxswc);
|
|
}
|
|
|
|
/**
|
|
* igb_vmdq_set_replication_pf - enable or disable vmdq replication
|
|
* @hw: pointer to the hardware struct
|
|
* @enable: state to enter, either enabled or disabled
|
|
*
|
|
* enables/disables replication of packets across multiple pools.
|
|
**/
|
|
void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
|
|
{
|
|
u32 vt_ctl = rd32(E1000_VT_CTL);
|
|
|
|
if (enable)
|
|
vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
|
|
else
|
|
vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
|
|
|
|
wr32(E1000_VT_CTL, vt_ctl);
|
|
}
|
|
|
|
static struct e1000_mac_operations e1000_mac_ops_82575 = {
|
|
.reset_hw = igb_reset_hw_82575,
|
|
.init_hw = igb_init_hw_82575,
|
|
.check_for_link = igb_check_for_link_82575,
|
|
.rar_set = igb_rar_set,
|
|
.read_mac_addr = igb_read_mac_addr_82575,
|
|
.get_speed_and_duplex = igb_get_speed_and_duplex_copper,
|
|
};
|
|
|
|
static struct e1000_phy_operations e1000_phy_ops_82575 = {
|
|
.acquire = igb_acquire_phy_82575,
|
|
.get_cfg_done = igb_get_cfg_done_82575,
|
|
.release = igb_release_phy_82575,
|
|
};
|
|
|
|
static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
|
|
.acquire = igb_acquire_nvm_82575,
|
|
.read = igb_read_nvm_eerd,
|
|
.release = igb_release_nvm_82575,
|
|
.write = igb_write_nvm_spi,
|
|
};
|
|
|
|
const struct e1000_info e1000_82575_info = {
|
|
.get_invariants = igb_get_invariants_82575,
|
|
.mac_ops = &e1000_mac_ops_82575,
|
|
.phy_ops = &e1000_phy_ops_82575,
|
|
.nvm_ops = &e1000_nvm_ops_82575,
|
|
};
|
|
|