137 lines
3.1 KiB
C
137 lines
3.1 KiB
C
/*
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* Helper functions for the SPI-3 bridge FPGA on the Radisys ENP2611
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* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
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* Dedicated to Marija Kulikova.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include "caleb.h"
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#define CALEB_IDLO 0x00
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#define CALEB_IDHI 0x01
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#define CALEB_RID 0x02
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#define CALEB_RESET 0x03
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#define CALEB_INTREN0 0x04
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#define CALEB_INTREN1 0x05
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#define CALEB_INTRSTAT0 0x06
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#define CALEB_INTRSTAT1 0x07
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#define CALEB_PORTEN 0x08
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#define CALEB_BURST 0x09
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#define CALEB_PORTPAUS 0x0A
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#define CALEB_PORTPAUSD 0x0B
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#define CALEB_PHY0RX 0x10
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#define CALEB_PHY1RX 0x11
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#define CALEB_PHY0TX 0x12
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#define CALEB_PHY1TX 0x13
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#define CALEB_IXPRX_HI_CNTR 0x15
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#define CALEB_PHY0RX_HI_CNTR 0x16
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#define CALEB_PHY1RX_HI_CNTR 0x17
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#define CALEB_IXPRX_CNTR 0x18
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#define CALEB_PHY0RX_CNTR 0x19
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#define CALEB_PHY1RX_CNTR 0x1A
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#define CALEB_IXPTX_CNTR 0x1B
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#define CALEB_PHY0TX_CNTR 0x1C
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#define CALEB_PHY1TX_CNTR 0x1D
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#define CALEB_DEBUG0 0x1E
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#define CALEB_DEBUG1 0x1F
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static u8 caleb_reg_read(int reg)
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{
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u8 value;
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value = *((volatile u8 *)(ENP2611_CALEB_VIRT_BASE + reg));
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// printk(KERN_INFO "caleb_reg_read(%d) = %.2x\n", reg, value);
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return value;
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}
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static void caleb_reg_write(int reg, u8 value)
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{
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u8 dummy;
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// printk(KERN_INFO "caleb_reg_write(%d, %.2x)\n", reg, value);
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*((volatile u8 *)(ENP2611_CALEB_VIRT_BASE + reg)) = value;
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dummy = *((volatile u8 *)ENP2611_CALEB_VIRT_BASE);
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__asm__ __volatile__("mov %0, %0" : "+r" (dummy));
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}
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void caleb_reset(void)
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{
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/*
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* Perform a chip reset.
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*/
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caleb_reg_write(CALEB_RESET, 0x02);
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udelay(1);
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/*
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* Enable all interrupt sources. This is needed to get
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* meaningful results out of the status bits (register 6
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* and 7.)
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*/
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caleb_reg_write(CALEB_INTREN0, 0xff);
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caleb_reg_write(CALEB_INTREN1, 0x07);
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/*
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* Set RX and TX FIFO thresholds to 1.5kb.
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*/
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caleb_reg_write(CALEB_PHY0RX, 0x11);
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caleb_reg_write(CALEB_PHY1RX, 0x11);
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caleb_reg_write(CALEB_PHY0TX, 0x11);
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caleb_reg_write(CALEB_PHY1TX, 0x11);
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/*
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* Program SPI-3 burst size.
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*/
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caleb_reg_write(CALEB_BURST, 0); // 64-byte RBUF mpackets
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// caleb_reg_write(CALEB_BURST, 1); // 128-byte RBUF mpackets
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// caleb_reg_write(CALEB_BURST, 2); // 256-byte RBUF mpackets
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}
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void caleb_enable_rx(int port)
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{
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u8 temp;
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temp = caleb_reg_read(CALEB_PORTEN);
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temp |= 1 << port;
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caleb_reg_write(CALEB_PORTEN, temp);
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}
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void caleb_disable_rx(int port)
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{
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u8 temp;
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temp = caleb_reg_read(CALEB_PORTEN);
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temp &= ~(1 << port);
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caleb_reg_write(CALEB_PORTEN, temp);
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}
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void caleb_enable_tx(int port)
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{
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u8 temp;
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temp = caleb_reg_read(CALEB_PORTEN);
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temp |= 1 << (port + 4);
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caleb_reg_write(CALEB_PORTEN, temp);
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}
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void caleb_disable_tx(int port)
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{
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u8 temp;
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temp = caleb_reg_read(CALEB_PORTEN);
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temp &= ~(1 << (port + 4));
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caleb_reg_write(CALEB_PORTEN, temp);
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}
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