211 lines
5.6 KiB
ArmAsm
211 lines
5.6 KiB
ArmAsm
; WARNING : The refill handler has been modified, see below !!!
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/*
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* Copyright (C) 2003 Axis Communications AB
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*
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* Authors: Mikael Starvik (starvik@axis.com)
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*
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* Code for the fault low-level handling routines.
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*
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*/
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#include <asm/page.h>
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#include <asm/pgtable.h>
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; Save all register. Must save in same order as struct pt_regs.
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.macro SAVE_ALL
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subq 12, $sp
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move $erp, [$sp]
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subq 4, $sp
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move $srp, [$sp]
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subq 4, $sp
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move $ccs, [$sp]
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subq 4, $sp
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move $spc, [$sp]
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subq 4, $sp
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move $mof, [$sp]
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subq 4, $sp
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move $srs, [$sp]
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subq 4, $sp
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move.d $acr, [$sp]
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subq 14*4, $sp
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movem $r13, [$sp]
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subq 4, $sp
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move.d $r10, [$sp]
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.endm
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; Bus fault handler. Extracts relevant information and calls mm subsystem
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; to handle the fault.
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.macro MMU_BUS_FAULT_HANDLER handler, mmu, we, ex
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.globl \handler
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\handler:
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SAVE_ALL
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move \mmu, $srs ; Select MMU support register bank
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move.d $sp, $r11 ; regs
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moveq 1, $r12 ; protection fault
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moveq \we, $r13 ; write exception?
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orq \ex << 1, $r13 ; execute?
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move $s3, $r10 ; rw_mm_cause
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and.d ~8191, $r10 ; Get faulting page start address
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jsr do_page_fault
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nop
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ba ret_from_intr
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nop
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.endm
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; Refill handler. Three cases may occur:
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; 1. PMD and PTE exists in mm subsystem but not in TLB
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; 2. PMD exists but not PTE
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; 3. PMD doesn't exist
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; The code below handles case 1 and calls the mm subsystem for case 2 and 3.
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; Do not touch this code without very good reasons and extensive testing.
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; Note that the code is optimized to minimize stalls (makes the code harder
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; to read).
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;
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; WARNING !!!
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; Modified by Mikael Asker 060725: added a workaround for strange TLB
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; behavior. If the same PTE is present in more than one set, the TLB
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; doesn't recognize it and we get stuck in a loop of refill exceptions.
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; The workaround detects such loops and exits them by flushing
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; the TLB contents. The problem and workaround were verified
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; in VCS by Mikael Starvik.
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;
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; Each page is 8 KB. Each PMD holds 8192/4 PTEs (each PTE is 4 bytes) so each
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; PMD holds 16 MB of virtual memory.
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; Bits 0-12 : Offset within a page
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; Bits 13-23 : PTE offset within a PMD
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; Bits 24-31 : PMD offset within the PGD
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.macro MMU_REFILL_HANDLER handler, mmu
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.data
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1: .dword 0 ; refill_count
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; == 0 <=> last_refill_cause is invalid
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2: .dword 0 ; last_refill_cause
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.text
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.globl \handler
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\handler:
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subq 4, $sp
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; (The pipeline stalls for one cycle; $sp used as address in the next cycle.)
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move $srs, [$sp]
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subq 4, $sp
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move \mmu, $srs ; Select MMU support register bank
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move.d $acr, [$sp]
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subq 12, $sp
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move.d 1b, $acr ; Point to refill_count
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movem $r2, [$sp]
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test.d [$acr] ; refill_count == 0 ?
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beq 5f ; yes, last_refill_cause is invalid
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move.d $acr, $r1
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; last_refill_cause is valid, investigate cause
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addq 4, $r1 ; Point to last_refill_cause
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move $s3, $r0 ; Get rw_mm_cause
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move.d [$r1], $r2 ; Get last_refill_cause
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cmp.d $r0, $r2 ; rw_mm_cause == last_refill_cause ?
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beq 6f ; yes, increment count
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moveq 1, $r2
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; rw_mm_cause != last_refill_cause
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move.d $r2, [$acr] ; refill_count = 1
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move.d $r0, [$r1] ; last_refill_cause = rw_mm_cause
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3: ; Probably not in a loop, continue normal processing
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#ifdef CONFIG_SMP
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move $s7, $acr ; PGD
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#else
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move.d per_cpu__current_pgd, $acr ; PGD
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#endif
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; Look up PMD in PGD
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lsrq 24, $r0 ; Get PMD index into PGD (bit 24-31)
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move.d [$acr], $acr ; PGD for the current process
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addi $r0.d, $acr, $acr
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move $s3, $r0 ; rw_mm_cause
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move.d [$acr], $acr ; Get PMD
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beq 8f
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; Look up PTE in PMD
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lsrq PAGE_SHIFT, $r0
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and.w PAGE_MASK, $acr ; Remove PMD flags
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and.d 0x7ff, $r0 ; Get PTE index into PMD (bit 13-23)
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addi $r0.d, $acr, $acr
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move.d [$acr], $acr ; Get PTE
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beq 9f
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movem [$sp], $r2 ; Restore r0-r2 in delay slot
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addq 12, $sp
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; Store in TLB
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move $acr, $s5
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4: ; Return
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move.d [$sp+], $acr
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move [$sp], $srs
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addq 4, $sp
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rete
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rfe
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5: ; last_refill_cause is invalid
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moveq 1, $r2
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addq 4, $r1 ; Point to last_refill_cause
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move.d $r2, [$acr] ; refill_count = 1
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move $s3, $r0 ; Get rw_mm_cause
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ba 3b ; Continue normal processing
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move.d $r0,[$r1] ; last_refill_cause = rw_mm_cause
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6: ; rw_mm_cause == last_refill_cause
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move.d [$acr], $r2 ; Get refill_count
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cmpq 4, $r2 ; refill_count > 4 ?
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bhi 7f ; yes
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addq 1, $r2 ; refill_count++
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ba 3b ; Continue normal processing
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move.d $r2, [$acr]
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7: ; refill_count > 4, error
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move.d $acr, $r0 ; Save pointer to refill_count
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clear.d [$r0] ; refill_count = 0
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;; rewind the short stack
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movem [$sp], $r2 ; Restore r0-r2
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addq 12, $sp
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move.d [$sp+], $acr
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move [$sp], $srs
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addq 4, $sp
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;; Keep it simple (slow), save all the regs.
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SAVE_ALL
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jsr __flush_tlb_all
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nop
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ba ret_from_intr ; Return
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nop
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8: ; PMD missing, let the mm subsystem fix it up.
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movem [$sp], $r2 ; Restore r0-r2
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9: ; PTE missing, let the mm subsystem fix it up.
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addq 12, $sp
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move.d [$sp+], $acr
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move [$sp], $srs
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addq 4, $sp
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SAVE_ALL
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move \mmu, $srs
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move.d $sp, $r11 ; regs
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clear.d $r12 ; Not a protection fault
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move.w PAGE_MASK, $acr
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move $s3, $r10 ; rw_mm_cause
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btstq 9, $r10 ; Check if write access
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smi $r13
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and.w PAGE_MASK, $r10 ; Get VPN (virtual address)
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jsr do_page_fault
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and.w $acr, $r10
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; Return
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ba ret_from_intr
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nop
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.endm
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; This is the MMU bus fault handlers.
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MMU_REFILL_HANDLER i_mmu_refill, 1
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MMU_BUS_FAULT_HANDLER i_mmu_invalid, 1, 0, 0
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MMU_BUS_FAULT_HANDLER i_mmu_access, 1, 0, 0
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MMU_BUS_FAULT_HANDLER i_mmu_execute, 1, 0, 1
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MMU_REFILL_HANDLER d_mmu_refill, 2
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MMU_BUS_FAULT_HANDLER d_mmu_invalid, 2, 0, 0
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MMU_BUS_FAULT_HANDLER d_mmu_access, 2, 0, 0
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MMU_BUS_FAULT_HANDLER d_mmu_write, 2, 1, 0
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