224 lines
7.1 KiB
C
224 lines
7.1 KiB
C
/*
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* cx18 ADEC firmware functions
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*
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* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
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* Copyright (C) 2008 Andy Walls <awalls@radix.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#include "cx18-driver.h"
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#include "cx18-io.h"
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#include <linux/firmware.h>
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#define CX18_AUDIO_ENABLE 0xc72014
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#define CX18_AI1_MUX_MASK 0x30
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#define CX18_AI1_MUX_I2S1 0x00
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#define CX18_AI1_MUX_I2S2 0x10
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#define CX18_AI1_MUX_843_I2S 0x20
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#define CX18_AI1_MUX_INVALID 0x30
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#define FWFILE "v4l-cx23418-dig.fw"
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static int cx18_av_verifyfw(struct cx18 *cx, const struct firmware *fw)
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{
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struct v4l2_subdev *sd = &cx->av_state.sd;
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int ret = 0;
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const u8 *data;
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u32 size;
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int addr;
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u32 expected, dl_control;
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/* Ensure we put the 8051 in reset and enable firmware upload mode */
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dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
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do {
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dl_control &= 0x00ffffff;
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dl_control |= 0x0f000000;
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cx18_av_write4_noretry(cx, CXADEC_DL_CTL, dl_control);
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dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
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} while ((dl_control & 0xff000000) != 0x0f000000);
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/* Read and auto increment until at address 0x0000 */
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while (dl_control & 0x3fff)
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dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
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data = fw->data;
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size = fw->size;
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for (addr = 0; addr < size; addr++) {
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dl_control &= 0xffff3fff; /* ignore top 2 bits of address */
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expected = 0x0f000000 | ((u32)data[addr] << 16) | addr;
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if (expected != dl_control) {
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CX18_ERR_DEV(sd, "verification of %s firmware load "
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"failed: expected %#010x got %#010x\n",
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FWFILE, expected, dl_control);
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ret = -EIO;
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break;
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}
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dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
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}
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if (ret == 0)
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CX18_INFO_DEV(sd, "verified load of %s firmware (%d bytes)\n",
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FWFILE, size);
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return ret;
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}
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int cx18_av_loadfw(struct cx18 *cx)
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{
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struct v4l2_subdev *sd = &cx->av_state.sd;
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const struct firmware *fw = NULL;
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u32 size;
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u32 u, v;
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const u8 *ptr;
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int i;
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int retries1 = 0;
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if (request_firmware(&fw, FWFILE, &cx->pci_dev->dev) != 0) {
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CX18_ERR_DEV(sd, "unable to open firmware %s\n", FWFILE);
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return -EINVAL;
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}
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/* The firmware load often has byte errors, so allow for several
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retries, both at byte level and at the firmware load level. */
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while (retries1 < 5) {
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cx18_av_write4_expect(cx, CXADEC_CHIP_CTRL, 0x00010000,
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0x00008430, 0xffffffff); /* cx25843 */
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cx18_av_write_expect(cx, CXADEC_STD_DET_CTL, 0xf6, 0xf6, 0xff);
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/* Reset the Mako core, Register is alias of CXADEC_CHIP_CTRL */
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cx18_av_write4_expect(cx, 0x8100, 0x00010000,
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0x00008430, 0xffffffff); /* cx25843 */
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/* Put the 8051 in reset and enable firmware upload */
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cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000);
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ptr = fw->data;
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size = fw->size;
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for (i = 0; i < size; i++) {
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u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16);
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u32 value = 0;
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int retries2;
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int unrec_err = 0;
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for (retries2 = 0; retries2 < CX18_MAX_MMIO_WR_RETRIES;
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retries2++) {
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cx18_av_write4_noretry(cx, CXADEC_DL_CTL,
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dl_control);
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udelay(10);
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value = cx18_av_read4(cx, CXADEC_DL_CTL);
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if (value == dl_control)
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break;
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/* Check if we can correct the byte by changing
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the address. We can only write the lower
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address byte of the address. */
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if ((value & 0x3F00) != (dl_control & 0x3F00)) {
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unrec_err = 1;
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break;
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}
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}
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if (unrec_err || retries2 >= CX18_MAX_MMIO_WR_RETRIES)
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break;
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}
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if (i == size)
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break;
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retries1++;
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}
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if (retries1 >= 5) {
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CX18_ERR_DEV(sd, "unable to load firmware %s\n", FWFILE);
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release_firmware(fw);
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return -EIO;
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}
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cx18_av_write4_expect(cx, CXADEC_DL_CTL,
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0x03000000 | fw->size, 0x03000000, 0x13000000);
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CX18_INFO_DEV(sd, "loaded %s firmware (%d bytes)\n", FWFILE, size);
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if (cx18_av_verifyfw(cx, fw) == 0)
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cx18_av_write4_expect(cx, CXADEC_DL_CTL,
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0x13000000 | fw->size, 0x13000000, 0x13000000);
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/* Output to the 416 */
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cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x78000);
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/* Audio input control 1 set to Sony mode */
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/* Audio output input 2 is 0 for slave operation input */
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/* 0xC4000914[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
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/* 0xC4000914[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
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after WS transition for first bit of audio word. */
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cx18_av_write4(cx, CXADEC_I2S_IN_CTL, 0x000000A0);
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/* Audio output control 1 is set to Sony mode */
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/* Audio output control 2 is set to 1 for master mode */
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/* 0xC4000918[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
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/* 0xC4000918[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
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after WS transition for first bit of audio word. */
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/* 0xC4000918[8]: 0 = slave operation, 1 = master (SCK_OUT and WS_OUT
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are generated) */
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cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0);
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/* set alt I2s master clock to /0x16 and enable alt divider i2s
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passthrough */
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cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687);
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cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6,
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0x3F00FFFF);
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/* CxDevWrReg(CXADEC_STD_DET_CTL, 0x000000FF); */
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/* Set bit 0 in register 0x9CC to signify that this is MiniMe. */
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/* Register 0x09CC is defined by the Merlin firmware, and doesn't
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have a name in the spec. */
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cx18_av_write4(cx, 0x09CC, 1);
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v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
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/* If bit 11 is 1, clear bit 10 */
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if (v & 0x800)
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cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE,
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0, 0x400);
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/* Toggle the AI1 MUX */
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v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
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u = v & CX18_AI1_MUX_MASK;
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v &= ~CX18_AI1_MUX_MASK;
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if (u == CX18_AI1_MUX_843_I2S || u == CX18_AI1_MUX_INVALID) {
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/* Switch to I2S1 */
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v |= CX18_AI1_MUX_I2S1;
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cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
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v, CX18_AI1_MUX_MASK);
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/* Switch back to the A/V decoder core I2S output */
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v = (v & ~CX18_AI1_MUX_MASK) | CX18_AI1_MUX_843_I2S;
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} else {
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/* Switch to the A/V decoder core I2S output */
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v |= CX18_AI1_MUX_843_I2S;
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cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
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v, CX18_AI1_MUX_MASK);
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/* Switch back to I2S1 or I2S2 */
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v = (v & ~CX18_AI1_MUX_MASK) | u;
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}
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cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
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v, CX18_AI1_MUX_MASK);
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/* Enable WW auto audio standard detection */
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v = cx18_av_read4(cx, CXADEC_STD_DET_CTL);
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v |= 0xFF; /* Auto by default */
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v |= 0x400; /* Stereo by default */
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v |= 0x14000000;
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cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, v, v, 0x3F00FFFF);
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release_firmware(fw);
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return 0;
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}
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