437 lines
13 KiB
C
437 lines
13 KiB
C
/*
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* pc300.h Cyclades-PC300(tm) Kernel API Definitions.
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*
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* Author: Ivan Passos <ivan@cyclades.com>
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*
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* Copyright: (c) 1999-2002 Cyclades Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* $Log: pc300.h,v $
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* Revision 3.12 2002/03/07 14:17:09 henrique
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* License data fixed
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*
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* Revision 3.11 2002/01/28 21:09:39 daniela
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* Included ';' after pc300hw.bus.
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*
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* Revision 3.10 2002/01/17 17:58:52 ivan
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* Support for PC300-TE/M (PMC).
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*
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* Revision 3.9 2001/09/28 13:30:53 daniela
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* Renamed dma_start routine to rx_dma_start.
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*
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* Revision 3.8 2001/09/24 13:03:45 daniela
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* Fixed BOF interrupt treatment. Created dma_start routine.
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*
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* Revision 3.7 2001/08/10 17:19:58 daniela
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* Fixed IOCTLs defines.
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*
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* Revision 3.6 2001/07/18 19:24:42 daniela
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* Included kernel version.
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*
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* Revision 3.5 2001/07/05 18:38:08 daniela
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* DMA transmission bug fix.
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*
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* Revision 3.4 2001/06/26 17:10:40 daniela
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* New configuration parameters (line code, CRC calculation and clock).
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*
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* Revision 3.3 2001/06/22 13:13:02 regina
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* MLPPP implementation
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*
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* Revision 3.2 2001/06/18 17:56:09 daniela
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* Increased DEF_MTU and TX_QUEUE_LEN.
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*
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* Revision 3.1 2001/06/15 12:41:10 regina
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* upping major version number
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*
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* Revision 1.1.1.1 2001/06/13 20:25:06 daniela
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* PC300 initial CVS version (3.4.0-pre1)
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*
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* Revision 2.3 2001/03/05 daniela
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* Created struct pc300conf, to provide the hardware information to pc300util.
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* Inclusion of 'alloc_ramsize' field on structure 'pc300hw'.
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*
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* Revision 2.2 2000/12/22 daniela
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* Structures and defines to support pc300util: statistics, status,
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* loopback tests, trace.
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*
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* Revision 2.1 2000/09/28 ivan
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* Inclusion of 'iophys' and 'iosize' fields on structure 'pc300hw', to
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* allow release of I/O region at module unload.
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* Changed location of include files.
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*
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* Revision 2.0 2000/03/27 ivan
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* Added support for the PC300/TE cards.
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*
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* Revision 1.1 2000/01/31 ivan
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* Replaced 'pc300[drv|sca].h' former PC300 driver include files.
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*
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* Revision 1.0 1999/12/16 ivan
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* First official release.
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* Inclusion of 'nchan' field on structure 'pc300hw', to allow variable
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* number of ports per card.
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* Inclusion of 'if_ptr' field on structure 'pc300dev'.
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*
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* Revision 0.6 1999/11/17 ivan
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* Changed X.25-specific function names to comply with adopted convention.
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*
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* Revision 0.5 1999/11/16 Daniela Squassoni
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* X.25 support.
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*
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* Revision 0.4 1999/11/15 ivan
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* Inclusion of 'clock' field on structure 'pc300hw'.
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*
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* Revision 0.3 1999/11/10 ivan
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* IOCTL name changing.
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* Inclusion of driver function prototypes.
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*
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* Revision 0.2 1999/11/03 ivan
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* Inclusion of 'tx_skb' and union 'ifu' on structure 'pc300dev'.
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*
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* Revision 0.1 1999/01/15 ivan
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* Initial version.
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*
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*/
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#ifndef _PC300_H
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#define _PC300_H
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#include <linux/hdlc.h>
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#include "hd64572.h"
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#include "pc300-falc-lh.h"
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#define PC300_PROTO_MLPPP 1
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#define PC300_MAXCHAN 2 /* Number of channels per card */
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#define PC300_RAMSIZE 0x40000 /* RAM window size (256Kb) */
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#define PC300_FALCSIZE 0x400 /* FALC window size (1Kb) */
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#define PC300_OSC_CLOCK 24576000
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#define PC300_PCI_CLOCK 33000000
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#define BD_DEF_LEN 0x0800 /* DMA buffer length (2KB) */
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#define DMA_TX_MEMSZ 0x8000 /* Total DMA Tx memory size (32KB/ch) */
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#define DMA_RX_MEMSZ 0x10000 /* Total DMA Rx memory size (64KB/ch) */
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#define N_DMA_TX_BUF (DMA_TX_MEMSZ / BD_DEF_LEN) /* DMA Tx buffers */
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#define N_DMA_RX_BUF (DMA_RX_MEMSZ / BD_DEF_LEN) /* DMA Rx buffers */
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/* DMA Buffer Offsets */
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#define DMA_TX_BASE ((N_DMA_TX_BUF + N_DMA_RX_BUF) * \
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PC300_MAXCHAN * sizeof(pcsca_bd_t))
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#define DMA_RX_BASE (DMA_TX_BASE + PC300_MAXCHAN*DMA_TX_MEMSZ)
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/* DMA Descriptor Offsets */
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#define DMA_TX_BD_BASE 0x0000
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#define DMA_RX_BD_BASE (DMA_TX_BD_BASE + ((PC300_MAXCHAN*DMA_TX_MEMSZ / \
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BD_DEF_LEN) * sizeof(pcsca_bd_t)))
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/* DMA Descriptor Macros */
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#define TX_BD_ADDR(chan, n) (DMA_TX_BD_BASE + \
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((N_DMA_TX_BUF*chan) + n) * sizeof(pcsca_bd_t))
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#define RX_BD_ADDR(chan, n) (DMA_RX_BD_BASE + \
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((N_DMA_RX_BUF*chan) + n) * sizeof(pcsca_bd_t))
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/* Macro to access the FALC registers (TE only) */
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#define F_REG(reg, chan) (0x200*(chan) + ((reg)<<2))
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/***************************************
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* Memory access functions/macros *
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* (required to support Alpha systems) *
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***************************************/
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#define cpc_writeb(port,val) {writeb((u8)(val),(port)); mb();}
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#define cpc_writew(port,val) {writew((ushort)(val),(port)); mb();}
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#define cpc_writel(port,val) {writel((u32)(val),(port)); mb();}
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#define cpc_readb(port) readb(port)
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#define cpc_readw(port) readw(port)
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#define cpc_readl(port) readl(port)
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/****** Data Structures *****************************************************/
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/*
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* RUNTIME_9050 - PLX PCI9050-1 local configuration and shared runtime
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* registers. This structure can be used to access the 9050 registers
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* (memory mapped).
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*/
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struct RUNTIME_9050 {
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u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
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u32 loc_rom_range; /* 10h : Local ROM Range */
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u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
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u32 loc_rom_base; /* 24h : Local ROM Base */
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u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
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u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
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u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
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u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
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u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
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};
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#define PLX_9050_LINT1_ENABLE 0x01
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#define PLX_9050_LINT1_POL 0x02
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#define PLX_9050_LINT1_STATUS 0x04
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#define PLX_9050_LINT2_ENABLE 0x08
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#define PLX_9050_LINT2_POL 0x10
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#define PLX_9050_LINT2_STATUS 0x20
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#define PLX_9050_INTR_ENABLE 0x40
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#define PLX_9050_SW_INTR 0x80
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/* Masks to access the init_ctrl PLX register */
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#define PC300_CLKSEL_MASK (0x00000004UL)
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#define PC300_CHMEDIA_MASK(chan) (0x00000020UL<<(chan*3))
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#define PC300_CTYPE_MASK (0x00000800UL)
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/* CPLD Registers (base addr = falcbase, TE only) */
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/* CPLD v. 0 */
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#define CPLD_REG1 0x140 /* Chip resets, DCD/CTS status */
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#define CPLD_REG2 0x144 /* Clock enable , LED control */
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/* CPLD v. 2 or higher */
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#define CPLD_V2_REG1 0x100 /* Chip resets, DCD/CTS status */
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#define CPLD_V2_REG2 0x104 /* Clock enable , LED control */
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#define CPLD_ID_REG 0x108 /* CPLD version */
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/* CPLD Register bit description: for the FALC bits, they should always be
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set based on the channel (use (bit<<(2*ch)) to access the correct bit for
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that channel) */
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#define CPLD_REG1_FALC_RESET 0x01
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#define CPLD_REG1_SCA_RESET 0x02
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#define CPLD_REG1_GLOBAL_CLK 0x08
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#define CPLD_REG1_FALC_DCD 0x10
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#define CPLD_REG1_FALC_CTS 0x20
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#define CPLD_REG2_FALC_TX_CLK 0x01
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#define CPLD_REG2_FALC_RX_CLK 0x02
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#define CPLD_REG2_FALC_LED1 0x10
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#define CPLD_REG2_FALC_LED2 0x20
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/* Structure with FALC-related fields (TE only) */
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#define PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */
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typedef struct falc {
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u8 sync; /* If true FALC is synchronized */
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u8 active; /* if TRUE then already active */
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u8 loop_active; /* if TRUE a line loopback UP was received */
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u8 loop_gen; /* if TRUE a line loopback UP was issued */
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u8 num_channels;
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u8 offset; /* 1 for T1, 0 for E1 */
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u8 full_bandwidth;
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u8 xmb_cause;
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u8 multiframe_mode;
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/* Statistics */
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u16 pden; /* Pulse Density violation count */
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u16 los; /* Loss of Signal count */
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u16 losr; /* Loss of Signal recovery count */
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u16 lfa; /* Loss of frame alignment count */
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u16 farec; /* Frame Alignment Recovery count */
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u16 lmfa; /* Loss of multiframe alignment count */
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u16 ais; /* Remote Alarm indication Signal count */
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u16 sec; /* One-second timer */
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u16 es; /* Errored second */
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u16 rai; /* remote alarm received */
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u16 bec;
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u16 fec;
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u16 cvc;
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u16 cec;
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u16 ebc;
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/* Status */
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u8 red_alarm;
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u8 blue_alarm;
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u8 loss_fa;
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u8 yellow_alarm;
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u8 loss_mfa;
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u8 prbs;
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} falc_t;
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typedef struct falc_status {
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u8 sync; /* If true FALC is synchronized */
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u8 red_alarm;
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u8 blue_alarm;
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u8 loss_fa;
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u8 yellow_alarm;
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u8 loss_mfa;
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u8 prbs;
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} falc_status_t;
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typedef struct rsv_x21_status {
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u8 dcd;
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u8 dsr;
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u8 cts;
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u8 rts;
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u8 dtr;
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} rsv_x21_status_t;
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typedef struct pc300stats {
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int hw_type;
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u32 line_on;
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u32 line_off;
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struct net_device_stats gen_stats;
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falc_t te_stats;
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} pc300stats_t;
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typedef struct pc300status {
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int hw_type;
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rsv_x21_status_t gen_status;
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falc_status_t te_status;
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} pc300status_t;
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typedef struct pc300loopback {
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char loop_type;
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char loop_on;
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} pc300loopback_t;
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typedef struct pc300patterntst {
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char patrntst_on; /* 0 - off; 1 - on; 2 - read num_errors */
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u16 num_errors;
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} pc300patterntst_t;
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typedef struct pc300dev {
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struct pc300ch *chan;
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u8 trace_on;
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u32 line_on; /* DCD(X.21, RSV) / sync(TE) change counters */
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u32 line_off;
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char name[16];
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struct net_device *dev;
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#ifdef CONFIG_PC300_MLPPP
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void *cpc_tty; /* information to PC300 TTY driver */
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#endif
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}pc300dev_t;
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typedef struct pc300hw {
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int type; /* RSV, X21, etc. */
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int bus; /* Bus (PCI, PMC, etc.) */
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int nchan; /* number of channels */
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int irq; /* interrupt request level */
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u32 clock; /* Board clock */
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u8 cpld_id; /* CPLD ID (TE only) */
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u16 cpld_reg1; /* CPLD reg 1 (TE only) */
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u16 cpld_reg2; /* CPLD reg 2 (TE only) */
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u16 gpioc_reg; /* PLX GPIOC reg */
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u16 intctl_reg; /* PLX Int Ctrl/Status reg */
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u32 iophys; /* PLX registers I/O base */
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u32 iosize; /* PLX registers I/O size */
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u32 plxphys; /* PLX registers MMIO base (physical) */
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void __iomem * plxbase; /* PLX registers MMIO base (virtual) */
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u32 plxsize; /* PLX registers MMIO size */
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u32 scaphys; /* SCA registers MMIO base (physical) */
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void __iomem * scabase; /* SCA registers MMIO base (virtual) */
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u32 scasize; /* SCA registers MMIO size */
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u32 ramphys; /* On-board RAM MMIO base (physical) */
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void __iomem * rambase; /* On-board RAM MMIO base (virtual) */
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u32 alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */
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u32 ramsize; /* On-board RAM MMIO size */
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u32 falcphys; /* FALC registers MMIO base (physical) */
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void __iomem * falcbase;/* FALC registers MMIO base (virtual) */
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u32 falcsize; /* FALC registers MMIO size */
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} pc300hw_t;
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typedef struct pc300chconf {
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sync_serial_settings phys_settings; /* Clock type/rate (in bps),
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loopback mode */
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raw_hdlc_proto proto_settings; /* Encoding, parity (CRC) */
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u32 media; /* HW media (RS232, V.35, etc.) */
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u32 proto; /* Protocol (PPP, X.25, etc.) */
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/* TE-specific parameters */
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u8 lcode; /* Line Code (AMI, B8ZS, etc.) */
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u8 fr_mode; /* Frame Mode (ESF, D4, etc.) */
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u8 lbo; /* Line Build Out */
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u8 rx_sens; /* Rx Sensitivity (long- or short-haul) */
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u32 tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */
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} pc300chconf_t;
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typedef struct pc300ch {
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struct pc300 *card;
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int channel;
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pc300dev_t d;
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pc300chconf_t conf;
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u8 tx_first_bd; /* First TX DMA block descr. w/ data */
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u8 tx_next_bd; /* Next free TX DMA block descriptor */
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u8 rx_first_bd; /* First free RX DMA block descriptor */
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u8 rx_last_bd; /* Last free RX DMA block descriptor */
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u8 nfree_tx_bd; /* Number of free TX DMA block descriptors */
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falc_t falc; /* FALC structure (TE only) */
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} pc300ch_t;
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typedef struct pc300 {
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pc300hw_t hw; /* hardware config. */
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pc300ch_t chan[PC300_MAXCHAN];
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spinlock_t card_lock;
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} pc300_t;
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typedef struct pc300conf {
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pc300hw_t hw;
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pc300chconf_t conf;
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} pc300conf_t;
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/* DEV ioctl() commands */
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#define N_SPPP_IOCTLS 2
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enum pc300_ioctl_cmds {
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SIOCCPCRESERVED = (SIOCDEVPRIVATE + N_SPPP_IOCTLS),
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SIOCGPC300CONF,
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SIOCSPC300CONF,
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SIOCGPC300STATUS,
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SIOCGPC300FALCSTATUS,
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SIOCGPC300UTILSTATS,
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SIOCGPC300UTILSTATUS,
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SIOCSPC300TRACE,
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SIOCSPC300LOOPBACK,
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SIOCSPC300PATTERNTEST,
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};
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/* Loopback types - PC300/TE boards */
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enum pc300_loopback_cmds {
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PC300LOCLOOP = 1,
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PC300REMLOOP,
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PC300PAYLOADLOOP,
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PC300GENLOOPUP,
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PC300GENLOOPDOWN,
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};
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/* Control Constant Definitions */
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#define PC300_RSV 0x01
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#define PC300_X21 0x02
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#define PC300_TE 0x03
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#define PC300_PCI 0x00
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#define PC300_PMC 0x01
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#define PC300_LC_AMI 0x01
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#define PC300_LC_B8ZS 0x02
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#define PC300_LC_NRZ 0x03
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#define PC300_LC_HDB3 0x04
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/* Framing (T1) */
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#define PC300_FR_ESF 0x01
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#define PC300_FR_D4 0x02
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#define PC300_FR_ESF_JAPAN 0x03
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/* Framing (E1) */
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#define PC300_FR_MF_CRC4 0x04
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#define PC300_FR_MF_NON_CRC4 0x05
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#define PC300_FR_UNFRAMED 0x06
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#define PC300_LBO_0_DB 0x00
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#define PC300_LBO_7_5_DB 0x01
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#define PC300_LBO_15_DB 0x02
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#define PC300_LBO_22_5_DB 0x03
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#define PC300_RX_SENS_SH 0x01
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#define PC300_RX_SENS_LH 0x02
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#define PC300_TX_TIMEOUT (2*HZ)
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#define PC300_TX_QUEUE_LEN 100
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#define PC300_DEF_MTU 1600
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/* Function Prototypes */
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int cpc_open(struct net_device *dev);
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#endif /* _PC300_H */
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