588 lines
14 KiB
C
588 lines
14 KiB
C
/*****************************************************************************
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*
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* File name : clock-fli7510.c
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* Description : Low Level API - HW specific implementation
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* Author: Francesco Virlinzi <francesco.virlinzi@st.com>
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*
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* COPYRIGHT (C) 2011 STMicroelectronics - All Rights Reserved
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* May be copied or modified under the terms of the GNU General Public
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* License V2 __ONLY__. See linux/COPYING for more information.
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*
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*****************************************************************************/
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/* ----- Modification history (most recent first)----
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* Original code from stx7111 platform
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*/
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/* Includes ----------------------------------------------------------------- */
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#include <linux/stm/fli7510.h>
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#include <linux/stm/clk.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include "clock-fli7510.h"
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#include "clock-regs-fli7510.h"
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#include "clock-oslayer.h"
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#include "clock-common.h"
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#include "clock-utils.h"
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static int clkgena_set_parent(clk_t *clk_p, clk_t *src_p);
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static int clkgena_set_rate(clk_t *clk_p, unsigned long freq);
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static int clkgena_set_div(clk_t *clk_p, unsigned long *div_p);
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static int clkgena_recalc(clk_t *clk_p);
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static int clkgena_enable(clk_t *clk_p);
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static int clkgena_disable(clk_t *clk_p);
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static int clkgena_init(clk_t *clk_p);
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#define SYSA_CLKIN 30 /* FE osc */
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_CLK_OPS(clkgena,
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"Clockgen A",
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clkgena_init,
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clkgena_set_parent,
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clkgena_set_rate,
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clkgena_recalc,
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clkgena_enable,
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clkgena_disable,
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NULL,
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NULL,
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NULL
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);
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/* Physical clocks description */
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clk_t clk_clocks[] = {
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/* Top level clocks */
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_CLK_F(CLK_SYSA, SYSA_CLKIN * 1000000),
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/* Clockgen A */
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_CLK_P(CLKA_REF, &clkgena, 0, 0, &clk_clocks[CLK_SYSA]),
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_CLK_P(CLKA_PLL0HS, &clkgena, 900000000, 0, &clk_clocks[CLKA_REF]),
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_CLK_P(CLKA_PLL0LS, &clkgena, 450000000, 0, &clk_clocks[CLKA_PLL0HS]),
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_CLK_P(CLKA_PLL1, &clkgena, 800000000, 0, &clk_clocks[CLKA_REF]),
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_CLK(CLKA_ST231_AUD_1, &clkgena, 0, 0),
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_CLK(CLKA_VCPU, &clkgena, 0, 0),
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_CLK(CLKA_TANGO, &clkgena, 0, 0),
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_CLK(CLKA_ST231_AUD_2, &clkgena, 0, 0),
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_CLK(CLKA_ST40_HOST, &clkgena, 0, 0),
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_CLK(CLKA_ST40_RT, &clkgena, 0, 0),
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_CLK(CLKA_ST231_DRA2, &clkgena, 0, 0),
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_CLK(CLKA_FDMA, &clkgena, 0, 0),
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_CLK(CLKA_BIT, &clkgena, 0, 0),
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_CLK(CLKA_AATV, &clkgena, 0, 0),
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_CLK(CLKA_EMI, &clkgena, 0, 0),
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_CLK(CLKA_PP, &clkgena, 0, 0),
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_CLK(CLKA_ETH_PHY, &clkgena, 0, 0),
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_CLK(CLKA_PCI, &clkgena, 0, 0),
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_CLK(CLKA_IC_100, &clkgena, 0, 0),
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_CLK(CLKA_IC_150, &clkgena, 0, 0),
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_CLK(CLKA_IC_266, &clkgena, 0, 0),
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_CLK(CLKA_IC_200, &clkgena, 0, 0),
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};
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/******************************************************************************
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CLOCKGEN A (CPU+interco+comms) clocks group
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******************************************************************************/
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/* ========================================================================
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Name: clkgena_get_index
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Description: Returns index of given clockgenA clock and source reg infos
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Returns: idx==-1 if error, else >=0
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======================================================================== */
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static int clkgena_get_index(int clkid, unsigned long *srcreg, int *shift)
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{
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int idx;
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/* Warning: This function assumes clock IDs are perfectly
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following real implementation order. Each "hole" has therefore
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to be filled with "CLKx_NOT_USED" */
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if (clkid < CLKA_ST231_AUD_1 || clkid > CLK_NOT_USED_2)
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return -1;
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idx = (clkid - CLKA_ST231_AUD_1) % 16;
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*srcreg = CKGA_CLKOPSRC_SWITCH_CFG + (0x10 * (idx / 16));
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*shift = 2 * (idx % 16);
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return idx;
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}
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/* ========================================================================
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Name: clkgena_set_parent
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Description: Set clock source for clockgenA when possible
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Returns: 0=NO error
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======================================================================== */
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static int clkgena_set_parent(clk_t *clk_p, clk_t *src_p)
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{
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unsigned long clk_src, val;
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int idx, shift;
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unsigned long srcreg;
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if (!clk_p || !src_p)
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return CLK_ERR_BAD_PARAMETER;
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if (clk_p->id < CLKA_ST231_AUD_1 || clk_p->id > CLK_NOT_USED_2)
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return CLK_ERR_BAD_PARAMETER;
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switch (src_p->id) {
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case CLKA_REF:
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clk_src = 0;
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break;
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case CLKA_PLL0LS:
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case CLKA_PLL0HS:
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clk_src = 1;
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break;
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case CLKA_PLL1:
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clk_src = 2;
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break;
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default:
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return CLK_ERR_BAD_PARAMETER;
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}
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idx = clkgena_get_index(clk_p->id, &srcreg, &shift);
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if (idx == -1)
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return CLK_ERR_BAD_PARAMETER;
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val = CLK_READ(CKGA_BASE_ADDRESS + srcreg) & ~(0x3 << shift);
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val = val | (clk_src << shift);
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CLK_WRITE(CKGA_BASE_ADDRESS + srcreg, val);
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clk_p->parent = &clk_clocks[src_p->id];
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return clkgena_recalc(clk_p);
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}
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/* ========================================================================
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Name: clkgena_identify_parent
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Description: Identify parent clock for clockgen A clocks.
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Returns: 'clk_err_t' error code
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======================================================================== */
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static int clkgena_identify_parent(clk_t *clk_p)
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{
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int idx;
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unsigned long src_sel;
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unsigned long srcreg;
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int shift;
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if (!clk_p)
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return CLK_ERR_BAD_PARAMETER;
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if (clk_p->id == CLKA_REF) {
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/*src_sel = SYSCONF_READ(SYS_STA, 1, 0, 1);*/
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clk_p->parent = &clk_clocks[CLK_SYSA + src_sel];
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return 0;
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}
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if (clk_p->id < CLKA_ST231_AUD_1)
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/* Statically initialized with _CLK_P() macro */
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return 0;
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/* Which divider to setup ? */
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idx = clkgena_get_index(clk_p->id, &srcreg, &shift);
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if (idx == -1)
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return CLK_ERR_BAD_PARAMETER;
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/* Identifying source */
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src_sel = (CLK_READ(CKGA_BASE_ADDRESS + srcreg) >> shift) & 0x3;
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switch (src_sel) {
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case 0:
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clk_p->parent = &clk_clocks[CLKA_REF];
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break;
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case 1:
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if (idx <= 3)
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clk_p->parent = &clk_clocks[CLKA_PLL0HS];
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else
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clk_p->parent = &clk_clocks[CLKA_PLL0LS];
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break;
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case 2:
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clk_p->parent = &clk_clocks[CLKA_PLL1];
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break;
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case 3:
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clk_p->parent = NULL;
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clk_p->rate = 0;
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break;
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}
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return 0;
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}
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/* ========================================================================
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Name: clkgena_xable_pll
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Description: Enable/disable PLL
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Returns: 'clk_err_t' error code
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======================================================================== */
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static int clkgena_xable_pll(clk_t *clk_p, int enable)
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{
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unsigned long val;
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int bit, err = 0;
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if (!clk_p)
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return CLK_ERR_BAD_PARAMETER;
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if (clk_p->id != CLKA_PLL0HS && clk_p->id != CLKA_PLL1)
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return CLK_ERR_BAD_PARAMETER;
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bit = (clk_p->id == CLKA_PLL0HS ? 0 : 1);
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val = CLK_READ(CKGA_BASE_ADDRESS + CKGA_POWER_CFG);
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if (enable)
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val &= ~(1 << bit);
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else
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val |= (1 << bit);
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CLK_WRITE(CKGA_BASE_ADDRESS + CKGA_POWER_CFG, val);
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if (enable)
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err = clkgena_recalc(clk_p);
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else
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clk_p->rate = 0;
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return err;
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}
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/* ========================================================================
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Name: clkgena_enable
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Description: Enable clock
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Returns: 'clk_err_t' error code
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======================================================================== */
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static int clkgena_enable(clk_t *clk_p)
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{
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int err;
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if (!clk_p)
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return CLK_ERR_BAD_PARAMETER;
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if (!clk_p->parent)
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/* Unsupported. Init must be called first. */
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return CLK_ERR_BAD_PARAMETER;
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/* PLL power up */
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if (clk_p->id >= CLKA_PLL0HS && clk_p->id <= CLKA_PLL1)
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return clkgena_xable_pll(clk_p, 1);
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err = clkgena_set_parent(clk_p, clk_p->parent);
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/* clkgena_set_parent() is performing also a recalc() */
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return err;
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}
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/* ========================================================================
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Name: clkgena_disable
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Description: Disable clock
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Returns: 'clk_err_t' error code
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======================================================================== */
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static int clkgena_disable(clk_t *clk_p)
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{
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unsigned long val;
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int idx, shift;
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unsigned long srcreg;
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if (!clk_p)
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return CLK_ERR_BAD_PARAMETER;
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if (clk_p->id < CLKA_PLL0HS || clk_p->id > CLK_NOT_USED_2)
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return CLK_ERR_BAD_PARAMETER;
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/* Can this clock be disabled ? */
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if (clk_p->flags & CLK_ALWAYS_ENABLED)
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return 0;
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/* PLL power down */
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if (clk_p->id >= CLKA_PLL0HS && clk_p->id <= CLKA_PLL1)
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return clkgena_xable_pll(clk_p, 0);
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idx = clkgena_get_index(clk_p->id, &srcreg, &shift);
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if (idx == -1)
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return CLK_ERR_BAD_PARAMETER;
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/* Disabling clock */
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val = CLK_READ(CKGA_BASE_ADDRESS + srcreg) & ~(0x3 << shift);
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val = val | (3 << shift); /* 3 = STOP clock */
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CLK_WRITE(CKGA_BASE_ADDRESS + srcreg, val);
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clk_p->rate = 0;
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return 0;
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}
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static int clkgena_set_div(clk_t *clk_p, unsigned long *div_p)
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{
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int idx;
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unsigned long div_cfg = 0;
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unsigned long srcreg, offset;
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int shift;
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if (!clk_p || !clk_p->parent)
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return CLK_ERR_BAD_PARAMETER;
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/* Computing divider config */
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div_cfg = (*div_p - 1) & 0x1F;
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/* Which divider to setup ? */
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idx = clkgena_get_index(clk_p->id, &srcreg, &shift);
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if (idx == -1)
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return CLK_ERR_BAD_PARAMETER;
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/* Now according to parent, let's write divider ratio */
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offset = CKGA_SOURCE_CFG(clk_p->parent->id - CLKA_REF);
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CLK_WRITE(CKGA_BASE_ADDRESS + offset + (4 * idx), div_cfg);
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return 0;
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}
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static int clkgena_set_rate(clk_t *clk_p, unsigned long freq)
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{
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unsigned long div;
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int err;
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if (!clk_p)
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return CLK_ERR_BAD_PARAMETER;
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if (clk_p->id < CLKA_PLL0HS || clk_p->id > CLK_NOT_USED_2)
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return CLK_ERR_BAD_PARAMETER;
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/* PLL set rate: to be completed */
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if ((clk_p->id >= CLKA_PLL0HS) && (clk_p->id <= CLKA_PLL1))
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return CLK_ERR_BAD_PARAMETER;
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/* We need a parent for these clocks */
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if (!clk_p->parent)
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return CLK_ERR_INTERNAL;
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div = clk_p->parent->rate / freq;
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err = clkgena_set_div(clk_p, &div);
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if (!err)
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clk_p->rate = clk_p->parent->rate / div;
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return err;
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}
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static int clkgena_recalc(clk_t *clk_p)
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{
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unsigned long data, ratio;
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int idx;
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unsigned long srcreg, offset;
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int shift, err;
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if (!clk_p)
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return CLK_ERR_BAD_PARAMETER;
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if (!clk_p->parent)
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return CLK_ERR_INTERNAL;
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/* Reading clock programmed value */
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switch (clk_p->id) {
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case CLKA_REF: /* Clockgen A reference clock */
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clk_p->rate = clk_p->parent->rate;
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break;
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case CLKA_PLL0HS:
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data = CLK_READ(CKGA_BASE_ADDRESS + CKGA_PLL0_CFG);
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err = clk_pll1600_get_rate(clk_p->parent->rate, data & 0x7,
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(data >> 8) & 0xff, &clk_p->rate);
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return err;
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case CLKA_PLL0LS:
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clk_p->rate = clk_p->parent->rate / 2;
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return 0;
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case CLKA_PLL1:
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data = CLK_READ(CKGA_BASE_ADDRESS + CKGA_PLL1_CFG);
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return clk_pll800_get_rate(clk_p->parent->rate, data & 0xff,
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(data >> 8) & 0xff, (data >> 16) & 0x7, &clk_p->rate);
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default:
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idx = clkgena_get_index(clk_p->id, &srcreg, &shift);
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if (idx == -1)
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return CLK_ERR_BAD_PARAMETER;
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/* Now according to source, let's get divider ratio */
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offset = CKGA_SOURCE_CFG(clk_p->parent->id - CLKA_REF);
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data = CLK_READ(CKGA_BASE_ADDRESS + offset + (4 * idx));
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ratio = (data & 0x1F) + 1;
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clk_p->rate = clk_p->parent->rate / ratio;
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break;
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}
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return 0;
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}
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/* ========================================================================
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Name: clkgena_init
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Description: Read HW status to initialize 'clk_t' structure.
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Returns: 'clk_err_t' error code.
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======================================================================== */
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static int clkgena_init(clk_t *clk_p)
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{
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int err;
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if (!clk_p)
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return CLK_ERR_BAD_PARAMETER;
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err = clkgena_identify_parent(clk_p);
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if (!err)
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err = clkgena_recalc(clk_p);
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return err;
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}
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/*
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* Most of the code on Clock_Gen_C was done by:
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* Pawel Moll
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*/
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static void *clkgen_audio_base;
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static int clkgen_audio_enable(struct clk *clk)
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{
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unsigned long value = readl(CTL_SYNTH4X_AUD_N(clkgen_audio_base,
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clk->id - CLKC_FS_FREE_RUN + 1));
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value &= ~NSB__MASK;
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value |= NSB__ACTIVE;
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writel(value, CTL_SYNTH4X_AUD_N(clkgen_audio_base,
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clk->id - CLKC_FS_FREE_RUN + 1));
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return 0;
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}
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static int clkgen_audio_disable(struct clk *clk)
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{
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unsigned long value = readl(CTL_SYNTH4X_AUD_N(clkgen_audio_base,
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clk->id - CLKC_FS_FREE_RUN + 1));
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value &= ~NSB__MASK;
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value |= NSB__STANDBY;
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writel(value, CTL_SYNTH4X_AUD_N(clkgen_audio_base,
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clk->id - CLKC_FS_FREE_RUN + 1));
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return 0;
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}
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static int clkgen_audio_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long pe, md, sdiv;
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unsigned long value;
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int divider = (int)clk->private_data;
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if (divider)
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rate *= divider;
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if (clk_fsyn_get_params(clk_get_rate(clk->parent), rate,
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&md, &pe, &sdiv) != 0)
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return -EINVAL;
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value = readl(CTL_SYNTH4X_AUD_N(clkgen_audio_base,
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clk->id - CLKC_FS_FREE_RUN + 1));
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value &= ~MD__MASK;
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value |= MD__(md);
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value &= ~PE__MASK;
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value |= PE__(pe);
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value &= ~SDIV__MASK;
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value |= SDIV__(sdiv);
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writel(value, CTL_SYNTH4X_AUD_N(clkgen_audio_base,
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clk->id - CLKC_FS_FREE_RUN + 1));
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if (clk_fsyn_get_rate(clk_get_rate(clk->parent), pe, md,
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sdiv, &clk->rate))
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return -EINVAL;
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if (divider)
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clk->rate /= divider;
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return 0;
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}
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static struct clk_ops clkgen_audio_clk_ops = {
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.enable = clkgen_audio_enable,
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.disable = clkgen_audio_disable,
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.set_rate = clkgen_audio_set_rate,
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};
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#define clk_c(_id, _private_data) \
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{ \
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.name = #_id, \
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.id = _id, \
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.parent = &clk_clocks[CLK_SYSA], \
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.ops = &clkgen_audio_clk_ops, \
|
|
.private_data = (void *)(_private_data) \
|
|
}
|
|
|
|
static struct clk clkgen_audio_clks[] = {
|
|
clk_c(CLKC_FS_FREE_RUN, 2),
|
|
clk_c(CLKC_FS_DEC_1, 0),
|
|
clk_c(CLKC_SPDIF, 0),
|
|
clk_c(CLKC_FS_DEC_2, 0)
|
|
};
|
|
|
|
static int __init clkgen_audio_init(void)
|
|
{
|
|
int err = 0;
|
|
unsigned long value;
|
|
int i;
|
|
|
|
if (cpu_data->type == CPU_FLI7510)
|
|
clkgen_audio_base = ioremap(0xfdee0000, 0x30);
|
|
else
|
|
clkgen_audio_base = ioremap(0xfe0e0000, 0x30);
|
|
|
|
if (!clkgen_audio_base)
|
|
return -EFAULT;
|
|
|
|
/* Configure clkgen */
|
|
|
|
value = EN_CLK_256FS_FREE_RUN__ENABLED;
|
|
value |= EN_CLK_256FS_DEC_1__ENABLED;
|
|
value |= EN_CLK_SPDIF_RX__ENABLED;
|
|
value |= EN_CLK_256FS_DEC_2__ENABLED;
|
|
writel(value, CTL_EN(clkgen_audio_base));
|
|
|
|
value = SYNTH4X_AUD_NDIV__30_MHZ;
|
|
value |= SYNTH4X_AUD_SELCLKIN__CLKIN1V2;
|
|
value |= SYNTH4X_AUD_SELBW__VERY_GOOD_REFERENCE;
|
|
value |= SYNTH4X_AUD_NPDA__ACTIVE;
|
|
value |= SYNTH4X_AUD_NRST__RESET;
|
|
writel(value, CTL_SYNTH4X_AUD(clkgen_audio_base));
|
|
|
|
value = SEL_CLK_OUT__FSYNTH;
|
|
value |= NSB__STANDBY;
|
|
value |= NSDIV3__BYPASSED;
|
|
for (i = 0; i < ARRAY_SIZE(clkgen_audio_clks); i++) {
|
|
writel(value, CTL_SYNTH4X_AUD_N(clkgen_audio_base,
|
|
i + 1));
|
|
/* Set "safe" rate */
|
|
clkgen_audio_set_rate(&clkgen_audio_clks[i], 32000 * 128);
|
|
}
|
|
|
|
/* Unreset ;-) it now */
|
|
value = readl(CTL_SYNTH4X_AUD(clkgen_audio_base));
|
|
value &= ~SYNTH4X_AUD_NRST__MASK;
|
|
value |= SYNTH4X_AUD_NRST__NORMAL;
|
|
writel(value, CTL_SYNTH4X_AUD(clkgen_audio_base));
|
|
|
|
/* Register clocks */
|
|
|
|
err = clk_register_table(clkgen_audio_clks,
|
|
ARRAY_SIZE(clkgen_audio_clks), 0);
|
|
|
|
return err;
|
|
}
|
|
|
|
int __init plat_clk_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = clk_register_table(clk_clocks, ARRAY_SIZE(clk_clocks), 1);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clkgen_audio_init();
|
|
|
|
return ret;
|
|
}
|