139 lines
5.5 KiB
C
139 lines
5.5 KiB
C
/*
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* arch/arm/mach-at91/include/mach/at91sam9260.h
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*
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* (C) 2006 Andrew Victor
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*
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* Common definitions.
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* Based on AT91SAM9260 datasheet revision A (Preliminary).
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*
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* Includes also definitions for AT91SAM9XE and AT91SAM9G families
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91SAM9260_H
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#define AT91SAM9260_H
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
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#define AT91_ID_SYS 1 /* System Peripherals */
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#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
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#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
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#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
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#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
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#define AT91SAM9260_ID_US0 6 /* USART 0 */
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#define AT91SAM9260_ID_US1 7 /* USART 1 */
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#define AT91SAM9260_ID_US2 8 /* USART 2 */
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#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
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#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
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#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
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#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
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#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
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#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
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#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
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#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
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#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
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#define AT91SAM9260_ID_UHP 20 /* USB Host port */
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#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
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#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
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#define AT91SAM9260_ID_US3 23 /* USART 3 */
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#define AT91SAM9260_ID_US4 24 /* USART 4 */
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#define AT91SAM9260_ID_US5 25 /* USART 5 */
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#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
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#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
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#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
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#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
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#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
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#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
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/*
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* User Peripheral physical base addresses.
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*/
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#define AT91SAM9260_BASE_TCB0 0xfffa0000
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#define AT91SAM9260_BASE_TC0 0xfffa0000
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#define AT91SAM9260_BASE_TC1 0xfffa0040
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#define AT91SAM9260_BASE_TC2 0xfffa0080
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#define AT91SAM9260_BASE_UDP 0xfffa4000
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#define AT91SAM9260_BASE_MCI 0xfffa8000
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#define AT91SAM9260_BASE_TWI 0xfffac000
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#define AT91SAM9260_BASE_US0 0xfffb0000
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#define AT91SAM9260_BASE_US1 0xfffb4000
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#define AT91SAM9260_BASE_US2 0xfffb8000
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#define AT91SAM9260_BASE_SSC 0xfffbc000
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#define AT91SAM9260_BASE_ISI 0xfffc0000
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#define AT91SAM9260_BASE_EMAC 0xfffc4000
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#define AT91SAM9260_BASE_SPI0 0xfffc8000
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#define AT91SAM9260_BASE_SPI1 0xfffcc000
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#define AT91SAM9260_BASE_US3 0xfffd0000
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#define AT91SAM9260_BASE_US4 0xfffd4000
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#define AT91SAM9260_BASE_US5 0xfffd8000
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#define AT91SAM9260_BASE_TCB1 0xfffdc000
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#define AT91SAM9260_BASE_TC3 0xfffdc000
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#define AT91SAM9260_BASE_TC4 0xfffdc040
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#define AT91SAM9260_BASE_TC5 0xfffdc080
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#define AT91SAM9260_BASE_ADC 0xfffe0000
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#define AT91_BASE_SYS 0xffffe800
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/*
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* System Peripherals (offset from AT91_BASE_SYS)
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*/
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#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
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#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
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#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
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#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
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#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
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#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
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#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
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#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
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#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
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#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
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#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
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#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
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#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
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#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
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#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
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#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
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#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
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#define AT91_USART0 AT91SAM9260_BASE_US0
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#define AT91_USART1 AT91SAM9260_BASE_US1
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#define AT91_USART2 AT91SAM9260_BASE_US2
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#define AT91_USART3 AT91SAM9260_BASE_US3
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#define AT91_USART4 AT91SAM9260_BASE_US4
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#define AT91_USART5 AT91SAM9260_BASE_US5
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/*
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* Internal Memory.
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*/
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#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
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#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
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#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
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#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
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#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
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#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
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#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
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#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
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#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
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#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */
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#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
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#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
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#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
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#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
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#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
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#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
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#endif
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