340 lines
9.7 KiB
C
340 lines
9.7 KiB
C
/*****************************************************************************
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*
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* File name : clock-common.c
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* Description : Low Level API - Common LLA functions (SOC independant)
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*
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* COPYRIGHT (C) 2009 STMicroelectronics - All Rights Reserved
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* May be copied or modified under the terms of the GNU General Public
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* License v2. See linux/COPYING for more information.
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*
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*****************************************************************************/
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/* ----- Modification history (most recent first)----
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11/mar/10 fabrice.charpentier@st.com
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clk_pll800_get_params() fully revisited.
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10/dec/09 francesco.virlinzi@st.com
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clk_pll1600_get_params() now same code for OS21 & Linux.
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13/oct/09 fabrice.charpentier@st.com
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clk_fsyn_get_rate() API changed. Now returns error code.
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30/sep/09 fabrice.charpentier@st.com
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Introducing clk_pll800_get_rate() & clk_pll1600_get_rate() to
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replace clk_pll800_freq() & clk_pll1600_freq().
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*/
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#include <linux/clk.h>
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#include <asm-generic/div64.h>
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/*
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* Linux specific function
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*/
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/* Return the number of set bits in x. */
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static unsigned int population(unsigned int x)
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{
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/* This is the traditional branch-less algorithm for population count */
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x = x - ((x >> 1) & 0x55555555);
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x = (x & 0x33333333) + ((x >> 2) & 0x33333333);
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x = (x + (x >> 4)) & 0x0f0f0f0f;
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x = x + (x << 8);
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x = x + (x << 16);
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return x >> 24;
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}
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/* Return the index of the most significant set in x.
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* The results are 'undefined' is x is 0 (0xffffffff as it happens
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* but this is a mere side effect of the algorithm. */
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static unsigned int most_significant_set_bit(unsigned int x)
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{
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/* propagate the MSSB right until all bits smaller than MSSB are set */
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x = x | (x >> 1);
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x = x | (x >> 2);
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x = x | (x >> 4);
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x = x | (x >> 8);
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x = x | (x >> 16);
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/* now count the number of set bits [clz is population(~x)] */
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return population(x) - 1;
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}
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#include "clock-oslayer.h"
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#include "clock-common.h"
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/* ========================================================================
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Name: clk_pll800_get_rate()
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Description: Convert input/mdiv/ndiv/pvid values to frequency for PLL800
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Params: 'input' freq (Hz), mdiv/ndiv/pvid values
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Output: '*rate' updated
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Return: Error code.
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======================================================================== */
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int clk_pll800_get_rate(unsigned long input, unsigned long mdiv,
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unsigned long ndiv, unsigned long pdiv, unsigned long *rate)
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{
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if (!mdiv)
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mdiv++; /* mdiv=0 or 1 => MDIV=1 */
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/* Note: input is divided by 1000 to avoid overflow */
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*rate = (((2 * (input/1000) * ndiv) / mdiv) / (1 << pdiv)) * 1000;
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return 0;
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}
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/* ========================================================================
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Name: clk_pll1600_get_rate()
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Description: Convert input/mdiv/ndiv values to frequency for PLL1600
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Params: 'input' freq (Hz), mdiv/ndiv values
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Info: mdiv also called rdiv, ndiv also called ddiv
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Output: '*rate' updated with value of HS output.
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Return: Error code.
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======================================================================== */
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int clk_pll1600_get_rate(unsigned long input, unsigned long mdiv,
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unsigned long ndiv, unsigned long *rate)
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{
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if (!mdiv)
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return CLK_ERR_BAD_PARAMETER;
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/* Note: input is divided by 1000 to avoid overflow */
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*rate = ((2 * (input/1000) * ndiv) / mdiv) * 1000;
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return 0;
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}
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/* ========================================================================
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Name: clk_pll800_get_params()
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Description: Freq to parameters computation for PLL800
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Input: input & output freqs (Hz)
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Output: updated *mdiv, *ndiv & *pdiv (register values)
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Return: 'clk_err_t' error code
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======================================================================== */
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/*
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* PLL800 in FS mode computation algo
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*
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* 2 * N * Fin Mhz
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* Fout Mhz = ----------------- [1]
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* M * (2 ^ P)
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*
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* Rules:
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* 6.25Mhz <= output <= 800Mhz
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* FS mode means 3 <= N <= 255
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* 1 <= M <= 255
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* 1Mhz <= PFDIN (input/M) <= 50Mhz
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* 200Mhz <= FVCO (input*2*N/M) <= 800Mhz
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* For better long term jitter select M minimum && P maximum
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*/
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int clk_pll800_get_params(unsigned long input, unsigned long output,
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unsigned long *mdiv, unsigned long *ndiv, unsigned long *pdiv)
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{
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unsigned long m, n, pfdin, fvco;
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unsigned long deviation, new_freq;
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long new_deviation, pi;
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/* Output clock range: 6.25Mhz to 800Mhz */
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if (output < 6250000 || output > 800000000)
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return CLK_ERR_BAD_PARAMETER;
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input /= 1000;
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output /= 1000;
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deviation = output;
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for (pi = 5; pi >= 0 && deviation; pi--) {
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for (m = 1; (m < 255) && deviation; m++) {
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n = m * (1 << pi) * output / (input * 2);
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/* Checks */
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if (n < 3)
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continue;
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if (n > 255)
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break;
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pfdin = input / m; /* 1Mhz <= PFDIN <= 50Mhz */
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if (pfdin < 1000 || pfdin > 50000)
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continue;
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/* 200Mhz <= FVCO <= 800Mhz */
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fvco = (input * 2 * n) / m;
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if (fvco > 800000)
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continue;
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if (fvco < 200000)
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break;
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new_freq = (input * 2 * n) / (m * (1 << pi));
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new_deviation = new_freq - output;
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if (new_deviation < 0)
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new_deviation = -new_deviation;
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if (!new_deviation || new_deviation < deviation) {
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*mdiv = m;
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*ndiv = n;
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*pdiv = pi;
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deviation = new_deviation;
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}
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}
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}
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if (deviation == output) /* No solution found */
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return CLK_ERR_BAD_PARAMETER;
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return 0;
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}
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/* ========================================================================
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Name: clk_pll1600_get_params()
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Description: Freq to parameters computation for PLL1600
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Input: input,output=input/output freqs (Hz)
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Output: updated *mdiv (rdiv) & *ndiv (ddiv)
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Return: 'clk_err_t' error code
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======================================================================== */
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/*
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* Rules:
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* 600Mhz <= output (FVCO) <= 1800Mhz
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* 1 <= M (also called R) <= 7
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* 4 <= N <= 255
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* 4Mhz <= PFDIN (input/M) <= 75Mhz
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*/
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int clk_pll1600_get_params(unsigned long input, unsigned long output,
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unsigned long *mdiv, unsigned long *ndiv)
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{
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unsigned long m, n, pfdin;
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unsigned long deviation, new_freq;
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long new_deviation;
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/* Output clock range: 600Mhz to 1800Mhz */
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if (output < 600000000 || output > 1800000000)
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return CLK_ERR_BAD_PARAMETER;
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input /= 1000;
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output /= 1000;
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deviation = output;
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for (m = 1; (m < 7) && deviation; m++) {
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n = m * output / (input * 2);
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/* Checks */
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if (n < 4)
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continue;
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if (n > 255)
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break;
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pfdin = input / m; /* 4Mhz <= PFDIN <= 75Mhz */
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if (pfdin < 4000 || pfdin > 75000)
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continue;
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new_freq = (input * 2 * n) / m;
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new_deviation = new_freq - output;
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if (new_deviation < 0)
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new_deviation = -new_deviation;
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if (!new_deviation || new_deviation < deviation) {
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*mdiv = m;
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*ndiv = n;
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deviation = new_deviation;
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}
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}
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if (deviation == output) /* No solution found */
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return CLK_ERR_BAD_PARAMETER;
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return 0;
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}
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/* ========================================================================
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Name: clk_fsyn_get_rate()
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Description: Parameters to freq computation for frequency synthesizers.
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WARNING: parameters are HARDWARE CODED values, not the one
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used in formula.
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======================================================================== */
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/* This has to be enhanced to support several Fsyn types */
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int clk_fsyn_get_rate(unsigned long input, unsigned long pe,
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unsigned long md, unsigned long sd, unsigned long *rate)
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{
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int md2 = md;
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long long p, q, r, s, t;
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if (md & 0x10)
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md2 = md | 0xfffffff0;/* adjust the md sign */
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input *= 8;
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p = 1048576ll * input;
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q = 32768 * md2;
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r = 1081344 - pe;
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s = r + q;
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t = (1 << (sd + 1)) * s;
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*rate = div64_u64(p, t);
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return 0;
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}
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/* ========================================================================
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Name: clk_fsyn_get_params()
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Description: Freq to parameters computation for frequency synthesizers
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Input: input=input freq (Hz), output=output freq (Hz)
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Output: updated *md, *pe & *sdiv
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WARNING: parameters are HARDWARE CODED values, not the one
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used in formula.
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Return: 'clk_err_t' error code
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======================================================================== */
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/* This has to be enhanced to support several Fsyn types.
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Currently based on C090_4FS216_25. */
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int clk_fsyn_get_params(unsigned long input, unsigned long output,
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unsigned long *md, unsigned long *pe,
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unsigned long *sdiv)
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{
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unsigned long long p, q;
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unsigned int predivide;
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int preshift; /* always +ve but used in subtraction */
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unsigned int lsdiv;
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int lmd;
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unsigned int lpe = 1 << 14;
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/* pre-divide the frequencies */
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p = 1048576ull * input * 8; /* <<20? */
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q = output;
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predivide = (unsigned int)div64_u64(p, q);
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/* determine an appropriate value for the output divider using eqn. #4
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* with md = -16 and pe = 32768 (and round down) */
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lsdiv = predivide / 524288;
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if (lsdiv > 1) {
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/* sdiv = fls(sdiv) - 1; // this doesn't work
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* for some unknown reason */
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lsdiv = most_significant_set_bit(lsdiv);
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} else
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lsdiv = 1;
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/* pre-shift a common sub-expression of later calculations */
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preshift = predivide >> lsdiv;
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/* determine an appropriate value for the coarse selection using eqn. #5
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* with pe = 32768 (and round down which for signed values means away
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* from zero) */
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lmd = ((preshift - 1048576) / 32768) - 1; /* >>15? */
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/* calculate a value for pe that meets the output target */
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lpe = -1 * (preshift - 1081344 - (32768 * lmd)); /* <<15? */
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/* finally give sdiv its true hardware form */
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lsdiv--;
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/* special case for 58593.75Hz and harmonics...
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* can't quite seem to get the rounding right */
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if (lmd == -17 && lpe == 0) {
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lmd = -16;
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lpe = 32767;
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}
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/* update the outgoing arguments */
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*sdiv = lsdiv;
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*md = lmd;
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*pe = lpe;
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/* return 0 if all variables meet their contraints */
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return (lsdiv <= 7 && -16 <= lmd && lmd <= -1 && lpe <= 32767) ? 0 : -1;
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}
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