115 lines
3.3 KiB
C
115 lines
3.3 KiB
C
/*
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* drivers/stm/pcie-regs.h
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*
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* Registers for STMicro PCIe hardware
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*
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* Copyright 2010 ST Microelectronics (R&D) Ltd.
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* Author: David J. McKay (david.mckay@st.com)
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the top level directory for more details.
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*
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*/
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#ifndef __PCIE_REGS_H__
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#define __PCIE_REGS_H__
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#define TRANSLATION_CONTROL 0x900
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/* No effect in RC mode */
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#define EP_TRANSLATION_ENABLE (1<<0)
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/* Controls if area is inclusive or exclusive */
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#define RC_PASS_ADDR_RANGE (1<<1)
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/* Reserved in RC mode */
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#define PIM0_MEM_ADDR_START 0x910
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#define PIM1_MEM_ADDR_START 0x914
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#define PIM2_MEM_ADDR_START 0x918
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/* Base of area reserved for config accesses. Fixed
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* size of 64K.
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*/
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#define CFG_BASE_ADDRESS 0x92c
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#define CFG_REGION_SIZE 65536
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/* The PCIe capability registers start at this offset in configuration
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* space. Strictly speaking we should follow the caps linked list pointer,
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* but there seems little point since this is fixed
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*/
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#define CFG_PCIE_CAP 0x70
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/* First 4K of config space has this BDF (bus,device,function) */
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#define FUNC0_BDF_NUM 0x930
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/* There are other registers to control function 1 etc, split up into
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* 4K chunks. I cannot see any use for these, it is simpler to always
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* use FUNC0 and reprogram it as needed to drive the appropriate config
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* cycle
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*/
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#define FUNC_BDF_NUM(x) (0x930 + (((x) / 2) * 4))
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/* Reserved in RC mode */
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#define POM0_MEM_ADDR_START 0x960
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/* Start address of region 0 to be blocked/passed */
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#define IN0_MEM_ADDR_START 0x964
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/* End address of region 0 to be blocked/passed */
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#define IN0_MEM_ADDR_LIMIT 0x968
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/* Reserved in RC mode */
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#define POM1_MEM_ADDR_START 0x970
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/* Start address of region 1 to be blocked/passed */
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#define IN1_MEM_ADDR_START 0x974
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/* End address of region 1 to be blocked/passed */
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#define IN1_MEM_ADDR_LIMIT 0x978
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/* MSI registers */
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#define MSI_ADDRESS 0x820
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#define MSI_UPPER_ADDRESS 0x824
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#define MSI_OFFSET_REG(n) ((n) * 0xc)
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#define MSI_INTERRUPT_ENABLE(n) (0x828 + MSI_OFFSET_REG(n))
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#define MSI_INTERRUPT_MASK(n) (0x82c + MSI_OFFSET_REG(n))
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#define MSI_INTERRUPT_STATUS(n) (0x830 + MSI_OFFSET_REG(n))
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#define MSI_GPIO_REG 0x888
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#define MSI_NUM_ENDPOINTS 8
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/* This actually containes the LTSSM state machine state */
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#define PORT_LOGIC_DEBUG_REG_0 0x728
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/* LTSSM state machine values */
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#define DEBUG_REG_0_LTSSM_MASK 0x1f
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#define S_DETECT_QUIET 0x00
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#define S_DETECT_ACT 0x01
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#define S_POLL_ACTIVE 0x02
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#define S_POLL_COMPLIANCE 0x03
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#define S_POLL_CONFIG 0x04
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#define S_PRE_DETECT_QUIET 0x05
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#define S_DETECT_WAIT 0x06
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#define S_CFG_LINKWD_START 0x07
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#define S_CFG_LINKWD_ACEPT 0x08
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#define S_CFG_LANENUM_WAIT 0x09
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#define S_CFG_LANENUM_ACEPT 0x0A
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#define S_CFG_COMPLETE 0x0B
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#define S_CFG_IDLE 0x0C
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#define S_RCVRY_LOCK 0x0D
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#define S_RCVRY_SPEED 0x0E
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#define S_RCVRY_RCVRCFG 0x0F
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#define S_RCVRY_IDLE 0x10
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#define S_L0 0x11
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#define S_L0S 0x12
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#define S_L123_SEND_EIDLE 0x13
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#define S_L1_IDLE 0x14
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#define S_L2_IDLE 0x15
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#define S_L2_WAKE 0x16
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#define S_DISABLED_ENTRY 0x17
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#define S_DISABLED_IDLE 0x18
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#define S_DISABLED 0x19
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#define S_LPBK_ENTRY 0x1A
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#define S_LPBK_ACTIVE 0x1B
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#define S_LPBK_EXIT 0x1C
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#define S_LPBK_EXIT_TIMEOUT 0x1D
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#define S_HOT_RESET_ENTRY 0x1E
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#define S_HOT_RESET 0x1F
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#endif /* __PCIE_REGS_H__ */
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