52 lines
1.4 KiB
Plaintext
52 lines
1.4 KiB
Plaintext
* Parallel I/O Ports
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This node configures Parallel I/O ports for CPUs with QE support.
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The node should reside in the "soc" node of the tree. For each
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device that using parallel I/O ports, a child node should be created.
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See the definition of the Pin configuration nodes below for more
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information.
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Required properties:
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- device_type : should be "par_io".
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- reg : offset to the register set and its length.
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- num-ports : number of Parallel I/O ports
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Example:
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par_io@1400 {
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reg = <1400 100>;
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "par_io";
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num-ports = <7>;
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ucc_pin@01 {
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......
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};
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Note that "par_io" nodes are obsolete, and should not be used for
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the new device trees. Instead, each Par I/O bank should be represented
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via its own gpio-controller node:
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Required properties:
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- #gpio-cells : should be "2".
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- compatible : should be "fsl,<chip>-qe-pario-bank",
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"fsl,mpc8323-qe-pario-bank".
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- reg : offset to the register set and its length.
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- gpio-controller : node to identify gpio controllers.
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Example:
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qe_pio_a: gpio-controller@1400 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8360-qe-pario-bank",
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"fsl,mpc8323-qe-pario-bank";
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reg = <0x1400 0x18>;
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gpio-controller;
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};
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qe_pio_e: gpio-controller@1460 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8360-qe-pario-bank",
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"fsl,mpc8323-qe-pario-bank";
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reg = <0x1460 0x18>;
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gpio-controller;
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};
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