39 lines
1.6 KiB
Diff
39 lines
1.6 KiB
Diff
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
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index cc616fd31d8b..f2d1d7bd87d3 100644
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--- a/drivers/gpu/drm/i915/display/intel_dp.c
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+++ b/drivers/gpu/drm/i915/display/intel_dp.c
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@@ -616,8 +616,10 @@ intel_dp_mode_valid(struct drm_connector *connector,
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{
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struct intel_dp *intel_dp = intel_attached_dp(connector);
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struct intel_connector *intel_connector = to_intel_connector(connector);
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+ struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
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struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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struct drm_i915_private *dev_priv = to_i915(connector->dev);
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+ struct intel_lspcon *lspcon = enc_to_intel_lspcon(&intel_encoder->base);
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int target_clock = mode->clock;
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int max_rate, mode_rate, max_lanes, max_link_clock;
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int max_dotclk;
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@@ -639,6 +641,21 @@ intel_dp_mode_valid(struct drm_connector *connector,
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target_clock = fixed_mode->clock;
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}
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+ /*
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+ * Reducing Blanking to incorporate DP and HDMI timing/link bandwidth
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+ * limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs
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+ * while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will
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+ * cause mode to blank out. Reduced Htotal by shortening the back porch
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+ * and front porch within permissible limits.
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+ */
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+ if (lspcon->active && lspcon->hdr_supported &&
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+ mode->clock > 570000) {
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+ mode->clock = 570000;
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+ mode->htotal -= 180;
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+ mode->hsync_start -= 72;
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+ mode->hsync_end -= 72;
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+ }
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+
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max_link_clock = intel_dp_max_link_rate(intel_dp);
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max_lanes = intel_dp_max_lane_count(intel_dp);
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--
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