mirror of
https://github.com/DigitalDevices/dddvb.git
synced 2023-10-10 13:37:43 +02:00
support other CI speeds
This commit is contained in:
Ralph Metzler
parent
50fee67d49
commit
16c0834b78
@ -28,7 +28,7 @@ DEFINE_MUTEX(redirect_lock);
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static int ci_bitrate = 72000;
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module_param(ci_bitrate, int, 0444);
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MODULE_PARM_DESC(ci_bitrate, " Bitrate for output to CI.");
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MODULE_PARM_DESC(ci_bitrate, " Bitrate in KHz for output to CI.");
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static int ts_loop = -1;
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module_param(ts_loop, int, 0444);
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@ -547,89 +547,74 @@ static void ddb_buffers_free(struct ddb *dev)
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}
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}
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static void calc_speed(struct ddb_output *output, u32 *con, u32 *con2)
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static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
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{
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struct ddb *dev = output->port->dev;
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u32 bitrate = output->port->obr;
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u32 flags = 0;//pdx->OutputStream[Stream].flags;
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u32 gap = 6;
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u32 NCOIncrement = 0;
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u32 Control = 0x3C; /* Turn clock on, Enable GAP, Enable NP, Phase = 1 */
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u32 Maxbitrate = 72000;
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u32 bitrate = output->port->obr, max_bitrate = 72000;
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u32 gap = 4, nco = 0;
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if (flags & 0x00000008) /* ts start */
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Control |= 0x2000;
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*con = 0x1C;
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if (output->port->gap != 0xffffffff) {
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flags |= 1;
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gap = output->port->gap;
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}
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if (dev->link[0].info->type == DDB_OCTOPUS_CI && output->port->nr > 1) {
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Control = 0x00;
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if (flags & 0x00000004) { /* Override timing */
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if (flags & 0x00000800)
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Control = 0x08; // Clock Edge
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Control |= (flags & 0x00000700); // Clock Delay
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} else
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Control = 0x00000300; // Rising edge 21 ns setup time
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if (dev->link[0].ids.regmapid >= 0x10003 &&
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(flags & 0x00000001) == 0) {
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if ((flags & 0x00000002) == 0) {
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// NCO
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Maxbitrate = 0;
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*con = 0x10c;
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if (dev->link[0].ids.regmapid >= 0x10003 && !(flags & 1)) {
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if (!(flags & 2)) {
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/* NCO */
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max_bitrate = 0;
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gap = 0;
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if (bitrate == 72000)
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Control |= 0x24;
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else
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if (bitrate != 72000) {
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if (bitrate >= 96000)
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Control |= 0x824;
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else {
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Control |= 0x1024;
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NCOIncrement = (bitrate * 8192 + 71999) / 72000;
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*con |= 0x800;
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else {
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*con |= 0x1000;
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nco = (bitrate * 8192 + 71999) / 72000;
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}
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}
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} else {
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// Divider
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Control |= 0x1834;
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/* Divider and gap */
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*con |= 0x1810;
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if (bitrate <= 64000) {
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Maxbitrate = 64000;
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NCOIncrement = 8;
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max_bitrate = 64000;
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nco = 8;
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} else if( bitrate <= 72000) {
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Maxbitrate = 72000;
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NCOIncrement = 7;
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max_bitrate = 72000;
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nco = 7;
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} else {
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Maxbitrate = 96000;
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NCOIncrement = 5;
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max_bitrate = 96000;
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nco = 5;
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}
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}
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} else {
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if (bitrate > 72000) {
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Control |= 0x834; // Enable 96 MBit/s CI+ Speed
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Maxbitrate = 96000;
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*con |= 0x810; /* 96 MBit/s and gap */
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max_bitrate = 96000;
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}
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}
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}
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if (Maxbitrate > 0) {
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if (bitrate > Maxbitrate)
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bitrate = Maxbitrate;
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if (max_bitrate > 0) {
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if (bitrate > max_bitrate)
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bitrate = max_bitrate;
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if (bitrate < 31000)
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bitrate = 31000;
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gap = ((Maxbitrate - bitrate) * 94) / bitrate;
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gap = ((max_bitrate - bitrate) * 94) / bitrate;
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if (gap < 2)
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Control &= ~0x10; // Disable gap
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*con &= ~0x10; /* Disable gap */
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else
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gap -= 2;
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if (gap > 127)
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gap = 127;
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}
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*con = Control;
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*con2 = (NCOIncrement << 16) | gap;
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*con2 = (nco << 16) | gap;
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return;
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}
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static void ddb_output_start(struct ddb_output *output)
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{
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struct ddb *dev = output->port->dev;
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u32 con2;
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con2 = ((output->port->obr << 13) + 71999) / 72000;
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con2 = (con2 << 16) | output->port->gap;
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u32 con = 0x11c, con2 = 0;
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if (output->dma) {
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spin_lock_irq(&output->dma->lock);
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@ -641,10 +626,14 @@ static void ddb_output_start(struct ddb_output *output)
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if (output->port->class == DDB_PORT_MOD)
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ddbridge_mod_output_start(output);
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else {
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if (output->port->input[0]->port->class == DDB_PORT_LOOP)
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con = (1UL << 13) | 0x14;
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else
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calc_con(output, &con, &con2, 0);
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ddbwritel(dev, 0, TS_CONTROL(output));
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ddbwritel(dev, 2, TS_CONTROL(output));
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ddbwritel(dev, 0, TS_CONTROL(output));
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ddbwritel(dev, 0x3c, TS_CONTROL(output));
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ddbwritel(dev, con, TS_CONTROL(output));
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ddbwritel(dev, con2, TS_CONTROL2(output));
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}
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if (output->dma) {
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@ -654,16 +643,8 @@ static void ddb_output_start(struct ddb_output *output)
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ddbwritel(dev, 1, DMA_BASE_READ);
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ddbwritel(dev, 3, DMA_BUFFER_CONTROL(output->dma));
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}
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if (output->port->class != DDB_PORT_MOD) {
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if (output->port->input[0]->port->class == DDB_PORT_LOOP)
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/*ddbwritel(dev, 0x15, TS_CONTROL(output));
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ddbwritel(dev, 0x45,
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TS_CONTROL(output));*/
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ddbwritel(dev, (1 << 13) | 0x15,
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TS_CONTROL(output));
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else
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ddbwritel(dev, 0x11d, TS_CONTROL(output));
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}
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if (output->port->class != DDB_PORT_MOD)
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ddbwritel(dev, con | 1, TS_CONTROL(output));
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if (output->dma) {
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output->dma->running = 1;
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spin_unlock_irq(&output->dma->lock);
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@ -3354,7 +3335,7 @@ static void ddb_ports_init(struct ddb *dev)
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port->nr = i;
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port->lnr = l;
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port->pnr = p;
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port->gap = 4;
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port->gap = 0xffffffff;
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port->obr = ci_bitrate;
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mutex_init(&port->i2c_gate_lock);
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if (!ddb_port_match_i2c(port))
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@ -4640,6 +4621,31 @@ static ssize_t gap_store(struct device *device, struct device_attribute *attr,
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return count;
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}
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static ssize_t obr_show(struct device *device,
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struct device_attribute *attr, char *buf)
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{
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struct ddb *dev = dev_get_drvdata(device);
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int num = attr->attr.name[3] - 0x30;
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return sprintf(buf, "%d\n", dev->port[num].obr);
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}
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static ssize_t obr_store(struct device *device, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct ddb *dev = dev_get_drvdata(device);
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int num = attr->attr.name[3] - 0x30;
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unsigned int val;
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if (sscanf(buf, "%u\n", &val) != 1)
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return -EINVAL;
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if (val > 96000)
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return -EINVAL;
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dev->port[num].obr = val;
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return count;
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}
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static ssize_t version_show(struct device *device,
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struct device_attribute *attr, char *buf)
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{
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@ -4732,6 +4738,10 @@ static struct device_attribute ddb_attrs[] = {
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__ATTR(gap1, 0664, gap_show, gap_store),
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__ATTR(gap2, 0664, gap_show, gap_store),
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__ATTR(gap3, 0664, gap_show, gap_store),
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__ATTR(obr0, 0664, obr_show, obr_store),
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__ATTR(obr1, 0664, obr_show, obr_store),
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__ATTR(obr2, 0664, obr_show, obr_store),
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__ATTR(obr3, 0664, obr_show, obr_store),
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__ATTR(vlan, 0664, vlan_show, vlan_store),
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__ATTR(fmode0, 0664, fmode_show, fmode_store),
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__ATTR(fmode1, 0664, fmode_show, fmode_store),
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