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https://github.com/DigitalDevices/dddvb.git
synced 2023-10-10 13:37:43 +02:00
change some pr_info to pr_debug
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d1387078f1
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26eedb3d26
@ -628,6 +628,29 @@ static void ddb_buffers_free(struct ddb *dev)
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}
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}
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}
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}
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/*
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* Control:
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*
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* Bit 0 - Enable TS
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* 1 - Reset
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* 2 - clock enable
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* 3 - clock phase
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* 4 - gap enable
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* 5 - send null packets on underrun
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* 6 - enable clock gating
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* 7 - set error bit on inserted null packets
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* 8-10 - fine adjust clock delay
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* 11- HS (high speed), if NCO mode=0: 0=72MHz 1=96Mhz
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* 12- enable NCO mode
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*
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* Control 2:
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*
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* Bit 0-6 : gap_size, Gap = (gap_size * 2) + 4
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* 16-31: HS = 0: Speed = 72 * Value / 8192 MBit/s
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* HS = 1: Speed = 72 * 8 / (Value + 1) MBit/s (only bit 19-16 used)
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*
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*/
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static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
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static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
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{
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{
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struct ddb *dev = output->port->dev;
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struct ddb *dev = output->port->dev;
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@ -3317,7 +3340,7 @@ static void ddb_dma_init(struct ddb_io *io, int nr, int out)
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dma->div = INPUT_DMA_IRQ_DIV;
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dma->div = INPUT_DMA_IRQ_DIV;
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}
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}
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ddbwritel(io->port->dev, 0, DMA_BUFFER_ACK(dma));
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ddbwritel(io->port->dev, 0, DMA_BUFFER_ACK(dma));
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pr_info("DDBridge: init link %u, io %u, dma %u, dmaregs %08x bufregs %08x\n",
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pr_debug("DDBridge: init link %u, io %u, dma %u, dmaregs %08x bufregs %08x\n",
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io->port->lnr, io->nr, nr, dma->regs, dma->bufregs);
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io->port->lnr, io->nr, nr, dma->regs, dma->bufregs);
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}
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}
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@ -3333,7 +3356,7 @@ static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr)
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rm = io_regmap(input, 1);
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rm = io_regmap(input, 1);
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input->regs = DDB_LINK_TAG(port->lnr) |
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input->regs = DDB_LINK_TAG(port->lnr) |
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(rm->input->base + rm->input->size * nr);
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(rm->input->base + rm->input->size * nr);
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pr_info("DDBridge: init link %u, input %u, regs %08x\n", port->lnr, nr, input->regs);
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pr_debug("DDBridge: init link %u, input %u, regs %08x\n", port->lnr, nr, input->regs);
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if (dev->has_dma) {
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if (dev->has_dma) {
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struct ddb_regmap *rm0 = io_regmap(input, 0);
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struct ddb_regmap *rm0 = io_regmap(input, 0);
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u32 base = rm0->irq_base_idma;
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u32 base = rm0->irq_base_idma;
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@ -3342,7 +3365,8 @@ static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr)
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if (port->lnr)
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if (port->lnr)
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dma_nr += 32 + (port->lnr - 1) * 8;
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dma_nr += 32 + (port->lnr - 1) * 8;
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pr_info("DDBridge: init link %u, input %u, handler %u\n", port->lnr, nr, dma_nr + base);
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pr_debug("DDBridge: init link %u, input %u, handler %u\n",
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port->lnr, nr, dma_nr + base);
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dev->handler[0][dma_nr + base] = input_handler;
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dev->handler[0][dma_nr + base] = input_handler;
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dev->handler_data[0][dma_nr + base] = (unsigned long) input;
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dev->handler_data[0][dma_nr + base] = (unsigned long) input;
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ddb_dma_init(input, dma_nr, 0);
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ddb_dma_init(input, dma_nr, 0);
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@ -3361,7 +3385,8 @@ static void ddb_output_init(struct ddb_port *port, int nr)
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rm = io_regmap(output, 1);
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rm = io_regmap(output, 1);
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output->regs = DDB_LINK_TAG(port->lnr) |
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output->regs = DDB_LINK_TAG(port->lnr) |
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(rm->output->base + rm->output->size * nr);
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(rm->output->base + rm->output->size * nr);
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pr_info("DDBridge: init link %u, output %u, regs %08x\n", port->lnr, nr, output->regs);
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pr_debug("DDBridge: init link %u, output %u, regs %08x\n",
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port->lnr, nr, output->regs);
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if (dev->has_dma) {
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if (dev->has_dma) {
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struct ddb_regmap *rm0 = io_regmap(output, 0);
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struct ddb_regmap *rm0 = io_regmap(output, 0);
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u32 base = rm0->irq_base_odma;
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u32 base = rm0->irq_base_odma;
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