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synced 2023-10-10 13:37:43 +02:00
add some symbol rate modes
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parent
22475860d5
commit
310a5e0f05
@ -1516,12 +1516,12 @@ static int mod3_set_ari(struct ddb_mod *mod, u32 rate)
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static int mod3_set_sample_rate(struct ddb_mod *mod, u32 rate)
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{
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u32 cic, inc;
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u32 cic, inc, bypass = 0;
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switch (rate) {
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/* 2^31 * freq*4*cic / 245.76Mhz */
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case SYS_DVBT_6:
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inc = 1917396114;
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inc = 0x72492492;
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cic = 8;
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break;
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case SYS_DVBT_7:
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@ -1533,19 +1533,45 @@ static int mod3_set_sample_rate(struct ddb_mod *mod, u32 rate)
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inc = 1917396114;
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cic = 6;
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break;
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case SYS_DVBC_6900:
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inc = 0x73000000; //1929379840;
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cic = 8;
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break;
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case 9:
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inc = 0x47e00000; //1929379840;
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cic = 10;
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bypass = 2;
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break;
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case SYS_J83B_64_6: /* 5056941 */
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inc = 0x695a5a1d;
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cic = 10;
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break;
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case SYS_J83B_256_6: /* 5360537 */
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inc = 0x6fad87da;
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cic = 10;
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break;
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case SYS_ISDBT_6:
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inc = 1988410754;
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inc = 0x7684BD82; //1988410754;
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cic = 7;
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break;
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case SYS_DVBS2_22:
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inc = 1922389333;
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inc = 0x72955555; // 1922389333;
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cic = 5;
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bypass = 2;
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break;
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case SYS_DVBS2_24:
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inc = 0x7d000000;
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cic = 5;
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bypass = 2;
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break;
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default:
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return -EINVAL;
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}
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ddbwritel(mod->port->dev, inc, SDR_CHANNEL_ARICW(mod->port->nr));
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ddbwritel(mod->port->dev, cic << 8, SDR_CHANNEL_CONFIG(mod->port->nr));
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ddbwritel(mod->port->dev, (cic << 8) | (bypass << 4),
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SDR_CHANNEL_CONFIG(mod->port->nr));
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return 0;
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}
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