mirror of
https://github.com/DigitalDevices/dddvb.git
synced 2023-10-10 13:37:43 +02:00
coding style fixes
This commit is contained in:
Ralph Metzler
parent
b3b7a0ef2e
commit
f44a9dfcbd
@ -427,7 +427,7 @@ static void ddb_set_dma_tables(struct ddb *dev)
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ddb_set_dma_table(dev->port[i].input[1]);
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if (dev->port[i].output)
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ddb_set_dma_table(dev->port[i].output);
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}
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}
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}
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@ -653,27 +653,27 @@ static void ddb_buffers_free(struct ddb *dev)
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}
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/*
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* Control:
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*
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* Bit 0 - Enable TS
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* 1 - Reset
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* 2 - clock enable
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* 3 - clock phase
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* 4 - gap enable
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* 5 - send null packets on underrun
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* 6 - enable clock gating
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* 7 - set error bit on inserted null packets
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* 8-10 - fine adjust clock delay
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* 11- HS (high speed), if NCO mode=0: 0=72MHz 1=96Mhz
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* 12- enable NCO mode
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*
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* Control 2:
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*
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* Bit 0-6 : gap_size, Gap = (gap_size * 2) + 4
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* 16-31: HS = 0: Speed = 72 * Value / 8192 MBit/s
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* HS = 1: Speed = 72 * 8 / (Value + 1) MBit/s (only bit 19-16 used)
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*
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*/
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* Control:
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*
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* Bit 0 - Enable TS
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* 1 - Reset
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* 2 - clock enable
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* 3 - clock phase
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* 4 - gap enable
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* 5 - send null packets on underrun
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* 6 - enable clock gating
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* 7 - set error bit on inserted null packets
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* 8-10 - fine adjust clock delay
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* 11- HS (high speed), if NCO mode=0: 0=72MHz 1=96Mhz
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* 12- enable NCO mode
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*
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* Control 2:
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*
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* Bit 0-6 : gap_size, Gap = (gap_size * 2) + 4
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* 16-31: HS = 0: Speed = 72 * Value / 8192 MBit/s
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* HS = 1: Speed = 72 * 8 / (Value + 1) MBit/s (only bit 19-16 used)
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*
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*/
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static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
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{
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@ -698,7 +698,8 @@ static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
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*con |= 0x800;
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else {
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*con |= 0x1000;
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nco = (bitrate * 8192 + 71999) / 72000;
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nco = (bitrate *
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8192 + 71999) / 72000;
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}
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}
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} else {
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@ -707,7 +708,7 @@ static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
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if (bitrate <= 64000) {
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max_bitrate = 64000;
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nco = 8;
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} else if( bitrate <= 72000) {
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} else if (bitrate <= 72000) {
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max_bitrate = 72000;
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nco = 7;
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} else {
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@ -736,7 +737,6 @@ static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
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gap = 127;
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}
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*con2 = (nco << 16) | gap;
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return;
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}
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static void ddb_output_start(struct ddb_output *output)
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@ -744,7 +744,7 @@ static void ddb_output_start(struct ddb_output *output)
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struct ddb *dev = output->port->dev;
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u32 con = 0x11c, con2 = 0;
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printk("Channel Base = %08x\n", output->regs);
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pr_info("Channel Base = %08x\n", output->regs);
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if (output->dma) {
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spin_lock_irq(&output->dma->lock);
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output->dma->cbuf = 0;
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@ -811,7 +811,8 @@ static void ddb_input_stop(struct ddb_input *input)
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spin_unlock_irq(&input->dma->lock);
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}
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/*printk("input_stop %u.%u.%u\n",
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dev->nr, input->port->lnr, input->nr);*/
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* dev->nr, input->port->lnr, input->nr);
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*/
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}
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static void ddb_input_start(struct ddb_input *input)
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@ -976,7 +977,8 @@ static ssize_t ddb_output_write(struct ddb_output *output,
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dma_sync_single_for_device(dev->dev,
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output->dma->pbuf[
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output->dma->cbuf],
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output->dma->size, DMA_TO_DEVICE);
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output->dma->size,
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DMA_TO_DEVICE);
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left -= len;
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buf += len;
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output->dma->coff += len;
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@ -1106,8 +1108,10 @@ static size_t ddb_input_read(struct ddb_input *input,
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free = left;
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if (alt_dma)
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dma_sync_single_for_cpu(dev->dev,
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input->dma->pbuf[input->dma->cbuf],
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input->dma->size, DMA_FROM_DEVICE);
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input->dma->pbuf[
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input->dma->cbuf],
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input->dma->size,
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DMA_FROM_DEVICE);
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ret = copy_to_user(buf, input->dma->vbuf[input->dma->cbuf] +
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input->dma->coff, free);
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if (ret)
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@ -1656,7 +1660,8 @@ static int lnb_command(struct ddb *dev, u32 link, u32 lnb, u32 cmd)
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msleep(20);
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}
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if (c == 10)
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pr_info("DDBridge: lnb_command lnb = %08x cmd = %08x\n", lnb, cmd);
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pr_info("DDBridge: lnb_command lnb = %08x cmd = %08x\n",
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lnb, cmd);
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return 0;
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}
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@ -1698,13 +1703,15 @@ static int lnb_send_diseqc(struct ddb *dev, u32 link, u32 input,
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return 0;
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}
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static int lnb_set_sat(struct ddb *dev, u32 link, u32 input, u32 sat, u32 band, u32 hor)
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static int lnb_set_sat(struct ddb *dev, u32 link,
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u32 input, u32 sat, u32 band, u32 hor)
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{
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struct dvb_diseqc_master_cmd cmd = {
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.msg = {0xe0, 0x10, 0x38, 0xf0, 0x00, 0x00},
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.msg_len = 4
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};
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cmd.msg[3] = 0xf0 | ( ((sat << 2) & 0x0c) | (band ? 1 : 0) | (hor ? 2 : 0));
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cmd.msg[3] = 0xf0 | (((sat << 2) & 0x0c) |
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(band ? 1 : 0) | (hor ? 2 : 0));
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return lnb_send_diseqc(dev, link, input, &cmd);
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}
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@ -2529,7 +2536,8 @@ static int init_xo2_ci(struct ddb_port *port)
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port->nr, data[0]);
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return -1;
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}
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pr_info("DDBridge: Port %d: DuoFlex CI %u.%u\n", port->nr, data[0], data[1]);
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pr_info("DDBridge: Port %d: DuoFlex CI %u.%u\n",
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port->nr, data[0], data[1]);
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i2c_read_reg(i2c, 0x10, 0x08, &val);
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if (val != 0) {
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@ -2617,7 +2625,7 @@ static void ddb_port_probe(struct ddb_port *port)
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}
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if (dev->link[l].info->type == DDB_OCTOPRO_HDIN) {
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if( port->nr == 0 ) {
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if (port->nr == 0) {
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dev->link[l].info->type = DDB_OCTOPUS;
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port->name = "HDIN";
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port->class = DDB_PORT_LOOP;
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@ -2657,7 +2665,7 @@ static void ddb_port_probe(struct ddb_port *port)
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ddbwritel(dev, I2C_SPEED_400,
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port->i2c->regs + I2C_TIMING);
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} else {
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pr_info(KERN_INFO "DDBridge: Port %d: Uninitialized DuoFlex\n",
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pr_info("DDBridge: Port %d: Uninitialized DuoFlex\n",
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port->nr);
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return;
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}
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@ -3214,7 +3222,8 @@ static void input_write_dvb(struct ddb_input *input,
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dma = dma2 = input->dma;
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/* if there also is an output connected, do not ACK.
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input_write_output will ACK. */
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* input_write_output will ACK.
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*/
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if (input->redo) {
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dma2 = input->redo->dma;
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ack = 0;
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@ -3229,7 +3238,7 @@ static void input_write_dvb(struct ddb_input *input,
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dma_sync_single_for_cpu(dev->dev, dma2->pbuf[dma->cbuf],
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dma2->size, DMA_FROM_DEVICE);
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#if 0
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pr_info("DDBridge: %02x %02x %02x %02x \n",
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pr_info("DDBridge: %02x %02x %02x %02x\n",
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dma2->vbuf[dma->cbuf][0], dma2->vbuf[dma->cbuf][1],
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dma2->vbuf[dma->cbuf][2], dma2->vbuf[dma->cbuf][3]);
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#endif
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@ -3286,8 +3295,9 @@ static void input_handler(unsigned long data)
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/* If there is no input connected, input_tasklet() will
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just copy pointers and ACK. So, there is no need to go
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through the tasklet scheduler. */
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* just copy pointers and ACK. So, there is no need to go
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* through the tasklet scheduler.
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*/
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#ifdef DDB_USE_WORK
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if (input->redi)
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queue_work(ddb_wq, &dma->work);
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@ -3390,7 +3400,8 @@ static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr)
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rm = io_regmap(input, 1);
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input->regs = DDB_LINK_TAG(port->lnr) |
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(rm->input->base + rm->input->size * nr);
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pr_debug("DDBridge: init link %u, input %u, regs %08x\n", port->lnr, nr, input->regs);
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pr_debug("DDBridge: init link %u, input %u, regs %08x\n",
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port->lnr, nr, input->regs);
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if (dev->has_dma) {
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struct ddb_regmap *rm0 = io_regmap(input, 0);
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u32 base = rm0->irq_base_idma;
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@ -3587,19 +3598,19 @@ static void ddb_ports_release(struct ddb *dev)
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dev->handler[0][_nr](dev->handler_data[0][_nr]); } \
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while (0)
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#define IRQ_HANDLE_BYTE(_n) \
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if (s & (0x000000ff << ((_n) & 0x1f))) { \
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IRQ_HANDLE(0 + _n); \
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IRQ_HANDLE(1 + _n); \
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IRQ_HANDLE(2 + _n); \
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IRQ_HANDLE(3 + _n); \
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IRQ_HANDLE(4 + _n); \
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IRQ_HANDLE(5 + _n); \
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IRQ_HANDLE(6 + _n); \
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IRQ_HANDLE(7 + _n); \
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#define IRQ_HANDLE_BYTE(_n) { \
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if (s & (0x000000ff << ((_n) & 0x1f))) { \
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IRQ_HANDLE(0 + (_n)); \
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IRQ_HANDLE(1 + (_n)); \
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IRQ_HANDLE(2 + (_n)); \
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IRQ_HANDLE(3 + (_n)); \
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IRQ_HANDLE(4 + (_n)); \
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IRQ_HANDLE(5 + (_n)); \
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IRQ_HANDLE(6 + (_n)); \
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IRQ_HANDLE(7 + (_n)); \
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} \
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}
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static void irq_handle_msg(struct ddb *dev, u32 s)
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{
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dev->i2c_irq++;
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@ -3721,18 +3732,18 @@ static irqreturn_t irq_handle_v2_n(struct ddb *dev, u32 n)
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ddbwritel(dev, s, reg);
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if ((s & 0x000000ff)) {
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IRQ_HANDLE( 0 + off);
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IRQ_HANDLE( 1 + off);
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IRQ_HANDLE( 2 + off);
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IRQ_HANDLE( 3 + off);
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IRQ_HANDLE( 4 + off);
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IRQ_HANDLE( 5 + off);
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IRQ_HANDLE( 6 + off);
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IRQ_HANDLE( 7 + off);
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IRQ_HANDLE(0 + off);
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IRQ_HANDLE(1 + off);
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IRQ_HANDLE(2 + off);
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IRQ_HANDLE(3 + off);
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IRQ_HANDLE(4 + off);
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IRQ_HANDLE(5 + off);
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IRQ_HANDLE(6 + off);
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IRQ_HANDLE(7 + off);
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}
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if ((s & 0x0000ff00)) {
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IRQ_HANDLE( 8 + off);
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IRQ_HANDLE( 9 + off);
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IRQ_HANDLE(8 + off);
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IRQ_HANDLE(9 + off);
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IRQ_HANDLE(10 + off);
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IRQ_HANDLE(11 + off);
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IRQ_HANDLE(12 + off);
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@ -3862,7 +3873,7 @@ static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg)
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return -EINVAL;
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ctrl = (input->port->lnr << 16) | ((input->nr & 7) << 8) |
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((ts->filter_mask & 3) << 2);
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/*pr_info("DDBridge: GET_TS %u.%u\n", input->port->lnr, input->nr);*/
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if (ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) {
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pr_info("DDBridge: ts capture busy\n");
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return -EBUSY;
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@ -4463,7 +4474,7 @@ static ssize_t fan_store(struct device *device, struct device_attribute *d,
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const char *buf, size_t count)
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{
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struct ddb *dev = dev_get_drvdata(device);
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unsigned val;
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u32 val;
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if (sscanf(buf, "%u\n", &val) != 1)
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return -EINVAL;
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@ -4639,7 +4650,7 @@ static ssize_t led_store(struct device *device,
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{
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struct ddb *dev = dev_get_drvdata(device);
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int num = attr->attr.name[3] - 0x30;
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unsigned val;
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u32 val;
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if (sscanf(buf, "%u\n", &val) != 1)
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return -EINVAL;
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@ -5016,7 +5027,8 @@ static void ddb_device_attrs_del(struct ddb *dev)
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for (i = 0; i < 4; i++)
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if (dev->link[i].info &&
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dev->link[i].info->tempmon_irq)
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device_remove_file(dev->ddb_dev, &ddb_attrs_fanspeed[i]);
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device_remove_file(dev->ddb_dev,
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&ddb_attrs_fanspeed[i]);
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for (i = 0; i < dev->link[0].info->temp_num; i++)
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device_remove_file(dev->ddb_dev, &ddb_attrs_temp[i]);
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for (i = 0; i < dev->link[0].info->port_num; i++)
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@ -5271,7 +5283,8 @@ static void tempmon_setfan(struct ddb_link *link)
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{
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u32 temp, temp2, pwm;
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if ((ddblreadl(link, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0) {
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if ((ddblreadl(link, TEMPMON_CONTROL) &
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TEMPMON_CONTROL_OVERTEMP) != 0) {
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pr_info("DDBridge: Over temperature condition\n");
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link->OverTemperatureError = 1;
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}
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@ -5289,10 +5302,10 @@ static void tempmon_setfan(struct ddb_link *link)
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pwm = 10;
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if (temp >= link->temp_tab[pwm]) {
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while( pwm < 10 && temp >= link->temp_tab[pwm + 1])
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while (pwm < 10 && temp >= link->temp_tab[pwm + 1])
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pwm += 1;
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} else {
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while( pwm > 1 && temp < link->temp_tab[pwm - 2])
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while (pwm > 1 && temp < link->temp_tab[pwm - 2])
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pwm -= 1;
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}
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ddblwritel(link, (pwm << 8), TEMPMON_FANCONTROL);
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@ -5316,9 +5329,11 @@ static int tempmon_init(struct ddb_link *link, int FirstTime)
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spin_lock_irq(&link->temp_lock);
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if (FirstTime) {
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static u8 TemperatureTable[11] = {30,35,40,45,50,55,60,65,70,75,80};
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static u8 TemperatureTable[11] = {
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30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80};
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memcpy(link->temp_tab, TemperatureTable, sizeof(TemperatureTable));
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memcpy(link->temp_tab, TemperatureTable,
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sizeof(TemperatureTable));
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}
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dev->handler[l][link->info->tempmon_irq] = temp_handler;
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dev->handler_data[l][link->info->tempmon_irq] = (unsigned long) link;
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@ -5328,7 +5343,8 @@ static int tempmon_init(struct ddb_link *link, int FirstTime)
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ddblwritel(link, (3 << 8), TEMPMON_FANCONTROL);
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link->OverTemperatureError =
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((ddblreadl(link, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0);
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((ddblreadl(link, TEMPMON_CONTROL) &
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TEMPMON_CONTROL_OVERTEMP) != 0);
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if (link->OverTemperatureError) {
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pr_info("DDBridge: Over temperature condition\n");
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status = -1;
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@ -5455,9 +5471,11 @@ static void ddb_reset_ios(struct ddb *dev)
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if (rm->input)
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for (i = 0; i < rm->input->num; i++)
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ddb_reset_io(dev, rm->input->base + i * rm->input->size);
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ddb_reset_io(dev,
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rm->input->base + i * rm->input->size);
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if (rm->output)
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for (i = 0; i < rm->output->num; i++)
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ddb_reset_io(dev, rm->output->base + i * rm->output->size);
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ddb_reset_io(dev,
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rm->output->base + i * rm->output->size);
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usleep_range(5000, 6000);
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}
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@ -76,57 +76,62 @@ inline s64 RoundPCRDown(s64 a)
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return a & ~(HW_LSB_MASK - 1);
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}
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// Calculating KF, LF from Symbolrate
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//
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// Symbolrate is usually calculated as (M/N) * 10.24 MS/s
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//
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// Common Values for M,N
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// J.83 Annex A,
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// Euro Docsis 6.952 MS/s : M = 869, N = 1280
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// 6.900 MS/s : M = 345, N = 512
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// 6.875 MS/s : M = 1375, N = 2048
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// 6.111 MS/s : M = 6111, N = 10240
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// J.83 Annex B **
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// QAM64 5.056941 : M = 401, N = 812
|
||||
// QAM256 5.360537 : M = 78, N = 149
|
||||
// J.83 Annex C **
|
||||
// 5.309734 : M = 1889, N = 3643
|
||||
//
|
||||
// For the present hardware
|
||||
// KF' = 256 * M
|
||||
// LF' = 225 * N
|
||||
// or
|
||||
// KF' = Symbolrate in Hz
|
||||
// LF' = 9000000
|
||||
//
|
||||
// KF = KF' / gcd(KF',LF')
|
||||
// LF = LF' / gcd(KF',LF')
|
||||
// Note: LF must not be a power of 2.
|
||||
// Maximum value for KF,LF = 13421727 ( 0x7FFFFFF )
|
||||
// ** using these M,N values will result in a small err (<5ppm)
|
||||
// calculating KF,LF directly gives the exact normative result
|
||||
// but with rather large KF,LF values
|
||||
/* Calculating KF, LF from Symbolrate
|
||||
*
|
||||
* Symbolrate is usually calculated as (M/N) * 10.24 MS/s
|
||||
*
|
||||
* Common Values for M,N
|
||||
* J.83 Annex A,
|
||||
* Euro Docsis 6.952 MS/s : M = 869, N = 1280
|
||||
* 6.900 MS/s : M = 345, N = 512
|
||||
* 6.875 MS/s : M = 1375, N = 2048
|
||||
* 6.111 MS/s : M = 6111, N = 10240
|
||||
* J.83 Annex B **
|
||||
* QAM64 5.056941 : M = 401, N = 812
|
||||
* QAM256 5.360537 : M = 78, N = 149
|
||||
* J.83 Annex C **
|
||||
* 5.309734 : M = 1889, N = 3643
|
||||
*
|
||||
* For the present hardware
|
||||
* KF' = 256 * M
|
||||
* LF' = 225 * N
|
||||
* or
|
||||
* KF' = Symbolrate in Hz
|
||||
* LF' = 9000000
|
||||
*
|
||||
* KF = KF' / gcd(KF',LF')
|
||||
* LF = LF' / gcd(KF',LF')
|
||||
* Note: LF must not be a power of 2.
|
||||
* Maximum value for KF,LF = 13421727 ( 0x7FFFFFF )
|
||||
* ** using these M,N values will result in a small err (<5ppm)
|
||||
* calculating KF,LF directly gives the exact normative result
|
||||
* but with rather large KF,LF values
|
||||
*/
|
||||
|
||||
static inline u32 gcd(u32 u,u32 v)
|
||||
static inline u32 gcd(u32 u, u32 v)
|
||||
{
|
||||
int s = 0;
|
||||
while (((u|v)&1) == 0) {
|
||||
s += 1;
|
||||
u >>= 1;
|
||||
v >>= 1;
|
||||
}
|
||||
while ((u&1) == 0)
|
||||
u >>= 1;
|
||||
do {
|
||||
while ( (v&1) == 0 ) v >>= 1;
|
||||
if( u > v ) {
|
||||
u32 t = v;
|
||||
v = u;
|
||||
u = t;
|
||||
}
|
||||
v = v - u;
|
||||
} while(v != 0);
|
||||
return u << s;
|
||||
int s = 0;
|
||||
|
||||
while (((u | v) & 1) == 0) {
|
||||
s += 1;
|
||||
u >>= 1;
|
||||
v >>= 1;
|
||||
}
|
||||
while ((u & 1) == 0)
|
||||
u >>= 1;
|
||||
do {
|
||||
while ((v & 1) == 0)
|
||||
v >>= 1;
|
||||
if (u > v) {
|
||||
u32 t = v;
|
||||
|
||||
v = u;
|
||||
u = t;
|
||||
}
|
||||
v = v - u;
|
||||
} while (v != 0);
|
||||
|
||||
return (u << s);
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
@ -139,11 +144,11 @@ static int mod_SendChannelCommand(struct ddb *dev, u32 Channel, u32 Command)
|
||||
|
||||
ControlReg = (ControlReg & ~CHANNEL_CONTROL_CMD_MASK)|Command;
|
||||
ddbwritel(dev, ControlReg, CHANNEL_CONTROL(Channel));
|
||||
while(1) {
|
||||
while (1) {
|
||||
ControlReg = ddbreadl(dev, CHANNEL_CONTROL(Channel));
|
||||
if (ControlReg == 0xFFFFFFFF)
|
||||
return -EIO;
|
||||
if((ControlReg & CHANNEL_CONTROL_CMD_STATUS) == 0)
|
||||
if ((ControlReg & CHANNEL_CONTROL_CMD_STATUS) == 0)
|
||||
break;
|
||||
}
|
||||
if (ControlReg & CHANNEL_CONTROL_ERROR_CMD)
|
||||
@ -173,7 +178,8 @@ void ddbridge_mod_output_stop(struct ddb_output *output)
|
||||
mod->State = CM_IDLE;
|
||||
mod->Control &= 0xfffffff0;
|
||||
if (dev->link[0].info->version == 2)
|
||||
mod_SendChannelCommand(dev, output->nr, CHANNEL_CONTROL_CMD_FREE);
|
||||
mod_SendChannelCommand(dev, output->nr,
|
||||
CHANNEL_CONTROL_CMD_FREE);
|
||||
ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
|
||||
#if 0
|
||||
udelay(10);
|
||||
@ -263,7 +269,8 @@ static int mod_set_symbolrate(struct ddb_mod *mod, u32 srate)
|
||||
|
||||
static u32 qamtab[6] = { 0x000, 0x600, 0x601, 0x602, 0x903, 0x604 };
|
||||
|
||||
static int mod_set_modulation(struct ddb_mod *mod, enum fe_modulation modulation)
|
||||
static int mod_set_modulation(struct ddb_mod *mod,
|
||||
enum fe_modulation modulation)
|
||||
{
|
||||
struct ddb *dev = mod->port->dev;
|
||||
|
||||
@ -271,7 +278,8 @@ static int mod_set_modulation(struct ddb_mod *mod, enum fe_modulation modulation
|
||||
return -EINVAL;
|
||||
mod->modulation = modulation;
|
||||
if (dev->link[0].info->version < 2)
|
||||
ddbwritel(dev, qamtab[modulation], CHANNEL_SETTINGS(mod->port->nr));
|
||||
ddbwritel(dev, qamtab[modulation],
|
||||
CHANNEL_SETTINGS(mod->port->nr));
|
||||
mod_calc_obitrate(mod);
|
||||
return 0;
|
||||
}
|
||||
@ -326,23 +334,22 @@ int ddbridge_mod_output_start(struct ddb_output *output)
|
||||
mod->StateCounter = CM_STARTUP_DELAY;
|
||||
|
||||
if (dev->link[0].info->version == 3)
|
||||
mod->Control = 0xfffffff0 & ddbreadl(dev, CHANNEL_CONTROL(output->nr));
|
||||
mod->Control = 0xfffffff0 &
|
||||
ddbreadl(dev, CHANNEL_CONTROL(output->nr));
|
||||
else
|
||||
mod->Control = 0;
|
||||
ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
|
||||
udelay(10);
|
||||
ddbwritel(dev, mod->Control | CHANNEL_CONTROL_RESET, CHANNEL_CONTROL(output->nr));
|
||||
ddbwritel(dev, mod->Control | CHANNEL_CONTROL_RESET,
|
||||
CHANNEL_CONTROL(output->nr));
|
||||
udelay(10);
|
||||
ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
|
||||
|
||||
//pr_info("DDBridge: CHANNEL_BASE = %08x\n", CHANNEL_BASE);
|
||||
///pr_info("DDBridge: CHANNEL_CONTROL = %08x\n", CHANNEL_CONTROL(Channel));
|
||||
if (dev->link[0].info->version == 2) {
|
||||
//u32 Output = ((dev->mod_base.frequency - 114000000)/8000000 + Channel) % 96;
|
||||
u32 Output = (mod->frequency - 114000000) / 8000000;
|
||||
u32 KF = Symbolrate;
|
||||
u32 LF = 9000000UL;
|
||||
u32 d = gcd(KF,LF);
|
||||
u32 d = gcd(KF, LF);
|
||||
u32 checkLF;
|
||||
|
||||
ddbwritel(dev, mod->modulation - 1, CHANNEL_SETTINGS(Channel));
|
||||
@ -351,7 +358,7 @@ int ddbridge_mod_output_start(struct ddb_output *output)
|
||||
KF = KF / d;
|
||||
LF = LF / d;
|
||||
|
||||
while( (KF > KFLF_MAX) || (LF > KFLF_MAX) ) {
|
||||
while ((KF > KFLF_MAX) || (LF > KFLF_MAX)) {
|
||||
KF >>= 1;
|
||||
LF >>= 1;
|
||||
}
|
||||
@ -362,20 +369,25 @@ int ddbridge_mod_output_start(struct ddb_output *output)
|
||||
if (checkLF <= 1)
|
||||
return -EINVAL;
|
||||
|
||||
pr_info("DDBridge: KF=%u LF=%u Output=%u mod=%u\n", KF, LF, Output, mod->modulation);
|
||||
pr_info("DDBridge: KF=%u LF=%u Output=%u mod=%u\n",
|
||||
KF, LF, Output, mod->modulation);
|
||||
ddbwritel(dev, KF, CHANNEL_KF(Channel));
|
||||
ddbwritel(dev, LF, CHANNEL_LF(Channel));
|
||||
|
||||
if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_SETUP))
|
||||
if (mod_SendChannelCommand(dev, Channel,
|
||||
CHANNEL_CONTROL_CMD_SETUP))
|
||||
return -EINVAL;
|
||||
mod->Control |= CHANNEL_CONTROL_ENABLE_DVB;
|
||||
} else if (dev->link[0].info->version == 1) {
|
||||
} else if (dev->link[0].info->version == 1) {
|
||||
/* QAM: 600 601 602 903 604 = 16 32 64 128 256 */
|
||||
/* ddbwritel(dev, 0x604, CHANNEL_SETTINGS(output->nr)); */
|
||||
ddbwritel(dev, qamtab[mod->modulation], CHANNEL_SETTINGS(output->nr));
|
||||
mod->Control |= (CHANNEL_CONTROL_ENABLE_IQ | CHANNEL_CONTROL_ENABLE_DVB);
|
||||
ddbwritel(dev, qamtab[mod->modulation],
|
||||
CHANNEL_SETTINGS(output->nr));
|
||||
mod->Control |= (CHANNEL_CONTROL_ENABLE_IQ |
|
||||
CHANNEL_CONTROL_ENABLE_DVB);
|
||||
} else if (dev->link[0].info->version == 3) {
|
||||
mod->Control |= (CHANNEL_CONTROL_ENABLE_IQ | CHANNEL_CONTROL_ENABLE_DVB);
|
||||
mod->Control |= (CHANNEL_CONTROL_ENABLE_IQ |
|
||||
CHANNEL_CONTROL_ENABLE_DVB);
|
||||
}
|
||||
if (dev->link[0].info->version < 3) {
|
||||
mod_set_rateinc(dev, output->nr);
|
||||
@ -385,7 +397,8 @@ int ddbridge_mod_output_start(struct ddb_output *output)
|
||||
|
||||
ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
|
||||
if (dev->link[0].info->version == 2)
|
||||
if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_UNMUTE))
|
||||
if (mod_SendChannelCommand(dev, Channel,
|
||||
CHANNEL_CONTROL_CMD_UNMUTE))
|
||||
return -EINVAL;
|
||||
pr_info("DDBridge: mod_output_start %d.%d ctrl=%08x\n",
|
||||
dev->nr, output->nr, mod->Control);
|
||||
@ -399,9 +412,11 @@ int ddbridge_mod_output_start(struct ddb_output *output)
|
||||
static int mod_write_max2871(struct ddb *dev, u32 val)
|
||||
{
|
||||
ddbwritel(dev, val, MAX2871_OUTDATA);
|
||||
ddbwritel(dev, MAX2871_CONTROL_CE | MAX2871_CONTROL_WRITE, MAX2871_CONTROL);
|
||||
while(1) {
|
||||
ddbwritel(dev, MAX2871_CONTROL_CE | MAX2871_CONTROL_WRITE,
|
||||
MAX2871_CONTROL);
|
||||
while (1) {
|
||||
u32 ControlReg = ddbreadl(dev, MAX2871_CONTROL);
|
||||
|
||||
if (ControlReg == 0xFFFFFFFF)
|
||||
return -EIO;
|
||||
if ((ControlReg & MAX2871_CONTROL_WRITE) == 0)
|
||||
@ -430,7 +445,7 @@ static int mod_setup_max2871(struct ddb *dev, u32 *reg)
|
||||
for (j = 5; j >= 0; j--) {
|
||||
val = reg[j];
|
||||
|
||||
if (j ==4)
|
||||
if (j == 4)
|
||||
val &= 0xFFFFFEDF;
|
||||
status = mod_write_max2871(dev, reg[j]);
|
||||
if (status)
|
||||
@ -452,7 +467,8 @@ static int mod_setup_max2871(struct ddb *dev, u32 *reg)
|
||||
return status;
|
||||
}
|
||||
|
||||
static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels)
|
||||
static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan,
|
||||
u32 MaxUsedChannels)
|
||||
{
|
||||
int status = 0;
|
||||
u32 Capacity;
|
||||
@ -463,7 +479,7 @@ static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels
|
||||
if (status)
|
||||
return status;
|
||||
ddbwritel(dev, FSM_CMD_RESET, FSM_CONTROL);
|
||||
msleep(10);
|
||||
msleep(20);
|
||||
|
||||
tmp = ddbreadl(dev, FSM_STATUS);
|
||||
if ((tmp & FSM_STATUS_READY) == 0)
|
||||
@ -475,7 +491,7 @@ static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels
|
||||
return -EBUSY;
|
||||
|
||||
ddbwritel(dev, FSM_CMD_SETUP, FSM_CONTROL);
|
||||
msleep(10);
|
||||
msleep(20);
|
||||
tmp = ddbreadl(dev, FSM_STATUS);
|
||||
|
||||
if ((tmp & FSM_STATUS_QAMREADY) == 0)
|
||||
@ -485,7 +501,7 @@ static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels
|
||||
MaxUsedChannels = (Capacity & FSM_CAPACITY_CUR) >> 16;
|
||||
|
||||
pr_info("DDBridge: max used chan = %u\n", MaxUsedChannels);
|
||||
if (MaxUsedChannels <= 1 )
|
||||
if (MaxUsedChannels <= 1)
|
||||
ddbwritel(dev, FSM_GAIN_N1, FSM_GAIN);
|
||||
else if (MaxUsedChannels <= 2)
|
||||
ddbwritel(dev, FSM_GAIN_N2, FSM_GAIN);
|
||||
@ -507,84 +523,12 @@ static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels
|
||||
|
||||
static int mod_set_vga(struct ddb *dev, u32 Gain)
|
||||
{
|
||||
if( Gain > 255 )
|
||||
if (Gain > 255)
|
||||
return -EINVAL;
|
||||
ddbwritel(dev, Gain, RF_VGA);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if 0
|
||||
static int mod_get_vga(struct ddb *dev, u32 *pGain)
|
||||
{
|
||||
*pGain = ddbreadl(dev, RF_VGA);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void TemperatureMonitorSetFan(struct ddb *dev)
|
||||
{
|
||||
u32 tqam, pwm;
|
||||
|
||||
if ((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0) {
|
||||
pr_info("DDBridge: Over temperature condition\n");
|
||||
dev->OverTemperatureError = 1;
|
||||
}
|
||||
tqam = (ddbreadl(dev, TEMPMON2_QAMCORE) >> 8) & 0xFF;
|
||||
if (tqam & 0x80)
|
||||
tqam = 0;
|
||||
|
||||
pwm = (ddbreadl(dev, TEMPMON_FANCONTROL) >> 8) & 0x0F;
|
||||
if (pwm > 10)
|
||||
pwm = 10;
|
||||
|
||||
if (tqam >= dev->temp_tab[pwm]) {
|
||||
while( pwm < 10 && tqam >= dev->temp_tab[pwm + 1])
|
||||
pwm += 1;
|
||||
} else {
|
||||
while( pwm > 1 && tqam < dev->temp_tab[pwm - 2])
|
||||
pwm -= 1;
|
||||
}
|
||||
ddbwritel(dev, (pwm << 8), TEMPMON_FANCONTROL);
|
||||
}
|
||||
|
||||
|
||||
static void temp_handler(unsigned long data)
|
||||
{
|
||||
struct ddb *dev = (struct ddb *) data;
|
||||
|
||||
pr_info("DDBridge: temp_handler\n");
|
||||
|
||||
spin_lock(&dev->temp_lock);
|
||||
TemperatureMonitorSetFan(dev);
|
||||
spin_unlock(&dev->temp_lock);
|
||||
}
|
||||
|
||||
static int TemperatureMonitorInit(struct ddb *dev, int FirstTime) {
|
||||
int status = 0;
|
||||
|
||||
spin_lock_irq(&dev->temp_lock);
|
||||
if (FirstTime) {
|
||||
static u8 TemperatureTable[11] = {30,35,40,45,50,55,60,65,70,75,80};
|
||||
|
||||
memcpy(dev->temp_tab, TemperatureTable, sizeof(TemperatureTable));
|
||||
}
|
||||
dev->handler[0][8] = temp_handler;
|
||||
dev->handler_data[0][8] = (unsigned long) dev;
|
||||
ddbwritel(dev, (TEMPMON_CONTROL_OVERTEMP | TEMPMON_CONTROL_AUTOSCAN |
|
||||
TEMPMON_CONTROL_INTENABLE),
|
||||
TEMPMON_CONTROL);
|
||||
ddbwritel(dev, (3 << 8), TEMPMON_FANCONTROL);
|
||||
|
||||
dev->OverTemperatureError =
|
||||
((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0);
|
||||
if (dev->OverTemperatureError) {
|
||||
pr_info("DDBridge: Over temperature condition\n");
|
||||
status = -1;
|
||||
}
|
||||
TemperatureMonitorSetFan(dev);
|
||||
spin_unlock_irq(&dev->temp_lock);
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
/****************************************************************************/
|
||||
/****************************************************************************/
|
||||
/****************************************************************************/
|
||||
@ -749,7 +693,8 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
|
||||
((u32)(Data[1] & 0xE0) >> 6)) + 1;
|
||||
fDCO = fOut * (u64)(HSDiv * N);
|
||||
m_fXtal = fDCO << 28;
|
||||
pr_info("DDBridge: fxtal %016llx rfreq %016llx\n", m_fXtal, RFreq);
|
||||
pr_info("DDBridge: fxtal %016llx rfreq %016llx\n",
|
||||
m_fXtal, RFreq);
|
||||
|
||||
m_fXtal += RFreq >> 1;
|
||||
m_fXtal = div64_u64(m_fXtal, RFreq);
|
||||
@ -950,9 +895,9 @@ static int mod_init_dac_input(struct ddb *dev)
|
||||
Seek = 1;
|
||||
for (Sample = 0; Sample < 32; Sample += 1) {
|
||||
/* printk(" %2d: %d %2d %2d\n",
|
||||
Sample, SeekTable[Sample], SetTable[Sample],
|
||||
HldTable[Sample]);
|
||||
*/
|
||||
* Sample, SeekTable[Sample], SetTable[Sample],
|
||||
* HldTable[Sample]);
|
||||
*/
|
||||
|
||||
if (Sample1 == 0xFF && SeekTable[Sample] == 1 && Seek == 0)
|
||||
Sample1 = Sample;
|
||||
@ -1244,7 +1189,8 @@ static int mod_init_1(struct ddb *dev, u32 Frequency)
|
||||
FrequencyCH10 = flash->DataSet[0].FlatStart + 4;
|
||||
DownFrequency = Frequency + 9 * 8 + FrequencyCH10 +
|
||||
UP1Frequency + UP2Frequency;
|
||||
pr_info("DDBridge: CH10 = %d, Down = %d\n", FrequencyCH10, DownFrequency);
|
||||
pr_info("DDBridge: CH10 = %d, Down = %d\n",
|
||||
FrequencyCH10, DownFrequency);
|
||||
|
||||
if ((FrequencyCH10 + 9 * 8) > (flash->DataSet[0].FlatEnd - 4)) {
|
||||
pr_err("DDBridge: Frequency out of range %d\n", FrequencyCH10);
|
||||
@ -1296,10 +1242,10 @@ fail:
|
||||
#define FACTOR (1ULL << 22)
|
||||
|
||||
/*
|
||||
double Increment = FACTOR*PACKET_CLOCKS/double(m_OutputBitrate);
|
||||
double Decrement = FACTOR*PACKET_CLOCKS/double(m_InputBitrate);
|
||||
27000000 * 1504 * 2^22 / (6900000 * 188 / 204) = 26785190066.1
|
||||
*/
|
||||
* double Increment = FACTOR*PACKET_CLOCKS/double(m_OutputBitrate);
|
||||
* double Decrement = FACTOR*PACKET_CLOCKS/double(m_InputBitrate);
|
||||
* 27000000 * 1504 * 2^22 / (6900000 * 188 / 204) = 26785190066.1
|
||||
*/
|
||||
|
||||
void ddbridge_mod_rate_handler(unsigned long data)
|
||||
{
|
||||
@ -1493,7 +1439,7 @@ static int mod3_set_base_frequency(struct ddb *dev, u32 frequency)
|
||||
tmp = frequency;
|
||||
tmp <<= 33;
|
||||
tmp = div64_s64(tmp, 4915200000);
|
||||
printk("set base frequency = %u regs = 0x%08llx\n", frequency, tmp);
|
||||
pr_info("set base frequency = %u regs = 0x%08llx\n", frequency, tmp);
|
||||
ddbwritel(dev, (u32) tmp, RFDAC_FCW);
|
||||
return 0;
|
||||
}
|
||||
@ -1509,7 +1455,7 @@ static void mod3_set_cfcw(struct ddb_mod *mod, u32 f)
|
||||
tmp = ((s64) (freq - dcf)) << 32;
|
||||
tmp = div64_s64(tmp, srdac);
|
||||
cfcw = (u32) tmp;
|
||||
printk("f=%u cfcw = %08x nr = %u\n", f, cfcw, mod->port->nr);
|
||||
pr_info("f=%u cfcw = %08x nr = %u\n", f, cfcw, mod->port->nr);
|
||||
ddbwritel(dev, cfcw, SDR_CHANNEL_CFCW(mod->port->nr));
|
||||
}
|
||||
|
||||
@ -1542,7 +1488,7 @@ static int mod3_set_ari(struct ddb_mod *mod, u32 rate)
|
||||
|
||||
static int mod3_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
|
||||
{
|
||||
switch(tvp->cmd) {
|
||||
switch (tvp->cmd) {
|
||||
case MODULATOR_OUTPUT_ARI:
|
||||
return mod3_set_ari(mod, tvp->u.data);
|
||||
|
||||
@ -1559,7 +1505,7 @@ static int mod_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
|
||||
{
|
||||
if (mod->port->dev->link[0].info->version == 3)
|
||||
return mod3_prop_proc(mod, tvp);
|
||||
switch(tvp->cmd) {
|
||||
switch (tvp->cmd) {
|
||||
case MODULATOR_SYMBOL_RATE:
|
||||
return mod_set_symbolrate(mod, tvp->u.data);
|
||||
|
||||
@ -1592,14 +1538,16 @@ int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg)
|
||||
switch (cmd) {
|
||||
case FE_SET_PROPERTY:
|
||||
{
|
||||
struct dtv_properties *tvps = (struct dtv_properties __user *) parg;
|
||||
struct dtv_properties *tvps =
|
||||
(struct dtv_properties __user *) parg;
|
||||
struct dtv_property *tvp = NULL;
|
||||
int i;
|
||||
|
||||
if ((tvps->num == 0) || (tvps->num > DTV_IOCTL_MAX_MSGS))
|
||||
return -EINVAL;
|
||||
|
||||
tvp = kmalloc(tvps->num * sizeof(struct dtv_property), GFP_KERNEL);
|
||||
tvp = kmalloc(tvps->num * sizeof(struct dtv_property),
|
||||
GFP_KERNEL);
|
||||
if (!tvp) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
@ -1610,11 +1558,12 @@ int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg)
|
||||
goto out;
|
||||
}
|
||||
for (i = 0; i < tvps->num; i++) {
|
||||
if ((ret = mod_prop_proc(mod, tvp + i)) < 0)
|
||||
ret = mod_prop_proc(mod, tvp + i);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
(tvp + i)->result = ret;
|
||||
}
|
||||
out:
|
||||
out:
|
||||
kfree(tvp);
|
||||
return ret;
|
||||
}
|
||||
@ -1743,42 +1692,42 @@ static int rfdac_init(struct ddb *dev)
|
||||
|
||||
ddbwritel(dev, RFDAC_CMD_POWERDOWN, RFDAC_CONTROL);
|
||||
for (i = 0; i < 10; i++) {
|
||||
msleep(10);
|
||||
msleep(20);
|
||||
tmp = ddbreadl(dev, RFDAC_CONTROL);
|
||||
if ((tmp & RFDAC_CMD_STATUS) == 0x00)
|
||||
break;
|
||||
}
|
||||
if (tmp & 0x80)
|
||||
return -1;
|
||||
printk("sync %d:%08x\n", i, tmp);
|
||||
pr_info("sync %d:%08x\n", i, tmp);
|
||||
ddbwritel(dev, RFDAC_CMD_RESET, RFDAC_CONTROL);
|
||||
for (i = 0; i < 10; i++) {
|
||||
msleep(10);
|
||||
msleep(20);
|
||||
tmp = ddbreadl(dev, RFDAC_CONTROL);
|
||||
if ((tmp & RFDAC_CMD_STATUS) == 0x00)
|
||||
break;
|
||||
}
|
||||
if (tmp & 0x80)
|
||||
return -1;
|
||||
printk("sync %d:%08x\n", i, tmp);
|
||||
pr_info("sync %d:%08x\n", i, tmp);
|
||||
ddbwritel(dev, RFDAC_CMD_SETUP, RFDAC_CONTROL);
|
||||
for (i = 0; i < 10; i++) {
|
||||
msleep(10);
|
||||
msleep(20);
|
||||
tmp = ddbreadl(dev, RFDAC_CONTROL);
|
||||
if ((tmp & RFDAC_CMD_STATUS) == 0x00)
|
||||
break;
|
||||
}
|
||||
if (tmp & 0x80)
|
||||
return -1;
|
||||
printk("sync %d:%08x\n", i, tmp);
|
||||
ddbwritel(dev, 0x01, JESD204B_BASE);
|
||||
pr_info("sync %d:%08x\n", i, tmp);
|
||||
ddbwritel(dev, 0x01, JESD204B_BASE);
|
||||
for (i = 0; i < 400; i++) {
|
||||
msleep(10);
|
||||
msleep(20);
|
||||
tmp = ddbreadl(dev, JESD204B_BASE);
|
||||
if ((tmp & 0xc0000000) == 0xc0000000)
|
||||
break;
|
||||
}
|
||||
printk("sync %d:%08x\n", i, tmp);
|
||||
pr_info("sync %d:%08x\n", i, tmp);
|
||||
if ((tmp & 0xc0000000) != 0xc0000000)
|
||||
return -1;
|
||||
return 0;
|
||||
@ -1801,8 +1750,8 @@ static int mod_init_3(struct ddb *dev, u32 Frequency)
|
||||
|
||||
for (i = 0; i < streams; i++) {
|
||||
struct ddb_mod *mod = &dev->mod[i];
|
||||
mod->port = &dev->port[i];
|
||||
|
||||
mod->port = &dev->port[i];
|
||||
mod_set_sdr_table(mod, vsb13500, 64);
|
||||
mod_set_sdr_table(mod, stage2, 16);
|
||||
}
|
||||
|
||||
@ -87,7 +87,6 @@ static int ns_alloc(struct dvbnss *nss)
|
||||
dev->ns[i].fe = input;
|
||||
nss->priv = &dev->ns[i];
|
||||
ret = 0;
|
||||
/*pr_info("DDBridge: %s i=%d fe=%d\n", __func__, i, input->nr); */
|
||||
break;
|
||||
}
|
||||
ddbwritel(dev, 0x03, RTP_MASTER_CONTROL);
|
||||
@ -446,8 +445,6 @@ static int ns_start(struct dvbnss *nss)
|
||||
if (dns->fe != input)
|
||||
ddb_dvb_ns_input_start(dns->fe);
|
||||
ddb_dvb_ns_input_start(input);
|
||||
/* printk("ns start ns %u, fe %u link %u\n",
|
||||
dns->nr, dns->fe->nr, dns->fe->port->lnr); */
|
||||
ddbwritel(dev, reg | (dns->fe->nr << 8) | (dns->fe->port->lnr << 16),
|
||||
STREAM_CONTROL(dns->nr));
|
||||
return 0;
|
||||
|
||||
@ -58,9 +58,9 @@
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* Interrupt controller
|
||||
How many MSI's are available depends on HW (Min 2 max 8)
|
||||
How many are usable also depends on Host platform
|
||||
*/
|
||||
* How many MSI's are available depends on HW (Min 2 max 8)
|
||||
* How many are usable also depends on Host platform
|
||||
*/
|
||||
|
||||
#define INTERRUPT_BASE (0x40)
|
||||
|
||||
@ -167,13 +167,15 @@
|
||||
#define TEMPMON_FANPWM (0x00000F00) // PWM speed in 10% steps
|
||||
#define TEMPMON_FANTACHO (0x000000FF) // Rotations in 100/min steps
|
||||
|
||||
// V1 Temperature Monitor
|
||||
// Temperature Monitor TEMPMON_CONTROL & 0x8000 == 0 : ( 2x LM75A @ 0x90,0x92 )
|
||||
// Temperature Monitor TEMPMON_CONTROL & 0x8000 == 1 : ( 1x LM75A @ 0x90, 1x ADM1032 @ 0x9A )
|
||||
/* V1 Temperature Monitor
|
||||
* Temperature Monitor TEMPMON_CONTROL & 0x8000 == 0 : ( 2x LM75A @ 0x90,0x92 )
|
||||
* Temperature Monitor TEMPMON_CONTROL & 0x8000 == 1 :
|
||||
* ( 1x LM75A @ 0x90, 1x ADM1032 @ 0x9A )
|
||||
*/
|
||||
|
||||
#define TEMPMON1_CORE (TEMPMON_SENSOR0) // SHORT Temperature in °C x 256 (ADM1032 ext)
|
||||
#define TEMPMON1_SENSOR1 (TEMPMON_BASE + 0x08) // SHORT Temperature in °C x 256 (LM75A 0x90)
|
||||
#define TEMPMON1_SENSOR2 (TEMPMON_BASE + 0x0C) // SHORT Temperature in °C x 256 (LM75A 0x92 or ADM1032 Int)
|
||||
#define TEMPMON1_CORE (TEMPMON_SENSOR0) // u16 Temperature in °C x 256 (ADM1032 ext)
|
||||
#define TEMPMON1_SENSOR1 (TEMPMON_BASE + 0x08) // SHORT Temperature in °C x 256 (LM75A 0x90)
|
||||
#define TEMPMON1_SENSOR2 (TEMPMON_BASE + 0x0C) // SHORT Temperature in °C x 256 (LM75A 0x92 or ADM1032 Int)
|
||||
|
||||
// V2 Temperature Monitor 2 ADM1032
|
||||
|
||||
@ -332,12 +334,12 @@
|
||||
/* Muxout from VCO (usually = Lock) */
|
||||
#define VCO3_CONTROL_MUXOUT (0x00000004)
|
||||
|
||||
// V2
|
||||
/* V2 */
|
||||
|
||||
#define MAX2871_BASE (0xC0)
|
||||
#define MAX2871_CONTROL (MAX2871_BASE + 0x00)
|
||||
#define MAX2871_OUTDATA (MAX2871_BASE + 0x04) // 32 Bit
|
||||
#define MAX2871_INDATA (MAX2871_BASE + 0x08) // 32 Bit
|
||||
#define MAX2871_OUTDATA (MAX2871_BASE + 0x04)
|
||||
#define MAX2871_INDATA (MAX2871_BASE + 0x08)
|
||||
#define MAX2871_CONTROL_WRITE (0x00000001) // 1 = Trigger write, resets when done
|
||||
#define MAX2871_CONTROL_CE (0x00000002) // 0 = Put VCO into power down
|
||||
#define MAX2871_CONTROL_MUXOUT (0x00000004) // Muxout from VCO
|
||||
@ -381,10 +383,10 @@
|
||||
#define RF_ATTENUATOR (0xD8)
|
||||
#define RF_ATTENUATOR (0xD8)
|
||||
/* 0x00 = 0 dB
|
||||
0x01 = 1 dB
|
||||
...
|
||||
0x1F = 31 dB
|
||||
*/
|
||||
* 0x01 = 1 dB
|
||||
* ...
|
||||
* 0x1F = 31 dB
|
||||
*/
|
||||
|
||||
#define RF_VGA (0xDC)
|
||||
/* Only V2 */
|
||||
@ -411,9 +413,9 @@
|
||||
#define RF_POWER_CONTROL_VALID (0x00000500)
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------------
|
||||
Output control
|
||||
*/
|
||||
/*
|
||||
* Output control
|
||||
*/
|
||||
|
||||
#define IQOUTPUT_BASE (0x240)
|
||||
#define IQOUTPUT_CONTROL (IQOUTPUT_BASE + 0x00)
|
||||
@ -581,7 +583,7 @@
|
||||
|
||||
// Additional Status Bits
|
||||
|
||||
#define DMA_PCIE_LANES_MASK ( 0x00070000 )
|
||||
#define DMA_PCIE_LANES_MASK (0x00070000)
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
@ -619,7 +621,7 @@
|
||||
#define SDR_FIR_SELECT_MASK (0x00C00000)
|
||||
#define SDR_VSB_LENGTH_MASK (0x01000000)
|
||||
|
||||
#define SDR_SET_FIR(select,tap,coeff,vsblen) \
|
||||
#define SDR_SET_FIR(select, tap, coeff, vsblen) \
|
||||
((((select)<<22)&SDR_FIR_SELECT_MASK)| \
|
||||
(((tap)<<16)&SDR_FIR_TAP_MASK)| \
|
||||
((coeff)&SDR_FIR_COEFF_MASK)| \
|
||||
|
||||
@ -191,7 +191,8 @@ struct ddb_info {
|
||||
};
|
||||
|
||||
/* DMA_SIZE MUST be smaller than 256k and
|
||||
MUST be divisible by 188 and 128 !!! */
|
||||
* MUST be divisible by 188 and 128 !!!
|
||||
*/
|
||||
|
||||
#define DMA_MAX_BUFS 32 /* hardware table limit */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user