18 Commits

Author	SHA1	Message	Date
Ralph Metzler	c831ccfc9e	add check for minimum FPGA firmware version	2018-05-02 15:39:09 +02:00
Ralph Metzler	3db30defab	use correct MODULE_LINCESE for GPL v2 only according to notice in header	2018-03-22 19:32:17 +01:00
Ralph Metzler	dedb5bd387	fixes for 3.x kernels	2018-03-02 10:46:28 +01:00
Ralph Metzler	ae9644d934	set devid entry for link 0	2018-02-12 22:43:45 +01:00
Ralph Metzler	e19f29dbfa	fix MSI handling for older kernels	2018-01-16 23:54:51 +01:00
Ralph Metzler	ea09ce3b7b	add device id 9 for MaxSX8 type cards	2017-12-05 19:26:26 +01:00
Ralph Metzler	e239a6d772	move common workqueue and class init/exit to core	2017-10-22 20:58:58 +02:00
Ralph Metzler	3a2e87eefe	add MSI-X support	2017-10-22 19:55:07 +02:00
mvoelkel	f84d196a1e	compiling for kernel 4.12.x	2017-09-25 19:20:17 +02:00
Ralph Metzler	0dd0997133	change FSM card channel number detection to use register 0x1c	2017-09-10 22:25:02 +02:00
Ralph Metzler	fe5f6b737c	convert all device information structs to const and fix related problems	2017-09-08 14:47:14 +02:00
Ralph Metzler	07f7720145	prefix irq handlers with ddb_ to avoid name collisions	2017-08-27 21:42:02 +02:00
Ralph Metzler	b2ca06e639	strict checkpatch style fixes	2017-08-26 22:04:37 +02:00
Ralph Metzler	2b6babfdc0	coding style fixes according to checkpatch	2017-08-26 10:32:53 +02:00
Ralph Metzler	5074e28e10	change output functions from pr_ to dev_	2017-08-25 23:30:58 +02:00
Ralph Metzler	7602ecf3e5	fixed regression for FSM modulators	2017-08-04 17:50:03 +02:00
Ralph Metzler	bf0315bcc0	move io functions to ddbridge-io.[ch]	2017-08-02 20:22:52 +02:00
Ralph Metzler	dcddb3437d	compile parts of ddbridge and octonet seperately	2017-08-02 17:40:24 +02:00