mirror of
https://github.com/DigitalDevices/dddvb.git
synced 2025-03-01 10:35:23 +00:00
Compare commits
22 Commits
Author | SHA1 | Date | |
---|---|---|---|
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faee02e446 | ||
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6d80791077 | ||
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1d3bb91eb8 | ||
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c18503fcad | ||
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906efafd5e | ||
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b479d9cdc2 | ||
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6038e87250 | ||
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1b0e822b07 | ||
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cdaf838cb1 | ||
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19fd6f1b26 | ||
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472cacb0c4 | ||
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fa66a70a35 | ||
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b5a44d581d | ||
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e8eaf4660c | ||
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81966f8982 | ||
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dd540699c3 | ||
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a8ed36fef2 | ||
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9ab1b7f533 | ||
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197897731e | ||
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781686c87d | ||
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b354113d15 | ||
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8d0bb02239 |
@@ -17,3 +17,4 @@ octonet: octonet.c
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||||
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octokey: octokey.c
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$(CC) -o octokey octokey.c
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@@ -91,6 +91,8 @@ enum {
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SSTI_SST25VF032B = 3,
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SSTI_SST25VF064C = 4,
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SPANSION_S25FL116K = 5,
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SPANSION_S25FL132K = 6,
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SPANSION_S25FL164K = 7,
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};
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static int flashread(int ddb, uint8_t *buf, uint32_t addr, uint32_t len)
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@@ -393,6 +395,8 @@ static int flashwrite(struct ddflash *ddf, int fs, uint32_t addr, uint32_t maxle
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case SSTI_SST25VF064C:
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return flashwrite_pagemode(ddf, fs, addr, 0x3c, fw_off);
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case SPANSION_S25FL116K:
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case SPANSION_S25FL132K:
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case SPANSION_S25FL164K:
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return flashwrite_pagemode(ddf, fs, addr, 0x1c, fw_off);
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}
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return -1;
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@@ -467,6 +471,16 @@ static int flash_detect(struct ddflash *ddf)
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printf("Flash: SPANSION S25FL116K 16 MBit\n");
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ddf->sector_size = 4096;
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ddf->size = 0x200000;
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} else if (id[0] == 0x01 && id[1] == 0x40 && id[2] == 0x16) {
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ddf->flash_type = SPANSION_S25FL132K;
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printf("Flash: SPANSION S25FL132K 32 MBit\n");
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ddf->sector_size = 4096;
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ddf->size = 0x400000;
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} else if (id[0] == 0x01 && id[1] == 0x40 && id[2] == 0x17) {
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ddf->flash_type = SPANSION_S25FL164K;
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printf("Flash: SPANSION S25FL164K 64 MBit\n");
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ddf->sector_size = 4096;
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ddf->size = 0x800000;
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} else if (id[0] == 0x1F && id[1] == 0x28) {
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ddf->flash_type = ATMEL_AT45DB642D;
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printf("Flash: Atmel AT45DB642D 64 MBit\n");
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|
File diff suppressed because it is too large
Load Diff
@@ -1,8 +1,8 @@
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EXTRA_CFLAGS += -DCONFIG_DVB_CXD2843 -DCONFIG_DVB_LNBP21 -DCONFIG_DVB_STV090x -DCONFIG_DVB_STV6110x -DCONFIG_DVB_DRXK -DCONFIG_DVB_STV0910 -DCONFIG_DVB_STV6111 -DCONFIG_DVB_LNBH25 -DCONFIG_DVB_MXL5XX
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obj-$(CONFIG_DVB_DDBRIDGE) += ddbridge.o
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obj-$(CONFIG_DVB_OCTONET) += octonet.o
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obj-$(CONFIG_DVB_DDBRIDGE) += ddbridge.o
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obj-$(CONFIG_DVB_OCTONET) += octonet.o
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EXTRA_CFLAGS += -Idrivers/media/dvb/frontends -Idrivers/media/dvb-frontends
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EXTRA_CFLAGS += -Idrivers/media/common/tuners
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NOSTDINC_FLAGS += -I$(SUBDIRS)/frontends -I$(SUBDIRS)/include -I$(SUBDIRS)/dvb-core
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EXTRA_CFLAGS += -Idrivers/media/common/tuners
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NOSTDINC_FLAGS += -I$(SUBDIRS)/frontends -I$(SUBDIRS)/include -I$(SUBDIRS)/dvb-core
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@@ -1,9 +1,9 @@
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KDIR ?= /lib/modules/$(shell uname -r)/build
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PWD := $(shell pwd)
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MODDEFS := CONFIG_DVB_DDBRIDGE=m
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MODDEFS := CONFIG_DVB_DDBRIDGE=m
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all:
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all:
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$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) $(MODDEFS) modules
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$(MAKE) -C apps
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|
@@ -4,7 +4,7 @@
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* Copyright (C) 2010-2015 Digital Devices GmbH
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* Marcus Metzler <mocm@metzlerbros.de>
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* Ralph Metzler <rjkm@metzlerbros.de>
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*
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*
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
|
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@@ -213,7 +213,7 @@ static void dma_free(struct pci_dev *pdev, struct ddb_dma *dma, int dir)
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dir ? DMA_TO_DEVICE :
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DMA_FROM_DEVICE);
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kfree(dma->vbuf[i]);
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dma->vbuf[i] = 0;
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dma->vbuf[i] = NULL;
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}
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}
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}
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@@ -255,7 +255,7 @@ static void dma_free(struct pci_dev *pdev, struct ddb_dma *dma, int dir)
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#else
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dma_free_coherent(&pdev->dev, dma->size,
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dma->vbuf[i], dma->pbuf[i]);
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#endif
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#endif
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dma->vbuf[i] = 0;
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}
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}
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@@ -292,20 +292,24 @@ static int ddb_buffers_alloc(struct ddb *dev)
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switch (port->class) {
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case DDB_PORT_TUNER:
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if (port->input[0]->dma)
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if (dma_alloc(dev->pdev, port->input[0]->dma, 0) < 0)
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if (dma_alloc(dev->pdev,
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port->input[0]->dma, 0) < 0)
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return -1;
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if (port->input[1]->dma)
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if (dma_alloc(dev->pdev, port->input[1]->dma, 0) < 0)
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if (dma_alloc(dev->pdev,
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port->input[1]->dma, 0) < 0)
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return -1;
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break;
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case DDB_PORT_CI:
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case DDB_PORT_LOOP:
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if (port->input[0]->dma)
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if (dma_alloc(dev->pdev, port->input[0]->dma, 0) < 0)
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if (dma_alloc(dev->pdev,
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port->input[0]->dma, 0) < 0)
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return -1;
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case DDB_PORT_MOD:
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if (port->output->dma)
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if (dma_alloc(dev->pdev, port->output->dma, 1) < 0)
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if (dma_alloc(dev->pdev,
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port->output->dma, 1) < 0)
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return -1;
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break;
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default:
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@@ -410,7 +414,8 @@ static void ddb_input_stop(struct ddb_input *input)
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input->dma->running = 0;
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spin_unlock_irq(&input->dma->lock);
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}
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//printk("input_stop %u.%u.%u\n", dev->nr, input->port->lnr, input->nr);
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/*printk("input_stop %u.%u.%u\n",
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dev->nr, input->port->lnr, input->nr);*/
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}
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static void ddb_input_start(struct ddb_input *input)
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@@ -446,7 +451,8 @@ static void ddb_input_start(struct ddb_input *input)
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input->dma->running = 1;
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spin_unlock_irq(&input->dma->lock);
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}
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//printk("input_start %u.%u.%u\n", dev->nr, input->port->lnr, input->nr);
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/*printk("input_start %u.%u.%u\n",
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dev->nr, input->port->lnr, input->nr); */
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}
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@@ -543,7 +549,7 @@ static u32 ddb_dma_free(struct ddb_dma *dma)
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#endif
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static ssize_t ddb_output_write(struct ddb_output *output,
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const u8 *buf, size_t count)
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const __user u8 *buf, size_t count)
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{
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struct ddb *dev = output->port->dev;
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u32 idx, off, stat = output->dma->stat;
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@@ -691,7 +697,8 @@ static u32 ddb_input_avail(struct ddb_input *input)
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return 0;
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}
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static size_t ddb_input_read(struct ddb_input *input, u8 *buf, size_t count)
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static size_t ddb_input_read(struct ddb_input *input,
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__user u8 *buf, size_t count)
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{
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struct ddb *dev = input->port->dev;
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u32 left = count;
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@@ -762,7 +769,7 @@ static ssize_t ts_write(struct file *file, const char *buf,
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return (left == count) ? -EAGAIN : (count - left);
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}
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static ssize_t ts_read(struct file *file, char *buf,
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static ssize_t ts_read(struct file *file, __user char *buf,
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size_t count, loff_t *ppos)
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{
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struct dvb_device *dvbdev = file->private_data;
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@@ -1033,7 +1040,7 @@ static int demod_attach_stv0367dd(struct ddb_input *input)
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struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
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struct dvb_frontend *fe;
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struct stv0367_cfg cfg = { .cont_clock = 0 };
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cfg.adr = 0x1f - (input->nr & 1);
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if (input->port->dev->link[input->port->lnr].info->con_clock)
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cfg.cont_clock = 1;
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@@ -1282,11 +1289,11 @@ static int lnb_command(struct ddb *dev, u32 link, u32 lnb, u32 cmd)
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u32 c, v = 0, tag = DDB_LINK_TAG(link);
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v = LNB_TONE & (dev->link[link].lnb.tone << (15 - lnb));
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//pr_info("lnb_control[%u] = %08x\n", lnb, cmd | v);
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/*pr_info("lnb_control[%u] = %08x\n", lnb, cmd | v);*/
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ddbwritel(dev, cmd | v, tag | LNB_CONTROL(lnb));
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for (c = 0; c < 10; c++) {
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v = ddbreadl(dev, tag | LNB_CONTROL(lnb));
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//pr_info("ctrl = %08x\n", v);
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/*pr_info("ctrl = %08x\n", v);*/
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if ((v & LNB_BUSY) == 0)
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break;
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msleep(20);
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@@ -1306,7 +1313,7 @@ static int max_send_master_cmd(struct dvb_frontend *fe,
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u32 tag = DDB_LINK_TAG(port->lnr);
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int i;
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u32 fmode = dev->link[port->lnr].lnb.fmode;
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if (fmode == 2 || fmode == 1)
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return 0;
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if (dvb->diseqc_send_master_cmd)
|
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@@ -1321,11 +1328,12 @@ static int max_send_master_cmd(struct dvb_frontend *fe,
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return 0;
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}
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static int lnb_set_tone(struct ddb *dev, u32 link, u32 input, fe_sec_tone_mode_t tone)
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static int lnb_set_tone(struct ddb *dev, u32 link, u32 input,
|
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fe_sec_tone_mode_t tone)
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{
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int s = 0;
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u32 mask = (1ULL << input);
|
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|
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u32 mask = (1ULL << input);
|
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|
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switch (tone) {
|
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case SEC_TONE_OFF:
|
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if (!(dev->link[link].lnb.tone & mask))
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@@ -1346,7 +1354,8 @@ static int lnb_set_tone(struct ddb *dev, u32 link, u32 input, fe_sec_tone_mode_t
|
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return s;
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}
|
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|
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static int lnb_set_voltage(struct ddb *dev, u32 link, u32 input, fe_sec_voltage_t voltage)
|
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static int lnb_set_voltage(struct ddb *dev, u32 link, u32 input,
|
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fe_sec_voltage_t voltage)
|
||||
{
|
||||
int s = 0;
|
||||
|
||||
@@ -1379,13 +1388,13 @@ static int max_set_input_unlocked(struct dvb_frontend *fe, int in)
|
||||
struct ddb *dev = port->dev;
|
||||
struct ddb_dvb *dvb = &port->dvb[input->nr & 1];
|
||||
int res = 0;
|
||||
|
||||
|
||||
if (in > 3)
|
||||
return -EINVAL;
|
||||
if (dvb->input != in) {
|
||||
u32 bit = (1ULL << input->nr);
|
||||
u32 obit = dev->link[port->lnr].lnb.voltage[dvb->input] & bit;
|
||||
|
||||
|
||||
dev->link[port->lnr].lnb.voltage[dvb->input] &= ~bit;
|
||||
dvb->input = in;
|
||||
dev->link[port->lnr].lnb.voltage[dvb->input] |= obit;
|
||||
@@ -1401,7 +1410,7 @@ static int max_set_input(struct dvb_frontend *fe, int in)
|
||||
struct ddb *dev = input->port->dev;
|
||||
int res;
|
||||
|
||||
mutex_lock(&dev->link[port->lnr].lnb.lock);
|
||||
mutex_lock(&dev->link[port->lnr].lnb.lock);
|
||||
res = max_set_input_unlocked(fe, in);
|
||||
mutex_unlock(&dev->link[port->lnr].lnb.lock);
|
||||
return res;
|
||||
@@ -1416,8 +1425,8 @@ static int max_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
|
||||
int tuner = 0;
|
||||
int res = 0;
|
||||
u32 fmode = dev->link[port->lnr].lnb.fmode;
|
||||
|
||||
mutex_lock(&dev->link[port->lnr].lnb.lock);
|
||||
|
||||
mutex_lock(&dev->link[port->lnr].lnb.lock);
|
||||
dvb->tone = tone;
|
||||
switch (fmode) {
|
||||
default:
|
||||
@@ -1455,31 +1464,35 @@ static int max_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
|
||||
u32 nv, ov = dev->link[port->lnr].lnb.voltages;
|
||||
int res = 0;
|
||||
u32 fmode = dev->link[port->lnr].lnb.fmode;
|
||||
|
||||
|
||||
mutex_lock(&dev->link[port->lnr].lnb.lock);
|
||||
dvb->voltage = voltage;
|
||||
|
||||
|
||||
switch (fmode) {
|
||||
case 3:
|
||||
default:
|
||||
case 0:
|
||||
if (fmode == 3)
|
||||
max_set_input_unlocked(fe, 0);
|
||||
if (voltage == SEC_VOLTAGE_OFF)
|
||||
dev->link[port->lnr].lnb.voltage[dvb->input] &= ~(1ULL << input->nr);
|
||||
else
|
||||
dev->link[port->lnr].lnb.voltage[dvb->input] |= (1ULL << input->nr);
|
||||
|
||||
if (voltage == SEC_VOLTAGE_OFF)
|
||||
dev->link[port->lnr].lnb.voltage[dvb->input] &=
|
||||
~(1ULL << input->nr);
|
||||
else
|
||||
dev->link[port->lnr].lnb.voltage[dvb->input] |=
|
||||
(1ULL << input->nr);
|
||||
|
||||
res = lnb_set_voltage(dev, port->lnr, dvb->input, voltage);
|
||||
break;
|
||||
case 1:
|
||||
case 2:
|
||||
if (voltage == SEC_VOLTAGE_OFF)
|
||||
dev->link[port->lnr].lnb.voltages &= ~(1ULL << input->nr);
|
||||
if (voltage == SEC_VOLTAGE_OFF)
|
||||
dev->link[port->lnr].lnb.voltages &=
|
||||
~(1ULL << input->nr);
|
||||
else
|
||||
dev->link[port->lnr].lnb.voltages |= (1ULL << input->nr);
|
||||
dev->link[port->lnr].lnb.voltages |=
|
||||
(1ULL << input->nr);
|
||||
nv = dev->link[port->lnr].lnb.voltages;
|
||||
|
||||
|
||||
if (old_quattro) {
|
||||
if (dvb->tone == SEC_TONE_ON)
|
||||
tuner |= 2;
|
||||
@@ -1492,27 +1505,42 @@ static int max_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
|
||||
tuner |= 2;
|
||||
}
|
||||
res = max_set_input_unlocked(fe, tuner);
|
||||
|
||||
|
||||
if (nv != ov) {
|
||||
if (nv) {
|
||||
lnb_set_voltage(dev, port->lnr, 0, SEC_VOLTAGE_13);
|
||||
lnb_set_voltage(dev, port->lnr, 0,
|
||||
SEC_VOLTAGE_13);
|
||||
if (fmode == 1) {
|
||||
lnb_set_voltage(dev, port->lnr, 0, SEC_VOLTAGE_13);
|
||||
lnb_set_voltage(dev, port->lnr, 0,
|
||||
SEC_VOLTAGE_13);
|
||||
if (old_quattro) {
|
||||
lnb_set_voltage(dev, port->lnr, 1, SEC_VOLTAGE_18);
|
||||
lnb_set_voltage(dev, port->lnr, 2, SEC_VOLTAGE_13);
|
||||
lnb_set_voltage(dev,
|
||||
port->lnr, 1,
|
||||
SEC_VOLTAGE_18);
|
||||
lnb_set_voltage(dev, port->lnr,
|
||||
2,
|
||||
SEC_VOLTAGE_13);
|
||||
} else {
|
||||
lnb_set_voltage(dev, port->lnr, 1, SEC_VOLTAGE_13);
|
||||
lnb_set_voltage(dev, port->lnr, 2, SEC_VOLTAGE_18);
|
||||
lnb_set_voltage(dev, port->lnr,
|
||||
1,
|
||||
SEC_VOLTAGE_13);
|
||||
lnb_set_voltage(dev, port->lnr,
|
||||
2,
|
||||
SEC_VOLTAGE_18);
|
||||
}
|
||||
lnb_set_voltage(dev, port->lnr, 3, SEC_VOLTAGE_18);
|
||||
lnb_set_voltage(dev, port->lnr, 3,
|
||||
SEC_VOLTAGE_18);
|
||||
}
|
||||
} else {
|
||||
lnb_set_voltage(dev, port->lnr, 0, SEC_VOLTAGE_OFF);
|
||||
lnb_set_voltage(dev, port->lnr,
|
||||
0, SEC_VOLTAGE_OFF);
|
||||
if (fmode == 1) {
|
||||
lnb_set_voltage(dev, port->lnr, 1, SEC_VOLTAGE_OFF);
|
||||
lnb_set_voltage(dev, port->lnr, 2, SEC_VOLTAGE_OFF);
|
||||
lnb_set_voltage(dev, port->lnr, 3, SEC_VOLTAGE_OFF);
|
||||
lnb_set_voltage(dev, port->lnr, 1,
|
||||
SEC_VOLTAGE_OFF);
|
||||
lnb_set_voltage(dev, port->lnr, 2,
|
||||
SEC_VOLTAGE_OFF);
|
||||
lnb_set_voltage(dev, port->lnr, 3,
|
||||
SEC_VOLTAGE_OFF);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1539,7 +1567,7 @@ static int mxl_fw_read(void *priv, u8 *buf, u32 len)
|
||||
struct ddb *dev = link->dev;
|
||||
|
||||
pr_info("Read mxl_fw from link %u\n", link->nr);
|
||||
|
||||
|
||||
return ddbridge_flashread(dev, link->nr, buf, 0xc0000, len);
|
||||
}
|
||||
|
||||
@@ -1589,7 +1617,7 @@ static int fe_attach_mxl5xx(struct ddb_input *input)
|
||||
cfg = mxl5xx;
|
||||
cfg.fw_priv = link;
|
||||
if (dev->link[0].info->type == DDB_OCTONET)
|
||||
;//cfg.ts_clk = 69;
|
||||
;/*cfg.ts_clk = 69;*/
|
||||
|
||||
demod = input->nr;
|
||||
tuner = demod & 3;
|
||||
@@ -1855,7 +1883,7 @@ static int dvb_input_attach(struct ddb_input *input)
|
||||
struct dvb_adapter *adap = dvb->adap;
|
||||
struct dvb_demux *dvbdemux = &dvb->demux;
|
||||
int par = 0;
|
||||
|
||||
|
||||
dvb->attached = 0x01;
|
||||
|
||||
ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
|
||||
@@ -1884,7 +1912,7 @@ static int dvb_input_attach(struct ddb_input *input)
|
||||
return ret;
|
||||
dvb->attached = 0x21;
|
||||
}
|
||||
dvb->fe = dvb->fe2 = 0;
|
||||
dvb->fe = dvb->fe2 = NULL;
|
||||
switch (port->type) {
|
||||
case DDB_TUNER_MXL5XX:
|
||||
if (fe_attach_mxl5xx(input) < 0)
|
||||
@@ -1937,7 +1965,8 @@ static int dvb_input_attach(struct ddb_input *input)
|
||||
case DDB_TUNER_DVBCT2_SONY_P:
|
||||
case DDB_TUNER_DVBC2T2_SONY_P:
|
||||
case DDB_TUNER_ISDBT_SONY_P:
|
||||
if (input->port->dev->link[input->port->lnr].info->ts_quirks & TS_QUIRK_SERIAL)
|
||||
if (input->port->dev->link[input->port->lnr].info->ts_quirks &
|
||||
TS_QUIRK_SERIAL)
|
||||
par = 0;
|
||||
else
|
||||
par = 1;
|
||||
@@ -2100,7 +2129,7 @@ static int init_xo2(struct ddb_port *port)
|
||||
}
|
||||
|
||||
usleep_range(2000, 3000);
|
||||
/* Start XO2 PLL */
|
||||
/* Start XO2 PLL */
|
||||
i2c_write_reg(i2c, 0x10, 0x08, 0x87);
|
||||
|
||||
return 0;
|
||||
@@ -2189,13 +2218,13 @@ static void ddb_port_probe(struct ddb_port *port)
|
||||
port->class = DDB_PORT_NONE;
|
||||
|
||||
/* Handle missing ports and ports without I2C */
|
||||
|
||||
|
||||
if (port->nr == ts_loop) {
|
||||
port->name = "TS LOOP";
|
||||
port->class = DDB_PORT_LOOP;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if (port->nr == 1 && dev->link[l].info->type == DDB_OCTOPUS_CI &&
|
||||
dev->link[l].info->i2c_mask == 1) {
|
||||
port->name = "NO TAB";
|
||||
@@ -2231,7 +2260,7 @@ static void ddb_port_probe(struct ddb_port *port)
|
||||
return;
|
||||
|
||||
/* Probe ports with I2C */
|
||||
|
||||
|
||||
if (port_has_cxd(port, &id)) {
|
||||
if (id == 1) {
|
||||
port->name = "CI";
|
||||
@@ -2325,7 +2354,7 @@ static void ddb_port_probe(struct ddb_port *port)
|
||||
} else if (port_has_encti(port)) {
|
||||
port->name = "ENCTI";
|
||||
port->class = DDB_PORT_LOOP;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -2489,7 +2518,7 @@ static int write_creg(struct ddb_ci *ci, u8 data, u8 mask)
|
||||
{
|
||||
struct i2c_adapter *i2c = &ci->port->i2c->adap;
|
||||
u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
|
||||
|
||||
|
||||
ci->port->creg = (ci->port->creg & ~mask) | data;
|
||||
return i2c_write_reg(i2c, adr, 0x02, ci->port->creg);
|
||||
}
|
||||
@@ -2502,7 +2531,7 @@ static int read_attribute_mem_xo2(struct dvb_ca_en50221 *ca,
|
||||
u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
|
||||
int res;
|
||||
u8 val;
|
||||
|
||||
|
||||
res = i2c_read_reg16(i2c, adr, 0x8000 | address, &val);
|
||||
return res ? res : val;
|
||||
}
|
||||
@@ -2525,7 +2554,7 @@ static int read_cam_control_xo2(struct dvb_ca_en50221 *ca,
|
||||
u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
|
||||
u8 val;
|
||||
int res;
|
||||
|
||||
|
||||
res = i2c_read_reg(i2c, adr, 0x20 | (address & 3), &val);
|
||||
return res ? res : val;
|
||||
}
|
||||
@@ -2536,7 +2565,7 @@ static int write_cam_control_xo2(struct dvb_ca_en50221 *ca, int slot,
|
||||
struct ddb_ci *ci = ca->data;
|
||||
struct i2c_adapter *i2c = &ci->port->i2c->adap;
|
||||
u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
|
||||
|
||||
|
||||
return i2c_write_reg(i2c, adr, 0x20 | (address & 3), value);
|
||||
}
|
||||
|
||||
@@ -2557,10 +2586,10 @@ static int slot_reset_xo2(struct dvb_ca_en50221 *ca, int slot)
|
||||
static int slot_shutdown_xo2(struct dvb_ca_en50221 *ca, int slot)
|
||||
{
|
||||
struct ddb_ci *ci = ca->data;
|
||||
|
||||
|
||||
pr_info("%s\n", __func__);
|
||||
//i2c_write_reg(i2c, adr, 0x03, 0x60);
|
||||
//i2c_write_reg(i2c, adr, 0x00, 0xc0);
|
||||
/*i2c_write_reg(i2c, adr, 0x03, 0x60);*/
|
||||
/*i2c_write_reg(i2c, adr, 0x00, 0xc0);*/
|
||||
write_creg(ci, 0x10, 0xff);
|
||||
write_creg(ci, 0x08, 0x08);
|
||||
return 0;
|
||||
@@ -2584,8 +2613,7 @@ static int poll_slot_status_xo2(struct dvb_ca_en50221 *ca, int slot, int open)
|
||||
int stat = 0;
|
||||
|
||||
i2c_read_reg(i2c, adr, 0x01, &val);
|
||||
//pr_info("%s %02x\n", __func__, val);
|
||||
|
||||
|
||||
if (val & 2)
|
||||
stat |= DVB_CA_EN50221_POLL_CAM_PRESENT;
|
||||
if (val & 1)
|
||||
@@ -2753,7 +2781,7 @@ static void ddb_ports_detach(struct ddb *dev)
|
||||
if (port->en) {
|
||||
dvb_ca_en50221_release(port->en);
|
||||
kfree(port->en);
|
||||
port->en = 0;
|
||||
port->en = NULL;
|
||||
}
|
||||
break;
|
||||
case DDB_PORT_MOD:
|
||||
@@ -2834,7 +2862,7 @@ static void input_tasklet(unsigned long data)
|
||||
#endif
|
||||
struct ddb *dev = input->port->dev;
|
||||
unsigned long flags;
|
||||
|
||||
|
||||
spin_lock_irqsave(&dma->lock, flags);
|
||||
if (!dma->running) {
|
||||
spin_unlock_irqrestore(&dma->lock, flags);
|
||||
@@ -2927,7 +2955,8 @@ static void ddb_dma_init(struct ddb_dma *dma, int nr, void *io, int out)
|
||||
}
|
||||
}
|
||||
|
||||
static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int dma_nr, int anr)
|
||||
static void ddb_input_init(struct ddb_port *port, int nr, int pnr,
|
||||
int dma_nr, int anr)
|
||||
{
|
||||
struct ddb *dev = port->dev;
|
||||
struct ddb_input *input = &dev->input[anr];
|
||||
@@ -2981,7 +3010,7 @@ static int ddb_port_match_i2c(struct ddb_port *port)
|
||||
{
|
||||
struct ddb *dev = port->dev;
|
||||
u32 i;
|
||||
|
||||
|
||||
for (i = 0; i < dev->i2c_num; i++) {
|
||||
if (dev->i2c[i].link == port->lnr &&
|
||||
dev->i2c[i].nr == port->nr) {
|
||||
@@ -3007,7 +3036,7 @@ static void ddb_ports_init(struct ddb *dev)
|
||||
if (!rm)
|
||||
continue;
|
||||
for (li2c = 0; li2c < dev->i2c_num; li2c++)
|
||||
if (dev->i2c[li2c].link == l)
|
||||
if (dev->i2c[li2c].link == l)
|
||||
break;
|
||||
for (i = 0; i < info->port_num; i++, p++) {
|
||||
port = &dev->port[p];
|
||||
@@ -3021,14 +3050,14 @@ static void ddb_ports_init(struct ddb *dev)
|
||||
|
||||
if (!ddb_port_match_i2c(port)) {
|
||||
if (info->type == DDB_OCTOPUS_MAX)
|
||||
port->i2c = &dev->i2c[li2c];
|
||||
port->i2c = &dev->i2c[li2c];
|
||||
}
|
||||
|
||||
ddb_port_probe(port);
|
||||
|
||||
|
||||
port->dvb[0].adap = &dev->adap[2 * p];
|
||||
port->dvb[1].adap = &dev->adap[2 * p + 1];
|
||||
|
||||
|
||||
if ((port->class == DDB_PORT_NONE) && i &&
|
||||
dev->port[p - 1].type == DDB_CI_EXTERNAL_XO2) {
|
||||
port->class = DDB_PORT_CI;
|
||||
@@ -3036,46 +3065,53 @@ static void ddb_ports_init(struct ddb *dev)
|
||||
port->name = "DuoFlex CI_B";
|
||||
port->i2c = dev->port[p - 1].i2c;
|
||||
}
|
||||
|
||||
|
||||
pr_info("Port %u: Link %u, Link Port %u (TAB %u): %s\n",
|
||||
port->pnr, port->lnr, port->nr, port->nr + 1, port->name);
|
||||
|
||||
port->pnr, port->lnr, port->nr,
|
||||
port->nr + 1, port->name);
|
||||
|
||||
if (port->class == DDB_PORT_CI &&
|
||||
port->type == DDB_CI_EXTERNAL_XO2) {
|
||||
ddb_input_init(port, 2 * i, 0, 2 * i, 2 * i);
|
||||
ddb_output_init(port, i, i + 8);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
||||
if (port->class == DDB_PORT_CI &&
|
||||
port->type == DDB_CI_EXTERNAL_XO2_B) {
|
||||
ddb_input_init(port, 2 * i - 1, 0, 2 * i - 1, 2 * i - 1);
|
||||
ddb_input_init(port, 2 * i - 1, 0,
|
||||
2 * i - 1, 2 * i - 1);
|
||||
ddb_output_init(port, i, i + 8);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
||||
switch (dev->link[l].info->type) {
|
||||
case DDB_OCTOPUS_CI:
|
||||
if (i >= 2) {
|
||||
ddb_input_init(port, 2 + i, 0, 2 + i, 2 + i);
|
||||
ddb_input_init(port, 4 + i, 1, 4 + i, 4 + i);
|
||||
ddb_input_init(port, 2 + i, 0,
|
||||
2 + i, 2 + i);
|
||||
ddb_input_init(port, 4 + i, 1,
|
||||
4 + i, 4 + i);
|
||||
ddb_output_init(port, i, i + 8);
|
||||
break;
|
||||
} /* fallthrough */
|
||||
case DDB_OCTONET:
|
||||
case DDB_OCTOPUS:
|
||||
ddb_input_init(port, 2 * i, 0, 2 * i, 2 * i);
|
||||
ddb_input_init(port, 2 * i + 1, 1, 2 * i + 1, 2 * i + 1);
|
||||
ddb_input_init(port, 2 * i + 1, 1,
|
||||
2 * i + 1, 2 * i + 1);
|
||||
ddb_output_init(port, i, i + 8);
|
||||
break;
|
||||
case DDB_OCTOPUS_MAX:
|
||||
case DDB_OCTOPUS_MAX_CT:
|
||||
ddb_input_init(port, 2 * i, 0, 2 * i, 2 * p);
|
||||
ddb_input_init(port, 2 * i + 1, 1, 2 * i + 1, 2 * p + 1);
|
||||
ddb_input_init(port, 2 * i + 1,
|
||||
1, 2 * i + 1, 2 * p + 1);
|
||||
break;
|
||||
case DDB_MOD:
|
||||
ddb_output_init(port, i, i);
|
||||
dev->handler[i + 18] = ddbridge_mod_rate_handler;
|
||||
dev->handler[i + 18] =
|
||||
ddbridge_mod_rate_handler;
|
||||
dev->handler_data[i + 18] =
|
||||
(unsigned long) &dev->output[i];
|
||||
break;
|
||||
@@ -3091,7 +3127,7 @@ static void ddb_ports_release(struct ddb *dev)
|
||||
{
|
||||
int i;
|
||||
struct ddb_port *port;
|
||||
|
||||
|
||||
for (i = 0; i < dev->port_num; i++) {
|
||||
port = &dev->port[i];
|
||||
#ifdef DDB_USE_WORK
|
||||
@@ -3303,7 +3339,7 @@ static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg)
|
||||
return -EINVAL;
|
||||
ctrl = (input->port->lnr << 16) | ((input->nr & 7) << 8) |
|
||||
((ts->filter_mask & 3) << 2);
|
||||
//pr_info("GET_TS %u.%u\n", input->port->lnr, input->nr);
|
||||
/*pr_info("GET_TS %u.%u\n", input->port->lnr, input->nr);*/
|
||||
if (ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) {
|
||||
pr_info("ts capture busy\n");
|
||||
return -EBUSY;
|
||||
@@ -3352,7 +3388,7 @@ static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg)
|
||||
case NSD_CANCEL_GET_TS:
|
||||
{
|
||||
u32 ctrl = 0;
|
||||
|
||||
|
||||
/*pr_info("cancel ts capture: 0x%x\n", ctrl);*/
|
||||
ddbwritel(dev, ctrl, TS_CAPTURE_CONTROL);
|
||||
ctrl = ddbreadl(dev, TS_CAPTURE_CONTROL);
|
||||
@@ -3368,7 +3404,7 @@ static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg)
|
||||
if (!input)
|
||||
return -EINVAL;
|
||||
if (ctrl & 1) {
|
||||
pr_info("cannot stop ts capture, while it was neither finished not canceled\n");
|
||||
pr_info("cannot stop ts capture, while it was neither finished nor canceled\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
/*pr_info("ts capture stopped\n");*/
|
||||
@@ -3438,7 +3474,7 @@ static void ddb_nsd_detach(struct ddb *dev)
|
||||
static int reg_wait(struct ddb *dev, u32 reg, u32 bit)
|
||||
{
|
||||
u32 count = 0;
|
||||
|
||||
|
||||
while (ddbreadl(dev, reg) & bit) {
|
||||
ndelay(10);
|
||||
if (++count == 100)
|
||||
@@ -3447,7 +3483,8 @@ static int reg_wait(struct ddb *dev, u32 reg, u32 bit)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int flashio(struct ddb *dev, u32 lnr, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen)
|
||||
static int flashio(struct ddb *dev, u32 lnr,
|
||||
u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen)
|
||||
{
|
||||
u32 data, shift;
|
||||
u32 tag = DDB_LINK_TAG(lnr);
|
||||
@@ -3485,7 +3522,7 @@ static int flashio(struct ddb *dev, u32 lnr, u8 *wbuf, u32 wlen, u8 *rbuf, u32 r
|
||||
ddbwritel(dev, data, tag | SPI_DATA);
|
||||
if (reg_wait(dev, tag | SPI_CONTROL, 4))
|
||||
goto fail;
|
||||
|
||||
|
||||
if (!rlen) {
|
||||
ddbwritel(dev, 0, tag | SPI_CONTROL);
|
||||
goto exit;
|
||||
@@ -3502,7 +3539,8 @@ static int flashio(struct ddb *dev, u32 lnr, u8 *wbuf, u32 wlen, u8 *rbuf, u32 r
|
||||
rbuf += 4;
|
||||
rlen -= 4;
|
||||
}
|
||||
ddbwritel(dev, 0x0003 | ((rlen << (8 + 3)) & 0x1F00), tag | SPI_CONTROL);
|
||||
ddbwritel(dev, 0x0003 | ((rlen << (8 + 3)) & 0x1F00),
|
||||
tag | SPI_CONTROL);
|
||||
ddbwritel(dev, 0xffffffff, tag | SPI_DATA);
|
||||
if (reg_wait(dev, tag | SPI_CONTROL, 4))
|
||||
goto fail;
|
||||
@@ -3670,7 +3708,8 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
|
||||
if (copy_from_user(wbuf, fio.write_buf, fio.write_len))
|
||||
return -EFAULT;
|
||||
res = flashio(dev, fio.link, wbuf, fio.write_len, rbuf, fio.read_len);
|
||||
res = flashio(dev, fio.link, wbuf,
|
||||
fio.write_len, rbuf, fio.read_len);
|
||||
if (res)
|
||||
return res;
|
||||
if (copy_to_user(fio.read_buf, rbuf, fio.read_len))
|
||||
@@ -4121,13 +4160,13 @@ static ssize_t bpsnr_show(struct device *device,
|
||||
{
|
||||
struct ddb *dev = dev_get_drvdata(device);
|
||||
char snr[32];
|
||||
|
||||
|
||||
if (!dev->i2c_num)
|
||||
return 0;
|
||||
|
||||
|
||||
if (i2c_read_regs16(&dev->i2c[0].adap,
|
||||
0x50, 0x0000, snr, 32) < 0 ||
|
||||
snr[0] == 0xff)
|
||||
snr[0] == 0xff)
|
||||
return sprintf(buf, "NO SNR\n");
|
||||
snr[31] = 0; /* in case it is not terminated on EEPROM */
|
||||
return sprintf(buf, "%s\n", snr);
|
||||
@@ -4209,7 +4248,7 @@ static ssize_t vlan_show(struct device *device,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct ddb *dev = dev_get_drvdata(device);
|
||||
|
||||
|
||||
return sprintf(buf, "%u\n", dev->vlan);
|
||||
}
|
||||
|
||||
@@ -4235,7 +4274,7 @@ static ssize_t fmode_show(struct device *device,
|
||||
{
|
||||
int num = attr->attr.name[5] - 0x30;
|
||||
struct ddb *dev = dev_get_drvdata(device);
|
||||
|
||||
|
||||
return sprintf(buf, "%u\n", dev->link[num].lnb.fmode);
|
||||
}
|
||||
|
||||
@@ -4244,7 +4283,7 @@ static ssize_t devid_show(struct device *device,
|
||||
{
|
||||
int num = attr->attr.name[5] - 0x30;
|
||||
struct ddb *dev = dev_get_drvdata(device);
|
||||
|
||||
|
||||
return sprintf(buf, "%08x\n", dev->link[num].ids.devid);
|
||||
}
|
||||
|
||||
@@ -4457,9 +4496,9 @@ static void gtl_link_handler(unsigned long priv)
|
||||
{
|
||||
struct ddb *dev = (struct ddb *) priv;
|
||||
u32 regs = dev->link[0].info->regmap->gtl->base;
|
||||
|
||||
printk("GT link change: %u\n",
|
||||
(1 & ddbreadl(dev, regs)));
|
||||
|
||||
pr_info("GT link change: %u\n",
|
||||
(1 & ddbreadl(dev, regs)));
|
||||
}
|
||||
|
||||
static void link_tasklet(unsigned long data)
|
||||
@@ -4467,10 +4506,10 @@ static void link_tasklet(unsigned long data)
|
||||
struct ddb_link *link = (struct ddb_link *) data;
|
||||
struct ddb *dev = link->dev;
|
||||
u32 s, off = 32 * link->nr, tag = DDB_LINK_TAG(link->nr);
|
||||
|
||||
|
||||
s = ddbreadl(dev, tag | INTERRUPT_STATUS);
|
||||
printk("gtl_irq %08x = %08x\n", tag | INTERRUPT_STATUS, s);
|
||||
|
||||
pr_info("gtl_irq %08x = %08x\n", tag | INTERRUPT_STATUS, s);
|
||||
|
||||
if (!s)
|
||||
return;
|
||||
ddbwritel(dev, s, tag | INTERRUPT_ACK);
|
||||
@@ -4486,7 +4525,7 @@ static void gtl_irq_handler(unsigned long priv)
|
||||
#if 1
|
||||
struct ddb *dev = link->dev;
|
||||
u32 s, off = 32 * link->nr, tag = DDB_LINK_TAG(link->nr);
|
||||
|
||||
|
||||
while ((s = ddbreadl(dev, tag | INTERRUPT_STATUS))) {
|
||||
ddbwritel(dev, s, tag | INTERRUPT_ACK);
|
||||
LINK_IRQ_HANDLE(0);
|
||||
@@ -4495,7 +4534,6 @@ static void gtl_irq_handler(unsigned long priv)
|
||||
LINK_IRQ_HANDLE(3);
|
||||
}
|
||||
#else
|
||||
printk("gtlirq\n");
|
||||
tasklet_schedule(&link->tasklet);
|
||||
#endif
|
||||
}
|
||||
@@ -4562,9 +4600,9 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l)
|
||||
u32 regs = dev->link[0].info->regmap->gtl->base +
|
||||
(l - 1) * dev->link[0].info->regmap->gtl->size;
|
||||
u32 id;
|
||||
|
||||
printk("Checking GT link %u: regs = %08x\n", l, regs);
|
||||
|
||||
|
||||
pr_info("Checking GT link %u: regs = %08x\n", l, regs);
|
||||
|
||||
spin_lock_init(&link->lock);
|
||||
mutex_init(&link->lnb.lock);
|
||||
link->lnb.fmode = 0xffffffff;
|
||||
@@ -4572,7 +4610,7 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l)
|
||||
|
||||
if (!(1 & ddbreadl(dev, regs))) {
|
||||
u32 c;
|
||||
|
||||
|
||||
for (c = 0; c < 5; c++) {
|
||||
ddbwritel(dev, 2, regs);
|
||||
msleep(20);
|
||||
@@ -4587,7 +4625,7 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l)
|
||||
link->nr = l;
|
||||
link->dev = dev;
|
||||
link->regs = regs;
|
||||
|
||||
|
||||
id = ddbreadl(dev, DDB_LINK_TAG(l) | 8);
|
||||
switch (id) {
|
||||
case 0x0007dd01:
|
||||
@@ -4597,25 +4635,24 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l)
|
||||
link->info = &octopus_ct_gtl;
|
||||
break;
|
||||
default:
|
||||
pr_info("DDBridge: Detected GT link but found invalid ID %08x. "
|
||||
"You might have to update (flash) the add-on card first.",
|
||||
pr_info("DDBridge: Detected GT link but found invalid ID %08x. You might have to update (flash) the add-on card first.",
|
||||
id);
|
||||
return -1;
|
||||
}
|
||||
link->ids.devid = id;
|
||||
|
||||
|
||||
ddbwritel(dev, 1, 0x1a0);
|
||||
|
||||
dev->handler_data[11] = (unsigned long) link;
|
||||
dev->handler[11] = gtl_irq_handler;
|
||||
|
||||
|
||||
pr_info("GTL %s\n", dev->link[l].info->name);
|
||||
pr_info("GTL HW %08x REGMAP %08x\n",
|
||||
ddbreadl(dev, DDB_LINK_TAG(l) | 0),
|
||||
ddbreadl(dev, DDB_LINK_TAG(l) | 4));
|
||||
pr_info("GTL ID %08x\n",
|
||||
ddbreadl(dev, DDB_LINK_TAG(l) | 8));
|
||||
|
||||
|
||||
tasklet_init(&link->tasklet, link_tasklet, (unsigned long) link);
|
||||
ddbwritel(dev, 0xffffffff, DDB_LINK_TAG(l) | INTERRUPT_ACK);
|
||||
ddbwritel(dev, 0xf, DDB_LINK_TAG(l) | INTERRUPT_ENABLE);
|
||||
@@ -4626,13 +4663,12 @@ static int ddb_gtl_init_link(struct ddb *dev, u32 l)
|
||||
static int ddb_gtl_init(struct ddb *dev)
|
||||
{
|
||||
u32 l;
|
||||
|
||||
|
||||
dev->handler_data[10] = (unsigned long) dev;
|
||||
dev->handler[10] = gtl_link_handler;
|
||||
|
||||
for (l = 1; l < dev->link[0].info->regmap->gtl->num + 1; l++) {
|
||||
for (l = 1; l < dev->link[0].info->regmap->gtl->num + 1; l++)
|
||||
ddb_gtl_init_link(dev, l);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -4640,7 +4676,7 @@ static int ddb_init_boards(struct ddb *dev)
|
||||
{
|
||||
struct ddb_info *info;
|
||||
u32 l;
|
||||
|
||||
|
||||
for (l = 0; l < DDB_MAX_LINK; l++) {
|
||||
info = dev->link[l].info;
|
||||
if (!info)
|
||||
@@ -4648,9 +4684,11 @@ static int ddb_init_boards(struct ddb *dev)
|
||||
if (info->board_control) {
|
||||
ddbwritel(dev, 0, DDB_LINK_TAG(l) | BOARD_CONTROL);
|
||||
msleep(100);
|
||||
ddbwritel(dev, info->board_control_2, DDB_LINK_TAG(l) | BOARD_CONTROL);
|
||||
ddbwritel(dev, info->board_control_2,
|
||||
DDB_LINK_TAG(l) | BOARD_CONTROL);
|
||||
usleep_range(2000, 3000);
|
||||
ddbwritel(dev, info->board_control_2 | info->board_control,
|
||||
ddbwritel(dev, info->board_control_2 |
|
||||
info->board_control,
|
||||
DDB_LINK_TAG(l) | BOARD_CONTROL);
|
||||
usleep_range(2000, 3000);
|
||||
}
|
||||
|
@@ -118,19 +118,24 @@ static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd)
|
||||
pr_err("DDBridge I2C timeout, card %d, port %d, link %u\n",
|
||||
dev->nr, i2c->nr, i2c->link);
|
||||
#if 1
|
||||
{
|
||||
{
|
||||
u32 istat = ddbreadl(dev, INTERRUPT_STATUS);
|
||||
|
||||
|
||||
dev_err(dev->dev, "DDBridge IRS %08x\n", istat);
|
||||
if (i2c->link) {
|
||||
u32 listat = ddbreadl(dev, DDB_LINK_TAG(i2c->link) | INTERRUPT_STATUS);
|
||||
dev_err(dev->dev, "DDBridge link %u IRS %08x\n",
|
||||
u32 listat =
|
||||
ddbreadl(dev,
|
||||
DDB_LINK_TAG(i2c->link) |
|
||||
INTERRUPT_STATUS);
|
||||
dev_err(dev->dev,
|
||||
"DDBridge link %u IRS %08x\n",
|
||||
i2c->link, listat);
|
||||
}
|
||||
if (istat & 1) {
|
||||
ddbwritel(dev, istat & 1, INTERRUPT_ACK);
|
||||
} else {
|
||||
u32 mon = ddbreadl(dev, i2c->regs + I2C_MONITOR);
|
||||
u32 mon = ddbreadl(dev,
|
||||
i2c->regs + I2C_MONITOR);
|
||||
|
||||
dev_err(dev->dev, "I2C cmd=%08x mon=%08x\n",
|
||||
val, mon);
|
||||
@@ -150,7 +155,7 @@ static int ddb_i2c_master_xfer(struct i2c_adapter *adapter,
|
||||
struct ddb_i2c *i2c = (struct ddb_i2c *) i2c_get_adapdata(adapter);
|
||||
struct ddb *dev = i2c->dev;
|
||||
u8 addr = 0;
|
||||
|
||||
|
||||
if (num != 1 && num != 2)
|
||||
return -EIO;
|
||||
addr = msg[0].addr;
|
||||
@@ -219,19 +224,20 @@ static int ddb_i2c_add(struct ddb *dev, struct ddb_i2c *i2c,
|
||||
struct ddb_regmap *regmap, int link, int i, int num)
|
||||
{
|
||||
struct i2c_adapter *adap;
|
||||
|
||||
|
||||
i2c->nr = i;
|
||||
i2c->dev = dev;
|
||||
i2c->link = link;
|
||||
i2c->bsize = regmap->i2c_buf->size;
|
||||
i2c->wbuf = DDB_LINK_TAG(link) | (regmap->i2c_buf->base + i2c->bsize * i);
|
||||
i2c->rbuf = i2c->wbuf;// + i2c->bsize / 2;
|
||||
i2c->regs = DDB_LINK_TAG(link) | (regmap->i2c->base + regmap->i2c->size * i);
|
||||
i2c->wbuf = DDB_LINK_TAG(link) |
|
||||
(regmap->i2c_buf->base + i2c->bsize * i);
|
||||
i2c->rbuf = i2c->wbuf;/* + i2c->bsize / 2; */
|
||||
i2c->regs = DDB_LINK_TAG(link) |
|
||||
(regmap->i2c->base + regmap->i2c->size * i);
|
||||
ddbwritel(dev, I2C_SPEED_100, i2c->regs + I2C_TIMING);
|
||||
ddbwritel(dev, ((i2c->rbuf & 0xffff) << 16) | (i2c->wbuf & 0xffff),
|
||||
i2c->regs + I2C_TASKADDRESS);
|
||||
init_completion(&i2c->completion);
|
||||
|
||||
adap = &i2c->adap;
|
||||
i2c_set_adapdata(adap, i2c);
|
||||
#ifdef I2C_ADAP_CLASS_TV_DIGITAL
|
||||
@@ -255,7 +261,7 @@ static int ddb_i2c_init(struct ddb *dev)
|
||||
struct ddb_i2c *i2c;
|
||||
struct i2c_adapter *adap;
|
||||
struct ddb_regmap *regmap;
|
||||
|
||||
|
||||
for (l = 0; l < DDB_MAX_LINK; l++) {
|
||||
if (!dev->link[l].info)
|
||||
continue;
|
||||
@@ -280,7 +286,7 @@ static int ddb_i2c_init(struct ddb *dev)
|
||||
adap = &i2c->adap;
|
||||
i2c_del_adapter(adap);
|
||||
}
|
||||
} else
|
||||
} else
|
||||
dev->i2c_num = num;
|
||||
return stat;
|
||||
}
|
||||
|
@@ -965,7 +965,8 @@ void ddbridge_mod_rate_handler(unsigned long data)
|
||||
InPacketDiff/1000));
|
||||
if (OutPacketDiff)
|
||||
mod->rate_inc =
|
||||
div_u64(mul, OutPacketDiff);
|
||||
div_u64(mul,
|
||||
OutPacketDiff);
|
||||
else
|
||||
mod->rate_inc = 0;
|
||||
mod_set_rateinc(dev, output->nr);
|
||||
@@ -975,7 +976,8 @@ void ddbridge_mod_rate_handler(unsigned long data)
|
||||
if (InPacketDiff)
|
||||
mod->PCRDecrement =
|
||||
div_u64(mod->PCRIncrement *
|
||||
(u64) OutPacketDiff,
|
||||
(u64)
|
||||
OutPacketDiff,
|
||||
InPacketDiff);
|
||||
else
|
||||
mod->PCRDecrement = 0;
|
||||
|
@@ -197,11 +197,14 @@ static int ns_set_ci(struct dvbnss *nss, u8 ci)
|
||||
ciport = citoport(dev, ci);
|
||||
if (ciport < 0)
|
||||
return -EINVAL;
|
||||
|
||||
pr_info("input %d.%d to ci %d at port %d\n", input->port->lnr, input->nr, ci, ciport);
|
||||
ddbwritel(dev, (input->port->lnr << 21) | (input->nr << 16) | 0x1c, TS_OUTPUT_CONTROL(ciport));
|
||||
|
||||
pr_info("input %d.%d to ci %d at port %d\n",
|
||||
input->port->lnr, input->nr, ci, ciport);
|
||||
ddbwritel(dev, (input->port->lnr << 21) | (input->nr << 16) | 0x1c,
|
||||
TS_OUTPUT_CONTROL(ciport));
|
||||
usleep_range(1, 5);
|
||||
ddbwritel(dev, (input->port->lnr << 21) | (input->nr << 16) | 0x1d, TS_OUTPUT_CONTROL(ciport));
|
||||
ddbwritel(dev, (input->port->lnr << 21) | (input->nr << 16) | 0x1d,
|
||||
TS_OUTPUT_CONTROL(ciport));
|
||||
dns->fe = dev->port[ciport].input[0];
|
||||
return 0;
|
||||
}
|
||||
@@ -443,7 +446,8 @@ static int ns_start(struct dvbnss *nss)
|
||||
if (dns->fe != input)
|
||||
ddb_dvb_ns_input_start(dns->fe);
|
||||
ddb_dvb_ns_input_start(input);
|
||||
printk("ns start ns %u, fe %u link %u\n", dns->nr, dns->fe->nr, dns->fe->port->lnr);
|
||||
/* printk("ns start ns %u, fe %u link %u\n",
|
||||
dns->nr, dns->fe->nr, dns->fe->port->lnr); */
|
||||
ddbwritel(dev, reg | (dns->fe->nr << 8) | (dns->fe->port->lnr << 16),
|
||||
STREAM_CONTROL(dns->nr));
|
||||
return 0;
|
||||
|
@@ -1,10 +1,10 @@
|
||||
/*
|
||||
* ddbridge.c: Digital Devices PCIe bridge driver
|
||||
*
|
||||
* Copyright (C) 2010-2015 Digital Devices GmbH
|
||||
* Copyright (C) 2010-2015 Digital Devices GmbH
|
||||
* Ralph Metzler <rjkm@metzlerbros.de>
|
||||
* Marcus Metzler <mocm@metzlerbros.de>
|
||||
*
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
@@ -84,7 +84,7 @@ static void __devexit ddb_remove(struct pci_dev *pdev)
|
||||
ddb_buffers_free(dev);
|
||||
|
||||
ddb_unmap(dev);
|
||||
pci_set_drvdata(pdev, 0);
|
||||
pci_set_drvdata(pdev, NULL);
|
||||
pci_disable_device(pdev);
|
||||
}
|
||||
|
||||
@@ -166,7 +166,8 @@ static int __devinit ddb_probe(struct pci_dev *pdev,
|
||||
stat = pci_enable_msi_range(dev->pdev, 1, 2);
|
||||
if (stat >= 1) {
|
||||
dev->msi = stat;
|
||||
pr_info("DDBridge: using %d MSI interrupt(s)\n", dev->msi);
|
||||
pr_info("DDBridge: using %d MSI interrupt(s)\n",
|
||||
dev->msi);
|
||||
irq_flag = 0;
|
||||
} else
|
||||
pr_info("DDBridge: MSI not available.\n");
|
||||
@@ -216,7 +217,7 @@ static int __devinit ddb_probe(struct pci_dev *pdev,
|
||||
ddbwritel(dev, 0, DMA_BASE_READ);
|
||||
if (dev->link[0].info->type != DDB_MOD)
|
||||
ddbwritel(dev, 0, DMA_BASE_WRITE);
|
||||
|
||||
|
||||
if (dev->link[0].info->type == DDB_MOD) {
|
||||
if (ddbreadl(dev, 0x1c) == 4)
|
||||
dev->link[0].info->port_num = 4;
|
||||
@@ -232,7 +233,7 @@ static int __devinit ddb_probe(struct pci_dev *pdev,
|
||||
}
|
||||
if (ddb_init(dev) == 0)
|
||||
return 0;
|
||||
|
||||
|
||||
ddbwritel(dev, 0, INTERRUPT_ENABLE);
|
||||
ddbwritel(dev, 0, MSI1_ENABLE);
|
||||
free_irq(dev->pdev->irq, dev);
|
||||
@@ -246,7 +247,7 @@ fail:
|
||||
pr_err("fail\n");
|
||||
|
||||
ddb_unmap(dev);
|
||||
pci_set_drvdata(pdev, 0);
|
||||
pci_set_drvdata(pdev, NULL);
|
||||
pci_disable_device(pdev);
|
||||
return -1;
|
||||
}
|
||||
@@ -484,6 +485,8 @@ static const struct pci_device_id ddb_id_tbl[] __devinitconst = {
|
||||
DDB_ID(DDVID, 0x0006, DDVID, 0x0033, ddb_ctv7),
|
||||
DDB_ID(DDVID, 0x0007, DDVID, 0x0023, ddb_s2_48),
|
||||
DDB_ID(DDVID, 0x0008, DDVID, 0x0034, ddb_ct_8),
|
||||
DDB_ID(DDVID, 0x0008, DDVID, 0x0035, ddb_ct_8),
|
||||
DDB_ID(DDVID, 0x0008, DDVID, 0x0036, ddb_ct_8),
|
||||
DDB_ID(DDVID, 0x0011, DDVID, 0x0040, ddb_ci),
|
||||
DDB_ID(DDVID, 0x0011, DDVID, 0x0041, ddb_cis),
|
||||
DDB_ID(DDVID, 0x0012, DDVID, 0x0042, ddb_ci),
|
||||
@@ -496,6 +499,7 @@ static const struct pci_device_id ddb_id_tbl[] __devinitconst = {
|
||||
DDB_ID(DDVID, 0x0005, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
|
||||
DDB_ID(DDVID, 0x0006, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
|
||||
DDB_ID(DDVID, 0x0007, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
|
||||
DDB_ID(DDVID, 0x0008, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
|
||||
DDB_ID(DDVID, 0x0011, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
|
||||
DDB_ID(DDVID, 0x0013, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
|
||||
DDB_ID(DDVID, 0x0201, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
|
||||
|
@@ -41,7 +41,7 @@
|
||||
#include <linux/poll.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/pci.h>
|
||||
//#include <linux/pci_ids.h>
|
||||
/*#include <linux/pci_ids.h>*/
|
||||
#include <linux/timer.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/swab.h>
|
||||
@@ -132,7 +132,7 @@ struct ddb_ids {
|
||||
u16 device;
|
||||
u16 subvendor;
|
||||
u16 subdevice;
|
||||
|
||||
|
||||
u32 hwid;
|
||||
u32 regmapid;
|
||||
u32 devid;
|
||||
@@ -191,7 +191,7 @@ struct ddb_dma {
|
||||
u32 size;
|
||||
u32 div;
|
||||
u32 bufreg;
|
||||
|
||||
|
||||
#ifdef DDB_USE_WORK
|
||||
struct work_struct work;
|
||||
#else
|
||||
@@ -205,7 +205,7 @@ struct ddb_dma {
|
||||
u32 cbuf;
|
||||
u32 coff;
|
||||
};
|
||||
|
||||
|
||||
struct ddb_dvb {
|
||||
struct dvb_adapter *adap;
|
||||
int adap_registered;
|
||||
@@ -221,14 +221,15 @@ struct ddb_dvb {
|
||||
int users;
|
||||
u32 attached;
|
||||
u8 input;
|
||||
|
||||
|
||||
fe_sec_tone_mode_t tone;
|
||||
fe_sec_voltage_t voltage;
|
||||
|
||||
|
||||
int (*i2c_gate_ctrl)(struct dvb_frontend *, int);
|
||||
int (*set_voltage)(struct dvb_frontend *fe, fe_sec_voltage_t voltage);
|
||||
int (*set_input)(struct dvb_frontend *fe, int input);
|
||||
int (*diseqc_send_master_cmd)(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd);
|
||||
int (*diseqc_send_master_cmd)(struct dvb_frontend *fe,
|
||||
struct dvb_diseqc_master_cmd *cmd);
|
||||
};
|
||||
|
||||
struct ddb_ci {
|
||||
@@ -374,7 +375,7 @@ struct ddb_ns {
|
||||
struct ddb_lnb {
|
||||
struct mutex lock;
|
||||
u32 tone;
|
||||
fe_sec_voltage_t oldvoltage[4];
|
||||
fe_sec_voltage_t oldvoltage[4];
|
||||
u32 voltage[4];
|
||||
u32 voltages;
|
||||
u32 fmode;
|
||||
@@ -396,12 +397,12 @@ struct ddb {
|
||||
struct pci_dev *pdev;
|
||||
struct platform_device *pfdev;
|
||||
struct device *dev;
|
||||
|
||||
|
||||
int msi;
|
||||
struct workqueue_struct *wq;
|
||||
u32 has_dma;
|
||||
u32 has_ns;
|
||||
|
||||
|
||||
struct ddb_link link[DDB_MAX_LINK];
|
||||
unsigned char *regs;
|
||||
u32 regs_len;
|
||||
@@ -413,7 +414,7 @@ struct ddb {
|
||||
struct ddb_output output[DDB_MAX_OUTPUT];
|
||||
struct dvb_adapter adap[DDB_MAX_INPUT];
|
||||
struct ddb_dma dma[DDB_MAX_INPUT + DDB_MAX_OUTPUT];
|
||||
|
||||
|
||||
void (*handler[128])(unsigned long);
|
||||
unsigned long handler_data[128];
|
||||
|
||||
@@ -461,36 +462,37 @@ static inline u32 ddbreadl0(struct ddb_link *link, u32 adr)
|
||||
#if 0
|
||||
static inline void gtlw(struct ddb_link *link)
|
||||
{
|
||||
u32 count = 0;
|
||||
static u32 max = 0;
|
||||
u32 count = 0;
|
||||
static u32 max;
|
||||
|
||||
while (1 & ddbreadl0(link, link->regs + 0x10)) {
|
||||
if (++count == 1024) {
|
||||
printk("LTO\n");
|
||||
while (1 & ddbreadl0(link, link->regs + 0x10)) {
|
||||
if (++count == 1024) {
|
||||
pr_info("LTO\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (count > max) {
|
||||
max = count;
|
||||
printk("TO=%u\n", max);
|
||||
pr_info("TO=%u\n", max);
|
||||
}
|
||||
if (ddbreadl0(link, link->regs + 0x10) & 0x8000)
|
||||
printk("link error\n");
|
||||
pr_err("link error\n");
|
||||
}
|
||||
#else
|
||||
static inline void gtlw(struct ddb_link *link)
|
||||
{
|
||||
while (1 & ddbreadl0(link, link->regs + 0x10));
|
||||
while (1 & ddbreadl0(link, link->regs + 0x10))
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
static u32 ddblreadl(struct ddb_link *link, u32 adr)
|
||||
{
|
||||
if (unlikely(link->nr)) {
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(&link->lock, flags);
|
||||
if (unlikely(link->nr)) {
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(&link->lock, flags);
|
||||
gtlw(link);
|
||||
ddbwritel0(link, adr & 0xfffc, link->regs + 0x14);
|
||||
ddbwritel0(link, 3, link->regs + 0x10);
|
||||
@@ -506,8 +508,8 @@ static void ddblwritel(struct ddb_link *link, u32 val, u32 adr)
|
||||
{
|
||||
if (unlikely(link->nr)) {
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&link->lock, flags);
|
||||
|
||||
spin_lock_irqsave(&link->lock, flags);
|
||||
gtlw(link);
|
||||
ddbwritel0(link, 0xf0000 | (adr & 0xfffc), link->regs + 0x14);
|
||||
ddbwritel0(link, val, link->regs + 0x18);
|
||||
@@ -520,12 +522,12 @@ static void ddblwritel(struct ddb_link *link, u32 val, u32 adr)
|
||||
|
||||
static u32 ddbreadl(struct ddb *dev, u32 adr)
|
||||
{
|
||||
if (unlikely(adr & 0xf0000000)) {
|
||||
unsigned long flags;
|
||||
u32 val, l = (adr >> DDB_LINK_SHIFT);
|
||||
if (unlikely(adr & 0xf0000000)) {
|
||||
unsigned long flags;
|
||||
u32 val, l = (adr >> DDB_LINK_SHIFT);
|
||||
struct ddb_link *link = &dev->link[l];
|
||||
|
||||
spin_lock_irqsave(&link->lock, flags);
|
||||
|
||||
spin_lock_irqsave(&link->lock, flags);
|
||||
gtlw(link);
|
||||
ddbwritel0(link, adr & 0xfffc, link->regs + 0x14);
|
||||
ddbwritel0(link, 3, link->regs + 0x10);
|
||||
@@ -543,8 +545,8 @@ static void ddbwritel(struct ddb *dev, u32 val, u32 adr)
|
||||
unsigned long flags;
|
||||
u32 l = (adr >> DDB_LINK_SHIFT);
|
||||
struct ddb_link *link = &dev->link[l];
|
||||
|
||||
spin_lock_irqsave(&link->lock, flags);
|
||||
|
||||
spin_lock_irqsave(&link->lock, flags);
|
||||
gtlw(link);
|
||||
ddbwritel0(link, 0xf0000 | (adr & 0xfffc), link->regs + 0x14);
|
||||
ddbwritel0(link, val, link->regs + 0x18);
|
||||
@@ -712,6 +714,6 @@ void ddbridge_mod_rate_handler(unsigned long data);
|
||||
|
||||
int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len);
|
||||
|
||||
#define DDBRIDGE_VERSION "0.9.21"
|
||||
#define DDBRIDGE_VERSION "0.9.23"
|
||||
|
||||
#endif
|
||||
|
@@ -176,9 +176,11 @@ static int __init octonet_probe(struct platform_device *pdev)
|
||||
dev->link[0].info = &ddb_octonet_gtl;
|
||||
else
|
||||
dev->link[0].info = &ddb_octonet_tbd;
|
||||
|
||||
pr_info("HW %08x REGMAP %08x\n", dev->link[0].ids.hwid, dev->link[0].ids.regmapid);
|
||||
pr_info("MAC %08x DEVID %08x\n", dev->link[0].ids.mac, dev->link[0].ids.devid);
|
||||
|
||||
pr_info("HW %08x REGMAP %08x\n",
|
||||
dev->link[0].ids.hwid, dev->link[0].ids.regmapid);
|
||||
pr_info("MAC %08x DEVID %08x\n",
|
||||
dev->link[0].ids.mac, dev->link[0].ids.devid);
|
||||
|
||||
ddbwritel(dev, 0, ETHER_CONTROL);
|
||||
ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE);
|
||||
|
@@ -1269,11 +1269,38 @@ static int get_tune_settings(struct dvb_frontend *fe,
|
||||
}
|
||||
}
|
||||
|
||||
static int read_snr(struct dvb_frontend *fe, u16 *snr);
|
||||
|
||||
static int get_stats(struct dvb_frontend *fe)
|
||||
{
|
||||
struct cxd_state *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
||||
u16 val;
|
||||
|
||||
if (fe->ops.tuner_ops.get_rf_strength)
|
||||
fe->ops.tuner_ops.get_rf_strength(fe, &val);
|
||||
else
|
||||
val = 0;
|
||||
|
||||
p->strength.len = 1;
|
||||
p->strength.stat[0].scale = FE_SCALE_DECIBEL;
|
||||
p->strength.stat[0].uvalue = 1000 * (s64) (s16) val;
|
||||
|
||||
read_snr(fe, &val);
|
||||
p->cnr.len = 1;
|
||||
p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
|
||||
p->cnr.stat[0].uvalue = 100 * (s64) (s16) val;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int read_status(struct dvb_frontend *fe, fe_status_t *status)
|
||||
{
|
||||
struct cxd_state *state = fe->demodulator_priv;
|
||||
u8 rdata;
|
||||
|
||||
get_stats(fe);
|
||||
|
||||
*status = 0;
|
||||
switch (state->state) {
|
||||
case ActiveC:
|
||||
@@ -1430,6 +1457,7 @@ static int get_ber_it(struct cxd_state *state, u32 *n, u32 *d)
|
||||
static int read_ber(struct dvb_frontend *fe, u32 *ber)
|
||||
{
|
||||
struct cxd_state *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
||||
u32 n, d;
|
||||
int s = 0;
|
||||
|
||||
@@ -1455,7 +1483,15 @@ static int read_ber(struct dvb_frontend *fe, u32 *ber)
|
||||
}
|
||||
if (s)
|
||||
return s;
|
||||
|
||||
|
||||
p->pre_bit_error.len = 1;
|
||||
p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
|
||||
p->pre_bit_error.stat[0].uvalue = n;
|
||||
p->pre_bit_count.len = 1;
|
||||
p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
|
||||
p->pre_bit_count.stat[0].uvalue = d;
|
||||
if (d)
|
||||
*ber = (n * 1000) / d;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1558,7 +1594,7 @@ static void GetSignalToNoiseIT(struct cxd_state *state, u32 *SignalToNoise)
|
||||
reg = (Data[0] << 8) | Data[1];
|
||||
if (reg > 51441)
|
||||
reg = 51441;
|
||||
|
||||
|
||||
if (state->bw == 8) {
|
||||
if (reg > 1143)
|
||||
reg = 1143;
|
||||
@@ -1654,6 +1690,7 @@ static void GetSignalToNoiseC(struct cxd_state *state, u32 *SignalToNoise)
|
||||
static int read_snr(struct dvb_frontend *fe, u16 *snr)
|
||||
{
|
||||
struct cxd_state *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
||||
u32 SNR = 0;
|
||||
|
||||
*snr = 0;
|
||||
@@ -1680,6 +1717,9 @@ static int read_snr(struct dvb_frontend *fe, u16 *snr)
|
||||
break;
|
||||
}
|
||||
*snr = SNR;
|
||||
p->cnr.len = 1;
|
||||
p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
|
||||
p->cnr.stat[0].uvalue = 10 * (s64) SNR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1851,7 +1891,7 @@ static int get_fe_c(struct cxd_state *state)
|
||||
freeze_regst(state);
|
||||
readregst_unlocked(state, 0x40, 0x19, &qam, 1);
|
||||
unfreeze_regst(state);
|
||||
p->modulation = qam & 0x07;
|
||||
p->modulation = 1 + (qam & 0x07);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@@ -222,6 +222,7 @@ static int send_command(struct mxl *state, u32 size, u8 *buf)
|
||||
}
|
||||
if (!count) {
|
||||
pr_info("mxl5xx: send_command busy\n");
|
||||
mutex_unlock(&state->base->i2c_lock);
|
||||
return -EBUSY;
|
||||
}
|
||||
}
|
||||
@@ -446,6 +447,18 @@ static int CfgDemodAbortTune(struct mxl *state)
|
||||
return send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, &cmdBuff[0]);
|
||||
}
|
||||
|
||||
static int reset_fec_counter(struct mxl *state)
|
||||
{
|
||||
MXL_HYDRA_DEMOD_ABORT_TUNE_T abortTuneCmd;
|
||||
u32 demodIndex = (u32) state->demod;
|
||||
u8 cmdSize = sizeof(u32);
|
||||
u8 cmdBuff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
|
||||
|
||||
BUILD_HYDRA_CMD(MXL_HYDRA_DEMOD_RESET_FEC_COUNTER_CMD,
|
||||
MXL_CMD_WRITE, cmdSize, &demodIndex, cmdBuff);
|
||||
return send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, &cmdBuff[0]);
|
||||
}
|
||||
|
||||
static int send_master_cmd(struct dvb_frontend *fe,
|
||||
struct dvb_diseqc_master_cmd *cmd)
|
||||
{
|
||||
@@ -516,6 +529,8 @@ static int set_parameters(struct dvb_frontend *fe)
|
||||
return stat;
|
||||
}
|
||||
|
||||
static int get_stats(struct dvb_frontend *fe);
|
||||
|
||||
static int read_status(struct dvb_frontend *fe, fe_status_t *status)
|
||||
{
|
||||
struct mxl *state = fe->demodulator_priv;
|
||||
@@ -532,7 +547,7 @@ static int read_status(struct dvb_frontend *fe, fe_status_t *status)
|
||||
mutex_unlock(&state->base->status_lock);
|
||||
|
||||
*status = (regData == 1) ? 0x1f : 0;
|
||||
|
||||
get_stats(fe);
|
||||
return stat;
|
||||
}
|
||||
|
||||
@@ -559,6 +574,7 @@ static int tune(struct dvb_frontend *fe, bool re_tune,
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
#if 0
|
||||
if (*status & FE_HAS_LOCK)
|
||||
return 0;
|
||||
|
||||
@@ -567,6 +583,7 @@ static int tune(struct dvb_frontend *fe, bool re_tune,
|
||||
else
|
||||
p->delivery_system = SYS_DVBS;
|
||||
set_parameters(fe);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -597,6 +614,7 @@ static int read_snr(struct dvb_frontend *fe, u16 *snr)
|
||||
struct mxl *state = fe->demodulator_priv;
|
||||
int stat;
|
||||
u32 regData = 0;
|
||||
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
||||
|
||||
mutex_lock(&state->base->status_lock);
|
||||
HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
|
||||
@@ -605,20 +623,68 @@ static int read_snr(struct dvb_frontend *fe, u16 *snr)
|
||||
®Data);
|
||||
HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
|
||||
mutex_unlock(&state->base->status_lock);
|
||||
*snr = (s16) (regData & 0xFFFF);
|
||||
*snr = (s16) (regData & 0xFFFF); /* 100x dB */
|
||||
p->cnr.len = 1;
|
||||
p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
|
||||
p->cnr.stat[0].uvalue = 10 * (s64) *snr;
|
||||
return stat;
|
||||
}
|
||||
|
||||
static int read_ber(struct dvb_frontend *fe, u32 *ber)
|
||||
{
|
||||
struct mxl *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
||||
u32 reg[8], reg2[4];
|
||||
int stat;
|
||||
|
||||
*ber = 0;
|
||||
|
||||
mutex_lock(&state->base->status_lock);
|
||||
HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
|
||||
stat = read_register_block(state,
|
||||
(HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET +
|
||||
HYDRA_DMD_STATUS_OFFSET(state->demod)),
|
||||
(7 * sizeof(u32)),
|
||||
(u8 *) ®[0]);
|
||||
stat = read_register_block(state,
|
||||
(HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET +
|
||||
HYDRA_DMD_STATUS_OFFSET(state->demod)),
|
||||
(4 * sizeof(u32)),
|
||||
(u8 *) ®2[0]);
|
||||
HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
|
||||
mutex_unlock(&state->base->status_lock);
|
||||
|
||||
|
||||
switch (p->delivery_system) {
|
||||
case SYS_DSS:
|
||||
break;
|
||||
case SYS_DVBS:
|
||||
p->pre_bit_error.len = 1;
|
||||
p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
|
||||
p->pre_bit_error.stat[0].uvalue = reg[5];
|
||||
p->pre_bit_count.len = 1;
|
||||
p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
|
||||
p->pre_bit_count.stat[0].uvalue = reg[6] * 188 * 8;
|
||||
break;
|
||||
case SYS_DVBS2:
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
pr_info("mxl5xx: ber %08x %08x %08x %08x %08x %08x %08x\n",
|
||||
reg[0], reg[1], reg[2], reg[3], reg[4], reg[5], reg[6]);
|
||||
pr_info("mxl5xx: ber2 %08x %08x %08x %08x\n",
|
||||
reg[0], reg[1], reg[2], reg[3]);
|
||||
//pre_bit_error, pre_bit_count
|
||||
//post_bit_error, post_bit_count;
|
||||
//block_error block_count;
|
||||
//reset_fec_counter(state);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int read_signal_strength(struct dvb_frontend *fe, u16 *strength)
|
||||
{
|
||||
struct mxl *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
||||
int stat;
|
||||
u32 regData = 0;
|
||||
|
||||
@@ -629,7 +695,10 @@ static int read_signal_strength(struct dvb_frontend *fe, u16 *strength)
|
||||
®Data);
|
||||
HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
|
||||
mutex_unlock(&state->base->status_lock);
|
||||
*strength = (u16) (regData & 0xFFFF);
|
||||
*strength = (u16) (regData & 0xFFFF); /* 10x dBm */
|
||||
p->strength.len = 1;
|
||||
p->strength.stat[0].scale = FE_SCALE_DECIBEL;
|
||||
p->strength.stat[0].uvalue = 10 * (s64) (s16) (regData & 0xFFFF);
|
||||
return stat;
|
||||
}
|
||||
|
||||
@@ -638,17 +707,102 @@ static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_stats(struct dvb_frontend *fe)
|
||||
{
|
||||
u16 val;
|
||||
u32 val32;
|
||||
|
||||
read_signal_strength(fe, &val);
|
||||
read_snr(fe, &val);
|
||||
read_ber(fe, &val32);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static fe_code_rate_t conv_fec(MXL_HYDRA_FEC_E fec)
|
||||
{
|
||||
enum fe_code_rate fec2fec[11] = {
|
||||
FEC_NONE, FEC_1_2, FEC_3_5, FEC_2_3,
|
||||
FEC_3_4, FEC_4_5, FEC_5_6, FEC_6_7,
|
||||
FEC_7_8, FEC_8_9, FEC_9_10
|
||||
};
|
||||
|
||||
if (fec > MXL_HYDRA_FEC_9_10)
|
||||
return FEC_NONE;
|
||||
return fec2fec[fec];
|
||||
}
|
||||
|
||||
static int get_frontend(struct dvb_frontend *fe)
|
||||
{
|
||||
//struct mxl *state = fe->demodulator_priv;
|
||||
struct mxl *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
||||
u32 regData[MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE];
|
||||
u32 freq;
|
||||
int stat;
|
||||
|
||||
mutex_lock(&state->base->status_lock);
|
||||
HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
|
||||
stat = read_register_block(state,
|
||||
(HYDRA_DMD_STANDARD_ADDR_OFFSET +
|
||||
HYDRA_DMD_STATUS_OFFSET(state->demod)),
|
||||
(MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE * 4), // 25 * 4 bytes
|
||||
(u8 *) ®Data[0]);
|
||||
// read demod channel parameters
|
||||
stat = read_register_block(state,
|
||||
(HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR +
|
||||
HYDRA_DMD_STATUS_OFFSET(state->demod)),
|
||||
(4), // 4 bytes
|
||||
(u8 *) &freq);
|
||||
HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
|
||||
mutex_unlock(&state->base->status_lock);
|
||||
|
||||
pr_info("mxl5xx: freq=%u delsys=%u srate=%u\n",
|
||||
freq * 1000, regData[DMD_STANDARD_ADDR],
|
||||
regData[DMD_SYMBOL_RATE_ADDR]);
|
||||
p->symbol_rate = regData[DMD_SYMBOL_RATE_ADDR];
|
||||
p->frequency = freq;
|
||||
//p->delivery_system = (MXL_HYDRA_BCAST_STD_E )regData[DMD_STANDARD_ADDR];
|
||||
//p->inversion = (MXL_HYDRA_SPECTRUM_E )regData[DMD_SPECTRUM_INVERSION_ADDR];
|
||||
//freqSearchRangeKHz = (regData[DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR]);
|
||||
|
||||
p->fec_inner = conv_fec(regData[DMD_FEC_CODE_RATE_ADDR]);
|
||||
switch (p->delivery_system) {
|
||||
case SYS_DSS:
|
||||
break;
|
||||
case SYS_DVBS:
|
||||
break;
|
||||
case SYS_DVBS2:
|
||||
switch ((MXL_HYDRA_PILOTS_E ) regData[DMD_DVBS2_PILOT_ON_OFF_ADDR]) {
|
||||
case MXL_HYDRA_PILOTS_OFF:
|
||||
p->pilot = PILOT_OFF;
|
||||
break;
|
||||
case MXL_HYDRA_PILOTS_ON:
|
||||
p->pilot = PILOT_ON;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
case SYS_DVBS:
|
||||
switch ((MXL_HYDRA_MODULATION_E) regData[DMD_MODULATION_SCHEME_ADDR]) {
|
||||
case MXL_HYDRA_MOD_QPSK:
|
||||
p->modulation = QPSK;
|
||||
break;
|
||||
case MXL_HYDRA_MOD_8PSK:
|
||||
p->modulation = PSK_8;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch ((MXL_HYDRA_ROLLOFF_E) regData[DMD_SPECTRUM_ROLL_OFF_ADDR]) {
|
||||
case MXL_HYDRA_ROLLOFF_0_20:
|
||||
p->rolloff = ROLLOFF_20;
|
||||
break;
|
||||
case MXL_HYDRA_ROLLOFF_0_35:
|
||||
p->rolloff = ROLLOFF_35;
|
||||
break;
|
||||
case MXL_HYDRA_ROLLOFF_0_25:
|
||||
p->rolloff = ROLLOFF_25;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
|
@@ -46,7 +46,6 @@ LIST_HEAD(stvlist);
|
||||
|
||||
enum ReceiveMode { Mode_None, Mode_DVBS, Mode_DVBS2, Mode_Auto };
|
||||
|
||||
|
||||
enum DVBS2_FECType { DVBS2_64K, DVBS2_16K };
|
||||
|
||||
enum DVBS2_ModCod {
|
||||
@@ -134,9 +133,9 @@ struct SInitTable {
|
||||
u8 Data;
|
||||
};
|
||||
|
||||
struct SLookupSNTable {
|
||||
s16 SignalToNoise;
|
||||
u16 RefValue;
|
||||
struct SLookup {
|
||||
s16 Value;
|
||||
u16 RegValue;
|
||||
};
|
||||
|
||||
static inline int i2c_write(struct i2c_adapter *adap, u8 adr,
|
||||
@@ -194,7 +193,7 @@ static int read_regs(struct stv *state, u16 reg, u8 *val, int len)
|
||||
reg, val, len);
|
||||
}
|
||||
|
||||
struct SLookupSNTable S1_SN_Lookup[] = {
|
||||
struct SLookup S1_SN_Lookup[] = {
|
||||
{ 0, 9242 }, /*C/N= 0dB*/
|
||||
{ 05, 9105 }, /*C/N=0.5dB*/
|
||||
{ 10, 8950 }, /*C/N=1.0dB*/
|
||||
@@ -251,7 +250,7 @@ struct SLookupSNTable S1_SN_Lookup[] = {
|
||||
{ 510, 425 } /*C/N=51.0dB*/
|
||||
};
|
||||
|
||||
struct SLookupSNTable S2_SN_Lookup[] = {
|
||||
struct SLookup S2_SN_Lookup[] = {
|
||||
{ -30, 13950 }, /*C/N=-2.5dB*/
|
||||
{ -25, 13580 }, /*C/N=-2.5dB*/
|
||||
{ -20, 13150 }, /*C/N=-2.0dB*/
|
||||
@@ -550,14 +549,48 @@ static int TrackingOptimization(struct stv *state)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static s32 TableLookup(struct SLookup *Table,
|
||||
int TableSize, u16 RegValue)
|
||||
{
|
||||
s32 Value;
|
||||
int imin = 0;
|
||||
int imax = TableSize - 1;
|
||||
int i;
|
||||
s32 RegDiff;
|
||||
|
||||
// Assumes Table[0].RegValue > Table[imax].RegValue
|
||||
if( RegValue >= Table[0].RegValue )
|
||||
Value = Table[0].Value;
|
||||
else if( RegValue <= Table[imax].RegValue )
|
||||
Value = Table[imax].Value;
|
||||
else
|
||||
{
|
||||
while(imax-imin > 1)
|
||||
{
|
||||
i = (imax + imin) / 2;
|
||||
if( (Table[imin].RegValue >= RegValue) && (RegValue >= Table[i].RegValue) )
|
||||
imax = i;
|
||||
else
|
||||
imin = i;
|
||||
}
|
||||
|
||||
RegDiff = Table[imax].RegValue - Table[imin].RegValue;
|
||||
Value = Table[imin].Value;
|
||||
if( RegDiff != 0 )
|
||||
Value += ((s32)(RegValue - Table[imin].RegValue) *
|
||||
(s32)(Table[imax].Value - Table[imin].Value))/(RegDiff);
|
||||
}
|
||||
|
||||
return Value;
|
||||
}
|
||||
|
||||
static int GetSignalToNoise(struct stv *state, s32 *SignalToNoise)
|
||||
{
|
||||
int i;
|
||||
u8 Data0;
|
||||
u8 Data1;
|
||||
u16 Data;
|
||||
int nLookup;
|
||||
struct SLookupSNTable *Lookup;
|
||||
struct SLookup *Lookup;
|
||||
|
||||
*SignalToNoise = 0;
|
||||
|
||||
@@ -576,25 +609,7 @@ static int GetSignalToNoise(struct stv *state, s32 *SignalToNoise)
|
||||
Lookup = S1_SN_Lookup;
|
||||
}
|
||||
Data = (((u16)Data1) << 8) | (u16) Data0;
|
||||
if (Data > Lookup[0].RefValue) {
|
||||
*SignalToNoise = Lookup[0].SignalToNoise;
|
||||
} else if (Data <= Lookup[nLookup-1].RefValue) {
|
||||
*SignalToNoise = Lookup[nLookup-1].SignalToNoise;
|
||||
} else {
|
||||
for (i = 0; i < nLookup - 1; i += 1) {
|
||||
if (Data <= Lookup[i].RefValue &&
|
||||
Data > Lookup[i+1].RefValue) {
|
||||
*SignalToNoise =
|
||||
(s32)(Lookup[i].SignalToNoise) +
|
||||
((s32)(Data - Lookup[i].RefValue) *
|
||||
(s32)(Lookup[i+1].SignalToNoise -
|
||||
Lookup[i].SignalToNoise)) /
|
||||
((s32)(Lookup[i+1].RefValue) -
|
||||
(s32)(Lookup[i].RefValue));
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
*SignalToNoise = TableLookup(Lookup, nLookup, Data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1039,15 +1054,91 @@ static int set_parameters(struct dvb_frontend *fe)
|
||||
return stat;
|
||||
}
|
||||
|
||||
static int get_frontend(struct dvb_frontend *fe)
|
||||
{
|
||||
struct stv *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
||||
u8 tmp;
|
||||
|
||||
if (state->ReceiveMode == Mode_DVBS2) {
|
||||
u32 mc;
|
||||
enum fe_modulation modcod2mod[0x20] = {
|
||||
QPSK, QPSK, QPSK, QPSK,
|
||||
QPSK, QPSK, QPSK, QPSK,
|
||||
QPSK, QPSK, QPSK, QPSK,
|
||||
PSK_8, PSK_8, PSK_8, PSK_8,
|
||||
PSK_8, PSK_8, APSK_16, APSK_16,
|
||||
APSK_16, APSK_16, APSK_16, APSK_16,
|
||||
APSK_32, APSK_32, APSK_32, APSK_32,
|
||||
APSK_32,
|
||||
};
|
||||
enum fe_code_rate modcod2fec[0x20] = {
|
||||
FEC_NONE, FEC_1_4, FEC_1_3, FEC_2_5,
|
||||
FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4,
|
||||
FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
|
||||
FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6,
|
||||
FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4,
|
||||
FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
|
||||
FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9,
|
||||
FEC_9_10
|
||||
};
|
||||
read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
|
||||
mc = ((tmp & 0x7c) >> 2);
|
||||
p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF;
|
||||
p->modulation = modcod2mod[mc];
|
||||
p->fec_inner = modcod2fec[mc];
|
||||
} else if (state->ReceiveMode == Mode_DVBS) {
|
||||
read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
|
||||
switch( tmp & 0x1F ) {
|
||||
case 0x0d:
|
||||
p->fec_inner = FEC_1_2;
|
||||
break;
|
||||
case 0x12:
|
||||
p->fec_inner = FEC_2_3;
|
||||
break;
|
||||
case 0x15:
|
||||
p->fec_inner = FEC_3_4;
|
||||
break;
|
||||
case 0x18:
|
||||
p->fec_inner = FEC_5_6;
|
||||
break;
|
||||
case 0x1a:
|
||||
p->fec_inner = FEC_7_8;
|
||||
break;
|
||||
default:
|
||||
p->fec_inner = FEC_NONE;
|
||||
break;
|
||||
}
|
||||
p->rolloff = ROLLOFF_35;
|
||||
} else {
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int read_snr(struct dvb_frontend *fe, u16 *snr);
|
||||
static int read_signal_strength(struct dvb_frontend *fe, u16 *strength);
|
||||
static int read_ber(struct dvb_frontend *fe, u32 *ber);
|
||||
|
||||
static int read_status(struct dvb_frontend *fe, fe_status_t *status)
|
||||
{
|
||||
struct stv *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
||||
u8 DmdState = 0;
|
||||
u8 DStatus = 0;
|
||||
enum ReceiveMode CurReceiveMode = Mode_None;
|
||||
u32 FECLock = 0;
|
||||
u16 val;
|
||||
u32 ber;
|
||||
|
||||
read_signal_strength(fe, &val);
|
||||
|
||||
read_snr(fe, &val);
|
||||
|
||||
read_ber(fe, &ber);
|
||||
|
||||
read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &DmdState);
|
||||
|
||||
if (DmdState & 0x40) {
|
||||
@@ -1065,7 +1156,7 @@ static int read_status(struct dvb_frontend *fe, fe_status_t *status)
|
||||
if (state->ReceiveMode == Mode_None) {
|
||||
state->ReceiveMode = CurReceiveMode;
|
||||
state->DemodLockTime = jiffies;
|
||||
state->FirstTimeLock = 0;
|
||||
state->FirstTimeLock = 1;
|
||||
|
||||
write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
|
||||
state->tscfgh);
|
||||
@@ -1259,21 +1350,28 @@ static int sleep(struct dvb_frontend *fe)
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int read_snr(struct dvb_frontend *fe, u16 *snr)
|
||||
{
|
||||
struct stv *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
||||
s32 SNR;
|
||||
|
||||
*snr = 0;
|
||||
if (GetSignalToNoise(state, &SNR))
|
||||
return -EIO;
|
||||
*snr = SNR;
|
||||
p->cnr.len = 1;
|
||||
p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
|
||||
p->cnr.stat[0].uvalue = 100 * (s64) SNR;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int read_ber(struct dvb_frontend *fe, u32 *ber)
|
||||
{
|
||||
struct stv *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
||||
u32 n, d;
|
||||
|
||||
GetBitErrorRate(state, &n, &d);
|
||||
@@ -1281,18 +1379,101 @@ static int read_ber(struct dvb_frontend *fe, u32 *ber)
|
||||
*ber = n / d;
|
||||
else
|
||||
*ber = 0;
|
||||
|
||||
p->pre_bit_error.len = 1;
|
||||
p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
|
||||
p->pre_bit_error.stat[0].uvalue = n;
|
||||
p->pre_bit_count.len = 1;
|
||||
p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
|
||||
p->pre_bit_count.stat[0].uvalue = d;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static s32 Log10x100(u32 x)
|
||||
{
|
||||
static u32 LookupTable[100] = {
|
||||
101157945, 103514217, 105925373, 108392691, 110917482,
|
||||
113501082, 116144861, 118850223, 121618600, 124451461,
|
||||
127350308, 130316678, 133352143, 136458314, 139636836,
|
||||
142889396, 146217717, 149623566, 153108746, 156675107,
|
||||
160324539, 164058977, 167880402, 171790839, 175792361,
|
||||
179887092, 184077200, 188364909, 192752491, 197242274,
|
||||
201836636, 206538016, 211348904, 216271852, 221309471,
|
||||
226464431, 231739465, 237137371, 242661010, 248313311,
|
||||
254097271, 260015956, 266072506, 272270131, 278612117,
|
||||
285101827, 291742701, 298538262, 305492111, 312607937,
|
||||
319889511, 327340695, 334965439, 342767787, 350751874,
|
||||
358921935, 367282300, 375837404, 384591782, 393550075,
|
||||
402717034, 412097519, 421696503, 431519077, 441570447,
|
||||
451855944, 462381021, 473151259, 484172368, 495450191,
|
||||
506990708, 518800039, 530884444, 543250331, 555904257,
|
||||
568852931, 582103218, 595662144, 609536897, 623734835,
|
||||
638263486, 653130553, 668343918, 683911647, 699841996,
|
||||
716143410, 732824533, 749894209, 767361489, 785235635,
|
||||
803526122, 822242650, 841395142, 860993752, 881048873,
|
||||
901571138, 922571427, 944060876, 966050879, 988553095,
|
||||
};
|
||||
s32 y;
|
||||
int i;
|
||||
|
||||
if (x == 0)
|
||||
return 0;
|
||||
y = 800;
|
||||
if (x >= 1000000000) {
|
||||
x /= 10;
|
||||
y += 100;
|
||||
}
|
||||
|
||||
while (x < 100000000) {
|
||||
x *= 10;
|
||||
y -= 100;
|
||||
}
|
||||
i = 0;
|
||||
while (i < 100 && x > LookupTable[i])
|
||||
i += 1;
|
||||
y += i;
|
||||
return y;
|
||||
}
|
||||
|
||||
static int read_signal_strength(struct dvb_frontend *fe, u16 *strength)
|
||||
{
|
||||
struct stv *state = fe->demodulator_priv;
|
||||
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
||||
u8 Agc1, Agc0;
|
||||
u8 Reg[2];
|
||||
s32 bbgain;
|
||||
s32 Power = 0;
|
||||
int i;
|
||||
|
||||
read_reg(state, RSTV0910_P2_AGCIQIN1 + state->regoff, &Agc1);
|
||||
read_reg(state, RSTV0910_P2_AGCIQIN0 + state->regoff, &Agc0);
|
||||
read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, Reg, 2);
|
||||
//KdPrintEx((MSG_INFO "_%d " __FUNCTION__ " AGCIQIN1 = %02x%02x\n",m_Instance,Reg[0],Reg[1]));
|
||||
|
||||
*strength = (((u32) Reg[0]) << 8) | Reg[1];
|
||||
|
||||
for (i = 0; i < 5; i += 1) {
|
||||
read_regs(state, RSTV0910_P2_POWERI + state->regoff, Reg, 2);
|
||||
Power += (u32) Reg[0] * (u32) Reg[0] + (u32) Reg[1] * (u32) Reg[1];
|
||||
msleep(3);
|
||||
}
|
||||
Power /= 5;
|
||||
|
||||
bbgain = (465 - Log10x100(Power)) * 10;
|
||||
|
||||
if (fe->ops.tuner_ops.get_rf_strength)
|
||||
fe->ops.tuner_ops.get_rf_strength(fe, strength);
|
||||
else
|
||||
*strength = 0;
|
||||
|
||||
printk("pwr = %d bb = %d str = %u\n", Power, bbgain, *strength);
|
||||
if (bbgain < (s32) *strength)
|
||||
*strength -= bbgain;
|
||||
else
|
||||
*strength = 0;
|
||||
|
||||
p->strength.len = 1;
|
||||
p->strength.stat[0].scale = FE_SCALE_DECIBEL;
|
||||
p->strength.stat[0].uvalue = 10 * (s64) (s16) *strength - 108750;
|
||||
|
||||
*strength = ((255 - Agc1) * 3300) / 256;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1324,6 +1505,7 @@ static struct dvb_frontend_ops stv0910_ops = {
|
||||
.release = release,
|
||||
.i2c_gate_ctrl = gate_ctrl,
|
||||
.get_frontend_algo = get_algo,
|
||||
.get_frontend = get_frontend,
|
||||
.tune = tune,
|
||||
.read_status = read_status,
|
||||
.set_tone = set_tone,
|
||||
@@ -1362,7 +1544,7 @@ struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c,
|
||||
state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40);
|
||||
state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00;
|
||||
state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4);
|
||||
state->tsspeed = 0x40;
|
||||
state->tsspeed = 0x28;
|
||||
state->nr = nr;
|
||||
state->regoff = state->nr ? 0 : 0x200;
|
||||
state->SearchRange = 16000000;
|
||||
|
@@ -50,6 +50,7 @@ struct stv {
|
||||
|
||||
u8 reg[11];
|
||||
u32 ref_freq;
|
||||
u32 Frequency;
|
||||
};
|
||||
|
||||
static int i2c_read(struct i2c_adapter *adap,
|
||||
@@ -87,14 +88,12 @@ static int write_regs(struct stv *state, int reg, int len)
|
||||
return i2c_write(state->i2c, state->adr, d, len + 1);
|
||||
}
|
||||
|
||||
#if 0
|
||||
static int write_reg(struct stv *state, u8 reg, u8 val)
|
||||
{
|
||||
u8 d[2] = {reg, val};
|
||||
|
||||
return i2c_write(state->i2c, state->adr, d, 2);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int read_reg(struct stv *state, u8 reg, u8 *val)
|
||||
{
|
||||
@@ -298,6 +297,8 @@ static int set_lof(struct stv *state, u32 LocalFrequency, u32 CutOffFrequency)
|
||||
}
|
||||
read_reg(state, 0x08, &tmp);
|
||||
|
||||
state->Frequency = Frequency;
|
||||
|
||||
dump_regs(state);
|
||||
return 0;
|
||||
}
|
||||
@@ -362,21 +363,352 @@ static u32 AGC_Gain[] = {
|
||||
67000, /* 2.9 */
|
||||
};
|
||||
|
||||
struct SLookup {
|
||||
s16 Value;
|
||||
u16 RegValue;
|
||||
};
|
||||
|
||||
|
||||
static struct SLookup LNAGain_NF_LookUp[] = {
|
||||
/*Gain *100dB*/ /*Reg*/
|
||||
{ 2572 , 0 },
|
||||
{ 2575 , 1 },
|
||||
{ 2580 , 2 },
|
||||
{ 2588 , 3 },
|
||||
{ 2596 , 4 },
|
||||
{ 2611 , 5 },
|
||||
{ 2633 , 6 },
|
||||
{ 2664 , 7 },
|
||||
{ 2701 , 8 },
|
||||
{ 2753 , 9 },
|
||||
{ 2816 , 10 },
|
||||
{ 2902 , 11 },
|
||||
{ 2995 , 12 },
|
||||
{ 3104 , 13 },
|
||||
{ 3215 , 14 },
|
||||
{ 3337 , 15 },
|
||||
{ 3492 , 16 },
|
||||
{ 3614 , 17 },
|
||||
{ 3731 , 18 },
|
||||
{ 3861 , 19 },
|
||||
{ 3988 , 20 },
|
||||
{ 4124 , 21 },
|
||||
{ 4253 , 22 },
|
||||
{ 4386 , 23 },
|
||||
{ 4505 , 24 },
|
||||
{ 4623 , 25 },
|
||||
{ 4726 , 26 },
|
||||
{ 4821 , 27 },
|
||||
{ 4903 , 28 },
|
||||
{ 4979 , 29 },
|
||||
{ 5045 , 30 },
|
||||
{ 5102 , 31 }
|
||||
};
|
||||
|
||||
static struct SLookup LNAGain_IIP3_LookUp[] = {
|
||||
/*Gain *100dB*/ /*reg*/
|
||||
{ 1548 , 0 },
|
||||
{ 1552 , 1 },
|
||||
{ 1569 , 2 },
|
||||
{ 1565 , 3 },
|
||||
{ 1577 , 4 },
|
||||
{ 1594 , 5 },
|
||||
{ 1627 , 6 },
|
||||
{ 1656 , 7 },
|
||||
{ 1700 , 8 },
|
||||
{ 1748 , 9 },
|
||||
{ 1805 , 10 },
|
||||
{ 1896 , 11 },
|
||||
{ 1995 , 12 },
|
||||
{ 2113 , 13 },
|
||||
{ 2233 , 14 },
|
||||
{ 2366 , 15 },
|
||||
{ 2543 , 16 },
|
||||
{ 2687 , 17 },
|
||||
{ 2842 , 18 },
|
||||
{ 2999 , 19 },
|
||||
{ 3167 , 20 },
|
||||
{ 3342 , 21 },
|
||||
{ 3507 , 22 },
|
||||
{ 3679 , 23 },
|
||||
{ 3827 , 24 },
|
||||
{ 3970 , 25 },
|
||||
{ 4094 , 26 },
|
||||
{ 4210 , 27 },
|
||||
{ 4308 , 28 },
|
||||
{ 4396 , 29 },
|
||||
{ 4468 , 30 },
|
||||
{ 4535 , 31 }
|
||||
};
|
||||
|
||||
static struct SLookup Gain_RFAGC_LookUp[] = {
|
||||
/*Gain *100dB*/ /*reg*/
|
||||
{ 4870 , 0x3000 },
|
||||
{ 4850 , 0x3C00 },
|
||||
{ 4800 , 0x4500 },
|
||||
{ 4750 , 0x4800 },
|
||||
{ 4700 , 0x4B00 },
|
||||
{ 4650 , 0x4D00 },
|
||||
{ 4600 , 0x4F00 },
|
||||
{ 4550 , 0x5100 },
|
||||
{ 4500 , 0x5200 },
|
||||
{ 4420 , 0x5500 },
|
||||
{ 4316 , 0x5800 },
|
||||
{ 4200 , 0x5B00 },
|
||||
{ 4119 , 0x5D00 },
|
||||
{ 3999 , 0x6000 },
|
||||
{ 3950 , 0x6100 },
|
||||
{ 3876 , 0x6300 },
|
||||
{ 3755 , 0x6600 },
|
||||
{ 3641 , 0x6900 },
|
||||
{ 3567 , 0x6B00 },
|
||||
{ 3425 , 0x6F00 },
|
||||
{ 3350 , 0x7100 },
|
||||
{ 3236 , 0x7400 },
|
||||
{ 3118 , 0x7700 },
|
||||
{ 3004 , 0x7A00 },
|
||||
{ 2917 , 0x7C00 },
|
||||
{ 2776 , 0x7F00 },
|
||||
{ 2635 , 0x8200 },
|
||||
{ 2516 , 0x8500 },
|
||||
{ 2406 , 0x8800 },
|
||||
{ 2290 , 0x8B00 },
|
||||
{ 2170 , 0x8E00 },
|
||||
{ 2073 , 0x9100 },
|
||||
{ 1949 , 0x9400 },
|
||||
{ 1836 , 0x9700 },
|
||||
{ 1712 , 0x9A00 },
|
||||
{ 1631 , 0x9C00 },
|
||||
{ 1515 , 0x9F00 },
|
||||
{ 1400 , 0xA200 },
|
||||
{ 1323 , 0xA400 },
|
||||
{ 1203 , 0xA700 },
|
||||
{ 1091 , 0xAA00 },
|
||||
{ 1011 , 0xAC00 },
|
||||
{ 904 , 0xAF00 },
|
||||
{ 787 , 0xB200 },
|
||||
{ 685 , 0xB500 },
|
||||
{ 571 , 0xB800 },
|
||||
{ 464 , 0xBB00 },
|
||||
{ 374 , 0xBE00 },
|
||||
{ 275 , 0xC200 },
|
||||
{ 181 , 0xC600 },
|
||||
{ 102 , 0xCC00 },
|
||||
{ 49 , 0xD900 }
|
||||
};
|
||||
|
||||
|
||||
// This table is 6 dB too low comapred to the others (probably created with a different BB_MAG setting)
|
||||
static struct SLookup Gain_Channel_AGC_NF_LookUp[] = {
|
||||
/*Gain *100dB*/ /*reg*/
|
||||
{ 7082 , 0x3000 },
|
||||
{ 7052 , 0x4000 },
|
||||
{ 7007 , 0x4600 },
|
||||
{ 6954 , 0x4A00 },
|
||||
{ 6909 , 0x4D00 },
|
||||
{ 6833 , 0x5100 },
|
||||
{ 6753 , 0x5400 },
|
||||
{ 6659 , 0x5700 },
|
||||
{ 6561 , 0x5A00 },
|
||||
{ 6472 , 0x5C00 },
|
||||
{ 6366 , 0x5F00 },
|
||||
{ 6259 , 0x6100 },
|
||||
{ 6151 , 0x6400 },
|
||||
{ 6026 , 0x6700 },
|
||||
{ 5920 , 0x6900 },
|
||||
{ 5835 , 0x6B00 },
|
||||
{ 5770 , 0x6C00 },
|
||||
{ 5681 , 0x6E00 },
|
||||
{ 5596 , 0x7000 },
|
||||
{ 5503 , 0x7200 },
|
||||
{ 5429 , 0x7300 },
|
||||
{ 5319 , 0x7500 },
|
||||
{ 5220 , 0x7700 },
|
||||
{ 5111 , 0x7900 },
|
||||
{ 4983 , 0x7B00 },
|
||||
{ 4876 , 0x7D00 },
|
||||
{ 4755 , 0x7F00 },
|
||||
{ 4635 , 0x8100 },
|
||||
{ 4499 , 0x8300 },
|
||||
{ 4405 , 0x8500 },
|
||||
{ 4323 , 0x8600 },
|
||||
{ 4233 , 0x8800 },
|
||||
{ 4156 , 0x8A00 },
|
||||
{ 4038 , 0x8C00 },
|
||||
{ 3935 , 0x8E00 },
|
||||
{ 3823 , 0x9000 },
|
||||
{ 3712 , 0x9200 },
|
||||
{ 3601 , 0x9500 },
|
||||
{ 3511 , 0x9700 },
|
||||
{ 3413 , 0x9900 },
|
||||
{ 3309 , 0x9B00 },
|
||||
{ 3213 , 0x9D00 },
|
||||
{ 3088 , 0x9F00 },
|
||||
{ 2992 , 0xA100 },
|
||||
{ 2878 , 0xA400 },
|
||||
{ 2769 , 0xA700 },
|
||||
{ 2645 , 0xAA00 },
|
||||
{ 2538 , 0xAD00 },
|
||||
{ 2441 , 0xB000 },
|
||||
{ 2350 , 0xB600 },
|
||||
{ 2237 , 0xBA00 },
|
||||
{ 2137 , 0xBF00 },
|
||||
{ 2039 , 0xC500 },
|
||||
{ 1938 , 0xDF00 },
|
||||
{ 1927 , 0xFF00 }
|
||||
};
|
||||
|
||||
|
||||
static struct SLookup Gain_Channel_AGC_IIP3_LookUp[] = {
|
||||
/*Gain *100dB*/ /*reg*/
|
||||
{ 7070 , 0x3000 },
|
||||
{ 7028 , 0x4000 },
|
||||
{ 7019 , 0x4600 },
|
||||
{ 6900 , 0x4A00 },
|
||||
{ 6811 , 0x4D00 },
|
||||
{ 6763 , 0x5100 },
|
||||
{ 6690 , 0x5400 },
|
||||
{ 6644 , 0x5700 },
|
||||
{ 6617 , 0x5A00 },
|
||||
{ 6598 , 0x5C00 },
|
||||
{ 6462 , 0x5F00 },
|
||||
{ 6348 , 0x6100 },
|
||||
{ 6197 , 0x6400 },
|
||||
{ 6154 , 0x6700 },
|
||||
{ 6098 , 0x6900 },
|
||||
{ 5893 , 0x6B00 },
|
||||
{ 5812 , 0x6C00 },
|
||||
{ 5773 , 0x6E00 },
|
||||
{ 5723 , 0x7000 },
|
||||
{ 5661 , 0x7200 },
|
||||
{ 5579 , 0x7300 },
|
||||
{ 5460 , 0x7500 },
|
||||
{ 5308 , 0x7700 },
|
||||
{ 5099 , 0x7900 },
|
||||
{ 4910 , 0x7B00 },
|
||||
{ 4800 , 0x7D00 },
|
||||
{ 4785 , 0x7F00 },
|
||||
{ 4635 , 0x8100 },
|
||||
{ 4466 , 0x8300 },
|
||||
{ 4314 , 0x8500 },
|
||||
{ 4295 , 0x8600 },
|
||||
{ 4144 , 0x8800 },
|
||||
{ 3920 , 0x8A00 },
|
||||
{ 3889 , 0x8C00 },
|
||||
{ 3771 , 0x8E00 },
|
||||
{ 3655 , 0x9000 },
|
||||
{ 3446 , 0x9200 },
|
||||
{ 3298 , 0x9500 },
|
||||
{ 3083 , 0x9700 },
|
||||
{ 3015 , 0x9900 },
|
||||
{ 2833 , 0x9B00 },
|
||||
{ 2746 , 0x9D00 },
|
||||
{ 2632 , 0x9F00 },
|
||||
{ 2598 , 0xA100 },
|
||||
{ 2480 , 0xA400 },
|
||||
{ 2236 , 0xA700 },
|
||||
{ 2171 , 0xAA00 },
|
||||
{ 2060 , 0xAD00 },
|
||||
{ 1999 , 0xB000 },
|
||||
{ 1974 , 0xB600 },
|
||||
{ 1820 , 0xBA00 },
|
||||
{ 1741 , 0xBF00 },
|
||||
{ 1655 , 0xC500 },
|
||||
{ 1444 , 0xDF00 },
|
||||
{ 1325 , 0xFF00 },
|
||||
};
|
||||
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
static s32 TableLookup(struct SLookup *Table, int TableSize, u16 RegValue)
|
||||
{
|
||||
s32 Gain;
|
||||
s32 RegDiff;
|
||||
int imin = 0;
|
||||
int imax = TableSize - 1;
|
||||
int i;
|
||||
|
||||
// Assumes Table[0].RegValue < Table[imax].RegValue
|
||||
if( RegValue <= Table[0].RegValue )
|
||||
Gain = Table[0].Value;
|
||||
else if( RegValue >= Table[imax].RegValue )
|
||||
Gain = Table[imax].Value;
|
||||
else {
|
||||
while(imax-imin > 1) {
|
||||
i = (imax + imin) / 2;
|
||||
if ((Table[imin].RegValue <= RegValue) &&
|
||||
(RegValue <= Table[i].RegValue) )
|
||||
imax = i;
|
||||
else
|
||||
imin = i;
|
||||
}
|
||||
RegDiff = Table[imax].RegValue - Table[imin].RegValue;
|
||||
Gain = Table[imin].Value;
|
||||
if (RegDiff != 0)
|
||||
Gain += ((s32) (RegValue - Table[imin].RegValue) *
|
||||
(s32)(Table[imax].Value - Table[imin].Value))/(RegDiff);
|
||||
}
|
||||
return Gain;
|
||||
}
|
||||
|
||||
static int get_rf_strength(struct dvb_frontend *fe, u16 *st)
|
||||
{
|
||||
*st = 0;
|
||||
#if 0
|
||||
struct stv *state = fe->tuner_priv;
|
||||
u16 RFAgc = *st;
|
||||
s32 Gain;
|
||||
u32 Index = RFAgc / 100;
|
||||
if (Index >= (sizeof(AGC_Gain) / sizeof(AGC_Gain[0]) - 1))
|
||||
Gain = AGC_Gain[sizeof(AGC_Gain) / sizeof(AGC_Gain[0]) - 1];
|
||||
else
|
||||
Gain = AGC_Gain[Index] +
|
||||
((AGC_Gain[Index+1] - AGC_Gain[Index]) *
|
||||
(RFAgc % 100)) / 100;
|
||||
*st = Gain;
|
||||
#endif
|
||||
|
||||
if ((state->reg[0x03] & 0x60) == 0 ) {
|
||||
// RF Mode
|
||||
// Read AGC ADC
|
||||
u8 Reg = 0;
|
||||
|
||||
if (fe->ops.i2c_gate_ctrl)
|
||||
fe->ops.i2c_gate_ctrl(fe, 1);
|
||||
write_reg(state, 0x02, state->reg[0x02] | 0x20);
|
||||
read_reg(state, 2, &Reg);
|
||||
if( Reg & 0x20 )
|
||||
read_reg(state, 2, &Reg);
|
||||
if (fe->ops.i2c_gate_ctrl)
|
||||
fe->ops.i2c_gate_ctrl(fe, 0);
|
||||
|
||||
if((state->reg[0x02] & 0x80) == 0)
|
||||
// NF
|
||||
Gain = TableLookup(LNAGain_NF_LookUp,
|
||||
ARRAY_SIZE(LNAGain_NF_LookUp), Reg & 0x1F);
|
||||
else
|
||||
// IIP3
|
||||
Gain = TableLookup(LNAGain_IIP3_LookUp,
|
||||
ARRAY_SIZE(LNAGain_IIP3_LookUp), Reg & 0x1F);
|
||||
Gain += TableLookup(Gain_RFAGC_LookUp,
|
||||
ARRAY_SIZE(Gain_RFAGC_LookUp), RFAgc);
|
||||
Gain -= 2400;
|
||||
} else {
|
||||
// Channel Mode
|
||||
if( (state->reg[0x02] & 0x80) == 0 ) {
|
||||
// NF
|
||||
Gain = TableLookup(Gain_Channel_AGC_NF_LookUp,
|
||||
ARRAY_SIZE(Gain_Channel_AGC_NF_LookUp), RFAgc);
|
||||
Gain += 600;
|
||||
} else {
|
||||
// IIP3
|
||||
Gain = TableLookup(Gain_Channel_AGC_IIP3_LookUp,
|
||||
ARRAY_SIZE(Gain_Channel_AGC_IIP3_LookUp), RFAgc);
|
||||
}
|
||||
}
|
||||
|
||||
if (state->Frequency > 0)
|
||||
// Tilt correction ( 0.00016 dB/MHz )
|
||||
Gain -= ((((s32)(state->Frequency / 1000) - 1550) * 2) / 12);
|
||||
|
||||
Gain += (s32)( (state->reg[0x01] & 0xC0 ) >> 6 ) * 600 - 1300;// + (BBGain * 10);
|
||||
|
||||
if( Gain < 0 )
|
||||
Gain = 0;
|
||||
else if (Gain > 10000)
|
||||
Gain = 10000;
|
||||
|
||||
*st = 10000 - Gain;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@@ -780,7 +780,7 @@ static int sleep(struct dvb_frontend *fe)
|
||||
write_reg(state, THERMO_2, 0x01);
|
||||
read_reg1(state, THERMO_1);
|
||||
write_reg(state, THERMO_2, 0x00);
|
||||
printk("sleep: temp = %u\n", state->Regs[THERMO_1]);
|
||||
/* printk("sleep: temp = %u\n", state->Regs[THERMO_1]); */
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@@ -165,6 +165,8 @@ typedef enum fe_code_rate {
|
||||
FEC_3_5,
|
||||
FEC_9_10,
|
||||
FEC_2_5,
|
||||
FEC_1_4,
|
||||
FEC_1_3,
|
||||
} fe_code_rate_t;
|
||||
|
||||
|
||||
|
Reference in New Issue
Block a user