bump version to 0.9.30

Build against specified kernel version (dkms ... -k VERSION) or against current running (uname -r) if not specified

CHANGELOG

@@ -1,3 +1,7 @@
+0.9.29 compiles with most kernels up to 4.11.1
+
+see git commit messages for newer changes
+
 0.9.24 2016.08.03
 - suport new V2 modulator cards
 

Makefile

@@ -1,4 +1,5 @@
-KDIR	?= /lib/modules/$(shell uname -r)/build
+kernelver ?= $(shell uname -r)
+KDIR	?= /lib/modules/$(kernelver)/build
 PWD	:= $(shell pwd)
 
 MODDEFS := CONFIG_DVB_CORE=m CONFIG_DVB_DDBRIDGE=m CONFIG_DVB_DRXK=m CONFIG_DVB_TDA18271C2DD=m CONFIG_DVB_CXD2099=m CONFIG_DVB_LNBP21=m  CONFIG_DVB_STV090x=m CONFIG_DVB_STV6110x=m CONFIG_DVB_STV0367=m CONFIG_DVB_TDA18212=m CONFIG_DVB_STV0367DD=m CONFIG_DVB_TDA18212DD=m CONFIG_DVB_OCTONET=m CONFIG_DVB_CXD2843=m CONFIG_DVB_STV0910=m CONFIG_DVB_STV6111=m CONFIG_DVB_LNBH25=m CONFIG_DVB_MXL5XX=m
@@ -14,6 +15,6 @@ install: all
 	$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules_install
 
 clean:
-	rm -rf */*.o */*.ko */*.mod.c */.*.cmd .tmp_versions Module* modules*
+	rm -rf */.*.o.d */*.o */*.ko */*.mod.c */.*.cmd .tmp_versions Module* modules*
 
 

README.md

@@ -1,10 +1,13 @@
 # DDBridge Driver
 
-###Prepare for Building
+### Patches
+We can only accept patches which don't break compilation for older kernels (as far back as 2.6.37).
+
+### Prepare for Building
 
    TBD
   
-###Building
+### Building
 
    TBD
   

apps/Makefile

@@ -1,22 +1,22 @@
 all: cit citin flashprog modt ddtest setmod ddflash setmod2
 
 cit: cit.c
-	gcc -o cit cit.c -lpthread
+	$(CC) -o cit cit.c -lpthread
 
 modt: modt.c
-	gcc -o modt modt.c -lpthread
+	$(CC) -o modt modt.c -lpthread
 
 setmod: setmod.c
-	gcc -o setmod setmod.c -I../include/
+	$(CC) -o setmod setmod.c -I../include/
 
 setmod2: setmod2.c
-	gcc -o setmod2 setmod2.c -I../include/
+	$(CC) -o setmod2 setmod2.c -I../include/
 
 flashprog: flashprog.c
-	gcc -o flashprog flashprog.c
+	$(CC) -o flashprog flashprog.c
 
 ddtest: ddtest.c
-	gcc -o ddtest ddtest.c
+	$(CC) -o ddtest ddtest.c
 
 ddflash: ddflash.c
-	gcc -o ddflash ddflash.c
+	$(CC) -o ddflash ddflash.c

apps/cit.c

@@ -91,8 +91,13 @@ void *get_ts(void *a)
 	if (!buf)
 		return NULL;
 	sprintf(fname, "/dev/dvb/adapter%u/ci%u", adapter, device);
+	printf("using %s for reading\n", fname);
 	fdi = open(fname, O_RDONLY);
-
+	if (fdi == -1) {
+		printf("Failed to open %s for read: %m\n", fname);
+		return NULL;
+	}
+	 
 	while (1) {
 		memset(buf, 0, 188*rnum);
 		len=read(fdi, buf, 188*rnum);
@@ -122,7 +127,12 @@ int send(void)
 	if (!buf)
 		return -1;
 	sprintf(fname, "/dev/dvb/adapter%u/ci%u", adapter, device);
+	printf("using %s for writing\n", fname);
 	fdo=open(fname, O_WRONLY);
+	if (fdo == -1) {
+		printf("Failed to open %s to write: %m\n", fname);
+		exit(2);
+	}
 
 	while (1) {
 		for (i=0; i<snum; i++) {
@@ -146,7 +156,7 @@ int send(void)
 int main(int argc, char **argv)
 {
 	pthread_t th;
-	
+
 	while (1) {
                 int option_index = 0;
 		int c;
@@ -178,6 +188,8 @@ int main(int argc, char **argv)
 			rnum = strtoul(optarg, NULL, 10);
 			break;
 		case 'h':
+			printf("cit -a<adapter> -d<device>\n");
+			exit(-1);
 		default:
 			break;
 			
@@ -186,6 +198,7 @@ int main(int argc, char **argv)
 	if (optind < argc) {
 		printf("Warning: unused arguments\n");
 	}
+	printf("adapter %d, device: %d\n", adapter, device);
 	memset(ts+8, 180, 0x5a);
 	pthread_create(&th, NULL, get_ts, NULL);
 	usleep(10000);

apps/flashprog.c

@@ -210,9 +210,13 @@ int main(int argc, char **argv)
 			printf("Octopus 35\n");
 			break;
 		case 0x0003:
-			fname="DVBBridgeV1B_DVBBridgeV1B.bit";
+			fname="DVBBridgeV1B_DVBBridgeV1B.fpga";
 			printf("Octopus\n");
 			break;
+		case 0x0005:
+			fname="DVBBridgeV2A_DD01_0005_STD.fpga";
+			printf("Octopus Classic\n");
+			break;
 		case 0x0006:
 			fname="DVBBridgeV2A_DD01_0006_STD.fpga";
 			printf("CineS2 V7\n");
@@ -249,6 +253,10 @@ int main(int argc, char **argv)
 			fname="DVBModulatorV2A_DD01_0210.fpga";
 			printf("Modulator V2\n");
 			break;
+		case 0x0220:
+			fname="SDRModulatorV1A_DD01_0220.fpga";
+			printf("SDRModulator\n");
+			break;
 		default:
 			printf("UNKNOWN\n");
 			break;
@@ -314,6 +322,7 @@ int main(int argc, char **argv)
 		err = FlashWritePageMode(ddb,FlashOffset,buffer,BufferSize,0x3C);
 		break;
         case SPANSION_S25FL116K:
+        case SPANSION_S25FL164K:
 		err = FlashWritePageMode(ddb,FlashOffset,buffer,BufferSize,0x1C);
 		break;            
 	}

apps/octonet/ddflash.c

@@ -426,7 +426,7 @@ static int flash_detect(struct ddflash *ddf)
 	}
 	if (ddf->sector_size) {
 		ddf->buffer = malloc(ddf->sector_size);
-		printf("allocated buffer %08x@%08x\n", ddf->sector_size, (uint32_t) ddf->buffer);
+		//printf("allocated buffer %08x@%08x\n", ddf->sector_size, (uint32_t) ddf->buffer);
 		if (!ddf->buffer)
 			return -1;
 	}
@@ -510,7 +510,12 @@ static int check_fw(struct ddflash *ddf, char *fn, uint32_t *fw_off)
 				goto out;
 			}
 		} else if (!strcasecmp(key, "Version")) {
-			sscanf(val, "%x", &version);
+			if (strchr(val,'.')) {
+				int major = 0, minor = 0;
+				sscanf(val,"%d.%d",&major,&minor);
+				version = (major << 16) + minor;
+			} else
+				sscanf(val, "%x", &version);
 		} else if (!strcasecmp(key, "Length")) {
 			sscanf(val, "%u", &length);
 		} 
@@ -565,8 +570,13 @@ static int update_image(struct ddflash *ddf, char *fn,
 	if (res < 0) 
 		goto out;
 	res = flashwrite(ddf, fs, adr, len, fw_off);
-	if (res == 0)
-		res = 1;
+	if (res == 0) {
+		res = flashcmp(ddf, fs, adr, len, fw_off);
+		if (res == -2) {
+			res = 1;
+		}
+	}
+ 
 out:
 	close(fs);
 	return res;
@@ -607,18 +617,40 @@ static int update_flash(struct ddflash *ddf)
 				if ((res = update_image(ddf, "/boot/fpga.img", 0x10000, 0xa0000, 1, 0)) == 1)
 					stat |= 1;
 		} else {
-			if ((res = update_image(ddf, "/config/fpga.img", 0x10000, 0xa0000, 1, 1)) == 1)
-				stat |= 1;
-			if (res == -1)
-				if ((res = update_image(ddf, "/boot/fpga.img", 0x10000, 0xa0000, 1, 1)) == 1)
-					stat |= 1;
-			if (res == -1)
-				if ((res = update_image(ddf, "/config/fpga_gtl.img", 0x10000, 0xa0000, 1, 1)) == 1)
-					stat |= 1;
-			if (res == -1)
-				if ((res = update_image(ddf, "/boot/fpga_gtl.img", 0x10000, 0xa0000, 1, 1)) == 1)
+			if (ddf->id.device == 0x0307) {
+				if (res == -1)
+					if ((res = update_image(ddf, "/config/fpga_gtl.img", 0x10000, 0xa0000, 1, 1)) == 1)
+						stat |= 1;
+				if (res == -1)
+					if ((res = update_image(ddf, "/boot/fpga_gtl.img", 0x10000, 0xa0000, 1, 1)) == 1)
+						stat |= 1;
+			} else {
+				if ((res = update_image(ddf, "/config/fpga.img", 0x10000, 0xa0000, 1, 1)) == 1)
 					stat |= 1;
+				if (res == -1)
+					if ((res = update_image(ddf, "/boot/fpga.img", 0x10000, 0xa0000, 1, 1)) == 1)
+						stat |= 1;
+			}
 		}
+#if 1
+		if ( (stat&1) && (ddf->id.hw & 0xffffff) <= 0x010001) {		
+			if (ddf->id.device == 0x0307) {
+				if ((res = update_image(ddf, "/config/fpga_gtl.img", 0x160000, 0x80000, 1, 0)) == 1)
+					stat |= 1;
+				if (res == -1)
+					if ((res = update_image(ddf, "/boot/fpga_gtl.img", 0x160000, 0x80000, 1, 0)) == 1)
+						stat |= 1;
+			} else {
+				if ((res = update_image(ddf, "/config/fpga.img", 0x160000, 0x80000, 1, 0)) == 1)
+					stat |= 1;
+				if (res == -1)
+					if ((res = update_image(ddf, "/boot/fpga.img", 0x160000, 0x80000, 1, 0)) == 1)
+						stat |= 1;
+			
+			}
+		}
+#endif
+
 		break;
 	case 0x320:
 		//fname="/boot/DVBNetV1A_DD01_0300.bit";

ddbridge/ddbridge-hw.c

@@ -0,0 +1,704 @@
+/*
+ * ddbridge.c: Digital Devices PCIe bridge driver
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ *                         Ralph Metzler <rjkm@metzlerbros.de>
+ *                         Marcus Metzler <mocm@metzlerbros.de>
+ *
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 only, as published by the Free Software Foundation.
+ *
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA
+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "ddbridge.h"
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+static struct ddb_regset octopus_mod_odma = {
+	.base = 0x300,
+	.num  = 0x0a,
+	.size = 0x10,
+};
+
+static struct ddb_regset octopus_mod_odma_buf = {
+	.base = 0x2000,
+	.num  = 0x0a,
+	.size = 0x100,
+};
+
+static struct ddb_regset octopus_mod_channel = {
+	.base = 0x400,
+	.num  = 0x0a,
+	.size = 0x40,
+};
+
+/****************************************************************************/
+
+static struct ddb_regset octopus_mod_2_odma = {
+	.base = 0x400,
+	.num  = 0x18,
+	.size = 0x10,
+};
+
+static struct ddb_regset octopus_mod_2_odma_buf = {
+	.base = 0x8000,
+	.num  = 0x18,
+	.size = 0x100,
+};
+
+static struct ddb_regset octopus_mod_2_channel = {
+	.base = 0x800,
+	.num  = 0x18,
+	.size = 0x40,
+};
+
+static struct ddb_regset octopus_sdr_output = {
+	.base = 0x240,
+	.num  = 0x14,
+	.size = 0x10,
+};
+
+/****************************************************************************/
+
+static struct ddb_regset octopus_input = {
+	.base = 0x200,
+	.num  = 0x08,
+	.size = 0x10,
+};
+
+static struct ddb_regset octopus_output = {
+	.base = 0x280,
+	.num  = 0x08,
+	.size = 0x10,
+};
+
+static struct ddb_regset octopus_idma = {
+	.base = 0x300,
+	.num  = 0x08,
+	.size = 0x10,
+};
+
+static struct ddb_regset octopus_idma_buf = {
+	.base = 0x2000,
+	.num  = 0x08,
+	.size = 0x100,
+};
+
+static struct ddb_regset octopus_odma = {
+	.base = 0x380,
+	.num  = 0x04,
+	.size = 0x10,
+};
+
+static struct ddb_regset octopus_odma_buf = {
+	.base = 0x2800,
+	.num  = 0x04,
+	.size = 0x100,
+};
+
+static struct ddb_regset octopus_i2c = {
+	.base = 0x80,
+	.num  = 0x04,
+	.size = 0x20,
+};
+
+static struct ddb_regset octopus_i2c_buf = {
+	.base = 0x1000,
+	.num  = 0x04,
+	.size = 0x200,
+};
+
+/****************************************************************************/
+
+static struct ddb_regset octopro_input = {
+	.base = 0x400,
+	.num  = 0x14,
+	.size = 0x10,
+};
+
+static struct ddb_regset octopro_output = {
+	.base = 0x600,
+	.num  = 0x0a,
+	.size = 0x10,
+};
+
+static struct ddb_regset octopro_idma = {
+	.base = 0x800,
+	.num  = 0x40,
+	.size = 0x10,
+};
+
+static struct ddb_regset octopro_idma_buf = {
+	.base = 0x4000,
+	.num  = 0x40,
+	.size = 0x100,
+};
+
+static struct ddb_regset octopro_odma = {
+	.base = 0xc00,
+	.num  = 0x20,
+	.size = 0x10,
+};
+
+static struct ddb_regset octopro_odma_buf = {
+	.base = 0x8000,
+	.num  = 0x20,
+	.size = 0x100,
+};
+
+static struct ddb_regset octopro_i2c = {
+	.base = 0x200,
+	.num  = 0x0a,
+	.size = 0x20,
+};
+
+static struct ddb_regset octopro_i2c_buf = {
+	.base = 0x2000,
+	.num  = 0x0a,
+	.size = 0x200,
+};
+
+static struct ddb_regset octopro_gtl = {
+	.base = 0xe00,
+	.num  = 0x03,
+	.size = 0x40,
+};
+
+/****************************************************************************/
+/****************************************************************************/
+
+
+static struct ddb_regmap octopus_map = {
+	.irq_version = 1,
+	.irq_base_i2c = 0,
+	.irq_base_idma = 8,
+	.irq_base_odma = 16,
+	.i2c = &octopus_i2c,
+	.i2c_buf = &octopus_i2c_buf,
+	.idma = &octopus_idma,
+	.idma_buf = &octopus_idma_buf,
+	.odma = &octopus_odma,
+	.odma_buf = &octopus_odma_buf,
+	.input = &octopus_input,
+	.output = &octopus_output,
+};
+
+static struct ddb_regmap octopro_map = {
+	.irq_version = 2,
+	.irq_base_i2c = 32,
+	.irq_base_idma = 64,
+	.irq_base_odma = 128,
+	.irq_base_gtl = 8,
+	.i2c = &octopro_i2c,
+	.i2c_buf = &octopro_i2c_buf,
+	.idma = &octopro_idma,
+	.idma_buf = &octopro_idma_buf,
+	.odma = &octopro_odma,
+	.odma_buf = &octopro_odma_buf,
+	.input = &octopro_input,
+	.output = &octopro_output,
+	.gtl = &octopro_gtl,
+};
+
+static struct ddb_regmap octopro_hdin_map = {
+	.irq_version = 2,
+	.irq_base_i2c = 32,
+	.irq_base_idma = 64,
+	.irq_base_odma = 128,
+	.i2c = &octopro_i2c,
+	.i2c_buf = &octopro_i2c_buf,
+	.idma = &octopro_idma,
+	.idma_buf = &octopro_idma_buf,
+	.odma = &octopro_odma,
+	.odma_buf = &octopro_odma_buf,
+	.input = &octopro_input,
+	.output = &octopro_output,
+};
+
+static struct ddb_regmap octopus_mod_map = {
+	.irq_version = 1,
+	.irq_base_odma = 8,
+	.irq_base_rate = 18,
+	.output = &octopus_output,
+	.odma = &octopus_mod_odma,
+	.odma_buf = &octopus_mod_odma_buf,
+	.channel = &octopus_mod_channel,
+};
+
+static struct ddb_regmap octopus_mod_2_map = {
+	.irq_version = 2,
+	.irq_base_odma = 64,
+	.irq_base_rate = 32,
+	.output = &octopus_output,
+	.odma = &octopus_mod_2_odma,
+	.odma_buf = &octopus_mod_2_odma_buf,
+	.channel = &octopus_mod_2_channel,
+};
+
+static struct ddb_regmap octopus_sdr_map = {
+	.irq_version = 2,
+	.irq_base_odma = 64,
+	.irq_base_rate = 32,
+	.output = &octopus_sdr_output,
+	.odma = &octopus_mod_2_odma,
+	.odma_buf = &octopus_mod_2_odma_buf,
+	.channel = &octopus_mod_2_channel,
+};
+
+
+/****************************************************************************/
+/****************************************************************************/
+
+static struct ddb_info ddb_none = {
+	.type     = DDB_NONE,
+	.name     = "unknown Digital Devices device, install newer driver",
+	.regmap   = &octopus_map,
+};
+
+static struct ddb_info ddb_octopus = {
+	.type     = DDB_OCTOPUS,
+	.name     = "Digital Devices Octopus DVB adapter",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+};
+
+static struct ddb_info ddb_octopusv3 = {
+	.type     = DDB_OCTOPUS,
+	.name     = "Digital Devices Octopus V3 DVB adapter",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+};
+
+static struct ddb_info ddb_octopus_le = {
+	.type     = DDB_OCTOPUS,
+	.name     = "Digital Devices Octopus LE DVB adapter",
+	.regmap   = &octopus_map,
+	.port_num = 2,
+	.i2c_mask = 0x03,
+};
+
+static struct ddb_info ddb_octopus_oem = {
+	.type     = DDB_OCTOPUS,
+	.name     = "Digital Devices Octopus OEM",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.led_num  = 1,
+	.fan_num  = 1,
+	.temp_num = 1,
+	.temp_bus = 0,
+};
+
+static struct ddb_info ddb_octopus_mini = {
+	.type     = DDB_OCTOPUS,
+	.name     = "Digital Devices Octopus Mini",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+};
+
+static struct ddb_info ddb_v6 = {
+	.type     = DDB_OCTOPUS,
+	.name     = "Digital Devices Cine S2 V6 DVB adapter",
+	.regmap   = &octopus_map,
+	.port_num = 3,
+	.i2c_mask = 0x07,
+};
+
+static struct ddb_info ddb_v6_5 = {
+	.type     = DDB_OCTOPUS,
+	.name     = "Digital Devices Cine S2 V6.5 DVB adapter",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+};
+
+static struct ddb_info ddb_v7a = {
+	.type     = DDB_OCTOPUS,
+	.name     = "Digital Devices Cine S2 V7 Advanced DVB adapter",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.board_control   = 2,
+	.board_control_2 = 4,
+	.ts_quirks = TS_QUIRK_REVERSED,
+};
+
+static struct ddb_info ddb_v7 = {
+	.type     = DDB_OCTOPUS,
+	.name     = "Digital Devices Cine S2 V7 DVB adapter",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.board_control   = 2,
+	.board_control_2 = 4,
+	.ts_quirks = TS_QUIRK_REVERSED,
+};
+
+static struct ddb_info ddb_ctv7 = {
+	.type     = DDB_OCTOPUS,
+	.name     = "Digital Devices Cine CT V7 DVB adapter",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.board_control   = 3,
+	.board_control_2 = 4,
+};
+
+static struct ddb_info ddb_satixS2v3 = {
+	.type     = DDB_OCTOPUS,
+	.name     = "Mystique SaTiX-S2 V3 DVB adapter",
+	.regmap   = &octopus_map,
+	.port_num = 3,
+	.i2c_mask = 0x07,
+};
+
+static struct ddb_info ddb_ci = {
+	.type     = DDB_OCTOPUS_CI,
+	.name     = "Digital Devices Octopus CI",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x03,
+};
+
+static struct ddb_info ddb_cis = {
+	.type     = DDB_OCTOPUS_CI,
+	.name     = "Digital Devices Octopus CI single",
+	.regmap   = &octopus_map,
+	.port_num = 3,
+	.i2c_mask = 0x03,
+};
+
+static struct ddb_info ddb_ci_s2_pro = {
+	.type     = DDB_OCTOPUS_CI,
+	.name     = "Digital Devices Octopus CI S2 Pro",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x01,
+	.board_control   = 2,
+	.board_control_2 = 4,
+};
+
+static struct ddb_info ddb_ci_s2_pro_a = {
+	.type     = DDB_OCTOPUS_CI,
+	.name     = "Digital Devices Octopus CI S2 Pro Advanced",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x01,
+	.board_control   = 2,
+	.board_control_2 = 4,
+};
+
+static struct ddb_info ddb_dvbct = {
+	.type     = DDB_OCTOPUS,
+	.name     = "Digital Devices DVBCT V6.1 DVB adapter",
+	.regmap   = &octopus_map,
+	.port_num = 3,
+	.i2c_mask = 0x07,
+};
+
+/****************************************************************************/
+
+static struct ddb_info ddb_mod = {
+	.type     = DDB_MOD,
+	.name     = "Digital Devices DVB-C modulator",
+	.regmap   = &octopus_mod_map,
+	.port_num = 10,
+	.temp_num = 1,
+};
+
+static struct ddb_info ddb_mod_fsm_24 = {
+	.type     = DDB_MOD,
+	.version  = 2,
+	.name     = "Digital Devices DVB-C modulator FSM-24",
+	.regmap   = &octopus_mod_2_map,
+	.port_num = 24,
+	.temp_num = 1,
+	.tempmon_irq = 8,
+};
+
+static struct ddb_info ddb_mod_fsm_16 = {
+	.type     = DDB_MOD,
+	.version  = 2,
+	.name     = "Digital Devices DVB-C modulator FSM-16",
+	.regmap   = &octopus_mod_2_map,
+	.port_num = 16,
+	.temp_num = 1,
+	.tempmon_irq = 8,
+};
+
+static struct ddb_info ddb_mod_fsm_8 = {
+	.type     = DDB_MOD,
+	.name     = "Digital Devices DVB-C modulator FSM-8",
+	.version  = 2,
+	.regmap   = &octopus_mod_2_map,
+	.port_num = 8,
+	.temp_num = 1,
+	.tempmon_irq = 8,
+};
+
+static struct ddb_info ddb_sdr = {
+	.type     = DDB_MOD,
+	.name     = "Digital Devices SDR",
+	.version  = 3,
+	.regmap   = &octopus_sdr_map,
+	.port_num = 16,
+	.temp_num = 1,
+	.tempmon_irq = 8,
+};
+
+static struct ddb_info ddb_octopro_hdin = {
+	.type     = DDB_OCTOPRO_HDIN,
+	.name     = "Digital Devices OctopusNet Pro HDIN",
+	.regmap   = &octopro_hdin_map,
+	.port_num = 10,
+	.i2c_mask = 0x3ff,
+	.mdio_num = 1,
+};
+
+static struct ddb_info ddb_octopro = {
+	.type     = DDB_OCTOPRO,
+	.name     = "Digital Devices OctopusNet Pro",
+	.regmap   = &octopro_map,
+	.port_num = 10,
+	.i2c_mask = 0x3ff,
+	.mdio_num = 1,
+};
+
+
+static struct ddb_info ddb_s2_48 = {
+	.type     = DDB_OCTOPUS_MAX,
+	.name     = "Digital Devices MAX S8 4/8",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x01,
+	.board_control = 1,
+	.tempmon_irq = 24,
+};
+
+static struct ddb_info ddb_ct2_8 = {
+	.type     = DDB_OCTOPUS_MAX_CT,
+	.name     = "Digital Devices MAX A8 CT2",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.board_control   = 0x0ff,
+	.board_control_2 = 0xf00,
+	.ts_quirks = TS_QUIRK_SERIAL,
+	.tempmon_irq = 24,
+};
+
+static struct ddb_info ddb_c2t2_8 = {
+	.type     = DDB_OCTOPUS_MAX_CT,
+	.name     = "Digital Devices MAX A8 C2T2",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.board_control   = 0x0ff,
+	.board_control_2 = 0xf00,
+	.ts_quirks = TS_QUIRK_SERIAL,
+	.tempmon_irq = 24,
+};
+
+static struct ddb_info ddb_isdbt_8 = {
+	.type     = DDB_OCTOPUS_MAX_CT,
+	.name     = "Digital Devices MAX A8 ISDBT",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.board_control   = 0x0ff,
+	.board_control_2 = 0xf00,
+	.ts_quirks = TS_QUIRK_SERIAL,
+	.tempmon_irq = 24,
+};
+
+static struct ddb_info ddb_c2t2i_v0_8 = {
+	.type     = DDB_OCTOPUS_MAX_CT,
+	.name     = "Digital Devices MAX A8 C2T2I V0",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.board_control   = 0x0ff,
+	.board_control_2 = 0xf00,
+	.ts_quirks = TS_QUIRK_SERIAL | TS_QUIRK_ALT_OSC,
+	.tempmon_irq = 24,
+};
+
+static struct ddb_info ddb_c2t2i_8 = {
+	.type     = DDB_OCTOPUS_MAX_CT,
+	.name     = "Digital Devices MAX A8 C2T2I",
+	.regmap   = &octopus_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.board_control   = 0x0ff,
+	.board_control_2 = 0xf00,
+	.ts_quirks = TS_QUIRK_SERIAL,
+	.tempmon_irq = 24,
+};
+
+
+/****************************************************************************/
+/****************************************************************************/
+
+static struct ddb_regmap octopus_net_map = {
+	.irq_version = 1,
+	.irq_base_i2c = 0,
+	.i2c = &octopus_i2c,
+	.i2c_buf = &octopus_i2c_buf,
+	.input = &octopus_input,
+	.output = &octopus_output,
+};
+
+
+static struct ddb_regset octopus_gtl = {
+	.base = 0x180,
+	.num  = 0x01,
+	.size = 0x20,
+};
+
+static struct ddb_regmap octopus_net_gtl = {
+	.irq_version = 1,
+	.irq_base_i2c = 0,
+	.irq_base_gtl = 10,
+	.i2c = &octopus_i2c,
+	.i2c_buf = &octopus_i2c_buf,
+	.input = &octopus_input,
+	.output = &octopus_output,
+	.gtl = &octopus_gtl,
+};
+
+static struct ddb_info ddb_octonet = {
+	.type     = DDB_OCTONET,
+	.name     = "Digital Devices OctopusNet network DVB adapter",
+	.regmap   = &octopus_net_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.ns_num   = 12,
+	.mdio_num = 1,
+};
+
+static struct ddb_info ddb_octonet_jse = {
+	.type     = DDB_OCTONET,
+	.name     = "Digital Devices OctopusNet network DVB adapter JSE",
+	.regmap   = &octopus_net_map,
+	.port_num = 4,
+	.i2c_mask = 0x0f,
+	.ns_num   = 15,
+	.mdio_num = 1,
+};
+
+static struct ddb_info ddb_octonet_gtl = {
+	.type     = DDB_OCTONET,
+	.name     = "Digital Devices OctopusNet GTL",
+	.regmap   = &octopus_net_gtl,
+	.port_num = 4,
+	.i2c_mask = 0x05,
+	.ns_num   = 12,
+	.mdio_num = 1,
+	.con_clock = 1,
+};
+
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+struct ddb_device_id {
+	u16 vendor;
+	u16 device;
+	u16 subvendor;
+	u16 subdevice;
+	struct ddb_info *info;
+};
+
+#define DDB_DEVID(_device, _subdevice, _info) { \
+		.vendor = 0xdd01, \
+		.device = _device, \
+		.subvendor = 0xdd01, \
+		.subdevice = _subdevice, \
+		.info = &_info }
+
+static struct ddb_device_id ddb_device_ids[] = {
+	/* OctopusNet */
+	DDB_DEVID(0x0300, 0xffff, ddb_octonet),
+	DDB_DEVID(0x0301, 0xffff, ddb_octonet_jse),
+	DDB_DEVID(0x0307, 0xffff, ddb_octonet_gtl),
+	/* PCIe devices */
+	DDB_DEVID(0x0002, 0x0001, ddb_octopus),
+	DDB_DEVID(0x0003, 0x0001, ddb_octopus),
+	DDB_DEVID(0x0005, 0x0004, ddb_octopusv3),
+	DDB_DEVID(0x0003, 0x0002, ddb_octopus_le),
+	DDB_DEVID(0x0003, 0x0003, ddb_octopus_oem),
+	DDB_DEVID(0x0003, 0x0010, ddb_octopus_mini),
+	DDB_DEVID(0x0005, 0x0011, ddb_octopus_mini),
+	DDB_DEVID(0x0003, 0x0020, ddb_v6),
+	DDB_DEVID(0x0003, 0x0021, ddb_v6_5),
+	DDB_DEVID(0x0006, 0x0022, ddb_v7),
+	DDB_DEVID(0x0006, 0x0024, ddb_v7a),
+	DDB_DEVID(0x0003, 0x0030, ddb_dvbct),
+	DDB_DEVID(0x0003, 0xdb03, ddb_satixS2v3),
+	DDB_DEVID(0x0006, 0x0031, ddb_ctv7),
+	DDB_DEVID(0x0006, 0x0032, ddb_ctv7),
+	DDB_DEVID(0x0006, 0x0033, ddb_ctv7),
+	DDB_DEVID(0x0007, 0x0023, ddb_s2_48),
+	DDB_DEVID(0x0008, 0x0034, ddb_ct2_8),
+	DDB_DEVID(0x0008, 0x0035, ddb_c2t2_8),
+	DDB_DEVID(0x0008, 0x0036, ddb_isdbt_8),
+	DDB_DEVID(0x0008, 0x0037, ddb_c2t2i_v0_8),
+	DDB_DEVID(0x0008, 0x0038, ddb_c2t2i_8),
+	DDB_DEVID(0x0006, 0x0039, ddb_ctv7),
+	DDB_DEVID(0x0011, 0x0040, ddb_ci),
+	DDB_DEVID(0x0011, 0x0041, ddb_cis),
+	DDB_DEVID(0x0012, 0x0042, ddb_ci),
+	DDB_DEVID(0x0013, 0x0043, ddb_ci_s2_pro),
+	DDB_DEVID(0x0013, 0x0044, ddb_ci_s2_pro_a),
+	DDB_DEVID(0x0201, 0x0001, ddb_mod),
+	DDB_DEVID(0x0201, 0x0002, ddb_mod),
+	DDB_DEVID(0x0203, 0x0001, ddb_mod),
+	DDB_DEVID(0x0210, 0x0001, ddb_mod_fsm_24),
+	DDB_DEVID(0x0210, 0x0002, ddb_mod_fsm_16),
+	DDB_DEVID(0x0210, 0x0003, ddb_mod_fsm_8),
+	DDB_DEVID(0x0220, 0x0001, ddb_sdr),
+	/* testing on OctopusNet Pro */
+	DDB_DEVID(0x0320, 0xffff, ddb_octopro_hdin),
+	DDB_DEVID(0x0321, 0xffff, ddb_none),
+	DDB_DEVID(0x0322, 0xffff, ddb_octopro),
+	DDB_DEVID(0x0323, 0xffff, ddb_none),
+	DDB_DEVID(0x0328, 0xffff, ddb_none),
+	DDB_DEVID(0x0329, 0xffff, ddb_octopro_hdin),
+};
+
+struct ddb_info *get_ddb_info(u16 vendor, u16 device, u16 subvendor, u16 subdevice)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ddb_device_ids); i++) {
+		struct ddb_device_id *id  = &ddb_device_ids[i];
+		
+		if (vendor == id->vendor &&
+		    device == id->device &&
+		    subvendor == id->subvendor && 
+		    ((subdevice == id->subdevice) ||
+		     id->subdevice == 0xffff))
+			return id->info;
+	}
+	return &ddb_none;
+}

ddbridge/ddbridge-i2c.c

@@ -1,7 +1,7 @@
 /*
  * ddbridge-i2c.c: Digital Devices bridge i2c driver
  *
- * Copyright (C) 2010-2015 Digital Devices GmbH
+ * Copyright (C) 2010-2017 Digital Devices GmbH
  *                         Ralph Metzler <rjkm@metzlerbros.de>
  *                         Marcus Metzler <mocm@metzlerbros.de>
  *
@@ -156,38 +156,43 @@ static int ddb_i2c_master_xfer(struct i2c_adapter *adapter,
 	struct ddb *dev = i2c->dev;
 	u8 addr = 0;
 
-	if (num != 1 && num != 2)
-		return -EIO;
 	addr = msg[0].addr;
 	if (msg[0].len > i2c->bsize)
 		return -EIO;
-	if (num == 2 && msg[1].flags & I2C_M_RD &&
-	    !(msg[0].flags & I2C_M_RD)) {
-		if (msg[1].len > i2c->bsize)
-			return -EIO;
-		ddbcpyto(dev, i2c->wbuf, msg[0].buf, msg[0].len);
-		ddbwritel(dev, msg[0].len | (msg[1].len << 16),
-			  i2c->regs + I2C_TASKLENGTH);
-		if (!ddb_i2c_cmd(i2c, addr, 1)) {
-			ddbcpyfrom(dev, msg[1].buf,
-				   i2c->rbuf,
-				   msg[1].len);
-			return num;
-		}
-	}
-	if (num == 1 && !(msg[0].flags & I2C_M_RD)) {
-		ddbcpyto(dev, i2c->wbuf, msg[0].buf, msg[0].len);
-		ddbwritel(dev, msg[0].len, i2c->regs + I2C_TASKLENGTH);
-		if (!ddb_i2c_cmd(i2c, addr, 2))
-			return num;
-	}
-	if (num == 1 && (msg[0].flags & I2C_M_RD)) {
-		ddbwritel(dev, msg[0].len << 16, i2c->regs + I2C_TASKLENGTH);
-		if (!ddb_i2c_cmd(i2c, addr, 3)) {
+	switch (num) {
+	case 1:
+		if (msg[0].flags & I2C_M_RD) {
+			ddbwritel(dev, msg[0].len << 16,
+				  i2c->regs + I2C_TASKLENGTH);
+			if (ddb_i2c_cmd(i2c, addr, 3))
+				break;
 			ddbcpyfrom(dev, msg[0].buf,
 				   i2c->rbuf, msg[0].len);
 			return num;
 		}
+		ddbcpyto(dev, i2c->wbuf, msg[0].buf, msg[0].len);
+		ddbwritel(dev, msg[0].len, i2c->regs + I2C_TASKLENGTH);
+		if (ddb_i2c_cmd(i2c, addr, 2))
+			break;
+		return num;
+	case 2:
+		if ((msg[0].flags & I2C_M_RD) == I2C_M_RD)
+			break;
+		if ((msg[1].flags & I2C_M_RD) != I2C_M_RD)
+			break;
+		if (msg[1].len > i2c->bsize)
+			break;
+		ddbcpyto(dev, i2c->wbuf, msg[0].buf, msg[0].len);
+		ddbwritel(dev, msg[0].len | (msg[1].len << 16),
+			  i2c->regs + I2C_TASKLENGTH);
+		if (ddb_i2c_cmd(i2c, addr, 1))
+			break;
+		ddbcpyfrom(dev, msg[1].buf,
+			   i2c->rbuf,
+			   msg[1].len);
+		return num;
+	default:
+		break;
 	}
 	return -EIO;
 }
@@ -247,11 +252,10 @@ static int ddb_i2c_add(struct ddb *dev, struct ddb_i2c *i2c,
 	adap->class = I2C_CLASS_TV_ANALOG;
 #endif
 #endif
-	/*strcpy(adap->name, "ddbridge");*/
 	snprintf(adap->name, I2C_NAME_SIZE, "ddbridge_%02x.%x.%x",
 		 dev->nr, i2c->link, i);
 	adap->algo = &ddb_i2c_algo;
-	adap->algo_data = (void *)i2c;
+	adap->algo_data = (void *) i2c;
 	adap->dev.parent = dev->dev;
 	return i2c_add_adapter(adap);
 }

ddbridge/ddbridge-i2c.h

@@ -1,7 +1,7 @@
 /*
  * ddbridge-i2c.h: Digital Devices bridge i2c driver
  *
- * Copyright (C) 2010-2015 Digital Devices GmbH
+ * Copyright (C) 2010-2017 Digital Devices GmbH
  *                         Marcus Metzler <mocm@metzlerbros.de>
  *                         Ralph Metzler <rjkm@metzlerbros.de>
  *

ddbridge/ddbridge-mod.c

@@ -1,7 +1,7 @@
 /*
  * ddbridge.c: Digital Devices PCIe bridge driver
  *
- * Copyright (C) 2010-2015 Digital Devices GmbH
+ * Copyright (C) 2010-2017 Digital Devices GmbH
  *                         Marcus Metzler <mocm@metzlerbros.de>
  *                         Ralph Metzler <rjkm@metzlerbros.de>
  *
@@ -76,57 +76,62 @@ inline s64 RoundPCRDown(s64 a)
 	return a & ~(HW_LSB_MASK - 1);
 }
 
-// Calculating KF, LF from Symbolrate
-//
-//  Symbolrate is usually calculated as (M/N) * 10.24 MS/s
-//  
-//   Common Values for M,N 
-//     J.83 Annex A,
-//     Euro Docsis  6.952 MS/s : M =   869, N =  1280
-//                  6.900 MS/s : M =   345, N =   512
-//                  6.875 MS/s : M =  1375, N =  2048
-//                  6.111 MS/s : M =  6111, N = 10240
-//     J.83 Annex B **
-//      QAM64       5.056941   : M =   401, N =   812
-//      QAM256      5.360537   : M =    78, N =   149
-//     J.83 Annex C **
-//                  5.309734   : M =  1889, N =  3643
-//
-//    For the present hardware 
-//      KF' = 256 * M 
-//      LF' = 225 * N 
-//       or
-//      KF' = Symbolrate in Hz
-//      LF' = 9000000
-//
-//      KF  = KF' / gcd(KF',LF')
-//      LF  = LF' / gcd(KF',LF')
-// Note: LF must not be a power of 2.
-//       Maximum value for KF,LF = 13421727 ( 0x7FFFFFF )
-//    ** using these M,N values will result in a small err (<5ppm)
-//       calculating KF,LF directly gives the exact normative result
-//       but with rather large KF,LF values
+/* Calculating KF, LF from Symbolrate
+ *
+ *  Symbolrate is usually calculated as (M/N) * 10.24 MS/s
+ *
+ *   Common Values for M,N
+ *     J.83 Annex A,
+ *     Euro Docsis  6.952 MS/s : M =   869, N =  1280
+ *                  6.900 MS/s : M =   345, N =   512
+ *                  6.875 MS/s : M =  1375, N =  2048
+ *                  6.111 MS/s : M =  6111, N = 10240
+ *     J.83 Annex B **
+ *      QAM64       5.056941   : M =   401, N =   812
+ *      QAM256      5.360537   : M =    78, N =   149
+ *     J.83 Annex C **
+ *                  5.309734   : M =  1889, N =  3643
+ *
+ *    For the present hardware
+ *      KF' = 256 * M
+ *      LF' = 225 * N
+ *       or
+ *      KF' = Symbolrate in Hz
+ *      LF' = 9000000
+ *
+ *      KF  = KF' / gcd(KF',LF')
+ *      LF  = LF' / gcd(KF',LF')
+ * Note: LF must not be a power of 2.
+ *       Maximum value for KF,LF = 13421727 ( 0x7FFFFFF )
+ *    ** using these M,N values will result in a small err (<5ppm)
+ *       calculating KF,LF directly gives the exact normative result
+ *       but with rather large KF,LF values
+ */
 
-static inline u32 gcd(u32 u,u32 v)
+static inline u32 gcd(u32 u, u32 v)
 {
-    int s = 0;
-    while (((u|v)&1) == 0) {
-	    s += 1;
-	    u >>= 1;
-	    v >>= 1;
-    }
-    while ((u&1) == 0)
-	    u >>= 1;
-    do {
-	    while ( (v&1) == 0 ) v >>= 1;
-	    if( u > v ) {
-		    u32 t = v;
-		    v = u;
-		    u = t;
-	    }
-	    v = v - u;
-    } while(v != 0);
-    return u << s;
+	int s = 0;
+
+	while (((u | v) & 1) == 0) {
+		s += 1;
+		u >>= 1;
+		v >>= 1;
+	}
+	while ((u & 1) == 0)
+		u >>= 1;
+	do {
+		while ((v & 1) == 0)
+			v >>= 1;
+		if (u > v) {
+			u32 t = v;
+
+			v = u;
+			u = t;
+		}
+		v = v - u;
+	} while (v != 0);
+
+	return (u << s);
 }
 
 /****************************************************************************/
@@ -136,14 +141,14 @@ static inline u32 gcd(u32 u,u32 v)
 static int mod_SendChannelCommand(struct ddb *dev, u32 Channel, u32 Command)
 {
 	u32 ControlReg = ddbreadl(dev, CHANNEL_CONTROL(Channel));
-	
+
 	ControlReg = (ControlReg & ~CHANNEL_CONTROL_CMD_MASK)|Command;
 	ddbwritel(dev, ControlReg, CHANNEL_CONTROL(Channel));
-	while(1) {
+	while (1) {
 		ControlReg = ddbreadl(dev, CHANNEL_CONTROL(Channel));
 		if (ControlReg == 0xFFFFFFFF)
 			return -EIO;
-		if((ControlReg & CHANNEL_CONTROL_CMD_STATUS) == 0)
+		if ((ControlReg & CHANNEL_CONTROL_CMD_STATUS) == 0)
 			break;
 	}
 	if (ControlReg & CHANNEL_CONTROL_ERROR_CMD)
@@ -171,10 +176,11 @@ void ddbridge_mod_output_stop(struct ddb_output *output)
 	struct ddb_mod *mod = &dev->mod[output->nr];
 
 	mod->State = CM_IDLE;
-	mod->Control = 0;
+	mod->Control &= 0xfffffff0;
 	if (dev->link[0].info->version == 2)
-		mod_SendChannelCommand(dev, output->nr, CHANNEL_CONTROL_CMD_FREE);
-	ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr));
+		mod_SendChannelCommand(dev, output->nr,
+				       CHANNEL_CONTROL_CMD_FREE);
+	ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
 #if 0
 	udelay(10);
 	ddbwritel(dev, CHANNEL_CONTROL_RESET, CHANNEL_CONTROL(output->nr));
@@ -216,13 +222,13 @@ static void mod_set_rateinc(struct ddb *dev, u32 chan)
 static void mod_calc_rateinc(struct ddb_mod *mod)
 {
 	u32 ri;
-	
+
 	pr_info("DDBridge: ibitrate %llu\n", mod->ibitrate);
 	pr_info("DDBridge: obitrate %llu\n", mod->obitrate);
-	
+
 	if (mod->ibitrate != 0) {
 		u64 d = mod->obitrate - mod->ibitrate;
-		
+
 		d = div64_u64(d, mod->obitrate >> 24);
 		if (d > 0xfffffe)
 			ri = 0xfffffe;
@@ -237,8 +243,7 @@ static void mod_calc_rateinc(struct ddb_mod *mod)
 
 static int mod_calc_obitrate(struct ddb_mod *mod)
 {
-	struct ddb *dev = mod->port->dev;
-	u64 ofac; 
+	u64 ofac;
 
 	ofac = (((u64) mod->symbolrate) << 32) * 188;
 	ofac = div_u64(ofac, 204);
@@ -249,7 +254,6 @@ static int mod_calc_obitrate(struct ddb_mod *mod)
 static int mod_set_symbolrate(struct ddb_mod *mod, u32 srate)
 {
 	struct ddb *dev = mod->port->dev;
-	u64 ofac; 
 
 	if (dev->link[0].info->version < 2) {
 		if (srate != 6900000)
@@ -265,16 +269,17 @@ static int mod_set_symbolrate(struct ddb_mod *mod, u32 srate)
 
 static u32 qamtab[6] = { 0x000, 0x600, 0x601, 0x602, 0x903, 0x604 };
 
-static int mod_set_modulation(struct ddb_mod *mod, enum fe_modulation modulation)
+static int mod_set_modulation(struct ddb_mod *mod,
+			      enum fe_modulation modulation)
 {
 	struct ddb *dev = mod->port->dev;
-	u64 ofac; 
 
 	if (modulation > QAM_256 || modulation < QAM_16)
 		return -EINVAL;
 	mod->modulation = modulation;
-	if (dev->link[0].info->version < 2) 
-		ddbwritel(dev, qamtab[modulation], CHANNEL_SETTINGS(mod->nr));
+	if (dev->link[0].info->version < 2)
+		ddbwritel(dev, qamtab[modulation],
+			  CHANNEL_SETTINGS(mod->port->nr));
 	mod_calc_obitrate(mod);
 	return 0;
 }
@@ -282,7 +287,7 @@ static int mod_set_modulation(struct ddb_mod *mod, enum fe_modulation modulation
 static int mod_set_frequency(struct ddb_mod *mod, u32 frequency)
 {
 	u32 freq = frequency / 1000000;
-	
+
 	if (frequency % 1000000)
 		return -EINVAL;
 	if ((freq - 114) % 8)
@@ -309,9 +314,8 @@ int ddbridge_mod_output_start(struct ddb_output *output)
 	struct ddb_mod *mod = &dev->mod[output->nr];
 	u32 Symbolrate = mod->symbolrate;
 
-	mod_calc_rateinc(mod);
-	/*PCRIncrement = RoundPCR(PCRIncrement);*/
-	/*PCRDecrement = RoundPCR(PCRDecrement);*/
+	if (dev->link[0].info->version < 3)
+		mod_calc_rateinc(mod);
 
 	mod->LastInPacketCount = 0;
 	mod->LastOutPacketCount = 0;
@@ -329,62 +333,75 @@ int ddbridge_mod_output_start(struct ddb_output *output)
 	mod->State = CM_STARTUP;
 	mod->StateCounter = CM_STARTUP_DELAY;
 
-	ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr));
+	if (dev->link[0].info->version == 3)
+		mod->Control = 0xfffffff0 &
+			ddbreadl(dev, CHANNEL_CONTROL(output->nr));
+	else
+		mod->Control = 0;
+	ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
 	udelay(10);
-	ddbwritel(dev, CHANNEL_CONTROL_RESET, CHANNEL_CONTROL(output->nr));
+	ddbwritel(dev, mod->Control | CHANNEL_CONTROL_RESET,
+		  CHANNEL_CONTROL(output->nr));
 	udelay(10);
-	ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr));
+	ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
 
-	pr_info("DDBridge: CHANNEL_BASE = %08x\n", CHANNEL_BASE);
-	pr_info("DDBridge: CHANNEL_CONTROL = %08x\n", CHANNEL_CONTROL(Channel));
 	if (dev->link[0].info->version == 2) {
-		//u32 Output = ((dev->mod_base.frequency - 114000000)/8000000 + Channel) % 96;
 		u32 Output = (mod->frequency - 114000000) / 8000000;
 		u32 KF = Symbolrate;
 		u32 LF = 9000000UL;
-		u32 d = gcd(KF,LF);
+		u32 d = gcd(KF, LF);
 		u32 checkLF;
 
 		ddbwritel(dev, mod->modulation - 1, CHANNEL_SETTINGS(Channel));
 		ddbwritel(dev, Output, CHANNEL_SETTINGS2(Channel));
-		
+
 		KF = KF / d;
 		LF = LF / d;
-		
-		while( (KF > KFLF_MAX) || (LF > KFLF_MAX) ) {
+
+		while ((KF > KFLF_MAX) || (LF > KFLF_MAX)) {
 			KF >>= 1;
 			LF >>= 1;
 		}
-		
+
 		checkLF = LF;
 		while ((checkLF & 1) == 0)
 			checkLF >>= 1;
 		if (checkLF <= 1)
 			return -EINVAL;
 
-		pr_info("DDBridge: KF=%u LF=%u Output=%u mod=%u\n", KF, LF, Output, mod->modulation);
+		pr_info("DDBridge: KF=%u LF=%u Output=%u mod=%u\n",
+			KF, LF, Output, mod->modulation);
 		ddbwritel(dev, KF, CHANNEL_KF(Channel));
 		ddbwritel(dev, LF, CHANNEL_LF(Channel));
-		
-		if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_SETUP))
+
+		if (mod_SendChannelCommand(dev, Channel,
+					   CHANNEL_CONTROL_CMD_SETUP))
 			return -EINVAL;
-		mod->Control = CHANNEL_CONTROL_ENABLE_DVB;
-	} else {
+		mod->Control |= CHANNEL_CONTROL_ENABLE_DVB;
+	} else if (dev->link[0].info->version == 1) {
 		/* QAM: 600 601 602 903 604 = 16 32 64 128 256 */
 		/* ddbwritel(dev, 0x604, CHANNEL_SETTINGS(output->nr)); */
-		ddbwritel(dev, qamtab[mod->modulation], CHANNEL_SETTINGS(output->nr));
-		mod->Control = (CHANNEL_CONTROL_ENABLE_IQ | CHANNEL_CONTROL_ENABLE_DVB);
+		ddbwritel(dev, qamtab[mod->modulation],
+			  CHANNEL_SETTINGS(output->nr));
+		mod->Control |= (CHANNEL_CONTROL_ENABLE_IQ |
+				 CHANNEL_CONTROL_ENABLE_DVB);
+	} else if (dev->link[0].info->version == 3) {
+		mod->Control |= (CHANNEL_CONTROL_ENABLE_IQ |
+				 CHANNEL_CONTROL_ENABLE_DVB);
+	}
+	if (dev->link[0].info->version < 3) {
+		mod_set_rateinc(dev, output->nr);
+		mod_set_incs(output);
 	}
-	mod_set_rateinc(dev, output->nr);
-	mod_set_incs(output);
-
 	mod->Control |= CHANNEL_CONTROL_ENABLE_SOURCE;
 
 	ddbwritel(dev, mod->Control, CHANNEL_CONTROL(output->nr));
 	if (dev->link[0].info->version == 2)
-		if (mod_SendChannelCommand(dev, Channel, CHANNEL_CONTROL_CMD_UNMUTE))
+		if (mod_SendChannelCommand(dev, Channel,
+					   CHANNEL_CONTROL_CMD_UNMUTE))
 			return -EINVAL;
-	pr_info("DDBridge: mod_output_start %d.%d\n", dev->nr, output->nr);
+	pr_info("DDBridge: mod_output_start %d.%d ctrl=%08x\n",
+		dev->nr, output->nr, mod->Control);
 	return 0;
 }
 
@@ -395,9 +412,11 @@ int ddbridge_mod_output_start(struct ddb_output *output)
 static int mod_write_max2871(struct ddb *dev, u32 val)
 {
 	ddbwritel(dev, val, MAX2871_OUTDATA);
-	ddbwritel(dev, MAX2871_CONTROL_CE | MAX2871_CONTROL_WRITE, MAX2871_CONTROL);
-	while(1) {
+	ddbwritel(dev, MAX2871_CONTROL_CE | MAX2871_CONTROL_WRITE,
+		  MAX2871_CONTROL);
+	while (1) {
 		u32 ControlReg = ddbreadl(dev, MAX2871_CONTROL);
+
 		if (ControlReg == 0xFFFFFFFF)
 			return -EIO;
 		if ((ControlReg & MAX2871_CONTROL_WRITE) == 0)
@@ -406,58 +425,62 @@ static int mod_write_max2871(struct ddb *dev, u32 val)
 	return 0;
 }
 
-static int mod_setup_max2871(struct ddb *dev)
+static u32 max2871_fsm[6] = {
+	0x00730040, 0x600080A1, 0x510061C2, 0x010000CB, 0x6199003C, 0x60440005,
+};
+
+static u32 max2871_sdr[6] = {
+	0x007A8098, 0x600080C9, 0x510061C2, 0x010000CB, 0x6199003C, 0x60440005
+};
+
+static int mod_setup_max2871(struct ddb *dev, u32 *reg)
 {
 	int status = 0;
-	int i;
-	
-	ddbwritel(dev, MAX2871_CONTROL_CE, MAX2871_CONTROL);
-	for (i = 0; i < 2; i++) {
-		status = mod_write_max2871(dev, 0x00440005);
-		if (status)
-			break;
-		status = mod_write_max2871(dev, 0x6199003C);
-		if (status)
-			break;
-		status = mod_write_max2871(dev, 0x000000CB);
-		if (status)
-			break;
-		status = mod_write_max2871(dev, 0x510061C2);
-		if (status)
-			break;
-		status = mod_write_max2871(dev, 0x600080A1);
-		if (status)
-			break;
-		status = mod_write_max2871(dev, 0x00730040);
-		if (status)
-			break;
-		msleep(30);
-	} while(0);
+	int i, j;
+	u32 val;
 
+	ddbwritel(dev, MAX2871_CONTROL_CE, MAX2871_CONTROL);
+	msleep(30);
+	for (i = 0; i < 2; i++) {
+		for (j = 5; j >= 0; j--) {
+			val = reg[j];
+
+			if (j == 4)
+				val &= 0xFFFFFEDF;
+			status = mod_write_max2871(dev, reg[j]);
+			if (status)
+				break;
+			msleep(30);
+		}
+	}
 	if (status == 0) {
-		u32 ControlReg = ddbreadl(dev, MAX2871_CONTROL);
-		
+		u32 ControlReg;
+
+		if (reg[3] & (1 << 24))
+			msleep(100);
+		ControlReg = ddbreadl(dev, MAX2871_CONTROL);
+
 		if ((ControlReg & MAX2871_CONTROL_LOCK) == 0)
 			status = -EIO;
+		status = mod_write_max2871(dev, reg[4]);
 	}
-
 	return status;
 }
 
-
-static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels)
+static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan,
+			 u32 MaxUsedChannels)
 {
 	int status = 0;
 	u32 Capacity;
 	u32 tmp = ddbreadl(dev, FSM_STATUS);
-	
+
 	if ((tmp & FSM_STATUS_READY) == 0) {
-		status = mod_setup_max2871(dev);
+		status = mod_setup_max2871(dev, max2871_fsm);
 		if (status)
 			return status;
 		ddbwritel(dev, FSM_CMD_RESET, FSM_CONTROL);
-		msleep(10);
-		
+		msleep(20);
+
 		tmp = ddbreadl(dev, FSM_STATUS);
 		if ((tmp & FSM_STATUS_READY) == 0)
 			return -1;
@@ -466,23 +489,23 @@ static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels
 	if (((tmp & FSM_STATUS_QAMREADY) != 0) &&
 	    ((Capacity & FSM_CAPACITY_INUSE) != 0))
 		return -EBUSY;
-	
+
 	ddbwritel(dev, FSM_CMD_SETUP, FSM_CONTROL);
-	msleep(10);
+	msleep(20);
 	tmp = ddbreadl(dev, FSM_STATUS);
-	
+
 	if ((tmp & FSM_STATUS_QAMREADY) == 0)
 		return -1;
-	
+
 	if (MaxUsedChannels == 0)
 		MaxUsedChannels = (Capacity & FSM_CAPACITY_CUR) >> 16;
 
 	pr_info("DDBridge: max used chan = %u\n", MaxUsedChannels);
-	if (MaxUsedChannels <= 1 )
+	if (MaxUsedChannels <= 1)
 		ddbwritel(dev, FSM_GAIN_N1, FSM_GAIN);
 	else if (MaxUsedChannels <= 2)
 		ddbwritel(dev, FSM_GAIN_N2, FSM_GAIN);
-	else if (MaxUsedChannels <= 4) 
+	else if (MaxUsedChannels <= 4)
 		ddbwritel(dev, FSM_GAIN_N4, FSM_GAIN);
 	else if (MaxUsedChannels <= 8)
 		ddbwritel(dev, FSM_GAIN_N8, FSM_GAIN);
@@ -493,90 +516,19 @@ static int mod_fsm_setup(struct ddb *dev, u32 FrequencyPlan, u32 MaxUsedChannels
 	else
 		ddbwritel(dev, FSM_GAIN_N96, FSM_GAIN);
 
-	ddbwritel(dev, FSM_CONTROL_ENABLE, FSM_CONTROL);
+	dev->link[0].info->port_num = MaxUsedChannels;
 
 	return status;
 }
 
 static int mod_set_vga(struct ddb *dev, u32 Gain)
 {
-	if( Gain > 255 )
+	if (Gain > 255)
 		return -EINVAL;
 	ddbwritel(dev, Gain, RF_VGA);
 	return 0;
 }
 
-static int mod_get_vga(struct ddb *dev, u32 *pGain)
-{
-	*pGain = ddbreadl(dev, RF_VGA);
-	return 0;
-}
-#if 0
-static void TemperatureMonitorSetFan(struct ddb *dev)
-{
-	u32 tqam, pwm;
-	
-	if ((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0) {
-		pr_info("DDBridge: Over temperature condition\n");
-		dev->OverTemperatureError = 1;
-	}
-	tqam  = (ddbreadl(dev, TEMPMON2_QAMCORE) >> 8) & 0xFF;
-	if (tqam & 0x80)
-		tqam = 0;
-	
-	pwm = (ddbreadl(dev, TEMPMON_FANCONTROL) >> 8) & 0x0F;
-	if (pwm > 10)
-		pwm = 10;   
-	
-	if (tqam >= dev->temp_tab[pwm]) {
-		while( pwm < 10 && tqam >= dev->temp_tab[pwm + 1])
-			pwm += 1;
-	} else {
-		while( pwm > 1 && tqam < dev->temp_tab[pwm - 2])
-			pwm -= 1;
-	}
-	ddbwritel(dev, (pwm << 8), TEMPMON_FANCONTROL);
-}
-
-
-static void temp_handler(unsigned long data)
-{
-	struct ddb *dev = (struct ddb *) data;
-
-	pr_info("DDBridge: temp_handler\n");
-
-	spin_lock(&dev->temp_lock);
-	TemperatureMonitorSetFan(dev);
-	spin_unlock(&dev->temp_lock);
-}
-
-static int TemperatureMonitorInit(struct ddb *dev, int FirstTime) {
-	int status = 0;
-	
-	spin_lock_irq(&dev->temp_lock);
-	if (FirstTime) {
-		static u8 TemperatureTable[11] = {30,35,40,45,50,55,60,65,70,75,80};
-		
-		memcpy(dev->temp_tab, TemperatureTable, sizeof(TemperatureTable));
-	}
-	dev->handler[0][8] = temp_handler;
-	dev->handler_data[0][8] = (unsigned long) dev;
-	ddbwritel(dev, (TEMPMON_CONTROL_OVERTEMP | TEMPMON_CONTROL_AUTOSCAN |
-			TEMPMON_CONTROL_INTENABLE),
-		  TEMPMON_CONTROL);
-	ddbwritel(dev, (3 << 8), TEMPMON_FANCONTROL);
-	
-	dev->OverTemperatureError =
-		((ddbreadl(dev, TEMPMON_CONTROL) & TEMPMON_CONTROL_OVERTEMP ) != 0);
-	if (dev->OverTemperatureError)	{
-		pr_info("DDBridge: Over temperature condition\n");
-		status = -1;
-	}
-	TemperatureMonitorSetFan(dev);
-	spin_unlock_irq(&dev->temp_lock);
-	return status;
-}
-#endif
 /****************************************************************************/
 /****************************************************************************/
 /****************************************************************************/
@@ -741,7 +693,8 @@ static int mod_set_si598(struct ddb *dev, u32 freq)
 		     ((u32)(Data[1] & 0xE0) >> 6)) + 1;
 		fDCO = fOut * (u64)(HSDiv * N);
 		m_fXtal = fDCO << 28;
-		pr_info("DDBridge: fxtal %016llx  rfreq %016llx\n", m_fXtal, RFreq);
+		pr_info("DDBridge: fxtal %016llx  rfreq %016llx\n",
+			m_fXtal, RFreq);
 
 		m_fXtal += RFreq >> 1;
 		m_fXtal = div64_u64(m_fXtal, RFreq);
@@ -942,9 +895,9 @@ static int mod_init_dac_input(struct ddb *dev)
 	Seek = 1;
 	for (Sample = 0; Sample < 32; Sample += 1) {
 		/* printk(" %2d: %d %2d %2d\n",
-		   Sample, SeekTable[Sample], SetTable[Sample],
-		   HldTable[Sample]);
-		*/
+		 * Sample, SeekTable[Sample], SetTable[Sample],
+		 * HldTable[Sample]);
+		 */
 
 		if (Sample1 == 0xFF && SeekTable[Sample] == 1 && Seek == 0)
 			Sample1 = Sample;
@@ -1236,7 +1189,8 @@ static int mod_init_1(struct ddb *dev, u32 Frequency)
 	FrequencyCH10 = flash->DataSet[0].FlatStart + 4;
 	DownFrequency = Frequency + 9 * 8 + FrequencyCH10 +
 		UP1Frequency + UP2Frequency;
-	pr_info("DDBridge: CH10 = %d, Down = %d\n", FrequencyCH10, DownFrequency);
+	pr_info("DDBridge: CH10 = %d, Down = %d\n",
+			FrequencyCH10, DownFrequency);
 
 	if ((FrequencyCH10 + 9 * 8) > (flash->DataSet[0].FlatEnd - 4)) {
 		pr_err("DDBridge: Frequency out of range %d\n", FrequencyCH10);
@@ -1288,10 +1242,10 @@ fail:
 #define FACTOR         (1ULL << 22)
 
 /*
-  double Increment =  FACTOR*PACKET_CLOCKS/double(m_OutputBitrate);
-  double Decrement =  FACTOR*PACKET_CLOCKS/double(m_InputBitrate);
-  27000000 * 1504 * 2^22 / (6900000 * 188 / 204) = 26785190066.1
-*/
+ * double Increment =  FACTOR*PACKET_CLOCKS/double(m_OutputBitrate);
+ * double Decrement =  FACTOR*PACKET_CLOCKS/double(m_InputBitrate);
+ * 27000000 * 1504 * 2^22 / (6900000 * 188 / 204) = 26785190066.1
+ */
 
 void ddbridge_mod_rate_handler(unsigned long data)
 {
@@ -1473,11 +1427,91 @@ void ddbridge_mod_rate_handler(unsigned long data)
 		PCRAdjustExtFrac, PCRCorr, mod->PCRIncrement);
 }
 
-static int mod_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
+static int mod3_set_base_frequency(struct ddb *dev, u32 frequency)
+{
+	u64 tmp;
+
+	if (frequency % 1000)
+		return -EINVAL;
+	if ((frequency < 114000000) || (frequency > 874000000))
+		return -EINVAL;
+	dev->mod_base.frequency = frequency;
+	tmp = frequency;
+	tmp <<= 33;
+	tmp = div64_s64(tmp, 4915200000);
+	pr_info("set base frequency = %u  regs = 0x%08llx\n", frequency, tmp);
+	ddbwritel(dev, (u32) tmp, RFDAC_FCW);
+	return 0;
+}
+
+static void mod3_set_cfcw(struct ddb_mod *mod, u32 f)
 {
 	struct ddb *dev = mod->port->dev;
+	s32 freq = f;
+	s32 dcf = dev->mod_base.frequency;
+	s64 tmp, srdac = 245760000;
+	u32 cfcw;
 
-	switch(tvp->cmd) {
+	tmp = ((s64) (freq - dcf)) << 32;
+	tmp = div64_s64(tmp, srdac);
+	cfcw = (u32) tmp;
+	pr_info("f=%u cfcw = %08x nr = %u\n", f, cfcw, mod->port->nr);
+	ddbwritel(dev, cfcw, SDR_CHANNEL_CFCW(mod->port->nr));
+}
+
+static int mod3_set_frequency(struct ddb_mod *mod, u32 frequency)
+{
+#if 0
+	struct ddb *dev = mod->port->dev;
+
+	if (frequency % 1000)
+		return -EINVAL;
+	if ((frequency < 114000000) || (frequency > 874000000))
+		return -EINVAL;
+	if (frequency > dev->mod_base.frequency)
+		if (frequency - dev->mod_base.frequency > 100000000)
+			return -EINVAL;
+	else
+		if (dev->mod_base.frequency - frequency > 100000000)
+			return -EINVAL;
+#endif
+	mod3_set_cfcw(mod, frequency);
+	return 0;
+}
+
+static int mod3_set_ari(struct ddb_mod *mod, u32 rate)
+{
+	ddbwritel(mod->port->dev, rate, SDR_CHANNEL_ARICW(mod->port->nr));
+	return 0;
+}
+
+
+static int mod3_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
+{
+	switch (tvp->cmd) {
+	case MODULATOR_OUTPUT_ARI:
+		return mod3_set_ari(mod, tvp->u.data);
+
+	case MODULATOR_FREQUENCY:
+		return mod3_set_frequency(mod, tvp->u.data);
+
+	case MODULATOR_BASE_FREQUENCY:
+		return mod3_set_base_frequency(mod->port->dev, tvp->u.data);
+      
+	case MODULATOR_ATTENUATOR:
+		return mod_set_attenuator(mod->port->dev, tvp->u.data);
+      
+	case MODULATOR_GAIN:
+		return mod_set_vga(mod->port->dev, tvp->u.data);
+	}
+	return -EINVAL;
+}
+
+static int mod_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
+{
+	if (mod->port->dev->link[0].info->version == 3)
+		return mod3_prop_proc(mod, tvp);
+	switch (tvp->cmd) {
 	case MODULATOR_SYMBOL_RATE:
 		return mod_set_symbolrate(mod, tvp->u.data);
 
@@ -1492,6 +1526,11 @@ static int mod_prop_proc(struct ddb_mod *mod, struct dtv_property *tvp)
 
 	case MODULATOR_INPUT_BITRATE:
 		return mod_set_ibitrate(mod, tvp->u.data);
+
+	case MODULATOR_GAIN:
+		if (mod->port->dev->link[0].info->version == 2)
+			return mod_set_vga(mod->port->dev, tvp->u.data);
+		return -EINVAL;
 	}
 	return 0;
 }
@@ -1504,17 +1543,21 @@ int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg)
 	struct ddb_mod *mod = &dev->mod[output->nr];
 	int ret = 0;
 
+	if (dev->link[0].info->version == 3 && cmd != FE_SET_PROPERTY)
+		return -EINVAL;
 	switch (cmd) {
 	case FE_SET_PROPERTY:
 	{
-		struct dtv_properties *tvps = (struct dtv_properties __user *) parg;
+		struct dtv_properties *tvps =
+			(struct dtv_properties __user *) parg;
 		struct dtv_property *tvp = NULL;
 		int i;
-		
+
 		if ((tvps->num == 0) || (tvps->num > DTV_IOCTL_MAX_MSGS))
 			return -EINVAL;
-		
-		tvp = kmalloc(tvps->num * sizeof(struct dtv_property), GFP_KERNEL);
+
+		tvp = kmalloc(tvps->num * sizeof(struct dtv_property),
+			      GFP_KERNEL);
 		if (!tvp) {
 			ret = -ENOMEM;
 			goto out;
@@ -1525,11 +1568,12 @@ int ddbridge_mod_do_ioctl(struct file *file, unsigned int cmd, void *parg)
 			goto out;
 		}
 		for (i = 0; i < tvps->num; i++) {
-			if ((ret = mod_prop_proc(mod, tvp + i)) < 0)
+			ret = mod_prop_proc(mod, tvp + i);
+			if (ret < 0)
 				goto out;
 			(tvp + i)->result = ret;
 		}
-	out:
+out:
 		kfree(tvp);
 		return ret;
 	}
@@ -1588,30 +1632,158 @@ static int mod_init_2(struct ddb *dev, u32 Frequency)
 	dev->mod_base.frequency = Frequency;
 	status = mod_fsm_setup(dev, 0, 0);
 
+	if (status) {
+		pr_err("FSM setup failed!\n");
+		return -1;
+	}
 	for (i = 0; i < streams; i++) {
 		struct ddb_mod *mod = &dev->mod[i];
 
 		mod->port = &dev->port[i];
 		mod_set_modulation(mod, QAM_256);
 		mod_set_symbolrate(mod, 6900000);
-		mod_set_frequency(mod, 114000000 + i * 8000000);
+		mod_set_frequency(mod, dev->mod_base.frequency + i * 8000000);
 	}
-	if (streams <= 8)
-		mod_set_vga(dev, RF_VGA_GAIN_N8);
-	else if (streams <= 16)
-		mod_set_vga(dev, RF_VGA_GAIN_N16);
-	else
-		mod_set_vga(dev, RF_VGA_GAIN_N24);
-	
 	mod_set_attenuator(dev, 0);
 	return 0;
 }
 
+
+/****************************************************************************/
+
+static u32 vsb13500[64] = {
+	0x0000000E, 0x00010004, 0x00020003, 0x00030009,
+	0x0004FFFA, 0x00050002, 0x0006FFF8, 0x0007FFF0,
+	0x00080000, 0x0009FFEA, 0x000A0001, 0x000B0003,
+	0x000CFFF9, 0x000D0025,	0x000E0004, 0x000F001F,
+	0x00100023, 0x0011FFEE, 0x00120020, 0x0013FFD0,
+	0x0014FFD5, 0x0015FFED, 0x0016FF8B, 0x0017000B,
+	0x0018FFC8, 0x0019FFF1, 0x001A009E, 0x001BFFEF,
+	0x001C013B, 0x001D00CB, 0x001E0031, 0x001F05F6,
+
+	0x0040FFFF, 0x00410004, 0x0042FFF8, 0x0043FFFE,
+	0x0044FFFA, 0x0045FFF3, 0x00460003, 0x0047FFF4,
+	0x00480005, 0x0049000D, 0x004A0000, 0x004B0022,
+	0x004C0005, 0x004D000D, 0x004E0013, 0x004FFFDF,
+	0x00500007, 0x0051FFD4, 0x0052FFD2, 0x0053FFFD,
+	0x0054FFB7, 0x00550021, 0x00560009, 0x00570010,
+	0x00580097, 0x00590003, 0x005A009D, 0x005B004F,
+	0x005CFF89, 0x005D0097, 0x005EFD42, 0x005FFCBE
+};
+
+static u32 stage2[16] = {
+	0x0080FFFF, 0x00810000, 0x00820005, 0x00830000,
+	0x0084FFF0, 0x00850000, 0x00860029, 0x00870000,
+	0x0088FFA2, 0x0089FFFF, 0x008A00C9, 0x008B000C,
+	0x008CFE49, 0x008DFF9B, 0x008E04D4, 0x008F07FF
+};
+
+static void mod_set_sdr_table(struct ddb_mod *mod, u32 *tab, u32 len)
+{
+	struct ddb *dev = mod->port->dev;
+	u32 i;
+
+	for (i = 0; i < len; i++)
+		ddbwritel(dev, tab[i], SDR_CHANNEL_SETFIR(mod->port->nr));
+}
+
+static int rfdac_init(struct ddb *dev)
+{
+	int i;
+	u32 tmp;
+
+	ddbwritel(dev, RFDAC_CMD_POWERDOWN, RFDAC_CONTROL);
+	for (i = 0; i < 10; i++) {
+		msleep(20);
+		tmp = ddbreadl(dev, RFDAC_CONTROL);
+		if ((tmp & RFDAC_CMD_STATUS) == 0x00)
+			break;
+	}
+	if (tmp & 0x80)
+		return -1;
+	pr_info("sync %d:%08x\n", i, tmp);
+	ddbwritel(dev, RFDAC_CMD_RESET, RFDAC_CONTROL);
+	for (i = 0; i < 10; i++) {
+		msleep(20);
+		tmp = ddbreadl(dev, RFDAC_CONTROL);
+		if ((tmp & RFDAC_CMD_STATUS) == 0x00)
+			break;
+	}
+	if (tmp & 0x80)
+		return -1;
+	pr_info("sync %d:%08x\n", i, tmp);
+	ddbwritel(dev, RFDAC_CMD_SETUP, RFDAC_CONTROL);
+	for (i = 0; i < 10; i++) {
+		msleep(20);
+		tmp = ddbreadl(dev, RFDAC_CONTROL);
+		if ((tmp & RFDAC_CMD_STATUS) == 0x00)
+			break;
+	}
+	if (tmp & 0x80)
+		return -1;
+	pr_info("sync %d:%08x\n", i, tmp);
+	ddbwritel(dev, 0x01, JESD204B_BASE);
+	for (i = 0; i < 400; i++) {
+		msleep(20);
+		tmp = ddbreadl(dev, JESD204B_BASE);
+		if ((tmp & 0xc0000000) == 0xc0000000)
+			break;
+	}
+	pr_info("sync %d:%08x\n", i, tmp);
+	if ((tmp & 0xc0000000) != 0xc0000000)
+		return -1;
+	return 0;
+}
+
+static int mod_init_3(struct ddb *dev, u32 Frequency)
+{
+	int streams = dev->link[0].info->port_num;
+	int i, ret = 0;
+
+	ret = mod_setup_max2871(dev, max2871_sdr);
+	if (ret)
+		pr_err("DDBridge: PLL setup failed\n");
+	ret = rfdac_init(dev);
+	if (ret)
+		ret = rfdac_init(dev);
+	if (ret)
+		pr_err("DDBridge: RFDAC setup failed\n");
+
+	for (i = 0; i < streams; i++) {
+		struct ddb_mod *mod = &dev->mod[i];
+
+		mod->port = &dev->port[i];
+		mod_set_sdr_table(mod, vsb13500, 64);
+		mod_set_sdr_table(mod, stage2, 16);
+	}
+	ddbwritel(dev, 0x1800, 0x244);
+	ddbwritel(dev, 0x01, 0x240);
+
+	mod3_set_base_frequency(dev, 602000000);
+	for (i = 0; i < streams; i++) {
+		struct ddb_mod *mod = &dev->mod[i];
+
+		ddbwritel(dev, 0x00, SDR_CHANNEL_CONTROL(i));
+		ddbwritel(dev, 0x06, SDR_CHANNEL_CONFIG(i));
+		ddbwritel(dev, 0x70800000, SDR_CHANNEL_ARICW(i));
+		mod3_set_frequency(mod, Frequency + 7000000 * i);
+
+		ddbwritel(dev, 0x00011f80, SDR_CHANNEL_RGAIN(i));
+		ddbwritel(dev, 0x00002000, SDR_CHANNEL_FM1GAIN(i));
+		ddbwritel(dev, 0x00001000, SDR_CHANNEL_FM2GAIN(i));
+	}
+	mod_set_attenuator(dev, 0);
+	mod_set_vga(dev, 64);
+	return ret;
+}
+
 int ddbridge_mod_init(struct ddb *dev)
 {
 	if (dev->link[0].info->version <= 1)
 		return mod_init_1(dev, 722000000);
 	if (dev->link[0].info->version == 2)
 		return mod_init_2(dev, 114000000);
+	if (dev->link[0].info->version == 3)
+		return mod_init_3(dev, 503250000);
 	return -1;
 }

ddbridge/ddbridge-ns.c

@@ -1,7 +1,7 @@
 /*
  * ddbridge-ns.c: Digital Devices PCIe bridge driver net streaming
  *
- * Copyright (C) 2010-2015 Marcus Metzler <mocm@metzlerbros.de>
+ * Copyright (C) 2010-2017Marcus Metzler <mocm@metzlerbros.de>
  *                         Ralph Metzler <rjkm@metzlerbros.de>
  *                         Digital Devices GmbH
  *
@@ -87,7 +87,6 @@ static int ns_alloc(struct dvbnss *nss)
 		dev->ns[i].fe = input;
 		nss->priv = &dev->ns[i];
 		ret = 0;
-		/*pr_info("DDBridge: %s i=%d fe=%d\n", __func__, i, input->nr); */
 		break;
 	}
 	ddbwritel(dev, 0x03, RTP_MASTER_CONTROL);
@@ -446,8 +445,6 @@ static int ns_start(struct dvbnss *nss)
 	if (dns->fe != input)
 		ddb_dvb_ns_input_start(dns->fe);
 	ddb_dvb_ns_input_start(input);
-	/* printk("ns start ns %u, fe %u link %u\n",
-	   dns->nr, dns->fe->nr, dns->fe->port->lnr); */
 	ddbwritel(dev, reg | (dns->fe->nr << 8) | (dns->fe->port->lnr << 16),
 		  STREAM_CONTROL(dns->nr));
 	return 0;

ddbridge/ddbridge-regs.h

@@ -1,7 +1,7 @@
 /*
  * ddbridge-regs.h: Digital Devices PCIe bridge driver
  *
- * Copyright (C) 2010-2016 Digital Devices GmbH
+ * Copyright (C) 2010-2017 Digital Devices GmbH
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -25,6 +25,7 @@
 
 #define CUR_REGISTERMAP_VERSION_V1  0x00010001
 #define CUR_REGISTERMAP_VERSION_V2  0x00020000
+#define CUR_REGISTERMAP_VERSION_022X  0x00020001
 
 #define HARDWARE_VERSION            0x00000000
 #define REGISTERMAP_VERSION         0x00000004
@@ -57,9 +58,9 @@
 /* ------------------------------------------------------------------------- */
 
 /* Interrupt controller
-   How many MSI's are available depends on HW (Min 2 max 8)
-   How many are usable also depends on Host platform
-*/
+ * How many MSI's are available depends on HW (Min 2 max 8)
+ * How many are usable also depends on Host platform
+ */
 
 #define INTERRUPT_BASE   (0x40)
 
@@ -166,19 +167,22 @@
 #define TEMPMON_FANPWM      (0x00000F00)            // PWM speed in 10% steps
 #define TEMPMON_FANTACHO    (0x000000FF)            // Rotations in 100/min steps
 
-// V1 Temperature Monitor
-// Temperature Monitor TEMPMON_CONTROL & 0x8000 == 0 : ( 2x LM75A @ 0x90,0x92 )
-// Temperature Monitor TEMPMON_CONTROL & 0x8000 == 1 : ( 1x LM75A @ 0x90, 1x ADM1032 @ 0x9A )
+/* V1 Temperature Monitor
+ * Temperature Monitor TEMPMON_CONTROL & 0x8000 == 0 : ( 2x LM75A @ 0x90,0x92 )
+ * Temperature Monitor TEMPMON_CONTROL & 0x8000 == 1 :
+ * ( 1x LM75A @ 0x90, 1x ADM1032 @ 0x9A )
+ */
 
-#define TEMPMON1_CORE       (TEMPMON_SENSOR0)    // SHORT Temperature in <20>C x 256 (ADM1032 ext)
-#define TEMPMON1_SENSOR1    (TEMPMON_BASE + 0x08)    // SHORT Temperature in <20>C x 256 (LM75A 0x90)
-#define TEMPMON1_SENSOR2    (TEMPMON_BASE + 0x0C)    // SHORT Temperature in <20>C x 256 (LM75A 0x92 or ADM1032 Int)
+#define TEMPMON1_CORE       (TEMPMON_SENSOR0)    // u16 Temperature in <20>C x 256 (ADM1032 ext)
+#define TEMPMON1_SENSOR1    (TEMPMON_BASE + 0x08) // SHORT Temperature in <20>C x 256 (LM75A 0x90)
+#define TEMPMON1_SENSOR2    (TEMPMON_BASE + 0x0C) // SHORT Temperature in <20>C x 256 (LM75A 0x92 or ADM1032 Int)
 
 // V2 Temperature Monitor 2 ADM1032
 
 #define TEMPMON2_BOARD      (TEMPMON_SENSOR0)    // SHORT Temperature in <20>C x 256 (ADM1032 int)
 #define TEMPMON2_FPGACORE   (TEMPMON_SENSOR1)    // SHORT Temperature in <20>C x 256 (ADM1032 ext)
 #define TEMPMON2_QAMCORE    (TEMPMON_SENSOR2)    // SHORT Temperature in <20>C x 256 (ADM1032 ext)
+#define TEMPMON2_DACCORE    (TEMPMON_SENSOR2)    // SHORT Temperature in <20>C x 256 (ADM1032 ext)
 
 /* ------------------------------------------------------------------------- */
 /* I2C Master Controller */
@@ -242,7 +246,7 @@
 #define LNB_CMD_HIGH   4
 #define LNB_CMD_OFF    5
 #define LNB_CMD_DISEQC 6
-#define LNB_CMD_UNI    7
+#define LNB_CMD_SCIF   7
 
 #define LNB_BUSY  (1ULL <<  4)
 #define LNB_TONE  (1ULL << 15)
@@ -330,16 +334,16 @@
 /* Muxout from VCO (usually = Lock) */
 #define VCO3_CONTROL_MUXOUT (0x00000004)
 
-// V2
+/* V2 */
 
 #define MAX2871_BASE            (0xC0)
 #define MAX2871_CONTROL         (MAX2871_BASE + 0x00)
-#define MAX2871_OUTDATA         (MAX2871_BASE + 0x04)  // 32 Bit
-#define MAX2871_INDATA          (MAX2871_BASE + 0x08)  // 32 Bit
+#define MAX2871_OUTDATA         (MAX2871_BASE + 0x04)
+#define MAX2871_INDATA          (MAX2871_BASE + 0x08)
 #define MAX2871_CONTROL_WRITE   (0x00000001)   // 1 = Trigger write, resets when done
 #define MAX2871_CONTROL_CE      (0x00000002)   // 0 = Put VCO into power down
-#define MAX2871_CONTROL_MUXOUT  (0x00000004)   // Muxout from VCO 
-#define MAX2871_CONTROL_LOCK    (0x00000008)   // Lock from VCO 
+#define MAX2871_CONTROL_MUXOUT  (0x00000004)   // Muxout from VCO
+#define MAX2871_CONTROL_LOCK    (0x00000008)   // Lock from VCO
 
 #define FSM_BASE                (0x200)
 #define FSM_CONTROL             (FSM_BASE + 0x00)
@@ -358,9 +362,9 @@
 
 
 #define FSM_CAPACITY            (FSM_BASE + 0x04)
-#define FSM_CAPACITY_MAX        (0x3F000000)  
-#define FSM_CAPACITY_CUR        (0x003F0000)  
-#define FSM_CAPACITY_INUSE      (0x0000003F)  
+#define FSM_CAPACITY_MAX        (0x3F000000)
+#define FSM_CAPACITY_CUR        (0x003F0000)
+#define FSM_CAPACITY_INUSE      (0x0000003F)
 
 #define FSM_GAIN                (FSM_BASE + 0x10)
 #define FSM_GAINMASK            (0x000000FF)
@@ -379,15 +383,15 @@
 #define RF_ATTENUATOR   (0xD8)
 #define RF_ATTENUATOR   (0xD8)
 /*  0x00 =  0 dB
-    0x01 =  1 dB
-      ...
-    0x1F = 31 dB
-*/
+ *  0x01 =  1 dB
+ *    ...
+ *  0x1F = 31 dB
+ */
 
 #define RF_VGA  (0xDC)
 /* Only V2 */
 /* 8 bit range 0 - 31.75 dB Gain  */
-	
+
 /* VGA Gain for same output level as V1 Modulator */
 #define RF_VGA_GAIN_N8          (85)
 #define RF_VGA_GAIN_N16         (117)
@@ -409,9 +413,9 @@
 #define RF_POWER_CONTROL_VALID     (0x00000500)
 
 
-/* --------------------------------------------------------------------------
-   Output control
-*/
+/*
+ *  Output control
+ */
 
 #define IQOUTPUT_BASE           (0x240)
 #define IQOUTPUT_CONTROL        (IQOUTPUT_BASE + 0x00)
@@ -552,3 +556,76 @@
 
 
 
+// V2
+
+// MAX2871 same as DVB Modulator V2
+
+#define RFDAC_BASE                (0x200)
+#define RFDAC_CONTROL             (RFDAC_BASE + 0x00)
+
+#define RFDAC_CMD_MASK            (0x00000087)
+#define RFDAC_CMD_STATUS          (0x00000080)
+#define RFDAC_CMD_RESET           (0x00000080)
+#define RFDAC_CMD_POWERDOWN       (0x00000081)
+#define RFDAC_CMD_SETUP           (0x00000082)
+
+#define RFDAC_STATUS              (RFDAC_BASE + 0x00)
+#define RFDAC_STATUS_READY        (0x00010000)
+#define RFDAC_STATUS_DACREADY     (0x00020000)
+
+#define RFDAC_FCW                 (RFDAC_BASE + 0x10)
+
+//
+// --------------------------------------------------------------------------
+//
+
+#define JESD204B_BASE             (0x280)
+
+// Additional Status Bits
+
+#define DMA_PCIE_LANES_MASK       (0x00070000)
+
+
+// --------------------------------------------------------------------------
+// Modulator Channels, partially compatible to DVB Modulator V1
+
+#define SDR_CHANNEL_BASE            (0x800)
+
+#define SDR_CHANNEL_CONTROL(i)      ((SDR_CHANNEL_BASE) + (i) * 64 + 0x00)
+#define SDR_CHANNEL_CONFIG(i)       ((SDR_CHANNEL_BASE) + (i) * 64 + 0x04)
+#define SDR_CHANNEL_CFCW(i)         ((SDR_CHANNEL_BASE) + (i) * 64 + 0x08)
+#define SDR_CHANNEL_ARICW(i)        ((SDR_CHANNEL_BASE) + (i) * 64 + 0x0C)
+#define SDR_CHANNEL_RGAIN(i)        ((SDR_CHANNEL_BASE) + (i) * 64 + 0x10)
+#define SDR_CHANNEL_SETFIR(i)       ((SDR_CHANNEL_BASE) + (i) * 64 + 0x14)
+
+#define SDR_CHANNEL_FMDCW(i)        ((SDR_CHANNEL_BASE) + (i) * 64 + 0x20)
+#define SDR_CHANNEL_FM1FCW(i)       ((SDR_CHANNEL_BASE) + (i) * 64 + 0x24)
+#define SDR_CHANNEL_FM2FCW(i)       ((SDR_CHANNEL_BASE) + (i) * 64 + 0x28)
+#define SDR_CHANNEL_FM1GAIN(i)      ((SDR_CHANNEL_BASE) + (i) * 64 + 0x2C)
+#define SDR_CHANNEL_FM2GAIN(i)      ((SDR_CHANNEL_BASE) + (i) * 64 + 0x30)
+
+// Control and status bits
+#define SDR_CONTROL_ENABLE_CHANNEL  (0x00000004)
+#define SDR_CONTROL_ENABLE_DMA      (0x00000008)
+#define SDR_STATUS_DMA_UNDERRUN     (0x00010000)
+
+// Config
+#define SDR_CONFIG_ENABLE_FM1       (0x00000002)
+#define SDR_CONFIG_ENABLE_FM2       (0x00000004)
+#define SDR_CONFIG_DISABLE_ARI      (0x00000010)
+#define SDR_CONFIG_DISABLE_VSB      (0x00000020)
+
+// SET FIR
+#define SDR_FIR_COEFF_MASK          (0x00000FFF)
+#define SDR_FIR_TAP_MASK            (0x001F0000)
+#define SDR_FIR_SELECT_MASK         (0x00C00000)
+#define SDR_VSB_LENGTH_MASK         (0x01000000)
+
+#define SDR_SET_FIR(select, tap, coeff, vsblen)	\
+	((((select)<<22)&SDR_FIR_SELECT_MASK)|			\
+	 (((tap)<<16)&SDR_FIR_TAP_MASK)|				\
+	 ((coeff)&SDR_FIR_COEFF_MASK)|					\
+	 (((vsblen)<<24)&SDR_VSB_LENGTH_MASK)|				\
+	 0								\
+		)
+

ddbridge/ddbridge.c

@@ -1,7 +1,7 @@
 /*
  * ddbridge.c: Digital Devices PCIe bridge driver
  *
- * Copyright (C) 2010-2015 Digital Devices GmbH
+ * Copyright (C) 2010-2017 Digital Devices GmbH
  *                         Ralph Metzler <rjkm@metzlerbros.de>
  *                         Marcus Metzler <mocm@metzlerbros.de>
  *
@@ -29,34 +29,12 @@
 
 #include "ddbridge.h"
 #include "ddbridge-regs.h"
-
-static struct workqueue_struct *ddb_wq;
-
-static int adapter_alloc;
-module_param(adapter_alloc, int, 0444);
-MODULE_PARM_DESC(adapter_alloc,
-		 "0-one adapter per io, 1-one per tab with io, 2-one per tab, 3-one for all");
-
-#ifdef CONFIG_PCI_MSI
-static int msi = 1;
-module_param(msi, int, 0444);
-MODULE_PARM_DESC(msi,
-		 " Control MSI interrupts: 0-disable, 1-enable (default)");
-#endif
-
 #include "ddbridge-core.c"
 
 /****************************************************************************/
 /****************************************************************************/
 /****************************************************************************/
 
-static void ddb_unmap(struct ddb *dev)
-{
-	if (dev->regs)
-		iounmap(dev->regs);
-	vfree(dev);
-}
-
 static void __devexit ddb_irq_disable(struct ddb *dev)
 {
 	if (dev->link[0].info->regmap->irq_version == 2) {
@@ -113,19 +91,23 @@ static void __devexit ddb_remove(struct pci_dev *pdev)
 
 static int __devinit ddb_irq_msi(struct ddb *dev, int nr)
 {
-	int stat;
+	int stat = 0;
 
 #ifdef CONFIG_PCI_MSI
 	if (msi && pci_msi_enabled()) {
 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0))
+		stat = pci_alloc_irq_vectors(dev->pdev, 1, nr, PCI_IRQ_MSI);
+#else
 		stat = pci_enable_msi_range(dev->pdev, 1, nr);
+#endif
 		if (stat >= 1) {
 			dev->msi = stat;
 			pr_info("DDBridge: using %d MSI interrupt(s)\n",
 				dev->msi);
 		} else
 			pr_info("DDBridge: MSI not available.\n");
-		
+
 #else
 		stat = pci_enable_msi_block(dev->pdev, nr);
 		if (stat == 0) {
@@ -135,10 +117,11 @@ static int __devinit ddb_irq_msi(struct ddb *dev, int nr)
 			stat = pci_enable_msi(dev->pdev);
 			dev->msi = 1;
 		}
-		if (stat < 0) 
+		if (stat < 0)
 			pr_info("DDBridge: MSI not available.\n");
 #endif
 	}
+#endif	
 	return stat;
 }
 
@@ -166,7 +149,7 @@ static int __devinit ddb_irq_init2(struct ddb *dev)
 			   irq_flag, "ddbridge", (void *) dev);
 	if (stat < 0)
 		return stat;
-	
+
 	ddbwritel(dev, 0x0000ff7f, INTERRUPT_V2_CONTROL);
 	ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_1);
 	ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_2);
@@ -177,15 +160,15 @@ static int __devinit ddb_irq_init2(struct ddb *dev)
 	ddbwritel(dev, 0xffffffff, INTERRUPT_V2_ENABLE_7);
 	return stat;
 }
-	
+
 static int __devinit ddb_irq_init(struct ddb *dev)
 {
 	int stat;
 	int irq_flag = IRQF_SHARED;
-	
+
 	if (dev->link[0].info->regmap->irq_version == 2)
 		return ddb_irq_init2(dev);
-	
+
 	ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE);
 	ddbwritel(dev, 0x00000000, MSI1_ENABLE);
 	ddbwritel(dev, 0x00000000, MSI2_ENABLE);
@@ -210,9 +193,7 @@ static int __devinit ddb_irq_init(struct ddb *dev)
 			free_irq(dev->pdev->irq, dev);
 			return stat;
 		}
-	} else
-#endif
-	{
+	} else {
 #ifdef DDB_TEST_THREADED
 		stat = request_threaded_irq(dev->pdev->irq, irq_handler,
 					    irq_thread,
@@ -250,7 +231,7 @@ static int __devinit ddb_probe(struct pci_dev *pdev,
 	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
 		if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
 			return -ENODEV;
-	
+
 	dev = vzalloc(sizeof(struct ddb));
 	if (dev == NULL)
 		return -ENOMEM;
@@ -264,10 +245,11 @@ static int __devinit ddb_probe(struct pci_dev *pdev,
 	dev->link[0].ids.vendor = id->vendor;
 	dev->link[0].ids.device = id->device;
 	dev->link[0].ids.subvendor = id->subvendor;
-	dev->link[0].ids.subdevice = id->subdevice;
-
+	dev->link[0].ids.subdevice = pdev->subsystem_device;
+	
 	dev->link[0].dev = dev;
-	dev->link[0].info = (struct ddb_info *) id->driver_data;
+	dev->link[0].info = get_ddb_info(id->vendor, id->device,
+					 id->subvendor, pdev->subsystem_device);
 	pr_info("DDBridge: device name: %s\n", dev->link[0].info->name);
 
 	dev->regs_len = pci_resource_len(dev->pdev, 0);
@@ -300,18 +282,19 @@ static int __devinit ddb_probe(struct pci_dev *pdev,
 		ddbwritel(dev, 0, DMA_BASE_WRITE);
 
 	if (dev->link[0].info->type == DDB_MOD) {
-		if  (ddbreadl(dev, 0x1c) == 4)
-			dev->link[0].info->port_num = 4;
+		if (dev->link[0].info->version == 1)
+			if (ddbreadl(dev, 0x1c) == 4)
+				dev->link[0].info->port_num = 4;
 	}
 
 	stat = ddb_irq_init(dev);
 	if (stat < 0)
 		goto fail0;
-	
+
 	if (ddb_init(dev) == 0)
 		return 0;
 
-	ddb_irq_disable(dev);
+	ddb_irq_exit(dev);
 fail0:
 	pr_err("DDBridge: fail0\n");
 	if (dev->msi)
@@ -329,284 +312,35 @@ fail:
 /****************************************************************************/
 /****************************************************************************/
 
-static struct ddb_info ddb_none = {
-	.type     = DDB_NONE,
-	.name     = "unknown Digital Devices PCIe card, install newer driver",
-	.regmap   = &octopus_map,
-};
+#define DDB_DEVICE_ANY(_device) { PCI_DEVICE_SUB(0xdd01, _device, 0xdd01, PCI_ANY_ID) }
 
-static struct ddb_info ddb_octopus = {
-	.type     = DDB_OCTOPUS,
-	.name     = "Digital Devices Octopus DVB adapter",
-	.regmap   = &octopus_map,
-	.port_num = 4,
-	.i2c_mask = 0x0f,
-};
-
-static struct ddb_info ddb_octopusv3 = {
-	.type     = DDB_OCTOPUS,
-	.name     = "Digital Devices Octopus V3 DVB adapter",
-	.regmap   = &octopus_map,
-	.port_num = 4,
-	.i2c_mask = 0x0f,
-};
-
-static struct ddb_info ddb_octopus_le = {
-	.type     = DDB_OCTOPUS,
-	.name     = "Digital Devices Octopus LE DVB adapter",
-	.regmap   = &octopus_map,
-	.port_num = 2,
-	.i2c_mask = 0x03,
-};
-
-static struct ddb_info ddb_octopus_oem = {
-	.type     = DDB_OCTOPUS,
-	.name     = "Digital Devices Octopus OEM",
-	.regmap   = &octopus_map,
-	.port_num = 4,
-	.i2c_mask = 0x0f,
-	.led_num  = 1,
-	.fan_num  = 1,
-	.temp_num = 1,
-	.temp_bus = 0,
-};
-
-static struct ddb_info ddb_octopus_mini = {
-	.type     = DDB_OCTOPUS,
-	.name     = "Digital Devices Octopus Mini",
-	.regmap   = &octopus_map,
-	.port_num = 4,
-	.i2c_mask = 0x0f,
-};
-
-static struct ddb_info ddb_v6 = {
-	.type     = DDB_OCTOPUS,
-	.name     = "Digital Devices Cine S2 V6 DVB adapter",
-	.regmap   = &octopus_map,
-	.port_num = 3,
-	.i2c_mask = 0x07,
-};
-
-static struct ddb_info ddb_v6_5 = {
-	.type     = DDB_OCTOPUS,
-	.name     = "Digital Devices Cine S2 V6.5 DVB adapter",
-	.regmap   = &octopus_map,
-	.port_num = 4,
-	.i2c_mask = 0x0f,
-};
-
-static struct ddb_info ddb_v7a = {
-	.type     = DDB_OCTOPUS,
-	.name     = "Digital Devices Cine S2 V7 Advanced DVB adapter",
-	.regmap   = &octopus_map,
-	.port_num = 4,
-	.i2c_mask = 0x0f,
-	.board_control   = 2,
-	.board_control_2 = 4,
-	.ts_quirks = TS_QUIRK_REVERSED,
-};
-
-static struct ddb_info ddb_v7 = {
-	.type     = DDB_OCTOPUS,
-	.name     = "Digital Devices Cine S2 V7 DVB adapter",
-	.regmap   = &octopus_map,
-	.port_num = 4,
-	.i2c_mask = 0x0f,
-	.board_control   = 2,
-	.board_control_2 = 4,
-	.ts_quirks = TS_QUIRK_REVERSED,
-};
-
-static struct ddb_info ddb_ctv7 = {
-	.type     = DDB_OCTOPUS,
-	.name     = "Digital Devices Cine CT V7 DVB adapter",
-	.regmap   = &octopus_map,
-	.port_num = 4,
-	.i2c_mask = 0x0f,
-	.board_control   = 3,
-	.board_control_2 = 4,
-};
-
-static struct ddb_info ddb_satixS2v3 = {
-	.type     = DDB_OCTOPUS,
-	.name     = "Mystique SaTiX-S2 V3 DVB adapter",
-	.regmap   = &octopus_map,
-	.port_num = 3,
-	.i2c_mask = 0x07,
-};
-
-static struct ddb_info ddb_ci = {
-	.type     = DDB_OCTOPUS_CI,
-	.name     = "Digital Devices Octopus CI",
-	.regmap   = &octopus_map,
-	.port_num = 4,
-	.i2c_mask = 0x03,
-};
-
-static struct ddb_info ddb_cis = {
-	.type     = DDB_OCTOPUS_CI,
-	.name     = "Digital Devices Octopus CI single",
-	.regmap   = &octopus_map,
-	.port_num = 3,
-	.i2c_mask = 0x03,
-};
-
-static struct ddb_info ddb_ci_s2_pro = {
-	.type     = DDB_OCTOPUS_CI,
-	.name     = "Digital Devices Octopus CI S2 Pro",
-	.regmap   = &octopus_map,
-	.port_num = 4,
-	.i2c_mask = 0x01,
-	.board_control   = 2,
-	.board_control_2 = 4,
-};
-
-static struct ddb_info ddb_ci_s2_pro_a = {
-	.type     = DDB_OCTOPUS_CI,
-	.name     = "Digital Devices Octopus CI S2 Pro Advanced",
-	.regmap   = &octopus_map,
-	.port_num = 4,
-	.i2c_mask = 0x01,
-	.board_control   = 2,
-	.board_control_2 = 4,
-};
-
-static struct ddb_info ddb_dvbct = {
-	.type     = DDB_OCTOPUS,
-	.name     = "Digital Devices DVBCT V6.1 DVB adapter",
-	.regmap   = &octopus_map,
-	.port_num = 3,
-	.i2c_mask = 0x07,
-};
-
-/****************************************************************************/
-
-static struct ddb_info ddb_mod = {
-	.type     = DDB_MOD,
-	.name     = "Digital Devices DVB-C modulator",
-	.regmap   = &octopus_mod_map,
-	.port_num = 10,
-	.temp_num = 1,
-};
-
-static struct ddb_info ddb_mod_fsm_24 = {
-	.type     = DDB_MOD,
-	.version  = 2,
-	.name     = "Digital Devices DVB-C modulator FSM-24",
-	.regmap   = &octopus_mod_2_map,
-	.port_num = 24,
-	.temp_num = 1,
-	.tempmon_irq = 8,
-};
-
-static struct ddb_info ddb_mod_fsm_16 = {
-	.type     = DDB_MOD,
-	.version  = 2,
-	.name     = "Digital Devices DVB-C modulator FSM-16",
-	.regmap   = &octopus_mod_2_map,
-	.port_num = 16,
-	.temp_num = 1,
-	.tempmon_irq = 8,
-};
-
-static struct ddb_info ddb_mod_fsm_8 = {
-	.type     = DDB_MOD,
-	.name     = "Digital Devices DVB-C modulator FSM-8",
-	.version  = 2,
-	.regmap   = &octopus_mod_2_map,
-	.port_num = 8,
-	.temp_num = 1,
-	.tempmon_irq = 8,
-};
-
-static struct ddb_info ddb_octopro_hdin = {
-	.type     = DDB_OCTOPRO_HDIN,
-	.name     = "Digital Devices OctopusNet Pro HDIN",
-	.regmap   = &octopro_hdin_map,
-	.port_num = 10,
-	.i2c_mask = 0x3ff,
-	.mdio_num = 1,
-};
-
-static struct ddb_info ddb_octopro = {
-	.type     = DDB_OCTOPRO,
-	.name     = "Digital Devices OctopusNet Pro",
-	.regmap   = &octopro_map,
-	.port_num = 10,
-	.i2c_mask = 0x3ff,
-	.mdio_num = 1,
-};
-
-/****************************************************************************/
-/****************************************************************************/
-/****************************************************************************/
-
-#define DDVID 0xdd01 /* Digital Devices Vendor ID */
-
-#define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \
-	.vendor      = _vend,    .device    = _dev, \
-	.subvendor   = _subvend, .subdevice = _subdev, \
-	.driver_data = (unsigned long)&_driverdata }
-
-static const struct pci_device_id ddb_id_tbl[] __devinitconst = {
-	DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus),
-	DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus),
-	DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopusv3),
-	DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le),
-	DDB_ID(DDVID, 0x0003, DDVID, 0x0003, ddb_octopus_oem),
-	DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini),
-	DDB_ID(DDVID, 0x0005, DDVID, 0x0011, ddb_octopus_mini),
-	DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6),
-	DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5),
-	DDB_ID(DDVID, 0x0006, DDVID, 0x0022, ddb_v7),
-	DDB_ID(DDVID, 0x0006, DDVID, 0x0024, ddb_v7a),
-	DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct),
-	DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3),
-	DDB_ID(DDVID, 0x0006, DDVID, 0x0031, ddb_ctv7),
-	DDB_ID(DDVID, 0x0006, DDVID, 0x0032, ddb_ctv7),
-	DDB_ID(DDVID, 0x0006, DDVID, 0x0033, ddb_ctv7),
-	DDB_ID(DDVID, 0x0007, DDVID, 0x0023, ddb_s2_48),
-	DDB_ID(DDVID, 0x0008, DDVID, 0x0034, ddb_ct2_8),
-	DDB_ID(DDVID, 0x0008, DDVID, 0x0035, ddb_c2t2_8),
-	DDB_ID(DDVID, 0x0008, DDVID, 0x0036, ddb_isdbt_8),
-	DDB_ID(DDVID, 0x0008, DDVID, 0x0037, ddb_c2t2i_v0_8),
-	DDB_ID(DDVID, 0x0008, DDVID, 0x0038, ddb_c2t2i_8),
-	DDB_ID(DDVID, 0x0006, DDVID, 0x0039, ddb_ctv7),
-	DDB_ID(DDVID, 0x0011, DDVID, 0x0040, ddb_ci),
-	DDB_ID(DDVID, 0x0011, DDVID, 0x0041, ddb_cis),
-	DDB_ID(DDVID, 0x0012, DDVID, 0x0042, ddb_ci),
-	DDB_ID(DDVID, 0x0013, DDVID, 0x0043, ddb_ci_s2_pro),
-	DDB_ID(DDVID, 0x0013, DDVID, 0x0044, ddb_ci_s2_pro_a),
-	DDB_ID(DDVID, 0x0201, DDVID, 0x0001, ddb_mod),
-	DDB_ID(DDVID, 0x0201, DDVID, 0x0002, ddb_mod),
-	DDB_ID(DDVID, 0x0203, DDVID, 0x0001, ddb_mod),
-	DDB_ID(DDVID, 0x0210, DDVID, 0x0001, ddb_mod_fsm_24),
-	DDB_ID(DDVID, 0x0210, DDVID, 0x0002, ddb_mod_fsm_16),
-	DDB_ID(DDVID, 0x0210, DDVID, 0x0003, ddb_mod_fsm_8),
-	/* testing on OctopusNet Pro */
-	DDB_ID(DDVID, 0x0320, PCI_ANY_ID, PCI_ANY_ID, ddb_octopro_hdin),
-	DDB_ID(DDVID, 0x0321, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
-	DDB_ID(DDVID, 0x0322, PCI_ANY_ID, PCI_ANY_ID, ddb_octopro),
-	DDB_ID(DDVID, 0x0323, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
-	DDB_ID(DDVID, 0x0328, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
-	DDB_ID(DDVID, 0x0329, PCI_ANY_ID, PCI_ANY_ID, ddb_octopro_hdin),
-	/* in case sub-ids got deleted in flash */
-	DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
-	DDB_ID(DDVID, 0x0005, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
-	DDB_ID(DDVID, 0x0006, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
-	DDB_ID(DDVID, 0x0007, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
-	DDB_ID(DDVID, 0x0008, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
-	DDB_ID(DDVID, 0x0011, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
-	DDB_ID(DDVID, 0x0013, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
-	DDB_ID(DDVID, 0x0201, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
-	DDB_ID(DDVID, 0x0320, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
+static const struct pci_device_id ddb_id_table[] __devinitconst = {
+	DDB_DEVICE_ANY(0x0002),
+	DDB_DEVICE_ANY(0x0003),
+	DDB_DEVICE_ANY(0x0005),
+	DDB_DEVICE_ANY(0x0006),
+	DDB_DEVICE_ANY(0x0007),
+	DDB_DEVICE_ANY(0x0008),
+	DDB_DEVICE_ANY(0x0011),
+	DDB_DEVICE_ANY(0x0012),
+	DDB_DEVICE_ANY(0x0013),
+	DDB_DEVICE_ANY(0x0201),
+	DDB_DEVICE_ANY(0x0203),
+	DDB_DEVICE_ANY(0x0210),
+	DDB_DEVICE_ANY(0x0220),
+	DDB_DEVICE_ANY(0x0320),
+	DDB_DEVICE_ANY(0x0321),
+	DDB_DEVICE_ANY(0x0322),
+	DDB_DEVICE_ANY(0x0323),
+	DDB_DEVICE_ANY(0x0328),
+	DDB_DEVICE_ANY(0x0329),
 	{0}
 };
-MODULE_DEVICE_TABLE(pci, ddb_id_tbl);
+MODULE_DEVICE_TABLE(pci, ddb_id_table);
 
 static struct pci_driver ddb_pci_driver = {
 	.name        = "ddbridge",
-	.id_table    = ddb_id_tbl,
+	.id_table    = ddb_id_table,
 	.probe       = ddb_probe,
 	.remove      = ddb_remove,
 };
@@ -617,7 +351,7 @@ static __init int module_init_ddbridge(void)
 
 	pr_info("DDBridge: Digital Devices PCIE bridge driver "
 		DDBRIDGE_VERSION
-		", Copyright (C) 2010-16 Digital Devices GmbH\n");
+		", Copyright (C) 2010-17 Digital Devices GmbH\n");
 	if (ddb_class_create() < 0)
 		return -1;
 	ddb_wq = create_workqueue("ddbridge");

ddbridge/ddbridge.h

@@ -1,7 +1,7 @@
 /*
  * ddbridge.h: Digital Devices PCIe bridge driver
  *
- * Copyright (C) 2010-2015 Digital Devices GmbH
+ * Copyright (C) 2010-2017 Digital Devices GmbH
  *                         Ralph Metzler <rmetzler@digitaldevices.de>
  *
  * This program is free software; you can redistribute it and/or
@@ -55,7 +55,6 @@
 #include <linux/completion.h>
 
 #include <linux/types.h>
-#include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/mutex.h>
 #include <asm/dma.h>
@@ -123,7 +122,7 @@ struct ddb_regmap {
 
 	struct ddb_regset *input;
 	struct ddb_regset *output;
-	
+
 	struct ddb_regset *channel;
 	//struct ddb_regset *ci;
 	//struct ddb_regset *pid_filter;
@@ -178,7 +177,8 @@ struct ddb_info {
 };
 
 /* DMA_SIZE MUST be smaller than 256k and
-   MUST be divisible by 188 and 128 !!! */
+ * MUST be divisible by 188 and 128 !!!
+ */
 
 #define DMA_MAX_BUFS 32      /* hardware table limit */
 
@@ -199,6 +199,10 @@ struct ddb_info {
 #define OUTPUT_DMA_SIZE (128*47*21)
 #define OUTPUT_DMA_IRQ_DIV 1
 #endif
+#define OUTPUT_DMA_BUFS_SDR 32
+#define OUTPUT_DMA_SIZE_SDR (256*1024)
+#define OUTPUT_DMA_IRQ_DIV_SDR 1
+
 
 struct ddb;
 struct ddb_port;
@@ -345,13 +349,13 @@ struct mod_base {
 
 struct ddb_mod {
 	struct ddb_port       *port;
-	u32                    nr;
-	u32                    regs;
-	
+	//u32                    nr;
+	//u32                    regs;
+
 	u32                    frequency;
 	u32                    modulation;
 	u32                    symbolrate;
-	
+
 	u64                    obitrate;
 	u64                    ibitrate;
 	u32                    pcr_correction;
@@ -678,15 +682,6 @@ static void ddbcpyfrom(struct ddb *dev, void *dst, u32 adr, long count)
 	return memcpy_fromio(dst, (char *) (dev->regs + adr), count);
 }
 
-#if 0
-
-#define ddbcpyto(_dev, _adr, _src, _count) \
-	memcpy_toio((char *) (_dev->regs + (_adr)), (_src), (_count))
-
-#define ddbcpyfrom(_dev, _dst, _adr, _count) \
-	memcpy_fromio((_dst), (char *) (_dev->regs + (_adr)), (_count))
-#endif
-
 #define ddbmemset(_dev, _adr, _val, _count) \
 	memset_io((char *) (_dev->regs + (_adr)), (_val), (_count))
 
@@ -753,6 +748,10 @@ void ddbridge_mod_rate_handler(unsigned long data);
 
 int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len);
 
-#define DDBRIDGE_VERSION "0.9.28"
+#define DDBRIDGE_VERSION "0.9.30"
+
+/* linked functions */
+
+struct ddb_info *get_ddb_info(u16 vendor, u16 device, u16 subvendor, u16 subdevice);
 
 #endif

ddbridge/octonet.c

@@ -1,7 +1,7 @@
 /*
  * octonet.c: Digital Devices network tuner driver
  *
- * Copyright (C) 2012-16 Digital Devices GmbH
+ * Copyright (C) 2012-17 Digital Devices GmbH
  *                       Marcus Metzler <mocm@metzlerbros.de>
  *                       Ralph Metzler <rjkm@metzlerbros.de>
  *
@@ -31,83 +31,8 @@
 #include <linux/pci-dma-compat.h>
 #endif
 
-static int adapter_alloc = 3;
-module_param(adapter_alloc, int, 0444);
-MODULE_PARM_DESC(adapter_alloc,
-"0-one adapter per io, 1-one per tab with io, 2-one per tab, 3-one for all");
-
 #include "ddbridge-core.c"
 
-static struct ddb_regmap octopus_net_map = {
-	.irq_version = 1,
-	.irq_base_i2c = 0,
-	.i2c = &octopus_i2c,
-	.i2c_buf = &octopus_i2c_buf,
-	.input = &octopus_input,
-	.output = &octopus_output,
-};
-
-static struct ddb_regset octopus_gtl = {
-	.base = 0x180,
-	.num  = 0x01,
-	.size = 0x20,
-};
-
-static struct ddb_regmap octopus_net_gtl = {
-	.irq_version = 1,
-	.irq_base_i2c = 0,
-	.irq_base_gtl = 10,
-	.i2c = &octopus_i2c,
-	.i2c_buf = &octopus_i2c_buf,
-	.input = &octopus_input,
-	.output = &octopus_output,
-	.gtl = &octopus_gtl,
-};
-
-static struct ddb_info ddb_octonet = {
-	.type     = DDB_OCTONET,
-	.name     = "Digital Devices OctopusNet network DVB adapter",
-	.regmap   = &octopus_net_map,
-	.port_num = 4,
-	.i2c_mask = 0x0f,
-	.ns_num   = 12,
-	.mdio_num = 1,
-};
-
-static struct ddb_info ddb_octonet_jse = {
-	.type     = DDB_OCTONET,
-	.name     = "Digital Devices OctopusNet network DVB adapter JSE",
-	.regmap   = &octopus_net_map,
-	.port_num = 4,
-	.i2c_mask = 0x0f,
-	.ns_num   = 15,
-	.mdio_num = 1,
-};
-
-static struct ddb_info ddb_octonet_gtl = {
-	.type     = DDB_OCTONET,
-	.name     = "Digital Devices OctopusNet GTL",
-	.regmap   = &octopus_net_gtl,
-	.port_num = 4,
-	.i2c_mask = 0x05,
-	.ns_num   = 12,
-	.mdio_num = 1,
-	.con_clock = 1,
-};
-
-static struct ddb_info ddb_octonet_tbd = {
-	.type     = DDB_OCTONET,
-	.name     = "Digital Devices OctopusNet",
-	.regmap   = &octopus_net_map,
-};
-
-static void octonet_unmap(struct ddb *dev)
-{
-	if (dev->regs)
-		iounmap(dev->regs);
-	vfree(dev);
-}
-
 static int __exit octonet_remove(struct platform_device *pdev)
 {
 	struct ddb *dev;
@@ -125,7 +50,7 @@ static int __exit octonet_remove(struct platform_device *pdev)
 
 	free_irq(platform_get_irq(dev->pfdev, 0), dev);
 	ddb_ports_release(dev);
-	octonet_unmap(dev);
+	ddb_unmap(dev);
 	platform_set_drvdata(pdev, 0);
 	return 0;
 }
@@ -168,6 +93,7 @@ static int __init octonet_probe(struct platform_device *pdev)
 	dev->link[0].ids.subdevice = dev->link[0].ids.devid >> 16;
 
 	dev->link[0].dev = dev;
+#if 0
 	if (dev->link[0].ids.devid == 0x0300dd01)
 		dev->link[0].info = &ddb_octonet;
 	else if (dev->link[0].ids.devid == 0x0301dd01)
@@ -176,7 +102,11 @@ static int __init octonet_probe(struct platform_device *pdev)
 		dev->link[0].info = &ddb_octonet_gtl;
 	else
 		dev->link[0].info = &ddb_octonet_tbd;
-
+#else
+	dev->link[0].info = get_ddb_info(dev->link[0].ids.vendor,
+					 dev->link[0].ids.device,
+					 0xdd01, 0xffff);
+#endif
 	pr_info("DDBridge: HW  %08x REGMAP %08x\n",
 		dev->link[0].ids.hwid, dev->link[0].ids.regmapid);
 	pr_info("DDBridge: MAC %08x DEVID  %08x\n",
@@ -203,7 +133,7 @@ fail:
 	dev_err(dev->dev, "fail\n");
 	ddbwritel(dev, 0, ETHER_CONTROL);
 	ddbwritel(dev, 0, INTERRUPT_ENABLE);
-	octonet_unmap(dev);
+	ddb_unmap(dev);
 	platform_set_drvdata(pdev, 0);
 	return -1;
 }
@@ -217,7 +147,7 @@ static const struct of_device_id octonet_dt_ids[] = {
 MODULE_DEVICE_TABLE(of, octonet_dt_ids);
 #endif
 
-static struct platform_driver octonet_driver = {
+static struct platform_driver octonet_driver __refdata = {
 	.remove	= __exit_p(octonet_remove),
 	.probe	= octonet_probe,
 	.driver		= {
@@ -258,4 +188,4 @@ module_exit(exit_octonet);
 MODULE_DESCRIPTION("GPL");
 MODULE_AUTHOR("Marcus and Ralph Metzler, Metzler Brothers Systementwicklung GbR");
 MODULE_LICENSE("GPL");
-MODULE_VERSION("0.6");
+MODULE_VERSION(DDBRIDGE_VERSION);

dvb-core/dvb_ca_en50221.c

@@ -35,7 +35,12 @@
 #include <linux/vmalloc.h>
 #include <linux/delay.h>
 #include <linux/spinlock.h>
+#include <linux/version.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0))
+#include <linux/sched/signal.h>
+#else
 #include <linux/sched.h>
+#endif
 #include <linux/kthread.h>
 
 #include "dvb_ca_en50221.h"
@@ -763,7 +768,7 @@ static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, u8 * b
 		status = -EAGAIN;
 		goto exit;
 	}
-#if 0
+
 	/* It may need some time for the CAM to settle down, or there might be a
 	   race condition between the CAM, writing HC and our last check for DA.
 	   This happens, if the CAM asserts DA, just after checking DA before we
@@ -781,7 +786,7 @@ static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, u8 * b
 		status = -EAGAIN;
 		goto exit;
 	}
-#endif
+
 	/* send the amount of data */
 	if ((status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_SIZE_HIGH, bytes_write >> 8)) != 0)
 		goto exit;

dvb-core/dvb_demux.c

@@ -21,7 +21,12 @@
  *
  */
 
+#include <linux/version.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0))
+#include <linux/sched/signal.h>
+#else
 #include <linux/sched.h>
+#endif
 #include <linux/spinlock.h>
 #include <linux/slab.h>
 #include <linux/vmalloc.h>

dvb-core/dvb_frontend.h

@@ -29,7 +29,12 @@
 #define _DVB_FRONTEND_H_
 
 #include <linux/types.h>
+#include <linux/version.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0))
+#include <linux/sched/signal.h>
+#else
 #include <linux/sched.h>
+#endif
 #include <linux/ioctl.h>
 #include <linux/i2c.h>
 #include <linux/module.h>

dvb-core/dvb_ringbuffer.c

@@ -31,7 +31,12 @@
 #include <linux/module.h>
 #include <linux/sched.h>
 #include <linux/string.h>
+#include <linux/version.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
 #include <asm/uaccess.h>
+#else
+#include <linux/uaccess.h>
+#endif
 
 #include "dvb_ringbuffer.h"
 

dvb-core/dvbdev.h

@@ -33,7 +33,7 @@
 #if defined(CONFIG_DVB_MAX_ADAPTERS) && CONFIG_DVB_MAX_ADAPTERS > 0
   #define DVB_MAX_ADAPTERS CONFIG_DVB_MAX_ADAPTERS
 #else
-  #define DVB_MAX_ADAPTERS 8
+  #define DVB_MAX_ADAPTERS 64
 #endif
 
 #define DVB_UNSET (-1)

frontends/cxd2099.c

@@ -662,15 +662,19 @@ static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
 static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
 {
 	struct cxd *ci = ca->data;
-
+	int status;
+	
 	if (ci->write_busy)
 		return -EAGAIN;
 	mutex_lock(&ci->lock);
 	write_reg(ci, 0x0d, ecount >> 8);
 	write_reg(ci, 0x0e, ecount & 0xff);
-	write_block(ci, 0x11, ebuf, ecount);
-	ci->write_busy = 1;
+	status = write_block(ci, 0x11, ebuf, ecount);
+	if (!status)
+		ci->write_busy = 1;
 	mutex_unlock(&ci->lock);
+	if (status)
+		return status;
 	return ecount;
 }
 #endif

frontends/cxd2843.c

@@ -270,9 +270,10 @@ static int writebitsx(struct cxd_state *cxd, u8 Bank, u8 Address,
 	mutex_lock(&cxd->mutex);
 	status = readregsx_unlocked(cxd, Bank, Address, &tmp, 1);
 	if (status < 0)
-		return status;
+		goto out;
 	tmp = (tmp & ~Mask) | Value;
 	status = writeregsx_unlocked(cxd, Bank, Address, &tmp, 1);
+out:
 	mutex_unlock(&cxd->mutex);
 	return status;
 }
@@ -286,9 +287,10 @@ static int writebitst(struct cxd_state *cxd, u8 Bank, u8 Address,
 	mutex_lock(&cxd->mutex);
 	status = readregst_unlocked(cxd, Bank, Address, &Tmp, 1);
 	if (status < 0)
-		return status;
+		goto out;
 	Tmp = (Tmp & ~Mask) | Value;
 	status = writeregst_unlocked(cxd, Bank, Address, &Tmp, 1);
+out:
 	mutex_unlock(&cxd->mutex);
 	return status;
 }

frontends/lnbh25.c

@@ -146,7 +146,7 @@ struct dvb_frontend *lnbh25_attach(struct dvb_frontend *fe,
 	fe->ops.enable_high_lnb_voltage = lnbh25_enable_high_lnb_voltage;
 	fe->ops.release_sec = lnbh25_release;
 
-	pr_info("LNB25 on %02x\n", lnbh->adr);
+	pr_info("LNBH25 on %02x\n", lnbh->adr);
 
 	return fe;
 }

frontends/mxl5xx.c

@@ -841,8 +841,8 @@ static struct dvb_frontend_ops mxl_ops = {
 	.xbar   = { 4, 0, 8 }, /* tuner_max, demod id, demod_max */
 	.info = {
 		.name			= "MXL5XX",
-		.frequency_min		= 950000,
-		.frequency_max		= 2150000,
+		.frequency_min		= 300000,
+		.frequency_max		= 2350000,
 		.frequency_stepsize	= 0,
 		.frequency_tolerance	= 0,
 		.symbol_rate_min	= 1000000,

frontends/stv0910.c

@@ -673,6 +673,7 @@ static int GetBitErrorRateS(struct stv *state, u32 *BERNumerator,
 static u32 DVBS2_nBCH(enum DVBS2_ModCod ModCod, enum DVBS2_FECType FECType)
 {
 	static u32 nBCH[][2] = {
+		{    0,     0}, /* dummy */
 		{16200,  3240}, /* QPSK_1_4, */
 		{21600,  5400}, /* QPSK_1_3, */
 		{25920,  6480}, /* QPSK_2_5, */
@@ -705,7 +706,7 @@ static u32 DVBS2_nBCH(enum DVBS2_ModCod ModCod, enum DVBS2_FECType FECType)
 
 	if (ModCod >= DVBS2_QPSK_1_4 &&
 	    ModCod <= DVBS2_32APSK_9_10 && FECType <= DVBS2_16K)
-		return nBCH[FECType][ModCod];
+		return nBCH[ModCod][FECType];
 	return 64800;
 }
 
@@ -1534,13 +1535,13 @@ static int tune(struct dvb_frontend *fe, bool re_tune,
 			return r;
 		state->tune_time = jiffies;
 	}
-	if (*status & FE_HAS_LOCK)
-		return 0;
-	*delay = HZ;
-
 	r = read_status(fe, status);
 	if (r)
 		return r;
+
+	if (*status & FE_HAS_LOCK)
+		return 0;
+	*delay = HZ / 10;
 	return 0;
 }
 
@@ -1781,7 +1782,8 @@ static struct dvb_frontend_ops stv0910_ops = {
 		.caps			= FE_CAN_INVERSION_AUTO |
 					  FE_CAN_FEC_AUTO       |
 					  FE_CAN_QPSK           |
-					  FE_CAN_2G_MODULATION
+					  FE_CAN_2G_MODULATION  |
+		                          FE_CAN_MULTISTREAM,
 	},
 	.init				= init,
 	.sleep				= sleep,

include/linux/dvb/mod.h

@@ -25,9 +25,11 @@ struct dvb_mod_channel_params {
 #define MODULATOR_FREQUENCY	  3
 #define MODULATOR_MODULATION	  4   
 #define MODULATOR_SYMBOL_RATE	  5   /* Hz */
+#define MODULATOR_BASE_FREQUENCY  6
 #define MODULATOR_ATTENUATOR     32  
 #define MODULATOR_INPUT_BITRATE  33  /* Hz */
 #define MODULATOR_PCR_MODE       34  /* 1=pcr correction enabled */
-
+#define MODULATOR_GAIN           35
+#define MODULATOR_OUTPUT_ARI     64
 
 #endif /*_UAPI_DVBMOD_H_*/