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initial commit from dddvb-0.9.19c

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mvoelkel
2015-08-05 17:22:42 +02:00
commit 9e2128c4fb
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37
frontends/Makefile Normal file
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#
# Makefile for the kernel DVB frontend device drivers.
#
EXTRA_CFLAGS += -DCONFIG_DVB_LNBP21
EXTRA_CFLAGS += -DCONFIG_DVB_STV090x
EXTRA_CFLAGS += -DCONFIG_DVB_STV6110x
#EXTRA_CFLAGS += -DCONFIG_DVB_STV0367
EXTRA_CFLAGS += -DCONFIG_DVB_STV0367DD
#EXTRA_CFLAGS += -DCONFIG_DVB_TDA18212
EXTRA_CFLAGS += -DCONFIG_DVB_TDA18212DD
EXTRA_CFLAGS += -DCONFIG_DVB_CXD2843
EXTRA_CFLAGS += -DCONFIG_DVB_STV6111
EXTRA_CFLAGS += -DCONFIG_DVB_STV0910
EXTRA_CFLAGS += -DCONFIG_DVB_LNBH25
EXTRA_CFLAGS += -DCONFIG_DVB_MXL5XX
EXTRA_CFLAGS += -DDBVALS
NOSTDINC_FLAGS += -I$(SUBDIRS)/include -I$(SUBDIRS)/dvb-core
drxk-objs := drxk_hard.o
obj-$(CONFIG_DVB_DRXK) += drxk.o
obj-$(CONFIG_DVB_LNBP21) += lnbp21.o
obj-$(CONFIG_DVB_STV090x) += stv090x.o
obj-$(CONFIG_DVB_STV6110x) += stv6110x.o
obj-$(CONFIG_DVB_CXD2099) += cxd2099.o
obj-$(CONFIG_DVB_TDA18271C2DD) += tda18271c2dd.o
#obj-$(CONFIG_DVB_STV0367) += stv0367.o
obj-$(CONFIG_DVB_STV0367DD) += stv0367dd.o
#obj-$(CONFIG_DVB_TDA18212) += tda18212.o
obj-$(CONFIG_DVB_TDA18212DD) += tda18212dd.o
obj-$(CONFIG_DVB_CXD2843) += cxd2843.o
obj-$(CONFIG_DVB_STV6111) += stv6111.o
obj-$(CONFIG_DVB_STV0910) += stv0910.o
obj-$(CONFIG_DVB_LNBH25) += lnbh25.o
obj-$(CONFIG_DVB_MXL5XX) += mxl5xx.o

726
frontends/cxd2099.c Normal file
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/*
* cxd2099.c: Driver for the CXD2099AR Common Interface Controller
*
* Copyright (C) 2010-2013 Digital Devices GmbH
*
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA
* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/version.h>
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/wait.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/io.h>
#include "cxd2099.h"
//#define BUFFER_MODE 1
static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount);
struct cxd {
struct dvb_ca_en50221 en;
struct i2c_adapter *i2c;
struct cxd2099_cfg cfg;
u8 regs[0x23];
u8 lastaddress;
u8 clk_reg_f;
u8 clk_reg_b;
int mode;
int ready;
int dr;
int write_busy;
int slot_stat;
u8 amem[1024];
int amem_read;
int cammode;
struct mutex lock;
u8 rbuf[1028];
u8 wbuf[1028];
};
static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr,
u8 reg, u8 data)
{
u8 m[2] = {reg, data};
struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2};
if (i2c_transfer(adapter, &msg, 1) != 1) {
pr_err("Failed to write to I2C register %02x@%02x!\n",
reg, adr);
return -1;
}
return 0;
}
static int i2c_write(struct i2c_adapter *adapter, u8 adr,
u8 *data, u16 len)
{
struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len};
if (i2c_transfer(adapter, &msg, 1) != 1) {
pr_err("Failed to write to I2C!\n");
return -1;
}
return 0;
}
static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr,
u8 reg, u8 *val)
{
struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
.buf = &reg, .len = 1},
{.addr = adr, .flags = I2C_M_RD,
.buf = val, .len = 1} };
if (i2c_transfer(adapter, msgs, 2) != 2) {
pr_err("error in i2c_read_reg\n");
return -1;
}
return 0;
}
static int i2c_read(struct i2c_adapter *adapter, u8 adr,
u8 reg, u8 *data, u16 n)
{
struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
.buf = &reg, .len = 1},
{.addr = adr, .flags = I2C_M_RD,
.buf = data, .len = n} };
if (i2c_transfer(adapter, msgs, 2) != 2) {
pr_err("error in i2c_read\n");
return -1;
}
return 0;
}
static int read_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
{
int status = 0;
if (ci->lastaddress != adr)
status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
if (!status) {
ci->lastaddress = adr;
while (n) {
int len = n;
if (ci->cfg.max_i2c &&
len > ci->cfg.max_i2c)
len = ci->cfg.max_i2c;
status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, len);
if (status)
return status;
data += len;
n -= len;
}
}
return status;
}
static int read_reg(struct cxd *ci, u8 reg, u8 *val)
{
return read_block(ci, reg, val, 1);
}
static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
{
int status;
u8 addr[3] = {2, address & 0xff, address >> 8};
status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
if (!status)
status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
return status;
}
static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
{
int status;
u8 addr[3] = {2, address & 0xff, address >> 8};
status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
if (!status) {
u8 buf[256] = {3};
memcpy(buf + 1, data, n);
status = i2c_write(ci->i2c, ci->cfg.adr, buf, n+1);
}
return status;
}
static int read_io(struct cxd *ci, u16 address, u8 *val)
{
int status;
u8 addr[3] = {2, address & 0xff, address >> 8};
status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
if (!status)
status = i2c_read(ci->i2c, ci->cfg.adr, 3, val, 1);
return status;
}
static int write_io(struct cxd *ci, u16 address, u8 val)
{
int status;
u8 addr[3] = {2, address & 0xff, address >> 8};
u8 buf[2] = {3, val};
status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
if (!status)
status = i2c_write(ci->i2c, ci->cfg.adr, buf, 2);
return status;
}
#if 0
static int read_io_data(struct cxd *ci, u8 *data, u16 n)
{
int status;
u8 addr[3] = { 2, 0, 0 };
status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
if (!status)
status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
return 0;
}
static int write_io_data(struct cxd *ci, u8 *data, u16 n)
{
int status;
u8 addr[3] = {2, 0, 0};
status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
if (!status) {
u8 buf[256] = {3};
memcpy(buf + 1, data, n);
status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1);
}
return 0;
}
#endif
static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
{
int status = 0;
if (ci->lastaddress != reg)
status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg);
if (!status && reg >= 6 && reg <= 8 && mask != 0xff)
status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]);
ci->lastaddress = reg;
ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
if (!status)
status = i2c_write_reg(ci->i2c, ci->cfg.adr, 1, ci->regs[reg]);
if (reg == 0x20)
ci->regs[reg] &= 0x7f;
return status;
}
static int write_reg(struct cxd *ci, u8 reg, u8 val)
{
return write_regm(ci, reg, val, 0xff);
}
#ifdef BUFFER_MODE
static int write_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
{
int status = 0;
u8 *buf = ci->wbuf;
if (ci->lastaddress != adr)
status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
if (status)
return status;
printk("write_block %d\n", n);
ci->lastaddress = adr;
buf[0] = 1;
while (n) {
int len = n;
if (ci->cfg.max_i2c &&
len + 1 > ci->cfg.max_i2c)
len = ci->cfg.max_i2c - 1;
printk("write %d\n", len);
memcpy(buf + 1, data, len);
status = i2c_write(ci->i2c, ci->cfg.adr, buf, len + 1);
if (status)
return status;
n -= len;
data += len;
}
return status;
}
#endif
static void set_mode(struct cxd *ci, int mode)
{
if (mode == ci->mode)
return;
switch (mode) {
case 0x00: /* IO mem */
write_regm(ci, 0x06, 0x00, 0x07);
break;
case 0x01: /* ATT mem */
write_regm(ci, 0x06, 0x02, 0x07);
break;
default:
break;
}
ci->mode = mode;
}
static void cam_mode(struct cxd *ci, int mode)
{
u8 dummy;
if (mode == ci->cammode)
return;
switch (mode) {
case 0x00:
write_regm(ci, 0x20, 0x80, 0x80);
break;
case 0x01:
if (!ci->en.read_data)
return;
ci->write_busy = 0;
pr_info("enable cam buffer mode\n");
write_reg(ci, 0x0d, 0x00);
write_reg(ci, 0x0e, 0x01);
write_regm(ci, 0x08, 0x40, 0x40);
read_reg(ci, 0x12, &dummy);
write_regm(ci, 0x08, 0x80, 0x80);
break;
default:
break;
}
ci->cammode = mode;
}
#define CHK_ERROR(s) if ((status = s)) break
static int init(struct cxd *ci)
{
int status;
mutex_lock(&ci->lock);
ci->mode = -1;
do {
CHK_ERROR(write_reg(ci, 0x00, 0x00));
CHK_ERROR(write_reg(ci, 0x01, 0x00));
CHK_ERROR(write_reg(ci, 0x02, 0x10));
CHK_ERROR(write_reg(ci, 0x03, 0x00));
CHK_ERROR(write_reg(ci, 0x05, 0xFF));
CHK_ERROR(write_reg(ci, 0x06, 0x1F));
CHK_ERROR(write_reg(ci, 0x07, 0x1F));
CHK_ERROR(write_reg(ci, 0x08, 0x28));
CHK_ERROR(write_reg(ci, 0x14, 0x20));
/* TOSTRT = 8, Mode B (gated clock), falling Edge,
Serial, POL=HIGH, MSB */
CHK_ERROR(write_reg(ci, 0x0A, 0xA7));
CHK_ERROR(write_reg(ci, 0x0B, 0x33));
CHK_ERROR(write_reg(ci, 0x0C, 0x33));
CHK_ERROR(write_regm(ci, 0x14, 0x00, 0x0F));
CHK_ERROR(write_reg(ci, 0x15, ci->clk_reg_b));
CHK_ERROR(write_regm(ci, 0x16, 0x00, 0x0F));
CHK_ERROR(write_reg(ci, 0x17, ci->clk_reg_f));
if (ci->cfg.clock_mode == 2) {
/* bitrate*2^13/ 72000 */
u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000;
if (ci->cfg.polarity) {
CHK_ERROR(write_reg(ci, 0x09, 0x6f));
} else {
CHK_ERROR(write_reg(ci, 0x09, 0x6d));
}
CHK_ERROR(write_reg(ci, 0x20, 0x08));
CHK_ERROR(write_reg(ci, 0x21, (reg >> 8) & 0xff));
CHK_ERROR(write_reg(ci, 0x22, reg & 0xff));
} else if (ci->cfg.clock_mode == 1) {
if (ci->cfg.polarity) {
CHK_ERROR(write_reg(ci, 0x09, 0x6f)); /* D */
} else {
CHK_ERROR(write_reg(ci, 0x09, 0x6d));
}
CHK_ERROR(write_reg(ci, 0x20, 0x68));
CHK_ERROR(write_reg(ci, 0x21, 0x00));
CHK_ERROR(write_reg(ci, 0x22, 0x02));
} else {
if (ci->cfg.polarity) {
CHK_ERROR(write_reg(ci, 0x09, 0x4f)); /* C */
} else {
CHK_ERROR(write_reg(ci, 0x09, 0x4d));
}
CHK_ERROR(write_reg(ci, 0x20, 0x28));
CHK_ERROR(write_reg(ci, 0x21, 0x00));
CHK_ERROR(write_reg(ci, 0x22, 0x07));
}
CHK_ERROR(write_regm(ci, 0x20, 0x80, 0x80));
CHK_ERROR(write_regm(ci, 0x03, 0x02, 0x02));
CHK_ERROR(write_reg(ci, 0x01, 0x04));
CHK_ERROR(write_reg(ci, 0x00, 0x31));
/* Put TS in bypass */
CHK_ERROR(write_regm(ci, 0x09, 0x08, 0x08));
ci->cammode = -1;
cam_mode(ci, 0);
} while (0);
mutex_unlock(&ci->lock);
return 0;
}
static int read_attribute_mem(struct dvb_ca_en50221 *ca,
int slot, int address)
{
struct cxd *ci = ca->data;
#if 0
if (ci->amem_read) {
if (address <= 0 || address > 1024)
return -EIO;
return ci->amem[address];
}
mutex_lock(&ci->lock);
write_regm(ci, 0x06, 0x00, 0x05);
read_pccard(ci, 0, &ci->amem[0], 128);
read_pccard(ci, 128, &ci->amem[0], 128);
read_pccard(ci, 256, &ci->amem[0], 128);
read_pccard(ci, 384, &ci->amem[0], 128);
write_regm(ci, 0x06, 0x05, 0x05);
mutex_unlock(&ci->lock);
return ci->amem[address];
#else
u8 val;
mutex_lock(&ci->lock);
set_mode(ci, 1);
read_pccard(ci, address, &val, 1);
mutex_unlock(&ci->lock);
return val;
#endif
}
static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
int address, u8 value)
{
struct cxd *ci = ca->data;
mutex_lock(&ci->lock);
set_mode(ci, 1);
write_pccard(ci, address, &value, 1);
mutex_unlock(&ci->lock);
return 0;
}
static int read_cam_control(struct dvb_ca_en50221 *ca,
int slot, u8 address)
{
struct cxd *ci = ca->data;
u8 val;
mutex_lock(&ci->lock);
set_mode(ci, 0);
read_io(ci, address, &val);
mutex_unlock(&ci->lock);
return val;
}
static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
u8 address, u8 value)
{
struct cxd *ci = ca->data;
mutex_lock(&ci->lock);
set_mode(ci, 0);
write_io(ci, address, value);
mutex_unlock(&ci->lock);
return 0;
}
static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
{
struct cxd *ci = ca->data;
if (ci->cammode)
read_data(ca, slot, ci->rbuf, 0);
mutex_lock(&ci->lock);
#if 0
write_reg(ci, 0x00, 0x21);
write_reg(ci, 0x06, 0x1F);
write_reg(ci, 0x00, 0x31);
#else
#if 0
write_reg(ci, 0x06, 0x1F);
write_reg(ci, 0x06, 0x2F);
#else
cam_mode(ci, 0);
write_reg(ci, 0x00, 0x21);
write_reg(ci, 0x06, 0x1F);
/*msleep(300);*/
write_reg(ci, 0x00, 0x31);
write_regm(ci, 0x20, 0x80, 0x80);
write_reg(ci, 0x03, 0x02);
ci->ready = 0;
#endif
#endif
ci->mode = -1;
{
int i;
#if 0
u8 val;
#endif
for (i = 0; i < 100; i++) {
msleep(20);
#if 0
read_reg(ci, 0x06, &val);
pr_info(KERN_INFO "%d:%02x\n", i, val);
if (!(val&0x10))
break;
#else
if (ci->ready)
break;
#endif
}
}
mutex_unlock(&ci->lock);
/* msleep(500); */
return 0;
}
static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
{
struct cxd *ci = ca->data;
pr_info("slot_shutdown\n");
if (ci->cammode)
read_data(ca, slot, ci->rbuf, 0);
mutex_lock(&ci->lock);
write_reg(ci, 0x00, 0x21);
write_reg(ci, 0x06, 0x1F);
msleep(300);
write_regm(ci, 0x09, 0x08, 0x08);
write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */
ci->mode = -1;
ci->write_busy = 0;
mutex_unlock(&ci->lock);
return 0;
}
static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
{
struct cxd *ci = ca->data;
mutex_lock(&ci->lock);
write_regm(ci, 0x09, 0x00, 0x08);
set_mode(ci, 0);
cam_mode(ci, 1);
mutex_unlock(&ci->lock);
return 0;
}
static int campoll(struct cxd *ci)
{
u8 istat;
read_reg(ci, 0x04, &istat);
if (!istat)
return 0;
write_reg(ci, 0x05, istat);
if (istat & 0x40)
ci->dr = 1;
if (istat & 0x20)
ci->write_busy = 0;
if (istat & 2) {
u8 slotstat;
read_reg(ci, 0x01, &slotstat);
if (!(2 & slotstat)) {
if (!ci->slot_stat) {
ci->slot_stat |=
DVB_CA_EN50221_POLL_CAM_PRESENT;
write_regm(ci, 0x03, 0x08, 0x08);
}
} else {
if (ci->slot_stat) {
ci->slot_stat = 0;
write_regm(ci, 0x03, 0x00, 0x08);
pr_info("NO CAM\n");
ci->ready = 0;
}
}
if ((istat & 8) &&
(ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT)) {
ci->ready = 1;
ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
}
}
return 0;
}
static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
{
struct cxd *ci = ca->data;
u8 slotstat;
mutex_lock(&ci->lock);
campoll(ci);
read_reg(ci, 0x01, &slotstat);
mutex_unlock(&ci->lock);
return ci->slot_stat;
}
static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
{
struct cxd *ci = ca->data;
u8 msb, lsb;
u16 len;
mutex_lock(&ci->lock);
campoll(ci);
mutex_unlock(&ci->lock);
if (!ci->dr)
return 0;
mutex_lock(&ci->lock);
read_reg(ci, 0x0f, &msb);
read_reg(ci, 0x10, &lsb);
len = ((u16) msb << 8) | lsb;
if (len > ecount || len < 2) {
/* read it anyway or cxd may hang */
read_block(ci, 0x12, ci->rbuf, len);
mutex_unlock(&ci->lock);
return -EIO;
}
read_block(ci, 0x12, ebuf, len);
ci->dr = 0;
mutex_unlock(&ci->lock);
#if 0
pr_info("read_data %d\n", len);
{
int i;
for (i = 0; i < len; i++)
pr_info("%02x ", ebuf[i]);
pr_info("\n");
}
#endif
return len;
}
#ifdef BUFFER_MODE
static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
{
struct cxd *ci = ca->data;
if (ci->write_busy)
return -EAGAIN;
mutex_lock(&ci->lock);
write_reg(ci, 0x0d, ecount >> 8);
write_reg(ci, 0x0e, ecount & 0xff);
write_block(ci, 0x11, ebuf, ecount);
ci->write_busy = 1;
mutex_unlock(&ci->lock);
return ecount;
}
#endif
static struct dvb_ca_en50221 en_templ = {
.read_attribute_mem = read_attribute_mem,
.write_attribute_mem = write_attribute_mem,
.read_cam_control = read_cam_control,
.write_cam_control = write_cam_control,
.slot_reset = slot_reset,
.slot_shutdown = slot_shutdown,
.slot_ts_enable = slot_ts_enable,
.poll_slot_status = poll_slot_status,
#ifdef BUFFER_MODE
.read_data = read_data,
.write_data = write_data,
#endif
};
struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg,
void *priv,
struct i2c_adapter *i2c)
{
struct cxd *ci = 0;
u8 val;
if (i2c_read_reg(i2c, cfg->adr, 0, &val) < 0) {
pr_info("No CXD2099 detected at %02x\n", cfg->adr);
return 0;
}
ci = kzalloc(sizeof(struct cxd), GFP_KERNEL);
if (!ci)
return 0;
mutex_init(&ci->lock);
memcpy(&ci->cfg, cfg, sizeof(struct cxd2099_cfg));
ci->i2c = i2c;
ci->lastaddress = 0xff;
ci->clk_reg_b = 0x4a;
ci->clk_reg_f = 0x1b;
memcpy(&ci->en, &en_templ, sizeof(en_templ));
ci->en.data = ci;
init(ci);
pr_info("Attached CXD2099AR at %02x\n", ci->cfg.adr);
return &ci->en;
}
EXPORT_SYMBOL(cxd2099_attach);
MODULE_DESCRIPTION("cxd2099");
MODULE_AUTHOR("Ralph Metzler");
MODULE_LICENSE("GPL");

43
frontends/cxd2099.h Normal file
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/*
* cxd2099.h: Driver for the CXD2099AR Common Interface Controller
*
* Copyright (C) 2010-2011 Digital Devices GmbH
*
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA
* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
*/
#ifndef _CXD2099_H_
#define _CXD2099_H_
#include <dvb_ca_en50221.h>
struct cxd2099_cfg {
u32 bitrate;
u8 adr;
u8 polarity;
u8 clock_mode;
u32 max_i2c;
};
struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg,
void *priv, struct i2c_adapter *i2c);
#endif

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#ifndef _CXD2843_H_
#define _CXD2843_H_
#include <linux/types.h>
#include <linux/i2c.h>
struct cxd2843_cfg {
u8 adr;
u32 ts_clock;
u8 parallel;
};
#if defined(CONFIG_DVB_CXD2843) || \
(defined(CONFIG_DVB_CXD2843_MODULE) && defined(MODULE))
extern struct dvb_frontend *cxd2843_attach(struct i2c_adapter *i2c,
struct cxd2843_cfg *cfg);
#else
static inline struct dvb_frontend *cxd2843_attach(struct i2c_adapter *i2c,
struct cxd2843_cfg *cfg)
{
pr_warn("%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

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#ifndef _DRXK_H_
#define _DRXK_H_
#include <linux/types.h>
#include <linux/i2c.h>
extern struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c,
u8 adr,
struct dvb_frontend **fe_t);
#endif

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#include "drxk_map.h"
#define DRXK_VERSION_MAJOR 0
#define DRXK_VERSION_MINOR 9
#define DRXK_VERSION_PATCH 4300
#define HI_I2C_DELAY 42
#define HI_I2C_BRIDGE_DELAY 350
#define DRXK_MAX_RETRIES 100
#define DRIVER_4400 1
#define DRXX_JTAGID 0x039210D9
#define DRXX_J_JTAGID 0x239310D9
#define DRXX_K_JTAGID 0x039210D9
#define DRX_UNKNOWN 254
#define DRX_AUTO 255
#define DRX_SCU_READY 0
#define DRXK_MAX_WAITTIME (200)
#define SCU_RESULT_OK 0
#define SCU_RESULT_UNKSTD -2
#define SCU_RESULT_UNKCMD -1
#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200)
#endif
#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/
#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/
#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/
#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/
#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/
#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/
#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/
#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/
#define IQM_CF_OUT_ENA_OFDM__M 0x4
#define IQM_FS_ADJ_SEL_B_QAM 0x1
#define IQM_FS_ADJ_SEL_B_OFF 0x0
#define IQM_FS_ADJ_SEL_B_VSB 0x2
#define IQM_RC_ADJ_SEL_B_OFF 0x0
#define IQM_RC_ADJ_SEL_B_QAM 0x1
#define IQM_RC_ADJ_SEL_B_VSB 0x2
enum OperationMode {
OM_NONE,
OM_QAM_ITU_A,
OM_QAM_ITU_B,
OM_QAM_ITU_C,
OM_DVBT
};
typedef enum {
DRX_POWER_UP = 0,
DRX_POWER_MODE_1,
DRX_POWER_MODE_2,
DRX_POWER_MODE_3,
DRX_POWER_MODE_4,
DRX_POWER_MODE_5,
DRX_POWER_MODE_6,
DRX_POWER_MODE_7,
DRX_POWER_MODE_8,
DRX_POWER_MODE_9,
DRX_POWER_MODE_10,
DRX_POWER_MODE_11,
DRX_POWER_MODE_12,
DRX_POWER_MODE_13,
DRX_POWER_MODE_14,
DRX_POWER_MODE_15,
DRX_POWER_MODE_16,
DRX_POWER_DOWN = 255
}DRXPowerMode_t, *pDRXPowerMode_t;
/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */
#ifndef DRXK_POWER_DOWN_OFDM
#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1
#endif
/** /brief Intermediate power mode for DRXK, power down core (sysclk) */
#ifndef DRXK_POWER_DOWN_CORE
#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9
#endif
/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */
#ifndef DRXK_POWER_DOWN_PLL
#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10
#endif
enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF };
enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN };
enum EDrxkCoefArrayIndex {
DRXK_COEF_IDX_MN = 0,
DRXK_COEF_IDX_FM ,
DRXK_COEF_IDX_L ,
DRXK_COEF_IDX_LP ,
DRXK_COEF_IDX_BG ,
DRXK_COEF_IDX_DK ,
DRXK_COEF_IDX_I ,
DRXK_COEF_IDX_MAX
};
enum EDrxkSifAttenuation {
DRXK_SIF_ATTENUATION_0DB,
DRXK_SIF_ATTENUATION_3DB,
DRXK_SIF_ATTENUATION_6DB,
DRXK_SIF_ATTENUATION_9DB
};
enum EDrxkConstellation {
DRX_CONSTELLATION_BPSK = 0,
DRX_CONSTELLATION_QPSK,
DRX_CONSTELLATION_PSK8,
DRX_CONSTELLATION_QAM16,
DRX_CONSTELLATION_QAM32,
DRX_CONSTELLATION_QAM64,
DRX_CONSTELLATION_QAM128,
DRX_CONSTELLATION_QAM256,
DRX_CONSTELLATION_QAM512,
DRX_CONSTELLATION_QAM1024,
DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
DRX_CONSTELLATION_AUTO = DRX_AUTO
};
enum EDrxkInterleaveMode {
DRXK_QAM_I12_J17 = 16,
DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN
};
enum {
DRXK_SPIN_A1 = 0,
DRXK_SPIN_A2,
DRXK_SPIN_A3,
DRXK_SPIN_UNKNOWN
};
enum DRXKCfgDvbtSqiSpeed {
DRXK_DVBT_SQI_SPEED_FAST = 0,
DRXK_DVBT_SQI_SPEED_MEDIUM,
DRXK_DVBT_SQI_SPEED_SLOW,
DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
} ;
enum DRXFftmode_t {
DRX_FFTMODE_2K = 0,
DRX_FFTMODE_4K,
DRX_FFTMODE_8K,
DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
DRX_FFTMODE_AUTO = DRX_AUTO
};
enum DRXMPEGStrWidth_t {
DRX_MPEG_STR_WIDTH_1,
DRX_MPEG_STR_WIDTH_8
};
enum DRXQamLockRange_t {
DRX_QAM_LOCKRANGE_NORMAL,
DRX_QAM_LOCKRANGE_EXTENDED
};
struct DRXKCfgDvbtEchoThres_t {
u16 threshold;
enum DRXFftmode_t fftMode;
} ;
struct SCfgAgc
{
enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */
u16 outputLevel; /* range dependent on AGC */
u16 minOutputLevel; /* range dependent on AGC */
u16 maxOutputLevel; /* range dependent on AGC */
u16 speed; /* range dependent on AGC */
u16 top; /* rf-agc take over point */
u16 cutOffCurrent; /* rf-agc is accelerated if output current
is below cut-off current */
u16 IngainTgtMax;
u16 FastClipCtrlDelay;
};
struct SCfgPreSaw
{
u16 reference; /* pre SAW reference value, range 0 .. 31 */
bool usePreSaw; /* TRUE algorithms must use pre SAW sense */
};
struct DRXKOfdmScCmd_t
{
u16 cmd; /**< Command number */
u16 subcmd; /**< Sub-command parameter*/
u16 param0; /**< General purpous param */
u16 param1; /**< General purpous param */
u16 param2; /**< General purpous param */
u16 param3; /**< General purpous param */
u16 param4; /**< General purpous param */
};
struct drxk_state {
struct dvb_frontend c_frontend;
struct dvb_frontend t_frontend;
#ifndef USE_API3
struct dtv_frontend_properties props;
#else
struct dvb_frontend_parameters param;
#endif
struct device *dev;
struct i2c_adapter *i2c;
u8 demod_address;
void *priv;
struct mutex mutex;
struct mutex ctlock;
u32 m_Instance; ///< Channel 1,2,3 or 4
int m_ChunkSize;
u8 Chunk[256];
bool m_hasLNA;
bool m_hasDVBT;
bool m_hasDVBC;
bool m_hasAudio;
bool m_hasATV;
bool m_hasOOB;
bool m_hasSAWSW; /**< TRUE if mat_tx is available */
bool m_hasGPIO1; /**< TRUE if mat_rx is available */
bool m_hasGPIO2; /**< TRUE if GPIO is available */
bool m_hasIRQN; /**< TRUE if IRQN is available */
u16 m_oscClockFreq;
u16 m_HICfgTimingDiv;
u16 m_HICfgBridgeDelay;
u16 m_HICfgWakeUpKey;
u16 m_HICfgTimeout;
u16 m_HICfgCtrl;
s32 m_sysClockFreq ; ///< system clock frequency in kHz
enum EDrxkState m_DrxkState; ///< State of Drxk (init,stopped,started)
enum OperationMode m_OperationMode; ///< digital standards
struct SCfgAgc m_vsbRfAgcCfg; ///< settings for VSB RF-AGC
struct SCfgAgc m_vsbIfAgcCfg; ///< settings for VSB IF-AGC
u16 m_vsbPgaCfg; ///< settings for VSB PGA
struct SCfgPreSaw m_vsbPreSawCfg; ///< settings for pre SAW sense
s32 m_Quality83percent; ///< MER level (*0.1 dB) for 83% quality indication
s32 m_Quality93percent; ///< MER level (*0.1 dB) for 93% quality indication
bool m_smartAntInverted;
bool m_bDebugEnableBridge;
bool m_bPDownOpenBridge; ///< only open DRXK bridge before power-down once it has been accessed
bool m_bPowerDown; ///< Power down when not used
u32 m_IqmFsRateOfs; ///< frequency shift as written to DRXK register (28bit fixpoint)
bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */
bool m_insertRSByte; /**< If TRUE, insert RS byte */
bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */
bool m_invertDATA; /**< If TRUE, invert DATA signals */
bool m_invertERR; /**< If TRUE, invert ERR signal */
bool m_invertSTR; /**< If TRUE, invert STR signals */
bool m_invertVAL; /**< If TRUE, invert VAL signals */
bool m_invertCLK; /**< If TRUE, invert CLK signals */
bool m_DVBCStaticCLK;
bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will
be used, otherwise clockrate will
adapt to the bitrate of the TS */
u32 m_DVBTBitrate;
u32 m_DVBCBitrate;
u8 m_TSDataStrength;
u8 m_TSClockkStrength;
enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width**/
u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case
static clockrate is selected */
//LARGE_INTEGER m_StartTime; ///< Contains the time of the last demod start
s32 m_MpegLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time)
s32 m_DemodLockTimeOut; ///< WaitForLockStatus Timeout (counts from start time)
bool m_disableTEIhandling;
bool m_RfAgcPol;
bool m_IfAgcPol;
struct SCfgAgc m_atvRfAgcCfg; ///< settings for ATV RF-AGC
struct SCfgAgc m_atvIfAgcCfg; ///< settings for ATV IF-AGC
struct SCfgPreSaw m_atvPreSawCfg; ///< settings for ATV pre SAW sense
bool m_phaseCorrectionBypass;
s16 m_atvTopVidPeak;
u16 m_atvTopNoiseTh;
enum EDrxkSifAttenuation m_sifAttenuation;
bool m_enableCVBSOutput;
bool m_enableSIFOutput;
bool m_bMirrorFreqSpect;
enum EDrxkConstellation m_Constellation; ///< Constellation type of the channel
u32 m_CurrSymbolRate; ///< Current QAM symbol rate
struct SCfgAgc m_qamRfAgcCfg; ///< settings for QAM RF-AGC
struct SCfgAgc m_qamIfAgcCfg; ///< settings for QAM IF-AGC
u16 m_qamPgaCfg; ///< settings for QAM PGA
struct SCfgPreSaw m_qamPreSawCfg; ///< settings for QAM pre SAW sense
enum EDrxkInterleaveMode m_qamInterleaveMode; ///< QAM Interleave mode
u16 m_fecRsPlen;
u16 m_fecRsPrescale;
enum DRXKCfgDvbtSqiSpeed m_sqiSpeed;
u16 m_GPIO;
u16 m_GPIOCfg;
struct SCfgAgc m_dvbtRfAgcCfg; ///< settings for QAM RF-AGC
struct SCfgAgc m_dvbtIfAgcCfg; ///< settings for QAM IF-AGC
struct SCfgPreSaw m_dvbtPreSawCfg; ///< settings for QAM pre SAW sense
u16 m_agcFastClipCtrlDelay;
bool m_adcCompPassed;
u16 m_adcCompCoef[64];
u16 m_adcState;
u8 *m_microcode;
int m_microcode_length;
bool m_DRXK_A1_PATCH_CODE;
bool m_DRXK_A1_ROM_CODE;
bool m_DRXK_A2_ROM_CODE;
bool m_DRXK_A3_ROM_CODE;
bool m_DRXK_A2_PATCH_CODE;
bool m_DRXK_A3_PATCH_CODE;
bool m_rfmirror;
u8 m_deviceSpin;
u32 m_iqmRcRate;
u16 m_AntennaDVBC;
u16 m_AntennaDVBT;
u16 m_AntennaSwitchDVBTDVBC;
DRXPowerMode_t m_currentPowerMode;
};
#define NEVER_LOCK 0
#define NOT_LOCKED 1
#define DEMOD_LOCK 2
#define FEC_LOCK 3
#define MPEG_LOCK 4

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/*
* lnbh24.h - driver for lnb supply and control ic lnbh24
*
* Copyright (C) 2009 NetUP Inc.
* Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _LNBH24_H
#define _LNBH24_H
/* system register bits */
#define LNBH24_OLF 0x01
#define LNBH24_OTF 0x02
#define LNBH24_EN 0x04
#define LNBH24_VSEL 0x08
#define LNBH24_LLC 0x10
#define LNBH24_TEN 0x20
#define LNBH24_TTX 0x40
#define LNBH24_PCL 0x80
#include <linux/dvb/frontend.h>
#if defined(CONFIG_DVB_LNBP21) || (defined(CONFIG_DVB_LNBP21_MODULE) \
&& defined(MODULE))
/* override_set and override_clear control which
system register bits (above) to always set & clear */
extern struct dvb_frontend *lnbh24_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 override_set,
u8 override_clear, u8 i2c_addr);
#else
static inline struct dvb_frontend *lnbh24_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 override_set,
u8 override_clear, u8 i2c_addr)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

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/*
* Driver for the ST LNBH25
*
* Copyright (C) 2014 Digital Devices GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA
* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include "dvb_frontend.h"
#include "lnbh25.h"
struct lnbh25 {
struct i2c_adapter *i2c;
u8 adr;
u8 reg[4];
u8 boost;
};
static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
{
struct i2c_msg msg = {.addr = adr, .flags = 0,
.buf = data, .len = len};
if (i2c_transfer(adap, &msg, 1) != 1) {
pr_err("lnbh25: i2c_write error\n");
return -1;
}
return 0;
}
static int lnbh25_write_regs(struct lnbh25 *lnbh, int reg, int len)
{
u8 d[5];
memcpy(&d[1], &lnbh->reg[reg], len);
d[0] = reg + 2;
return i2c_write(lnbh->i2c, lnbh->adr, d, len + 1);
}
static int lnbh25_set_voltage(struct dvb_frontend *fe,
fe_sec_voltage_t voltage)
{
struct lnbh25 *lnbh = (struct lnbh25 *) fe->sec_priv;
u8 oldreg0 = lnbh->reg[0];
switch (voltage) {
case SEC_VOLTAGE_OFF:
lnbh->reg[0] = 0x00;
lnbh->reg[1] &= ~0x01; /* Disable Tone */
lnbh->reg[2] = 0x00;
return lnbh25_write_regs(lnbh, 0, 3);
case SEC_VOLTAGE_13:
lnbh->reg[0] = lnbh->boost + 1;
break;
case SEC_VOLTAGE_18:
lnbh->reg[0] = lnbh->boost + 8;
break;
default:
return -EINVAL;
};
if (lnbh->reg[0] == 0x00) {
lnbh->reg[2] = 4;
lnbh25_write_regs(lnbh, 2, 2);
} else if (lnbh->reg[2] != 0x00) {
lnbh->reg[2] = 0;
lnbh25_write_regs(lnbh, 2, 2);
}
lnbh->reg[1] |= 0x01;
lnbh25_write_regs(lnbh, 0, 3);
if (oldreg0 == 0)
msleep(100);
return 0;
}
static int lnbh25_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg)
{
struct lnbh25 *lnbh = (struct lnbh25 *) fe->sec_priv;
lnbh->boost = arg ? 3 : 0;
return 0;
}
static int lnbh25_set_tone(struct dvb_frontend *fe,
fe_sec_tone_mode_t tone)
{
/* struct lnbh25 *lnbh = (struct lnbh25 *) fe->sec_priv; */
return 0;
}
static int lnbh25_init(struct lnbh25 *lnbh)
{
return lnbh25_write_regs(lnbh, 0, 2);
}
static void lnbh25_release(struct dvb_frontend *fe)
{
kfree(fe->sec_priv);
fe->sec_priv = NULL;
}
struct dvb_frontend *lnbh25_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
u8 adr)
{
struct lnbh25 *lnbh = kzalloc(sizeof(struct lnbh25), GFP_KERNEL);
if (!lnbh)
return NULL;
lnbh->i2c = i2c;
lnbh->adr = adr;
lnbh->boost = 3;
if (lnbh25_init(lnbh)) {
kfree(lnbh);
return NULL;
}
fe->sec_priv = lnbh;
fe->ops.set_voltage = lnbh25_set_voltage;
fe->ops.enable_high_lnb_voltage = lnbh25_enable_high_lnb_voltage;
fe->ops.release_sec = lnbh25_release;
pr_info("LNB25 on %02x\n", lnbh->adr);
return fe;
}
EXPORT_SYMBOL(lnbh25_attach);
MODULE_DESCRIPTION("LNBH25");
MODULE_AUTHOR("Ralph Metzler");
MODULE_LICENSE("GPL");

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/*
* lnbh25.h
*/
#ifndef _LNBH25_H
#define _LNBH25_H
#include <linux/dvb/frontend.h>
#if defined(CONFIG_DVB_LNBH25) || \
(defined(CONFIG_DVB_LNBH25_MODULE) && defined(MODULE))
extern struct dvb_frontend *lnbh25_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
u8 i2c_addr);
#else
static inline struct dvb_frontend *lnbh25_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
u8 i2c_addr)
{
pr_warn("%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

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/*
* lnbp21.c - driver for lnb supply and control ic lnbp21
*
* Copyright (C) 2006, 2009 Oliver Endriss <o.endriss@gmx.de>
* Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
*
*
* the project's page is at http://www.linuxtv.org
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include "dvb_frontend.h"
#include "lnbp21.h"
#include "lnbh24.h"
struct lnbp21 {
u8 config;
u8 override_or;
u8 override_and;
struct i2c_adapter *i2c;
u8 i2c_addr;
};
static int lnbp21_set_voltage(struct dvb_frontend *fe,
fe_sec_voltage_t voltage)
{
struct lnbp21 *lnbp21 = (struct lnbp21 *) fe->sec_priv;
struct i2c_msg msg = { .addr = lnbp21->i2c_addr, .flags = 0,
.buf = &lnbp21->config,
.len = sizeof(lnbp21->config) };
lnbp21->config &= ~(LNBP21_VSEL | LNBP21_EN);
if ((lnbp21->config & LNBP21_EN) == 0)
lnbp21->config |= 0x80;
else
lnbp21->config &= 0x7f;
switch(voltage) {
case SEC_VOLTAGE_OFF:
break;
case SEC_VOLTAGE_13:
lnbp21->config |= LNBP21_EN;
break;
case SEC_VOLTAGE_18:
lnbp21->config |= (LNBP21_EN | LNBP21_VSEL);
break;
default:
return -EINVAL;
};
lnbp21->config |= lnbp21->override_or;
lnbp21->config &= lnbp21->override_and;
return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO;
}
static int lnbp21_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg)
{
struct lnbp21 *lnbp21 = (struct lnbp21 *) fe->sec_priv;
struct i2c_msg msg = { .addr = lnbp21->i2c_addr, .flags = 0,
.buf = &lnbp21->config,
.len = sizeof(lnbp21->config) };
if (arg)
lnbp21->config |= LNBP21_LLC;
else
lnbp21->config &= ~LNBP21_LLC;
lnbp21->config |= lnbp21->override_or;
lnbp21->config &= lnbp21->override_and;
return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO;
}
static int lnbp21_set_tone(struct dvb_frontend *fe,
fe_sec_tone_mode_t tone)
{
struct lnbp21 *lnbp21 = (struct lnbp21 *) fe->sec_priv;
struct i2c_msg msg = { .addr = lnbp21->i2c_addr, .flags = 0,
.buf = &lnbp21->config,
.len = sizeof(lnbp21->config) };
switch (tone) {
case SEC_TONE_OFF:
lnbp21->config &= ~LNBP21_TEN;
break;
case SEC_TONE_ON:
lnbp21->config |= LNBP21_TEN;
break;
default:
return -EINVAL;
};
lnbp21->config |= lnbp21->override_or;
lnbp21->config &= lnbp21->override_and;
return (i2c_transfer(lnbp21->i2c, &msg, 1) == 1) ? 0 : -EIO;
}
static void lnbp21_release(struct dvb_frontend *fe)
{
/* LNBP power off */
lnbp21_set_voltage(fe, SEC_VOLTAGE_OFF);
/* free data */
kfree(fe->sec_priv);
fe->sec_priv = NULL;
}
static struct dvb_frontend *lnbx2x_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 override_set,
u8 override_clear, u8 i2c_addr, u8 config)
{
struct lnbp21 *lnbp21 = kmalloc(sizeof(struct lnbp21), GFP_KERNEL);
if (!lnbp21)
return NULL;
/* default configuration */
lnbp21->config = config;
lnbp21->i2c = i2c;
lnbp21->i2c_addr = i2c_addr;
fe->sec_priv = lnbp21;
/* bits which should be forced to '1' */
lnbp21->override_or = override_set;
/* bits which should be forced to '0' */
lnbp21->override_and = ~override_clear;
/* detect if it is present or not */
if (lnbp21_set_voltage(fe, SEC_VOLTAGE_OFF)) {
kfree(lnbp21);
return NULL;
}
/* install release callback */
fe->ops.release_sec = lnbp21_release;
/* override frontend ops */
fe->ops.set_voltage = lnbp21_set_voltage;
fe->ops.enable_high_lnb_voltage = lnbp21_enable_high_lnb_voltage;
if (!(override_clear & LNBH24_TEN)) /*22kHz logic controlled by demod*/
fe->ops.set_tone = lnbp21_set_tone;
printk(KERN_INFO "LNBx2x attached on addr=%x\n", lnbp21->i2c_addr);
return fe;
}
struct dvb_frontend *lnbh24_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 override_set,
u8 override_clear, u8 i2c_addr)
{
return lnbx2x_attach(fe, i2c, override_set, override_clear,
i2c_addr, LNBH24_TTX);
}
EXPORT_SYMBOL(lnbh24_attach);
struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 override_set,
u8 override_clear)
{
return lnbx2x_attach(fe, i2c, override_set, override_clear,
0x08, LNBP21_ISEL);
}
EXPORT_SYMBOL(lnbp21_attach);
MODULE_DESCRIPTION("Driver for lnb supply and control ic lnbp21, lnbh24");
MODULE_AUTHOR("Oliver Endriss, Igor M. Liplianin");
MODULE_LICENSE("GPL");

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/*
* lnbp21.h - driver for lnb supply and control ic lnbp21
*
* Copyright (C) 2006 Oliver Endriss
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
*
*
* the project's page is at http://www.linuxtv.org
*/
#ifndef _LNBP21_H
#define _LNBP21_H
/* system register bits */
/* [RO] 0=OK; 1=over current limit flag */
#define LNBP21_OLF 0x01
/* [RO] 0=OK; 1=over temperature flag (150 C) */
#define LNBP21_OTF 0x02
/* [RW] 0=disable LNB power, enable loopthrough
1=enable LNB power, disable loopthrough */
#define LNBP21_EN 0x04
/* [RW] 0=low voltage (13/14V, vert pol)
1=high voltage (18/19V,horiz pol) */
#define LNBP21_VSEL 0x08
/* [RW] increase LNB voltage by 1V:
0=13/18V; 1=14/19V */
#define LNBP21_LLC 0x10
/* [RW] 0=tone controlled by DSQIN pin
1=tone enable, disable DSQIN */
#define LNBP21_TEN 0x20
/* [RW] current limit select:
0:Iout=500-650mA Isc=300mA
1:Iout=400-550mA Isc=200mA */
#define LNBP21_ISEL 0x40
/* [RW] short-circuit protect:
0=pulsed (dynamic) curr limiting
1=static curr limiting */
#define LNBP21_PCL 0x80
#include <linux/dvb/frontend.h>
#if defined(CONFIG_DVB_LNBP21) || (defined(CONFIG_DVB_LNBP21_MODULE) \
&& defined(MODULE))
/* override_set and override_clear control which
system register bits (above) to always set & clear */
extern struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 override_set,
u8 override_clear);
#else
static inline struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 override_set,
u8 override_clear)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

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#ifndef _MXL5XX_H_
#define _MXL5XX_H_
#include <linux/types.h>
#include <linux/i2c.h>
struct mxl5xx_cfg {
u8 adr;
u8 type;
u32 cap;
u32 clk;
u32 ts_clk;
u8 *fw;
u32 fw_len;
int (*fw_read)(void *priv, u8 *buf, u32 len);
void *fw_priv;
};
#if defined(CONFIG_DVB_MXL5XX) || \
(defined(CONFIG_DVB_MXL5XX_MODULE) && defined(MODULE))
extern struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c,
struct mxl5xx_cfg *cfg,
u32 demod, u32 tuner);
#else
static inline struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c,
struct mxl5xx_cfg *cfg,
u32 demod, u32 tuner)
{
pr_warn("%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

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/*
* Defines for the Maxlinear MX58x family of tuners/demods
*
* Copyright (C) 2014 Digital Devices GmbH
*
* based on code:
* Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
* which was released under GPL V2
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2, as published by the Free Software Foundation.
*/
typedef enum
{
MXL_DISABLE = 0,
MXL_ENABLE = 1,
MXL_FALSE = 0,
MXL_TRUE = 1,
MXL_INVALID = 0,
MXL_VALID = 1,
MXL_NO = 0,
MXL_YES = 1,
MXL_OFF = 0,
MXL_ON = 1
} MXL_BOOL_E;
// Firmware-Host Command IDs
typedef enum
{
//--Device command IDs--
MXL_HYDRA_DEV_NO_OP_CMD = 0, //No OP
MXL_HYDRA_DEV_SET_POWER_MODE_CMD = 1,
MXL_HYDRA_DEV_SET_OVERWRITE_DEF_CMD = 2,
// Host-used CMD, not used by firmware
MXL_HYDRA_DEV_FIRMWARE_DOWNLOAD_CMD = 3,
// Additional CONTROL types from DTV
MXL_HYDRA_DEV_SET_BROADCAST_PID_STB_ID_CMD = 4,
MXL_HYDRA_DEV_GET_PMM_SLEEP_CMD = 5,
//--Tuner command IDs--
MXL_HYDRA_TUNER_TUNE_CMD = 6,
MXL_HYDRA_TUNER_GET_STATUS_CMD = 7,
//--Demod command IDs--
MXL_HYDRA_DEMOD_SET_PARAM_CMD = 8,
MXL_HYDRA_DEMOD_GET_STATUS_CMD = 9,
MXL_HYDRA_DEMOD_RESET_FEC_COUNTER_CMD = 10,
MXL_HYDRA_DEMOD_SET_PKT_NUM_CMD = 11,
MXL_HYDRA_DEMOD_SET_IQ_SOURCE_CMD = 12,
MXL_HYDRA_DEMOD_GET_IQ_DATA_CMD = 13,
MXL_HYDRA_DEMOD_GET_M68HC05_VER_CMD = 14,
MXL_HYDRA_DEMOD_SET_ERROR_COUNTER_MODE_CMD = 15,
//--- ABORT channel tune
MXL_HYDRA_ABORT_TUNE_CMD = 16, // Abort current tune command.
//--SWM/FSK command IDs--
MXL_HYDRA_FSK_RESET_CMD = 17,
MXL_HYDRA_FSK_MSG_CMD = 18,
MXL_HYDRA_FSK_SET_OP_MODE_CMD = 19,
//--DiSeqC command IDs--
MXL_HYDRA_DISEQC_MSG_CMD = 20,
MXL_HYDRA_DISEQC_COPY_MSG_TO_MAILBOX = 21,
MXL_HYDRA_DISEQC_CFG_MSG_CMD = 22,
//--- FFT Debug Command IDs--
MXL_HYDRA_REQ_FFT_SPECTRUM_CMD = 23,
// -- Demod scramblle code
MXL_HYDRA_DEMOD_SCRAMBLE_CODE_CMD = 24,
//---For host to know how many commands in total---
MXL_HYDRA_LAST_HOST_CMD = 25,
MXL_HYDRA_DEMOD_INTR_TYPE_CMD = 47,
MXL_HYDRA_DEV_INTR_CLEAR_CMD = 48,
MXL_HYDRA_TUNER_SPECTRUM_REQ_CMD = 53,
MXL_HYDRA_TUNER_ACTIVATE_CMD = 55,
MXL_HYDRA_DEV_CFG_POWER_MODE_CMD = 56,
MXL_HYDRA_DEV_XTAL_CAP_CMD = 57,
MXL_HYDRA_DEV_CFG_SKU_CMD = 58,
MXL_HYDRA_TUNER_SPECTRUM_MIN_GAIN_CMD = 59,
MXL_HYDRA_DISEQC_CONT_TONE_CFG = 60,
MXL_HYDRA_DEV_RF_WAKE_UP_CMD = 61,
MXL_HYDRA_DEMOD_CFG_EQ_CTRL_PARAM_CMD = 62,
MXL_HYDRA_DEMOD_FREQ_OFFSET_SEARCH_RANGE_CMD = 63,
MXL_HYDRA_DEV_REQ_PWR_FROM_ADCRSSI_CMD = 64,
MXL_XCPU_PID_FLT_CFG_CMD = 65,
MXL_XCPU_SHMEM_TEST_CMD = 66,
MXL_XCPU_ABORT_TUNE_CMD = 67,
MXL_XCPU_CHAN_TUNE_CMD = 68,
MXL_XCPU_FLT_BOND_HDRS_CMD = 69,
MXL_HYDRA_DEV_BROADCAST_WAKE_UP_CMD = 70,
MXL_HYDRA_FSK_CFG_FSK_FREQ_CMD = 71,
MXL_HYDRA_FSK_POWER_DOWN_CMD = 72,
MXL_XCPU_CLEAR_CB_STATS_CMD = 73,
MXL_XCPU_CHAN_BOND_RESTART_CMD = 74
} MXL_HYDRA_HOST_CMD_ID_E;
#define MXL_ENABLE_BIG_ENDIAN (0)
#define MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH 248
#define MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN (248)
#define MXL_HYDRA_CAP_MIN 10
#define MXL_HYDRA_CAP_MAX 33
#define MXL_HYDRA_PLID_REG_READ 0xFB // Read register PLID
#define MXL_HYDRA_PLID_REG_WRITE 0xFC // Write register PLID
#define MXL_HYDRA_PLID_CMD_READ 0xFD // Command Read PLID
#define MXL_HYDRA_PLID_CMD_WRITE 0xFE // Command Write PLID
#define MXL_HYDRA_REG_SIZE_IN_BYTES 4 // Hydra register size in bytes
#define MXL_HYDRA_I2C_HDR_SIZE (2 * sizeof(u8)) // PLID + LEN(0xFF)
#define MXL_HYDRA_CMD_HEADER_SIZE (MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE)
#define MXL_HYDRA_SKU_ID_581 0
#define MXL_HYDRA_SKU_ID_584 1
#define MXL_HYDRA_SKU_ID_585 2
#define MXL_HYDRA_SKU_ID_544 3
#define MXL_HYDRA_SKU_ID_561 4
#define MXL_HYDRA_SKU_ID_582 5
#define MXL_HYDRA_SKU_ID_568 6
// macro for register write data buffer size (PLID + LEN (0xFF) + RegAddr + RegData)
#define MXL_HYDRA_REG_WRITE_LEN (MXL_HYDRA_I2C_HDR_SIZE + (2 * MXL_HYDRA_REG_SIZE_IN_BYTES))
// maro to extract a single byte from 4-byte(32-bit) data
#define GET_BYTE(x,n) (((x) >> (8*(n))) & 0xFF)
#define MAX_CMD_DATA 512
#define MXL_GET_REG_MASK_32(lsbLoc,numOfBits) ((0xFFFFFFFF >> (32 - (numOfBits))) << (lsbLoc))
#define GET_REG_FIELD_DATA(fieldName, dataPtr) read_by_mnemonic(state, fieldName, dataPtr);
#define SET_REG_FIELD_DATA(fieldName, data) update_by_mnemonic(state, fieldName, data);
#define FW_DL_SIGN (0xDEADBEEF)
#define MBIN_FORMAT_VERSION '1'
#define MBIN_FILE_HEADER_ID 'M'
#define MBIN_SEGMENT_HEADER_ID 'S'
#define MBIN_MAX_FILE_LENGTH (1<<23)
typedef struct
{
u8 id;
u8 fmtVersion;
u8 headerLen;
u8 numSegments;
u8 entryAddress[4];
u8 imageSize24[3];
u8 imageChecksum;
u8 reserved[4];
} MBIN_FILE_HEADER_T;
typedef struct
{
MBIN_FILE_HEADER_T header;
u8 data[1];
} MBIN_FILE_T;
typedef struct
{
u8 id;
u8 len24[3];
u8 address[4];
} MBIN_SEGMENT_HEADER_T;
typedef struct
{
MBIN_SEGMENT_HEADER_T header;
u8 data[1];
} MBIN_SEGMENT_T;
typedef enum { MXL_CMD_WRITE = 0, MXL_CMD_READ} MXL_CMD_TYPE_E;
#define BUILD_HYDRA_CMD(cmdID, reqType, size, dataPtr, cmdBuff) \
do { \
cmdBuff[0] = ((reqType == MXL_CMD_WRITE) ? MXL_HYDRA_PLID_CMD_WRITE : MXL_HYDRA_PLID_CMD_READ); \
cmdBuff[1] = (size > 251) ? 0xff : (u8) (size + 4); \
cmdBuff[2] = size; \
cmdBuff[3] = cmdID; \
cmdBuff[4] = 0x00; \
cmdBuff[5] = 0x00; \
convert_endian(MXL_ENABLE_BIG_ENDIAN, size, (u8 *)dataPtr); \
memcpy((void *)&cmdBuff[6], dataPtr, size); \
} while(0) //;
typedef struct {
u32 regAddr;
u8 lsbPos;
u8 numOfBits;
} MXL_REG_FIELD_T;
typedef struct {
u32 dataSize;
u8 data[MAX_CMD_DATA];
} MXL_DEV_CMD_DATA_T;
typedef enum
{
MXL_HYDRA_SKU_TYPE_MIN = 0x00,
MXL_HYDRA_SKU_TYPE_581 = 0x00,
MXL_HYDRA_SKU_TYPE_584 = 0x01,
MXL_HYDRA_SKU_TYPE_585 = 0x02,
MXL_HYDRA_SKU_TYPE_544 = 0x03,
MXL_HYDRA_SKU_TYPE_561 = 0x04,
MXL_HYDRA_SKU_TYPE_5xx = 0x05,
MXL_HYDRA_SKU_TYPE_5yy = 0x06,
MXL_HYDRA_SKU_TYPE_511 = 0x07,
MXL_HYDRA_SKU_TYPE_561_DE = 0x08,
MXL_HYDRA_SKU_TYPE_582 = 0x09,
MXL_HYDRA_SKU_TYPE_541 = 0x0A,
MXL_HYDRA_SKU_TYPE_568 = 0x0B,
MXL_HYDRA_SKU_TYPE_542 = 0x0C,
MXL_HYDRA_SKU_TYPE_MAX = 0x0D,
} MXL_HYDRA_SKU_TYPE_E;
typedef struct
{
MXL_HYDRA_SKU_TYPE_E skuType;
} MXL_HYDRA_SKU_COMMAND_T;
typedef enum
{
MXL_HYDRA_DEMOD_ID_0 = 0,
MXL_HYDRA_DEMOD_ID_1,
MXL_HYDRA_DEMOD_ID_2,
MXL_HYDRA_DEMOD_ID_3,
MXL_HYDRA_DEMOD_ID_4,
MXL_HYDRA_DEMOD_ID_5,
MXL_HYDRA_DEMOD_ID_6,
MXL_HYDRA_DEMOD_ID_7,
MXL_HYDRA_DEMOD_MAX
} MXL_HYDRA_DEMOD_ID_E;
#define MXL_DEMOD_SCRAMBLE_SEQ_LEN 12
#define MAX_STEP_SIZE_24_XTAL_102_05_KHZ 195
#define MAX_STEP_SIZE_24_XTAL_204_10_KHZ 215
#define MAX_STEP_SIZE_24_XTAL_306_15_KHZ 203
#define MAX_STEP_SIZE_24_XTAL_408_20_KHZ 177
#define MAX_STEP_SIZE_27_XTAL_102_05_KHZ 195
#define MAX_STEP_SIZE_27_XTAL_204_10_KHZ 215
#define MAX_STEP_SIZE_27_XTAL_306_15_KHZ 203
#define MAX_STEP_SIZE_27_XTAL_408_20_KHZ 177
#define MXL_HYDRA_SPECTRUM_MIN_FREQ_KHZ 300000
#define MXL_HYDRA_SPECTRUM_MAX_FREQ_KHZ 2350000
typedef enum
{
DMD_STANDARD_ADDR = 0,
DMD_SPECTRUM_INVERSION_ADDR,
DMD_SPECTRUM_ROLL_OFF_ADDR,
DMD_SYMBOL_RATE_ADDR,
DMD_MODULATION_SCHEME_ADDR,
DMD_FEC_CODE_RATE_ADDR,
DMD_SNR_ADDR,
DMD_FREQ_OFFSET_ADDR,
DMD_CTL_FREQ_OFFSET_ADDR,
DMD_STR_FREQ_OFFSET_ADDR,
DMD_FTL_FREQ_OFFSET_ADDR,
DMD_STR_NBC_SYNC_LOCK_ADDR,
DMD_CYCLE_SLIP_COUNT_ADDR,
DMD_DISPLAY_IQ_ADDR,
DMD_DVBS2_CRC_ERRORS_ADDR,
DMD_DVBS2_PER_COUNT_ADDR,
DMD_DVBS2_PER_WINDOW_ADDR,
DMD_DVBS_CORR_RS_ERRORS_ADDR,
DMD_DVBS_UNCORR_RS_ERRORS_ADDR,
DMD_DVBS_BER_COUNT_ADDR,
DMD_DVBS_BER_WINDOW_ADDR,
DMD_TUNER_ID_ADDR,
DMD_DVBS2_PILOT_ON_OFF_ADDR,
DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR,
MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE,
} MXL_DEMOD_CHAN_PARAMS_OFFSET_E;
typedef enum
{
MXL_HYDRA_TUNER_ID_0 = 0,
MXL_HYDRA_TUNER_ID_1,
MXL_HYDRA_TUNER_ID_2,
MXL_HYDRA_TUNER_ID_3,
MXL_HYDRA_TUNER_MAX
} MXL_HYDRA_TUNER_ID_E;
typedef enum
{
MXL_HYDRA_DSS = 0,
MXL_HYDRA_DVBS,
MXL_HYDRA_DVBS2,
} MXL_HYDRA_BCAST_STD_E;
typedef enum
{
MXL_HYDRA_FEC_AUTO = 0,
MXL_HYDRA_FEC_1_2,
MXL_HYDRA_FEC_3_5,
MXL_HYDRA_FEC_2_3,
MXL_HYDRA_FEC_3_4,
MXL_HYDRA_FEC_4_5,
MXL_HYDRA_FEC_5_6,
MXL_HYDRA_FEC_6_7,
MXL_HYDRA_FEC_7_8,
MXL_HYDRA_FEC_8_9,
MXL_HYDRA_FEC_9_10,
} MXL_HYDRA_FEC_E;
typedef enum
{
MXL_HYDRA_MOD_AUTO = 0,
MXL_HYDRA_MOD_QPSK,
MXL_HYDRA_MOD_8PSK
} MXL_HYDRA_MODULATION_E;
typedef enum
{
MXL_HYDRA_SPECTRUM_AUTO = 0,
MXL_HYDRA_SPECTRUM_INVERTED,
MXL_HYDRA_SPECTRUM_NON_INVERTED,
} MXL_HYDRA_SPECTRUM_E;
typedef enum
{
MXL_HYDRA_ROLLOFF_AUTO = 0,
MXL_HYDRA_ROLLOFF_0_20,
MXL_HYDRA_ROLLOFF_0_25,
MXL_HYDRA_ROLLOFF_0_35
} MXL_HYDRA_ROLLOFF_E;
typedef enum
{
MXL_HYDRA_PILOTS_OFF = 0,
MXL_HYDRA_PILOTS_ON,
MXL_HYDRA_PILOTS_AUTO
} MXL_HYDRA_PILOTS_E;
typedef enum
{
MXL_HYDRA_FORMATTER = 0,
MXL_HYDRA_LEGACY_FEC,
MXL_HYDRA_FREQ_RECOVERY,
MXL_HYDRA_NBC,
MXL_HYDRA_CTL,
MXL_HYDRA_EQ,
} MXL_HYDRA_CONSTELLATION_SRC_E;
typedef struct
{
int agcLock; // AGC lock info
int fecLock; // Demod FEC block lock info
} MXL_HYDRA_DEMOD_LOCK_T;
typedef struct
{
u32 rsErrors; // RS decoder err counter
u32 berWindow; // Ber Windows
u32 berCount; // BER count
u32 berWindow_Iter1; // Ber Windows - post viterbi
u32 berCount_Iter1; // BER count - post viterbi
} MXL_HYDRA_DEMOD_STATUS_DVBS_T;
typedef struct
{
u32 rsErrors; // RS decoder err counter
u32 berWindow; // Ber Windows
u32 berCount; // BER count
} MXL_HYDRA_DEMOD_STATUS_DSS_T;
typedef struct
{
u32 crcErrors; // CRC error counter
u32 packetErrorCount; // Number of packet errors
u32 totalPackets; // Total packets
} MXL_HYDRA_DEMOD_STATUS_DVBS2_T;
typedef struct
{
MXL_HYDRA_BCAST_STD_E standardMask; // Standard DVB-S, DVB-S2 or DSS
union
{
MXL_HYDRA_DEMOD_STATUS_DVBS_T demodStatus_DVBS; // DVB-S demod status
MXL_HYDRA_DEMOD_STATUS_DVBS2_T demodStatus_DVBS2; // DVB-S2 demod status
MXL_HYDRA_DEMOD_STATUS_DSS_T demodStatus_DSS; // DSS demod status
} u;
} MXL_HYDRA_DEMOD_STATUS_T;
typedef struct
{
s32 carrierOffsetInHz; // CRL offset info
s32 symbolOffsetInSymbol; // SRL offset info
} MXL_HYDRA_DEMOD_SIG_OFFSET_INFO_T;
typedef struct
{
u8 scrambleSequence[MXL_DEMOD_SCRAMBLE_SEQ_LEN]; // scramble sequence
u32 scrambleCode; // scramble gold code
} MXL_HYDRA_DEMOD_SCRAMBLE_INFO_T;
typedef enum
{
MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, // 102.05 KHz for 24 MHz XTAL
MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, // 204.10 KHz for 24 MHz XTAL
MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, // 306.15 KHz for 24 MHz XTAL
MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, // 408.20 KHz for 24 MHz XTAL
MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, // 102.05 KHz for 27 MHz XTAL
MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, // 204.35 KHz for 27 MHz XTAL
MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, // 306.52 KHz for 27 MHz XTAL
MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, // 408.69 KHz for 27 MHz XTAL
} MXL_HYDRA_SPECTRUM_STEP_SIZE_E;
typedef enum
{
MXL_HYDRA_SPECTRUM_RESOLUTION_00_1_DB, // 0.1 dB
MXL_HYDRA_SPECTRUM_RESOLUTION_01_0_DB, // 1.0 dB
MXL_HYDRA_SPECTRUM_RESOLUTION_05_0_DB, // 5.0 dB
MXL_HYDRA_SPECTRUM_RESOLUTION_10_0_DB, // 10 dB
} MXL_HYDRA_SPECTRUM_RESOLUTION_E;
typedef enum
{
MXL_SPECTRUM_NO_ERROR,
MXL_SPECTRUM_INVALID_PARAMETER,
MXL_SPECTRUM_INVALID_STEP_SIZE,
MXL_SPECTRUM_BW_CANNOT_BE_COVERED,
MXL_SPECTRUM_DEMOD_BUSY,
MXL_SPECTRUM_TUNER_NOT_ENABLED,
} MXL_HYDRA_SPECTRUM_ERROR_CODE_E;
typedef struct
{
u32 tunerIndex; // TUNER Ctrl: one of MXL58x_TUNER_ID_E
u32 demodIndex; // DEMOD Ctrl: one of MXL58x_DEMOD_ID_E
MXL_HYDRA_SPECTRUM_STEP_SIZE_E stepSizeInKHz;
u32 startingFreqInkHz;
u32 totalSteps;
MXL_HYDRA_SPECTRUM_RESOLUTION_E spectrumDivision;
} MXL_HYDRA_SPECTRUM_REQ_T;
typedef enum
{
MXL_HYDRA_SEARCH_MAX_OFFSET = 0, // DMD searches for max freq offset (i.e. 5MHz)
MXL_HYDRA_SEARCH_BW_PLUS_ROLLOFF, // DMD searches for BW + ROLLOFF/2
} MXL_HYDRA_SEARCH_FREQ_OFFSET_TYPE_E;
typedef struct
{
u32 demodIndex;
MXL_HYDRA_SEARCH_FREQ_OFFSET_TYPE_E searchType;
} MXL58x_CFG_FREQ_OFF_SEARCH_RANGE_T;
// there are two slices
// slice0 - TS0, TS1, TS2 & TS3
// slice1 - TS4, TS5, TS6 & TS7
#define MXL_HYDRA_TS_SLICE_MAX 2
#define MAX_FIXED_PID_NUM 32
#define MXL_HYDRA_NCO_CLK 418 // 418 MHz
#define MXL_HYDRA_MAX_TS_CLOCK 139 // 139 MHz
#define MXL_HYDRA_TS_FIXED_PID_FILT_SIZE 32
#define MXL_HYDRA_SHARED_PID_FILT_SIZE_DEFAULT 33 // Shared PID filter size in 1-1 mux mode
#define MXL_HYDRA_SHARED_PID_FILT_SIZE_2_TO_1 66 // Shared PID filter size in 2-1 mux mode
#define MXL_HYDRA_SHARED_PID_FILT_SIZE_4_TO_1 132 // Shared PID filter size in 4-1 mux mode
typedef enum
{
MXL_HYDRA_SOFTWARE_PID_BANK = 0,
MXL_HYDRA_HARDWARE_PID_BANK,
} MXL_HYDRA_PID_BANK_TYPE_E;
typedef enum
{
MXL_HYDRA_TS_MUX_PID_REMAP = 0,
MXL_HYDRA_TS_MUX_PREFIX_EXTRA_HEADER = 1,
} MXL_HYDRA_TS_MUX_MODE_E;
typedef enum
{
MXL_HYDRA_TS_MUX_DISABLE = 0, // No Mux ( 1 TSIF to 1 TSIF)
MXL_HYDRA_TS_MUX_2_TO_1, // Mux 2 TSIF to 1 TSIF
MXL_HYDRA_TS_MUX_4_TO_1, // Mux 4 TSIF to 1 TSIF
} MXL_HYDRA_TS_MUX_TYPE_E;
typedef enum
{
MXL_HYDRA_TS_GROUP_0_3 = 0, // TS group 0 to 3 (TS0, TS1, TS2 & TS3)
MXL_HYDRA_TS_GROUP_4_7, // TS group 0 to 3 (TS4, TS5, TS6 & TS7)
} MXL_HYDRA_TS_GROUP_E;
typedef enum
{
MXL_HYDRA_TS_PIDS_ALLOW_ALL = 0, // Allow all pids
MXL_HYDRA_TS_PIDS_DROP_ALL, // Drop all pids
MXL_HYDRA_TS_INVALIDATE_PID_FILTER, // Delete current PD filter in the device
} MXL_HYDRA_TS_PID_FLT_CTRL_E;
typedef enum
{
MXL_HYDRA_TS_PID_FIXED = 0,
MXL_HYDRA_TS_PID_REGULAR,
} MXL_HYDRA_TS_PID_TYPE_E;
typedef struct
{
u16 originalPid; // pid from TS
u16 remappedPid; // remapped pid
MXL_BOOL_E enable; // enable or disable pid
MXL_BOOL_E allowOrDrop; // allow or drop pid
MXL_BOOL_E enablePidRemap; // enable or disable pid remap
u8 bondId; // Bond ID in A0 always 0 - Only for 568 Sku
u8 destId; // Output port ID for the PID - Only for 568 Sku
} MXL_HYDRA_TS_PID_T;
typedef struct
{
MXL_BOOL_E enable;
u8 numByte;
u8 header[12];
} MXL_HYDRA_TS_MUX_PREFIX_HEADER_T;
typedef enum
{
MXL_HYDRA_PID_BANK_A = 0,
MXL_HYDRA_PID_BANK_B,
} MXL_HYDRA_PID_FILTER_BANK_E;
typedef enum
{
MXL_HYDRA_MPEG_SERIAL_MSB_1ST = 0,
MXL_HYDRA_MPEG_SERIAL_LSB_1ST,
MXL_HYDRA_MPEG_SYNC_WIDTH_BIT = 0,
MXL_HYDRA_MPEG_SYNC_WIDTH_BYTE
} MXL_HYDRA_MPEG_DATA_FMT_E;
typedef enum
{
MXL_HYDRA_MPEG_MODE_SERIAL_4_WIRE = 0, // MPEG 4 Wire serial mode
MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE, // MPEG 3 Wire serial mode
MXL_HYDRA_MPEG_MODE_SERIAL_2_WIRE, // MPEG 2 Wire serial mode
MXL_HYDRA_MPEG_MODE_PARALLEL // MPEG parallel mode - valid only for MxL581
} MXL_HYDRA_MPEG_MODE_E;
typedef enum
{
MXL_HYDRA_MPEG_CLK_CONTINUOUS = 0, // Continuous MPEG clock
MXL_HYDRA_MPEG_CLK_GAPPED, // Gapped (gated) MPEG clock
} MXL_HYDRA_MPEG_CLK_TYPE_E;
typedef enum
{
MXL_HYDRA_MPEG_ACTIVE_LOW = 0,
MXL_HYDRA_MPEG_ACTIVE_HIGH,
MXL_HYDRA_MPEG_CLK_NEGATIVE = 0,
MXL_HYDRA_MPEG_CLK_POSITIVE,
MXL_HYDRA_MPEG_CLK_IN_PHASE = 0,
MXL_HYDRA_MPEG_CLK_INVERTED,
} MXL_HYDRA_MPEG_CLK_FMT_E;
typedef enum
{
MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG = 0,
MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_90_DEG,
MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_180_DEG,
MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_270_DEG
} MXL_HYDRA_MPEG_CLK_PHASE_E;
typedef enum
{
MXL_HYDRA_MPEG_ERR_REPLACE_SYNC = 0,
MXL_HYDRA_MPEG_ERR_REPLACE_VALID,
MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED
} MXL_HYDRA_MPEG_ERR_INDICATION_E;
typedef struct
{
int enable; // Enable or Disable MPEG OUT
MXL_HYDRA_MPEG_CLK_TYPE_E mpegClkType; // Continuous or gapped
MXL_HYDRA_MPEG_CLK_FMT_E mpegClkPol; // MPEG Clk polarity
u8 maxMpegClkRate; // Max MPEG Clk rate (0 – 104 MHz, 139 MHz)
MXL_HYDRA_MPEG_CLK_PHASE_E mpegClkPhase; // MPEG Clk phase
MXL_HYDRA_MPEG_DATA_FMT_E lsbOrMsbFirst; // LSB first or MSB first in TS transmission
MXL_HYDRA_MPEG_DATA_FMT_E mpegSyncPulseWidth; // MPEG SYNC pulse width (1-bit or 1-byte)
MXL_HYDRA_MPEG_CLK_FMT_E mpegValidPol; // MPEG VALID polarity
MXL_HYDRA_MPEG_CLK_FMT_E mpegSyncPol; // MPEG SYNC polarity
MXL_HYDRA_MPEG_MODE_E mpegMode; // config 4/3/2-wire serial or parallel TS out
MXL_HYDRA_MPEG_ERR_INDICATION_E mpegErrorIndication; // Enable or Disable MPEG error indication
} MXL_HYDRA_MPEGOUT_PARAM_T;
typedef enum
{
MXL_HYDRA_EXT_TS_IN_0 = 0,
MXL_HYDRA_EXT_TS_IN_1,
MXL_HYDRA_EXT_TS_IN_2,
MXL_HYDRA_EXT_TS_IN_3,
MXL_HYDRA_EXT_TS_IN_MAX
} MXL_HYDRA_EXT_TS_IN_ID_E;
typedef enum
{
MXL_HYDRA_TS_OUT_0 = 0,
MXL_HYDRA_TS_OUT_1,
MXL_HYDRA_TS_OUT_2,
MXL_HYDRA_TS_OUT_3,
MXL_HYDRA_TS_OUT_4,
MXL_HYDRA_TS_OUT_5,
MXL_HYDRA_TS_OUT_6,
MXL_HYDRA_TS_OUT_7,
MXL_HYDRA_TS_OUT_MAX
} MXL_HYDRA_TS_OUT_ID_E;
typedef enum
{
MXL_HYDRA_TS_DRIVE_STRENGTH_1x = 0,
MXL_HYDRA_TS_DRIVE_STRENGTH_2x,
MXL_HYDRA_TS_DRIVE_STRENGTH_3x,
MXL_HYDRA_TS_DRIVE_STRENGTH_4x,
MXL_HYDRA_TS_DRIVE_STRENGTH_5x,
MXL_HYDRA_TS_DRIVE_STRENGTH_6x,
MXL_HYDRA_TS_DRIVE_STRENGTH_7x,
MXL_HYDRA_TS_DRIVE_STRENGTH_8x
} MXL_HYDRA_TS_DRIVE_STRENGTH_E;
typedef enum
{
MXL_HYDRA_DEVICE_581 = 0,
MXL_HYDRA_DEVICE_584,
MXL_HYDRA_DEVICE_585,
MXL_HYDRA_DEVICE_544,
MXL_HYDRA_DEVICE_561,
MXL_HYDRA_DEVICE_TEST,
MXL_HYDRA_DEVICE_582,
MXL_HYDRA_DEVICE_541,
MXL_HYDRA_DEVICE_568,
MXL_HYDRA_DEVICE_542,
MXL_HYDRA_DEVICE_541S,
MXL_HYDRA_DEVICE_561S,
MXL_HYDRA_DEVICE_581S,
MXL_HYDRA_DEVICE_MAX
} MXL_HYDRA_DEVICE_E;
// Demod IQ data
typedef struct
{
u32 demodId;
u32 sourceOfIQ; // ==0, it means I/Q comes from Formatter
// ==1, Legacy FEC
// ==2, Frequency Recovery
// ==3, NBC
// ==4, CTL
// ==5, EQ
// ==6, FPGA
} MXL_HYDRA_DEMOD_IQ_SRC_T;
typedef struct
{
u32 demodId;
} MXL_HYDRA_DEMOD_ABORT_TUNE_T;
typedef struct
{
u8 tunerId;
u8 enable;
} MxL_HYDRA_TUNER_CMD;
// Demod Para for Channel Tune
typedef struct
{
u32 tunerIndex;
u32 demodIndex;
u32 frequencyInHz; // Frequency
u32 standard; // one of MXL_HYDRA_BCAST_STD_E
u32 spectrumInversion; // Input : Spectrum inversion.
u32 rollOff; /* rollOff (alpha) factor */
u32 symbolRateInHz; /* Symbol rate */
u32 pilots; /* TRUE = pilots enabled */
u32 modulationScheme; // Input : Modulation Scheme is one of MXL_HYDRA_MODULATION_E
u32 fecCodeRate; // Input : Forward error correction rate. Is one of MXL_HYDRA_FEC_E
u32 maxCarrierOffsetInMHz; // Maximum carrier freq offset in MHz. Same as freqSearchRangeKHz, but in unit of MHz.
} MXL_HYDRA_DEMOD_PARAM_T;
typedef struct
{
u32 demodIndex;
u8 scrambleSequence[12]; // scramble sequence
u32 scrambleCode; // scramble gold code
} MXL_HYDRA_DEMOD_SCRAMBLE_CODE_T;
typedef struct
{
u32 intrType;
u32 intrDurationInNanoSecs;
u32 intrMask;
} MXL_INTR_CFG_T;
typedef struct
{
u8 powerMode; // enumeration values are defined in MXL_HYDRA_PWR_MODE_E (device API.h)
} MxL_HYDRA_POWER_MODE_CMD;
typedef struct
{
u32 timeIntervalInSeconds; // in seconds
u32 tunerIndex;
s32 rssiThreshold;
} MXL_HYDRA_RF_WAKEUP_PARAM_T;
typedef struct
{
u32 tunerCount;
MXL_HYDRA_RF_WAKEUP_PARAM_T params;
} MXL_HYDRA_RF_WAKEUP_CFG_T;
typedef enum
{
MXL_HYDRA_AUX_CTRL_MODE_FSK = 0, // Select FSK controller
MXL_HYDRA_AUX_CTRL_MODE_DISEQC, // Select DiSEqC controller
} MXL_HYDRA_AUX_CTRL_MODE_E;
typedef enum
{
MXL_HYDRA_DISEQC_ENVELOPE_MODE = 0,
MXL_HYDRA_DISEQC_TONE_MODE,
} MXL_HYDRA_DISEQC_OPMODE_E;
typedef enum
{
MXL_HYDRA_DISEQC_1_X = 0, // Config DiSEqC 1.x mode
MXL_HYDRA_DISEQC_2_X, // Config DiSEqC 2.x mode
MXL_HYDRA_DISEQC_DISABLE // Disable DiSEqC
} MXL_HYDRA_DISEQC_VER_E;
typedef enum
{
MXL_HYDRA_DISEQC_CARRIER_FREQ_22KHZ= 0, // DiSEqC signal frequency of 22 KHz
MXL_HYDRA_DISEQC_CARRIER_FREQ_33KHZ, // DiSEqC signal frequency of 33 KHz
MXL_HYDRA_DISEQC_CARRIER_FREQ_44KHZ // DiSEqC signal frequency of 44 KHz
} MXL_HYDRA_DISEQC_CARRIER_FREQ_E;
typedef enum
{
MXL_HYDRA_DISEQC_ID_0 = 0,
MXL_HYDRA_DISEQC_ID_1,
MXL_HYDRA_DISEQC_ID_2,
MXL_HYDRA_DISEQC_ID_3
} MXL_HYDRA_DISEQC_ID_E;
typedef enum
{
MXL_HYDRA_FSK_CFG_TYPE_39KPBS = 0, // 39.0kbps
MXL_HYDRA_FSK_CFG_TYPE_39_017KPBS, // 39.017kbps
MXL_HYDRA_FSK_CFG_TYPE_115_2KPBS // 115.2kbps
} MXL_HYDRA_FSK_OP_MODE_E;
typedef struct
{
u32 diseqcId; // DSQ 0, 1, 2 or 3
u32 opMode; // Envelope mode (0) or internal tone mode (1)
u32 version; // 0: 1.0 , 1: 1.1 , 2: Disable
u32 centerFreq; // 0: 22KHz, 1: 33KHz and 2: 44 KHz
}MXL58x_DSQ_OP_MODE_T;
typedef struct
{
u32 diseqcId;
u32 contToneFlag; // 1: Enable , 0: Disable
} MXL_HYDRA_DISEQC_CFG_CONT_TONE_T;

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frontends/mxl5xx_regs.h Normal file
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/*
* Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
*
* License type: GPLv2
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License as published by the Free Software
* Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*
* This program may alternatively be licensed under a proprietary license from
* MaxLinear, Inc.
*
* See terms and conditions defined in file 'LICENSE.txt', which is part of this
* source code package.
*/
#ifndef __MXL58X_REGISTERS_H__
#define __MXL58X_REGISTERS_H__
#ifdef __cplusplus
extern "C" {
#endif
#define HYDRA_INTR_STATUS_REG 0x80030008
#define HYDRA_INTR_MASK_REG 0x8003000C
#define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 // 0 - 24 MHz & 1 - 27 MHz
#define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 // 0 - 24 MHz & 1 - 27 MHz
#define HYDRA_CPU_RESET_REG 0x8003003C
#define HYDRA_CPU_RESET_DATA 0x00000400
#define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028
#define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000
#define HYDRA_RESET_BBAND_REG 0x80030024
#define HYDRA_RESET_BBAND_DATA 0x00000000
#define HYDRA_RESET_XBAR_REG 0x80030020
#define HYDRA_RESET_XBAR_DATA 0x00000000
#define HYDRA_MODULES_CLK_1_REG 0x80030014
#define HYDRA_DISABLE_CLK_1 0x00000000
#define HYDRA_MODULES_CLK_2_REG 0x8003001C
#define HYDRA_DISABLE_CLK_2 0x0000000B
#define HYDRA_PRCM_ROOT_CLK_REG 0x80030018
#define HYDRA_PRCM_ROOT_CLK_DISABLE 0x00000000
#define HYDRA_CPU_RESET_CHECK_REG 0x80030008
#define HYDRA_CPU_RESET_CHECK_OFFSET 0x40000000 // <bit 30>
#define HYDRA_SKU_ID_REG 0x90000190
#define FW_DL_SIGN_ADDR 0x3FFFEAE0
// Register to check if FW is running or not
#define HYDRA_HEAR_BEAT 0x3FFFEDDC
// Firmware version
#define HYDRA_FIRMWARE_VERSION 0x3FFFEDB8
#define HYDRA_FW_RC_VERSION 0x3FFFCFAC
// Firmware patch version
#define HYDRA_FIRMWARE_PATCH_VERSION 0x3FFFEDC2
// SOC operating temperature in C
#define HYDRA_TEMPARATURE 0x3FFFEDB4
// Demod & Tuner status registers
// Demod 0 status base address
#define HYDRA_DEMOD_0_BASE_ADDR 0x3FFFC64C
// Tuner 0 status base address
#define HYDRA_TUNER_0_BASE_ADDR 0x3FFFCE4C
#define POWER_FROM_ADCRSSI_READBACK 0x3FFFEB6C
// Macros to determine base address of respective demod or tuner
#define HYDRA_DMD_STATUS_OFFSET(demodID) ((demodID) * 0x100)
#define HYDRA_TUNER_STATUS_OFFSET(tunerID) ((tunerID) * 0x40)
// Demod status address offset from respective demod's base address
#define HYDRA_DMD_AGC_DIG_LEVEL_ADDR_OFFSET 0x3FFFC64C
#define HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET 0x3FFFC650
#define HYDRA_DMD_ACQ_STATUS_ADDR_OFFSET 0x3FFFC654
#define HYDRA_DMD_STANDARD_ADDR_OFFSET 0x3FFFC658
#define HYDRA_DMD_SPECTRUM_INVERSION_ADDR_OFFSET 0x3FFFC65C
#define HYDRA_DMD_SPECTRUM_ROLL_OFF_ADDR_OFFSET 0x3FFFC660
#define HYDRA_DMD_SYMBOL_RATE_ADDR_OFFSET 0x3FFFC664
#define HYDRA_DMD_MODULATION_SCHEME_ADDR_OFFSET 0x3FFFC668
#define HYDRA_DMD_FEC_CODE_RATE_ADDR_OFFSET 0x3FFFC66C
#define HYDRA_DMD_SNR_ADDR_OFFSET 0x3FFFC670
#define HYDRA_DMD_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC674
#define HYDRA_DMD_CTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC678
#define HYDRA_DMD_STR_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC67C
#define HYDRA_DMD_FTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC680
#define HYDRA_DMD_STR_NBC_SYNC_LOCK_ADDR_OFFSET 0x3FFFC684
#define HYDRA_DMD_CYCLE_SLIP_COUNT_ADDR_OFFSET 0x3FFFC688
#define HYDRA_DMD_DISPLAY_I_ADDR_OFFSET 0x3FFFC68C
#define HYDRA_DMD_DISPLAY_Q_ADDR_OFFSET 0x3FFFC68E
#define HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET 0x3FFFC690
#define HYDRA_DMD_DVBS2_PER_COUNT_ADDR_OFFSET 0x3FFFC694
#define HYDRA_DMD_DVBS2_PER_WINDOW_ADDR_OFFSET 0x3FFFC698
#define HYDRA_DMD_DVBS_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC69C
#define HYDRA_DMD_DVBS_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6A0
#define HYDRA_DMD_DVBS_BER_COUNT_ADDR_OFFSET 0x3FFFC6A4
#define HYDRA_DMD_DVBS_BER_WINDOW_ADDR_OFFSET 0x3FFFC6A8
// Debug-purpose DVB-S DMD 0
#define HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6C8 // corrected RS Errors: 1st iteration
#define HYDRA_DMD_DVBS_1ST_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6CC // uncorrected RS Errors: 1st iteration
#define HYDRA_DMD_DVBS_BER_COUNT_1ST_ADDR_OFFSET 0x3FFFC6D0
#define HYDRA_DMD_DVBS_BER_WINDOW_1ST_ADDR_OFFSET 0x3FFFC6D4
#define HYDRA_DMD_TUNER_ID_ADDR_OFFSET 0x3FFFC6AC
#define HYDRA_DMD_DVBS2_PILOT_ON_OFF_ADDR_OFFSET 0x3FFFC6B0
#define HYDRA_DMD_FREQ_SEARCH_RANGE_KHZ_ADDR_OFFSET 0x3FFFC6B4
#define HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET 0x3FFFC6B8
#define HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR 0x3FFFC704
#define HYDRA_DMD_STATUS_INPUT_POWER_ADDR 0x3FFFC708
// DVB-S new scaled_BER_count for a new BER API, see HYDRA-1343 "DVB-S post viterbi information"
#define DMD0_STATUS_DVBS_1ST_SCALED_BER_COUNT_ADDR 0x3FFFC710 // DMD 0: 1st iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR
#define DMD0_STATUS_DVBS_SCALED_BER_COUNT_ADDR 0x3FFFC714 // DMD 0: 2nd iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR
#define DMD0_SPECTRUM_MIN_GAIN_STATUS 0x3FFFC73C
#define DMD0_SPECTRUM_MIN_GAIN_WB_SAGC_VALUE 0x3FFFC740
#define DMD0_SPECTRUM_ MIN_GAIN_NB_SAGC_VALUE 0x3FFFC744
#define HYDRA_DMD_STATUS_END_ADDR_OFFSET 0x3FFFC748
// Tuner status address offset from respective tuners's base address
#define HYDRA_TUNER_DEMOD_ID_ADDR_OFFSET 0x3FFFCE4C
#define HYDRA_TUNER_AGC_LOCK_OFFSET 0x3FFFCE50
#define HYDRA_TUNER_SPECTRUM_STATUS_OFFSET 0x3FFFCE54
#define HYDRA_TUNER_SPECTRUM_BIN_SIZE_OFFSET 0x3FFFCE58
#define HYDRA_TUNER_SPECTRUM_ADDRESS_OFFSET 0x3FFFCE5C
#define HYDRA_TUNER_ENABLE_COMPLETE 0x3FFFEB78
#define HYDRA_DEMOD_STATUS_LOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_YES)
#define HYDRA_DEMOD_STATUS_UNLOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_NO)
#define HYDRA_TUNER_STATUS_LOCK(devId,tunerId) MxLWare_HYDRA_WriteRegister(devId,(HYDRA_TUNER_STATUS_LOCK_ADDR_OFFSET + HYDRA_TUNER_STATUS_OFFSET(tunerId)), MXL_YES)
#define HYDRA_TUNER_STATUS_UNLOCK(devId,tunerId) MxLWare_HYDRA_WriteRegister(devId,(HYDRA_TUNER_STATUS_LOCK_ADDR_OFFSET + HYDRA_TUNER_STATUS_OFFSET(tunerId)), MXL_NO)
#define HYDRA_VERSION 0x3FFFEDB8
#define HYDRA_DEMOD0_VERSION 0x3FFFEDBC
#define HYDRA_DEMOD1_VERSION 0x3FFFEDC0
#define HYDRA_DEMOD2_VERSION 0x3FFFEDC4
#define HYDRA_DEMOD3_VERSION 0x3FFFEDC8
#define HYDRA_DEMOD4_VERSION 0x3FFFEDCC
#define HYDRA_DEMOD5_VERSION 0x3FFFEDD0
#define HYDRA_DEMOD6_VERSION 0x3FFFEDD4
#define HYDRA_DEMOD7_VERSION 0x3FFFEDD8
#define HYDRA_HEAR_BEAT 0x3FFFEDDC
#define HYDRA_SKU_MGMT 0x3FFFEBC0
#define MXL_HYDRA_FPGA_A_ADDRESS 0x91C00000
#define MXL_HYDRA_FPGA_B_ADDRESS 0x91D00000
// TS control base address
#define HYDRA_TS_CTRL_BASE_ADDR 0x90700000
#define MPEG_MUX_MODE_SLICE0_REG HYDRA_TS_CTRL_BASE_ADDR + 0x08
#define MPEG_MUX_MODE_SLICE0_OFFSET (0),(2)
#define MPEG_MUX_MODE_SLICE1_REG HYDRA_TS_CTRL_BASE_ADDR + 0x08
#define MPEG_MUX_MODE_SLICE1_OFFSET (2),(2)
#define PID_BANK_SEL_SLICE0_REG HYDRA_TS_CTRL_BASE_ADDR + 0x190
#define PID_BANK_SEL_SLICE1_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1B0
#define SW_REGULAR_PID_SW_BANK_OFFSET 0,1
#define SW_FIXED_PID_SW_BANK_OFFSET 1,1
#define HW_REGULAR_PID_BANK_OFFSET 8,4
#define HW_FIXED_PID_BANK_OFFSET 4,4
#define MPEG_CLK_GATED_REG HYDRA_TS_CTRL_BASE_ADDR + 0x20
#define MPEG_CLK_GATED_OFFSET 0,1
#define MPEG_CLK_ALWAYS_ON_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1D4
#define MPEG_CLK_ALWAYS_ON_OFFSET 0,1
#define HYDRA_REGULAR_PID_BANK_A_REG HYDRA_TS_CTRL_BASE_ADDR + 0x190
#define HYDRA_REGULAR_PID_BAN K_A_OFFSET 0,1
#define HYDRA_FIXED_PID_BANK_A_REG HYDRA_TS_CTRL_BASE_ADDR + 0x190
#define HYDRA_FIXED_PID_BANK_A_OFFSET 1,1
#define HYDRA_REGULAR_PID_BANK_B_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1B0
#define HYDRA_REGULAR_PID_BANK_B_OFFSET 0,1
#define HYDRA_FIXED_PID_BANK_B_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1B0
#define HYDRA_FIXED_PID_BANK_B_OFFSET 1,1
#define FIXED_PID_TBL_REG_ADDRESS_0 HYDRA_TS_CTRL_BASE_ADDR + 0x9000
#define FIXED_PID_TBL_REG_ADDRESS_1 HYDRA_TS_CTRL_BASE_ADDR + 0x9100
#define FIXED_PID_TBL_REG_ADDRESS_2 HYDRA_TS_CTRL_BASE_ADDR + 0x9200
#define FIXED_PID_TBL_REG_ADDRESS_3 HYDRA_TS_CTRL_BASE_ADDR + 0x9300
#define FIXED_PID_TBL_REG_ADDRESS_4 HYDRA_TS_CTRL_BASE_ADDR + 0xB000
#define FIXED_PID_TBL_REG_ADDRESS_5 HYDRA_TS_CTRL_BASE_ADDR + 0xB100
#define FIXED_PID_TBL_REG_ADDRESS_6 HYDRA_TS_CTRL_BASE_ADDR + 0xB200
#define FIXED_PID_TBL_REG_ADDRESS_7 HYDRA_TS_CTRL_BASE_ADDR + 0xB300
#define REGULAR_PID_TBL_REG_ADDRESS_0 HYDRA_TS_CTRL_BASE_ADDR + 0x8000
#define REGULAR_PID_TBL_REG_ADDRESS_1 HYDRA_TS_CTRL_BASE_ADDR + 0x8200
#define REGULAR_PID_TBL_REG_ADDRESS_2 HYDRA_TS_CTRL_BASE_ADDR + 0x8400
#define REGULAR_PID_TBL_REG_ADDRESS_3 HYDRA_TS_CTRL_BASE_ADDR + 0x8600
#define REGULAR_PID_TBL_REG_ADDRESS_4 HYDRA_TS_CTRL_BASE_ADDR + 0xA000
#define REGULAR_PID_TBL_REG_ADDRESS_5 HYDRA_TS_CTRL_BASE_ADDR + 0xA200
#define REGULAR_PID_TBL_REG_ADDRESS_6 HYDRA_TS_CTRL_BASE_ADDR + 0xA400
#define REGULAR_PID_TBL_REG_ADDRESS_7 HYDRA_TS_CTRL_BASE_ADDR + 0xA600
#define PID_VALID_OFFSET 0,1
#define PID_DROP_OFFSET 1,1
#define PID_REMAP_ENABLE_OFFSET 2,1
#define PID_VALUE_OFFSET 4,13
#define PID_MASK_OFFSET 19,13
#define REGULAR_PID_REMAP_VALUE_OFFSET 0,13
#define FIXED_PID_REMAP_VALUE_OFFSET 0,16
#define PID_DEMODID_OFFSET 16,3
///////////////////////////////////////////////
#if 0
#define AFE_REG_D2A_TA_ADC_CLK_OUT_FLIP 0x90200004,12,1
#define AFE_REG_D2A_TA_RFFE_LNACAPLOAD_1P8 0x90200028,24,4
#define AFE_REG_D2A_TA_RFFE_RF1_EN_1P8 0x90200028,5,1
#define AFE_REG_D2A_TA_RFFE_SPARE_1P8 0x90200028,8,8
#define AFE_REG_D2A_TB_ADC_CLK_OUT_FLIP 0x9020000C,23,1
#define AFE_REG_D2A_TB_RFFE_LNACAPLOAD_1P8 0x90200030,16,4
#define AFE_REG_D2A_TB_RFFE_RF1_EN_1P8 0x9020002C,21,1
#define AFE_REG_D2A_TB_RFFE_SPARE_1P8 0x90200030,0,8
#define AFE_REG_D2A_TC_ADC_CLK_OUT_FLIP 0x90200018,7,1
#define AFE_REG_D2A_TC_RFFE_LNACAPLOAD_1P8 0x90200038,2,4
#define AFE_REG_D2A_TC_RFFE_RF1_EN_1P8 0x90200034,14,1
#define AFE_REG_D2A_TC_RFFE_SPARE_1P8 0x90200034,17,8
#define AFE_REG_D2A_TD_ADC_CLK_OUT_FLIP 0x90200020,18,1
#define AFE_REG_D2A_TD_RFFE_LNACAPLOAD_1P8 0x9020003C,17,4
#define AFE_REG_D2A_TD_RFFE_RF1_EN_1P8 0x90200038,29,1
#define AFE_REG_D2A_TD_RFFE_SPARE_1P8 0x9020003C,1,8
#endif
#define AFE_REG_D2A_XTAL_EN_CLKOUT_1P8 0x90200054,23,1
#define PAD_MUX_TS0_IN_CLK_PINMUX_SEL 0x90000018,0,3
#define PAD_MUX_TS0_IN_DATA_PINMUX_SEL 0x90000018,4,3
#define PAD_MUX_TS1_IN_CLK_PINMUX_SEL 0x90000018,8,3
#define PAD_MUX_TS1_IN_DATA_PINMUX_SEL 0x90000018,12,3
#define PAD_MUX_TS2_IN_CLK_PINMUX_SEL 0x90000018,16,3
#define PAD_MUX_TS2_IN_DATA_PINMUX_SEL 0x90000018,20,3
#define PAD_MUX_TS3_IN_CLK_PINMUX_SEL 0x90000018,24,3
#define PAD_MUX_TS3_IN_DATA_PINMUX_SEL 0x90000018,28,3
#define PAD_MUX_GPIO_00_SYNC_BASEADDR 0x90000188
#define PAD_MUX_GPIO_01_SYNC_IN PAD_MUX_GPIO_00_SYNC_BASEADDR,1,1
#define PRCM_AFE_SOC_ID 0x80030004,24,8
#define PAD_MUX_UART_RX_C_PINMUX_BASEADDR 0x9000001C
#define PAD_MUX_UART_RX_C_PINMUX_SEL PAD_MUX_UART_RX_C_PINMUX_BASEADDR,0,3
#define PAD_MUX_UART_RX_D_PINMUX_SEL PAD_MUX_UART_RX_C_PINMUX_BASEADDR,4,3
#define PAD_MUX_BOND_OPTION 0x90000190,0,3
#define PAD_MUX_DIGIO_01_PINMUX_SEL 0x9000016C,4,3
#define PAD_MUX_DIGIO_02_PINMUX_SEL 0x9000016C,8,3
#define PAD_MUX_DIGIO_03_PINMUX_SEL 0x9000016C,12,3
#define PAD_MUX_DIGIO_04_PINMUX_SEL 0x9000016C,16,3
#define PAD_MUX_DIGIO_05_PINMUX_SEL 0x9000016C,20,3
#define PAD_MUX_DIGIO_06_PINMUX_SEL 0x9000016C,24,3
#define PAD_MUX_DIGIO_07_PINMUX_SEL 0x9000016C,28,3
#define PAD_MUX_DIGIO_08_PINMUX_SEL 0x90000170,0,3
#define PAD_MUX_DIGIO_09_PINMUX_SEL 0x90000170,4,3
#define PAD_MUX_DIGIO_10_PINMUX_SEL 0x90000170,8,3
#define PAD_MUX_DIGIO_11_PINMUX_SEL 0x90000170,12,3
#define PAD_MUX_DIGIO_12_PINMUX_SEL 0x90000170,16,3
#define PAD_MUX_DIGIO_13_PINMUX_SEL 0x90000170,20,3
#define PAD_MUX_DIGIO_14_PINMUX_SEL 0x90000170,24,3
#define PAD_MUX_DIGIO_15_PINMUX_SEL 0x90000170,28,3
#define PAD_MUX_DIGIO_16_PINMUX_SEL 0x90000174,0,3
#define PAD_MUX_DIGIO_17_PINMUX_SEL 0x90000174,4,3
#define PAD_MUX_DIGIO_18_PINMUX_SEL 0x90000174,8,3
#define PAD_MUX_DIGIO_19_PINMUX_SEL 0x90000174,12,3
#define PAD_MUX_DIGIO_20_PINMUX_SEL 0x90000174,16,3
#define PAD_MUX_DIGIO_21_PINMUX_SEL 0x90000174,20,3
#define PAD_MUX_DIGIO_22_PINMUX_SEL 0x90000174,24,3
#define PAD_MUX_DIGIO_23_PINMUX_SEL 0x90000174,28,3
#define PAD_MUX_DIGIO_24_PINMUX_SEL 0x90000178,0,3
#define PAD_MUX_DIGIO_25_PINMUX_SEL 0x90000178,4,3
#define PAD_MUX_DIGIO_26_PINMUX_SEL 0x90000178,8,3
#define PAD_MUX_DIGIO_27_PINMUX_SEL 0x90000178,12,3
#define PAD_MUX_DIGIO_28_PINMUX_SEL 0x90000178,16,3
#define PAD_MUX_DIGIO_29_PINMUX_SEL 0x90000178,20,3
#define PAD_MUX_DIGIO_30_PINMUX_SEL 0x90000178,24,3
#define PAD_MUX_DIGIO_31_PINMUX_SEL 0x90000178,28,3
#define PAD_MUX_DIGIO_32_PINMUX_SEL 0x9000017C,0,3
#define PAD_MUX_DIGIO_33_PINMUX_SEL 0x9000017C,4,3
#define PAD_MUX_DIGIO_34_PINMUX_SEL 0x9000017C,8,3
#define PAD_MUX_EJTAG_TCK_PINMUX_SEL 0x90000020,0,3
#define PAD_MUX_EJTAG_TDI_PINMUX_SEL 0x90000020,8,3
#define PAD_MUX_EJTAG_TMS_PINMUX_SEL 0x90000020,4,3
#define PAD_MUX_EJTAG_TRSTN_PINMUX_SEL 0x90000020,12,3
#define PAD_MUX_PAD_DRV_DIGIO_00 0x90000194,0,3
#define PAD_MUX_PAD_DRV_DIGIO_05 0x90000194,20,3
#define PAD_MUX_PAD_DRV_DIGIO_06 0x90000194,24,3
#define PAD_MUX_PAD_DRV_DIGIO_11 0x90000198,12,3
#define PAD_MUX_PAD_DRV_DIGIO_12 0x90000198,16,3
#define PAD_MUX_PAD_DRV_DIGIO_13 0x90000198,20,3
#define PAD_MUX_PAD_DRV_DIGIO_14 0x90000198,24,3
#define PAD_MUX_PAD_DRV_DIGIO_16 0x9000019C,0,3
#define PAD_MUX_PAD_DRV_DIGIO_17 0x9000019C,4,3
#define PAD_MUX_PAD_DRV_DIGIO_18 0x9000019C,8,3
#define PAD_MUX_PAD_DRV_DIGIO_22 0x9000019C,24,3
#define PAD_MUX_PAD_DRV_DIGIO_23 0x9000019C,28,3
#define PAD_MUX_PAD_DRV_DIGIO_24 0x900001A0,0,3
#define PAD_MUX_PAD_DRV_DIGIO_25 0x900001A0,4,3
#define PAD_MUX_PAD_DRV_DIGIO_29 0x900001A0,20,3
#define PAD_MUX_PAD_DRV_DIGIO_30 0x900001A0,24,3
#define PAD_MUX_PAD_DRV_DIGIO_31 0x900001A0,28,3
#define PRCM_AFE_REG_CLOCK_ENABLE 0x80030014,9,1
#define PRCM_CHIP_VERSION 0x80030000,12,4
#define PRCM_AFE_CHIP_MMSK_VER 0x80030004,8,8
#define PRCM_PRCM_AFE_REG_SOFT_RST_N 0x8003003C,12,1
#define PRCM_PRCM_CPU_SOFT_RST_N 0x8003003C,0,1
#define PRCM_PRCM_DIGRF_APB_DATA_BB0 0x80030074,0,20
#define PRCM_PRCM_DIGRF_APB_DATA_BB1 0x80030078,0,20
#define PRCM_PRCM_DIGRF_APB_DATA_BB2 0x8003007C,0,20
#define PRCM_PRCM_DIGRF_APB_DATA_BB3 0x80030080,0,20
#define PRCM_PRCM_DIGRF_APB_DATA_BB4 0x80030084,0,20
#define PRCM_PRCM_DIGRF_APB_DATA_BB5 0x80030088,0,20
#define PRCM_PRCM_DIGRF_APB_DATA_BB6 0x8003008C,0,20
#define PRCM_PRCM_DIGRF_APB_DATA_BB7 0x80030090,0,20
#define PRCM_PRCM_DIGRF_CAPT_DONE 0x80030070,24,8
#define PRCM_PRCM_DIGRF_START_CAPT 0x80030064,2,1
#define PRCM_PRCM_PAD_MUX_SOFT_RST_N 0x8003003C,11,1
#define PRCM_PRCM_XPT_PARALLEL_FIFO_RST_N 0x80030028,20,1
#define XPT_APPEND_BYTES0 0x90700008,4,2
#define XPT_APPEND_BYTES1 0x90700008,6,2
#define XPT_CLOCK_POLARITY0 0x90700010,16,1
#define XPT_CLOCK_POLARITY1 0x90700010,17,1
#define XPT_CLOCK_POLARITY2 0x90700010,18,1
#define XPT_CLOCK_POLARITY3 0x90700010,19,1
#define XPT_CLOCK_POLARITY4 0x90700010,20,1
#define XPT_CLOCK_POLARITY5 0x90700010,21,1
#define XPT_CLOCK_POLARITY6 0x90700010,22,1
#define XPT_CLOCK_POLARITY7 0x90700010,23,1
#define XPT_DSS_DVB_ENCAP_EN0 0x90700000,16,1
#define XPT_DSS_DVB_ENCAP_EN1 0x90700000,17,1
#define XPT_DSS_DVB_ENCAP_EN2 0x90700000,18,1
#define XPT_DSS_DVB_ENCAP_EN3 0x90700000,19,1
#define XPT_DSS_DVB_ENCAP_EN4 0x90700000,20,1
#define XPT_DSS_DVB_ENCAP_EN5 0x90700000,21,1
#define XPT_DSS_DVB_ENCAP_EN6 0x90700000,22,1
#define XPT_DSS_DVB_ENCAP_EN7 0x90700000,23,1
#define XPT_DVB_MATCH_BYTE 0x9070017C,16,8
#define XPT_DVB_PACKET_SIZE0 0x90700180,0,8
#define XPT_DVB_PACKET_SIZE1 0x90700180,8,8
#define XPT_DVB_PACKET_SIZE2 0x90700180,16,8
#define XPT_DVB_PACKET_SIZE3 0x90700180,24,8
#define XPT_ENABLE_DVB_INPUT0 0x90700178,0,1
#define XPT_ENABLE_DVB_INPUT1 0x90700178,1,1
#define XPT_ENABLE_DVB_INPUT2 0x90700178,2,1
#define XPT_ENABLE_DVB_INPUT3 0x90700178,3,1
#define XPT_ENABLE_INPUT0 0x90700000,0,1
#define XPT_ENABLE_INPUT1 0x90700000,1,1
#define XPT_ENABLE_INPUT2 0x90700000,2,1
#define XPT_ENABLE_INPUT3 0x90700000,3,1
#define XPT_ENABLE_INPUT4 0x90700000,4,1
#define XPT_ENABLE_INPUT5 0x90700000,5,1
#define XPT_ENABLE_INPUT6 0x90700000,6,1
#define XPT_ENABLE_INPUT7 0x90700000,7,1
#define XPT_ENABLE_OUTPUT0 0x9070000C,0,1
#define XPT_ENABLE_OUTPUT1 0x9070000C,1,1
#define XPT_ENABLE_OUTPUT2 0x9070000C,2,1
#define XPT_ENABLE_OUTPUT3 0x9070000C,3,1
#define XPT_ENABLE_OUTPUT4 0x9070000C,4,1
#define XPT_ENABLE_OUTPUT5 0x9070000C,5,1
#define XPT_ENABLE_OUTPUT6 0x9070000C,6,1
#define XPT_ENABLE_OUTPUT7 0x9070000C,7,1
#define XPT_ENABLE_PARALLEL_OUTPUT 0x90700010,27,1
#define XPT_ENABLE_PCR_COUNT 0x90700184,1,1
#define XPT_ERROR_REPLACE_SYNC0 0x9070000C,24,1
#define XPT_ERROR_REPLACE_SYNC1 0x9070000C,25,1
#define XPT_ERROR_REPLACE_SYNC2 0x9070000C,26,1
#define XPT_ERROR_REPLACE_SYNC3 0x9070000C,27,1
#define XPT_ERROR_REPLACE_SYNC4 0x9070000C,28,1
#define XPT_ERROR_REPLACE_SYNC5 0x9070000C,29,1
#define XPT_ERROR_REPLACE_SYNC6 0x9070000C,30,1
#define XPT_ERROR_REPLACE_SYNC7 0x9070000C,31,1
#define XPT_ERROR_REPLACE_VALID0 0x90700014,8,1
#define XPT_ERROR_REPLACE_VALID1 0x90700014,9,1
#define XPT_ERROR_REPLACE_VALID2 0x90700014,10,1
#define XPT_ERROR_REPLACE_VALID3 0x90700014,11,1
#define XPT_ERROR_REPLACE_VALID4 0x90700014,12,1
#define XPT_ERROR_REPLACE_VALID5 0x90700014,13,1
#define XPT_ERROR_REPLACE_VALID6 0x90700014,14,1
#define XPT_ERROR_REPLACE_VALID7 0x90700014,15,1
#define XPT_INP0_MERGE_HDR0 0x90700058,0,32
#define XPT_INP0_MERGE_HDR1 0x9070005C,0,32
#define XPT_INP0_MERGE_HDR2 0x90700060,0,32
#define XPT_INP1_MERGE_HDR0 0x90700064,0,32
#define XPT_INP1_MERGE_HDR1 0x90700068,0,32
#define XPT_INP1_MERGE_HDR2 0x9070006C,0,32
#define XPT_INP2_MERGE_HDR0 0x90700070,0,32
#define XPT_INP2_MERGE_HDR1 0x90700074,0,32
#define XPT_INP2_MERGE_HDR2 0x90700078,0,32
#define XPT_INP3_MERGE_HDR0 0x9070007C,0,32
#define XPT_INP3_MERGE_HDR1 0x90700080,0,32
#define XPT_INP3_MERGE_HDR2 0x90700084,0,32
#define XPT_INP4_MERGE_HDR0 0x90700088,0,32
#define XPT_INP4_MERGE_HDR1 0x9070008C,0,32
#define XPT_INP4_MERGE_HDR2 0x90700090,0,32
#define XPT_INP5_MERGE_HDR0 0x90700094,0,32
#define XPT_INP5_MERGE_HDR1 0x90700098,0,32
#define XPT_INP5_MERGE_HDR2 0x9070009C,0,32
#define XPT_INP6_MERGE_HDR0 0x907000A0,0,32
#define XPT_INP6_MERGE_HDR1 0x907000A4,0,32
#define XPT_INP6_MERGE_HDR2 0x907000A8,0,32
#define XPT_INP7_MERGE_HDR0 0x907000AC,0,32
#define XPT_INP7_MERGE_HDR1 0x907000B0,0,32
#define XPT_INP7_MERGE_HDR2 0x907000B4,0,32
#define XPT_INP_MODE_DSS0 0x90700000,8,1
#define XPT_INP_MODE_DSS1 0x90700000,9,1
#define XPT_INP_MODE_DSS2 0x90700000,10,1
#define XPT_INP_MODE_DSS3 0x90700000,11,1
#define XPT_INP_MODE_DSS4 0x90700000,12,1
#define XPT_INP_MODE_DSS5 0x90700000,13,1
#define XPT_INP_MODE_DSS6 0x90700000,14,1
#define XPT_INP_MODE_DSS7 0x90700000,15,1
#define XPT_KNOWN_PID_MUX_SELECT0 0x90700190,8,4
#define XPT_KNOWN_PID_MUX_SELECT1 0x907001B0,8,4
#define XPT_LSB_FIRST0 0x9070000C,16,1
#define XPT_LSB_FIRST1 0x9070000C,17,1
#define XPT_LSB_FIRST2 0x9070000C,18,1
#define XPT_LSB_FIRST3 0x9070000C,19,1
#define XPT_LSB_FIRST4 0x9070000C,20,1
#define XPT_LSB_FIRST5 0x9070000C,21,1
#define XPT_LSB_FIRST6 0x9070000C,22,1
#define XPT_LSB_FIRST7 0x9070000C,23,1
#define XPT_MODE_27MHZ 0x90700184,0,1
#define XPT_NCO_COUNT_MIN 0x90700044,16,8
#define XPT_OUTPUT_MODE_DSS0 0x9070000C,8,1
#define XPT_OUTPUT_MODE_DSS1 0x9070000C,9,1
#define XPT_OUTPUT_MODE_DSS2 0x9070000C,10,1
#define XPT_OUTPUT_MODE_DSS3 0x9070000C,11,1
#define XPT_OUTPUT_MODE_DSS4 0x9070000C,12,1
#define XPT_OUTPUT_MODE_DSS5 0x9070000C,13,1
#define XPT_OUTPUT_MODE_DSS6 0x9070000C,14,1
#define XPT_OUTPUT_MODE_DSS7 0x9070000C,15,1
#define XPT_OUTPUT_MODE_MUXGATING0 0x90700020,0,1
#define XPT_OUTPUT_MODE_MUXGATING1 0x90700020,1,1
#define XPT_OUTPUT_MODE_MUXGATING2 0x90700020,2,1
#define XPT_OUTPUT_MODE_MUXGATING3 0x90700020,3,1
#define XPT_OUTPUT_MODE_MUXGATING4 0x90700020,4,1
#define XPT_OUTPUT_MODE_MUXGATING5 0x90700020,5,1
#define XPT_OUTPUT_MODE_MUXGATING6 0x90700020,6,1
#define XPT_OUTPUT_MODE_MUXGATING7 0x90700020,7,1
#define XPT_OUTPUT_MUXSELECT0 0x9070001C,0,3
#define XPT_OUTPUT_MUXSELECT1 0x9070001C,4,3
#define XPT_OUTPUT_MUXSELECT2 0x9070001C,8,3
#define XPT_OUTPUT_MUXSELECT3 0x9070001C,12,3
#define XPT_OUTPUT_MUXSELECT4 0x9070001C,16,3
#define XPT_OUTPUT_MUXSELECT5 0x9070001C,20,3
#define XPT_PCR_RTS_CORRECTION_ENABLE 0x90700008,14,1
#define XPT_PID_DEFAULT_DROP0 0x90700190,12,1
#define XPT_PID_DEFAULT_DROP1 0x90700190,13,1
#define XPT_PID_DEFAULT_DROP2 0x90700190,14,1
#define XPT_PID_DEFAULT_DROP3 0x90700190,15,1
#define XPT_PID_DEFAULT_DROP4 0x907001B0,12,1
#define XPT_PID_DEFAULT_DROP5 0x907001B0,13,1
#define XPT_PID_DEFAULT_DROP6 0x907001B0,14,1
#define XPT_PID_DEFAULT_DROP7 0x907001B0,15,1
#define XPT_PID_MUX_SELECT0 0x90700190,4,4
#define XPT_PID_MUX_SELECT1 0x907001B0,4,4
#define XPT_STREAM_MUXMODE0 0x90700008,0,2
#define XPT_STREAM_MUXMODE1 0x90700008,2,2
#define XPT_SYNC_FULL_BYTE0 0x90700010,0,1
#define XPT_SYNC_FULL_BYTE1 0x90700010,1,1
#define XPT_SYNC_FULL_BYTE2 0x90700010,2,1
#define XPT_SYNC_FULL_BYTE3 0x90700010,3,1
#define XPT_SYNC_FULL_BYTE4 0x90700010,4,1
#define XPT_SYNC_FULL_BYTE5 0x90700010,5,1
#define XPT_SYNC_FULL_BYTE6 0x90700010,6,1
#define XPT_SYNC_FULL_BYTE7 0x90700010,7,1
#define XPT_SYNC_LOCK_THRESHOLD 0x9070017C,0,8
#define XPT_SYNC_MISS_THRESHOLD 0x9070017C,8,8
#define XPT_SYNC_POLARITY0 0x90700010,8,1
#define XPT_SYNC_POLARITY1 0x90700010,9,1
#define XPT_SYNC_POLARITY2 0x90700010,10,1
#define XPT_SYNC_POLARITY3 0x90700010,11,1
#define XPT_SYNC_POLARITY4 0x90700010,12,1
#define XPT_SYNC_POLARITY5 0x90700010,13,1
#define XPT_SYNC_POLARITY6 0x90700010,14,1
#define XPT_SYNC_POLARITY7 0x90700010,15,1
#define XPT_TS_CLK_OUT_EN0 0x907001D4,0,1
#define XPT_TS_CLK_OUT_EN1 0x907001D4,1,1
#define XPT_TS_CLK_OUT_EN2 0x907001D4,2,1
#define XPT_TS_CLK_OUT_EN3 0x907001D4,3,1
#define XPT_TS_CLK_OUT_EN4 0x907001D4,4,1
#define XPT_TS_CLK_OUT_EN5 0x907001D4,5,1
#define XPT_TS_CLK_OUT_EN6 0x907001D4,6,1
#define XPT_TS_CLK_OUT_EN7 0x907001D4,7,1
#define XPT_TS_CLK_OUT_EN_PARALLEL 0x907001D4,8,1
#define XPT_TS_CLK_PHASE0 0x90700018,0,3
#define XPT_TS_CLK_PHASE1 0x90700018,4,3
#define XPT_TS_CLK_PHASE2 0x90700018,8,3
#define XPT_TS_CLK_PHASE3 0x90700018,12,3
#define XPT_TS_CLK_PHASE4 0x90700018,16,3
#define XPT_TS_CLK_PHASE5 0x90700018,20,3
#define XPT_TS_CLK_PHASE6 0x90700018,24,3
#define XPT_TS_CLK_PHASE7 0x90700018,28,3
#define XPT_VALID_POLARITY0 0x90700014,0,1
#define XPT_VALID_POLARITY1 0x90700014,1,1
#define XPT_VALID_POLARITY2 0x90700014,2,1
#define XPT_VALID_POLARITY3 0x90700014,3,1
#define XPT_VALID_POLARITY4 0x90700014,4,1
#define XPT_VALID_POLARITY5 0x90700014,5,1
#define XPT_VALID_POLARITY6 0x90700014,6,1
#define XPT_VALID_POLARITY7 0x90700014,7,1
#define XPT_ZERO_FILL_COUNT 0x90700008,8,6
#define XPT_PACKET_GAP_MIN_BASEADDR 0x90700044
#define XPT_PACKET_GAP_MIN_TIMER XPT_PACKET_GAP_MIN_BASEADDR,0,16
#define XPT_NCO_COUNT_MIN0 XPT_PACKET_GAP_MIN_BASEADDR,16,8
#define XPT_NCO_COUNT_BASEADDR 0x90700238
#define XPT_NCO_COUNT_MIN1 XPT_NCO_COUNT_BASEADDR,0,8
#define XPT_NCO_COUNT_MIN2 XPT_NCO_COUNT_BASEADDR,8,8
#define XPT_NCO_COUNT_MIN3 XPT_NCO_COUNT_BASEADDR,16,8
#define XPT_NCO_COUNT_MIN4 XPT_NCO_COUNT_BASEADDR,24,8
#define XPT_NCO_COUNT_BASEADDR1 0x9070023C
#define XPT_NCO_COUNT_MIN5 XPT_NCO_COUNT_BASEADDR1,0,8
#define XPT_NCO_COUNT_MIN6 XPT_NCO_COUNT_BASEADDR1,8,8
#define XPT_NCO_COUNT_MIN7 XPT_NCO_COUNT_BASEADDR1,16,8
// V2 DigRF status register
#define BB0_DIGRF_CAPT_DONE 0x908000CC,0,1
#define PRCM_PRCM_CHIP_ID 0x80030000,0,12
#define XPT_PID_BASEADDR 0x90708000
#define XPT_PID_VALID0 XPT_PID_BASEADDR,0,1
#define XPT_PID_DROP0 XPT_PID_BASEADDR,1,1
#define XPT_PID_REMAP0 XPT_PID_BASEADDR,2,1
#define XPT_PID_VALUE0 XPT_PID_BASEADDR,4,13
#define XPT_PID_MASK0 XPT_PID_BASEADDR,19,13
#define XPT_PID_REMAP_BASEADDR 0x90708004
#define XPT_PID_REMAP_VALUE0 XPT_PID_REMAP_BASEADDR,0,13
#define XPT_PID_PORT_ID0 XPT_PID_REMAP_BASEADDR,16,3
#define XPT_KNOWN_PID_BASEADDR 0x90709000
#define XPT_KNOWN_PID_VALID0 XPT_KNOWN_PID_BASEADDR,0,1
#define XPT_KNOWN_PID_DROP0 XPT_KNOWN_PID_BASEADDR,1,1
#define XPT_KNOWN_PID_REMAP0 XPT_KNOWN_PID_BASEADDR,2,1
#define XPT_KNOWN_PID_REMAP_VALUE0 XPT_KNOWN_PID_BASEADDR,16,13
#define XPT_PID_BASEADDR1 0x9070A000
#define XPT_PID_VALID1 XPT_PID_BASEADDR1,0,1
#define XPT_PID_DROP1 XPT_PID_BASEADDR1,1,1
#define XPT_PID_REMAP1 XPT_PID_BASEADDR1,2,1
#define XPT_PID_VALUE1 XPT_PID_BASEADDR1,4,13
#define XPT_PID_MASK1 XPT_PID_BASEADDR1,19,13
#define XPT_PID_REMAP_BASEADDR1 0x9070A004
#define XPT_PID_REMAP_VALUE1 XPT_PID_REMAP_BASEADDR1,0,13
#define XPT_KNOWN_PID_BASEADDR1 0x9070B000
#define XPT_KNOWN_PID_VALID1 XPT_KNOWN_PID_BASEADDR1,0,1
#define XPT_KNOWN_PID_DROP1 XPT_KNOWN_PID_BASEADDR1,1,1
#define XPT_KNOWN_PID_REMAP1 XPT_KNOWN_PID_BASEADDR1,2,1
#define XPT_KNOWN_PID_REMAP_VALUE1 XPT_KNOWN_PID_BASEADDR1,16,13
#define XPT_BERT_LOCK_BASEADDR 0x907000B8
#define XPT_BERT_LOCK_THRESHOLD XPT_BERT_LOCK_BASEADDR,0,8
#define XPT_BERT_LOCK_WINDOW XPT_BERT_LOCK_BASEADDR,8,8
#define XPT_BERT_BASEADDR 0x907000BC
#define XPT_BERT_ENABLE0 XPT_BERT_BASEADDR,0,1
#define XPT_BERT_ENABLE1 XPT_BERT_BASEADDR,1,1
#define XPT_BERT_ENABLE2 XPT_BERT_BASEADDR,2,1
#define XPT_BERT_ENABLE3 XPT_BERT_BASEADDR,3,1
#define XPT_BERT_ENABLE4 XPT_BERT_BASEADDR,4,1
#define XPT_BERT_ENABLE5 XPT_BERT_BASEADDR,5,1
#define XPT_BERT_ENABLE6 XPT_BERT_BASEADDR,6,1
#define XPT_BERT_ENABLE7 XPT_BERT_BASEADDR,7,1
#define XPT_BERT_SEQUENCE_PN23_0 XPT_BERT_BASEADDR,8,1
#define XPT_BERT_SEQUENCE_PN23_1 XPT_BERT_BASEADDR,9,1
#define XPT_BERT_SEQUENCE_PN23_2 XPT_BERT_BASEADDR,10,1
#define XPT_BERT_SEQUENCE_PN23_3 XPT_BERT_BASEADDR,11,1
#define XPT_BERT_SEQUENCE_PN23_4 XPT_BERT_BASEADDR,12,1
#define XPT_BERT_SEQUENCE_PN23_5 XPT_BERT_BASEADDR,13,1
#define XPT_BERT_SEQUENCE_PN23_6 XPT_BERT_BASEADDR,14,1
#define XPT_BERT_SEQUENCE_PN23_7 XPT_BERT_BASEADDR,15,1
#define XPT_LOCK_RESYNC0 XPT_BERT_BASEADDR,16,1
#define XPT_LOCK_RESYNC1 XPT_BERT_BASEADDR,17,1
#define XPT_LOCK_RESYNC2 XPT_BERT_BASEADDR,18,1
#define XPT_LOCK_RESYNC3 XPT_BERT_BASEADDR,19,1
#define XPT_LOCK_RESYNC4 XPT_BERT_BASEADDR,20,1
#define XPT_LOCK_RESYNC5 XPT_BERT_BASEADDR,21,1
#define XPT_LOCK_RESYNC6 XPT_BERT_BASEADDR,22,1
#define XPT_LOCK_RESYNC7 XPT_BERT_BASEADDR,23,1
#define XPT_BERT_DATA_POLARITY0 XPT_BERT_BASEADDR,24,1
#define XPT_BERT_DATA_POLARITY1 XPT_BERT_BASEADDR,25,1
#define XPT_BERT_DATA_POLARITY2 XPT_BERT_BASEADDR,26,1
#define XPT_BERT_DATA_POLARITY3 XPT_BERT_BASEADDR,27,1
#define XPT_BERT_DATA_POLARITY4 XPT_BERT_BASEADDR,28,1
#define XPT_BERT_DATA_POLARITY5 XPT_BERT_BASEADDR,29,1
#define XPT_BERT_DATA_POLARITY6 XPT_BERT_BASEADDR,30,1
#define XPT_BERT_DATA_POLARITY7 XPT_BERT_BASEADDR,31,1
#define XPT_BERT_INVERT_BASEADDR 0x907000C0
#define XPT_BERT_INVERT_DATA0 XPT_BERT_INVERT_BASEADDR,0,1
#define XPT_BERT_INVERT_DATA1 XPT_BERT_INVERT_BASEADDR,1,1
#define XPT_BERT_INVERT_DATA2 XPT_BERT_INVERT_BASEADDR,2,1
#define XPT_BERT_INVERT_DATA3 XPT_BERT_INVERT_BASEADDR,3,1
#define XPT_BERT_INVERT_DATA4 XPT_BERT_INVERT_BASEADDR,4,1
#define XPT_BERT_INVERT_DATA5 XPT_BERT_INVERT_BASEADDR,5,1
#define XPT_BERT_INVERT_DATA6 XPT_BERT_INVERT_BASEADDR,6,1
#define XPT_BERT_INVERT_DATA7 XPT_BERT_INVERT_BASEADDR,7,1
#define XPT_BERT_INVERT_SEQUENCE0 XPT_BERT_INVERT_BASEADDR,8,1
#define XPT_BERT_INVERT_SEQUENCE1 XPT_BERT_INVERT_BASEADDR,9,1
#define XPT_BERT_INVERT_SEQUENCE2 XPT_BERT_INVERT_BASEADDR,10,1
#define XPT_BERT_INVERT_SEQUENCE3 XPT_BERT_INVERT_BASEADDR,11,1
#define XPT_BERT_INVERT_SEQUENCE4 XPT_BERT_INVERT_BASEADDR,12,1
#define XPT_BERT_INVERT_SEQUENCE5 XPT_BERT_INVERT_BASEADDR,13,1
#define XPT_BERT_INVERT_SEQUENCE6 XPT_BERT_INVERT_BASEADDR,14,1
#define XPT_BERT_INVERT_SEQUENCE7 XPT_BERT_INVERT_BASEADDR,15,1
#define XPT_BERT_OUTPUT_POLARITY0 XPT_BERT_INVERT_BASEADDR,16,1
#define XPT_BERT_OUTPUT_POLARITY1 XPT_BERT_INVERT_BASEADDR,17,1
#define XPT_BERT_OUTPUT_POLARITY2 XPT_BERT_INVERT_BASEADDR,18,1
#define XPT_BERT_OUTPUT_POLARITY3 XPT_BERT_INVERT_BASEADDR,19,1
#define XPT_BERT_OUTPUT_POLARITY4 XPT_BERT_INVERT_BASEADDR,20,1
#define XPT_BERT_OUTPUT_POLARITY5 XPT_BERT_INVERT_BASEADDR,21,1
#define XPT_BERT_OUTPUT_POLARITY6 XPT_BERT_INVERT_BASEADDR,22,1
#define XPT_BERT_OUTPUT_POLARITY7 XPT_BERT_INVERT_BASEADDR,23,1
#define XPT_BERT_HEADER_BASEADDR 0x907000C4
#define XPT_BERT_HEADER_MODE0 XPT_BERT_HEADER_BASEADDR,0,2
#define XPT_BERT_HEADER_MODE1 XPT_BERT_HEADER_BASEADDR,2,2
#define XPT_BERT_HEADER_MODE2 XPT_BERT_HEADER_BASEADDR,4,2
#define XPT_BERT_HEADER_MODE3 XPT_BERT_HEADER_BASEADDR,6,2
#define XPT_BERT_HEADER_MODE4 XPT_BERT_HEADER_BASEADDR,8,2
#define XPT_BERT_HEADER_MODE5 XPT_BERT_HEADER_BASEADDR,10,2
#define XPT_BERT_HEADER_MODE6 XPT_BERT_HEADER_BASEADDR,12,2
#define XPT_BERT_HEADER_MODE7 XPT_BERT_HEADER_BASEADDR,14,2
#define XPT_BERT_BASEADDR1 0x907000C8
#define XPT_BERT_LOCKED0 XPT_BERT_BASEADDR1,0,1
#define XPT_BERT_LOCKED1 XPT_BERT_BASEADDR1,1,1
#define XPT_BERT_LOCKED2 XPT_BERT_BASEADDR1,2,1
#define XPT_BERT_LOCKED3 XPT_BERT_BASEADDR1,3,1
#define XPT_BERT_LOCKED4 XPT_BERT_BASEADDR1,4,1
#define XPT_BERT_LOCKED5 XPT_BERT_BASEADDR1,5,1
#define XPT_BERT_LOCKED6 XPT_BERT_BASEADDR1,6,1
#define XPT_BERT_LOCKED7 XPT_BERT_BASEADDR1,7,1
#define XPT_BERT_BIT_COUNT_SAT0 XPT_BERT_BASEADDR1,8,1
#define XPT_BERT_BIT_COUNT_SAT1 XPT_BERT_BASEADDR1,9,1
#define XPT_BERT_BIT_COUNT_SAT2 XPT_BERT_BASEADDR1,10,1
#define XPT_BERT_BIT_COUNT_SAT3 XPT_BERT_BASEADDR1,11,1
#define XPT_BERT_BIT_COUNT_SAT4 XPT_BERT_BASEADDR1,12,1
#define XPT_BERT_BIT_COUNT_SAT5 XPT_BERT_BASEADDR1,13,1
#define XPT_BERT_BIT_COUNT_SAT6 XPT_BERT_BASEADDR1,14,1
#define XPT_BERT_BIT_COUNT_SAT7 XPT_BERT_BASEADDR1,15,1
#define XPT_BERT_BIT_COUNT0_BASEADDR 0x907000CC
#define XPT_BERT_BIT_COUNT0_LO XPT_BERT_BIT_COUNT0_BASEADDR,0,32
#define XPT_BERT_BIT_COUNT0_BASEADDR1 0x907000D0
#define XPT_BERT_BIT_COUNT0_HI XPT_BERT_BIT_COUNT0_BASEADDR1,0,18
#define XPT_BERT_BIT_COUNT1_BASEADDR 0x907000D4
#define XPT_BERT_BIT_COUNT1_LO XPT_BERT_BIT_COUNT1_BASEADDR,0,32
#define XPT_BERT_BIT_COUNT1_BASEADDR1 0x907000D8
#define XPT_BERT_BIT_COUNT1_HI XPT_BERT_BIT_COUNT1_BASEADDR1,0,18
#define XPT_BERT_BIT_COUNT2_BASEADDR 0x907000DC
#define XPT_BERT_BIT_COUNT2_LO XPT_BERT_BIT_COUNT2_BASEADDR,0,32
#define XPT_BERT_BIT_COUNT2_BASEADDR1 0x907000E0
#define XPT_BERT_BIT_COUNT2_HI XPT_BERT_BIT_COUNT2_BASEADDR1,0,18
#define XPT_BERT_BIT_COUNT3_BASEADDR 0x907000E4
#define XPT_BERT_BIT_COUNT3_LO XPT_BERT_BIT_COUNT3_BASEADDR,0,32
#define XPT_BERT_BIT_COUNT3_BASEADDR1 0x907000E8
#define XPT_BERT_BIT_COUNT3_HI XPT_BERT_BIT_COUNT3_BASEADDR1,0,18
#define XPT_BERT_BIT_COUNT4_BASEADDR 0x907000EC
#define XPT_BERT_BIT_COUNT4_LO XPT_BERT_BIT_COUNT4_BASEADDR,0,32
#define XPT_BERT_BIT_COUNT4_BASEADDR1 0x907000F0
#define XPT_BERT_BIT_COUNT4_HI XPT_BERT_BIT_COUNT4_BASEADDR1,0,18
#define XPT_BERT_BIT_COUNT5_BASEADDR 0x907000F4
#define XPT_BERT_BIT_COUNT5_LO XPT_BERT_BIT_COUNT5_BASEADDR,0,32
#define XPT_BERT_BIT_COUNT5_BASEADDR1 0x907000F8
#define XPT_BERT_BIT_COUNT5_HI XPT_BERT_BIT_COUNT5_BASEADDR1,0,18
#define XPT_BERT_BIT_COUNT6_BASEADDR 0x907000FC
#define XPT_BERT_BIT_COUNT6_LO XPT_BERT_BIT_COUNT6_BASEADDR,0,32
#define XPT_BERT_BIT_COUNT6_BASEADDR1 0x90700100
#define XPT_BERT_BIT_COUNT6_HI XPT_BERT_BIT_COUNT6_BASEADDR1,0,18
#define XPT_BERT_BIT_COUNT7_BASEADDR 0x90700104
#define XPT_BERT_BIT_COUNT7_LO XPT_BERT_BIT_COUNT7_BASEADDR,0,32
#define XPT_BERT_BIT_COUNT7_BASEADDR1 0x90700108
#define XPT_BERT_BIT_COUNT7_HI XPT_BERT_BIT_COUNT7_BASEADDR1,0,18
#define XPT_BERT_ERR_COUNT0_BASEADDR 0x9070010C
#define XPT_BERT_ERR_COUNT0_LO XPT_BERT_ERR_COUNT0_BASEADDR,0,32
#define XPT_BERT_ERR_COUNT0_BASEADDR1 0x90700110
#define XPT_BERT_ERR_COUNT0_HI XPT_BERT_ERR_COUNT0_BASEADDR1,0,8
#define XPT_BERT_ERR_COUNT1_BASEADDR 0x90700114
#define XPT_BERT_ERR_COUNT1_LO XPT_BERT_ERR_COUNT1_BASEADDR,0,32
#define XPT_BERT_ERR_COUNT1_BASEADDR1 0x90700118
#define XPT_BERT_ERR_COUNT1_HI XPT_BERT_ERR_COUNT1_BASEADDR1,0,8
#define XPT_BERT_ERR_COUNT2_BASEADDR 0x9070011C
#define XPT_BERT_ERR_COUNT2_LO XPT_BERT_ERR_COUNT2_BASEADDR,0,32
#define XPT_BERT_ERR_COUNT2_BASEADDR1 0x90700120
#define XPT_BERT_ERR_COUNT2_HI XPT_BERT_ERR_COUNT2_BASEADDR1,0,8
#define XPT_BERT_ERR_COUNT3_BASEADDR 0x90700124
#define XPT_BERT_ERR_COUNT3_LO XPT_BERT_ERR_COUNT3_BASEADDR,0,32
#define XPT_BERT_ERR_COUNT3_BASEADDR1 0x90700128
#define XPT_BERT_ERR_COUNT3_HI XPT_BERT_ERR_COUNT3_BASEADDR1,0,8
#define XPT_BERT_ERR_COUNT4_BASEADDR 0x9070012C
#define XPT_BERT_ERR_COUNT4_LO XPT_BERT_ERR_COUNT4_BASEADDR,0,32
#define XPT_BERT_ERR_COUNT4_BASEADDR1 0x90700130
#define XPT_BERT_ERR_COUNT4_HI XPT_BERT_ERR_COUNT4_BASEADDR1,0,8
#define XPT_BERT_ERR_COUNT5_BASEADDR 0x90700134
#define XPT_BERT_ERR_COUNT5_LO XPT_BERT_ERR_COUNT5_BASEADDR,0,32
#define XPT_BERT_ERR_COUNT5_BASEADDR1 0x90700138
#define XPT_BERT_ERR_COUNT5_HI XPT_BERT_ERR_COUNT5_BASEADDR1,0,8
#define XPT_BERT_ERR_COUNT6_BASEADDR 0x9070013C
#define XPT_BERT_ERR_COUNT6_LO XPT_BERT_ERR_COUNT6_BASEADDR,0,32
#define XPT_BERT_ERR_COUNT6_BASEADDR1 0x90700140
#define XPT_BERT_ERR_COUNT6_HI XPT_BERT_ERR_COUNT6_BASEADDR1,0,8
#define XPT_BERT_ERR_COUNT7_BASEADDR 0x90700144
#define XPT_BERT_ERR_COUNT7_LO XPT_BERT_ERR_COUNT7_BASEADDR,0,32
#define XPT_BERT_ERR_COUNT7_BASEADDR1 0x90700148
#define XPT_BERT_ERR_COUNT7_HI XPT_BERT_ERR_COUNT7_BASEADDR1,0,8
#define XPT_BERT_ERROR_BASEADDR 0x9070014C
#define XPT_BERT_ERROR_INSERT XPT_BERT_ERROR_BASEADDR,0,24
#define XPT_BERT_ANALYZER_BASEADDR 0x90700150
#define XPT_BERT_ANALYZER_ENABLE XPT_BERT_ANALYZER_BASEADDR,0,1
#define XPT_BERT_ANALYZER_PORT XPT_BERT_ANALYZER_BASEADDR,4,3
#define XPT_BERT_ANALYZER_ERR_THRES XPT_BERT_ANALYZER_BASEADDR,15,17
#define XPT_BERT_ANALYZER_BASEADDR1 0x90700154
#define XPT_BERT_ANALYZER_START XPT_BERT_ANALYZER_BASEADDR1,0,32
#define XPT_BERT_ANALYZER_BASEADDR2 0x90700158
#define XPT_BERT_ANALYZER_TSTAMP0 XPT_BERT_ANALYZER_BASEADDR2,0,32
#define XPT_BERT_ANALYZER_BASEADDR3 0x9070015C
#define XPT_BERT_ANALYZER_TSTAMP1 XPT_BERT_ANALYZER_BASEADDR3,0,32
#define XPT_BERT_ANALYZER_BASEADDR4 0x90700160
#define XPT_BERT_ANALYZER_TSTAMP2 XPT_BERT_ANALYZER_BASEADDR4,0,32
#define XPT_BERT_ANALYZER_BASEADDR5 0x90700164
#define XPT_BERT_ANALYZER_TSTAMP3 XPT_BERT_ANALYZER_BASEADDR5,0,32
#define XPT_BERT_ANALYZER_BASEADDR6 0x90700168
#define XPT_BERT_ANALYZER_TSTAMP4 XPT_BERT_ANALYZER_BASEADDR6,0,32
#define XPT_BERT_ANALYZER_BASEADDR7 0x9070016C
#define XPT_BERT_ANALYZER_TSTAMP5 XPT_BERT_ANALYZER_BASEADDR7,0,32
#define XPT_BERT_ANALYZER_BASEADDR8 0x90700170
#define XPT_BERT_ANALYZER_TSTAMP6 XPT_BERT_ANALYZER_BASEADDR8,0,32
#define XPT_BERT_ANALYZER_BASEADDR9 0x90700174
#define XPT_BERT_ANALYZER_TSTAMP7 XPT_BERT_ANALYZER_BASEADDR9,0,32
#define XPT_DMD0_BASEADDR 0x9070024C
#define XPT_DMD0_SEL XPT_DMD0_BASEADDR,0,3
#define XPT_DMD1_SEL XPT_DMD0_BASEADDR,4,3
#define XPT_DMD2_SEL XPT_DMD0_BASEADDR,8,3
#define XPT_DMD3_SEL XPT_DMD0_BASEADDR,12,3
#define XPT_DMD4_SEL XPT_DMD0_BASEADDR,16,3
#define XPT_DMD5_SEL XPT_DMD0_BASEADDR,20,3
#define XPT_DMD6_SEL XPT_DMD0_BASEADDR,24,3
#define XPT_DMD7_SEL XPT_DMD0_BASEADDR,28,3
// V2 AGC Gain Freeze & step
#define DBG_ENABLE_DISABLE_AGC (0x3FFFCF60) // 1: DISABLE, 0:ENABLE
#define WB_DFE0_DFE_FB_RF1_BASEADDR 0x903004A4
#define WB_DFE0_DFE_FB_RF1_BO WB_DFE0_DFE_FB_RF1_BASEADDR,0,3
#define WB_DFE0_DFE_FB_RF2_BO WB_DFE0_DFE_FB_RF1_BASEADDR,4,4
#define WB_DFE0_DFE_FB_LNA_BO WB_DFE0_DFE_FB_RF1_BASEADDR,8,2
#define WB_DFE1_DFE_FB_RF1_BASEADDR 0x904004A4
#define WB_DFE1_DFE_FB_RF1_BO WB_DFE1_DFE_FB_RF1_BASEADDR,0,3
#define WB_DFE1_DFE_FB_RF2_BO WB_DFE1_DFE_FB_RF1_BASEADDR,4,4
#define WB_DFE1_DFE_FB_LNA_BO WB_DFE1_DFE_FB_RF1_BASEADDR,8,2
#define WB_DFE2_DFE_FB_RF1_BASEADDR 0x905004A4
#define WB_DFE2_DFE_FB_RF1_BO WB_DFE2_DFE_FB_RF1_BASEADDR,0,3
#define WB_DFE2_DFE_FB_RF2_BO WB_DFE2_DFE_FB_RF1_BASEADDR,4,4
#define WB_DFE2_DFE_FB_LNA_BO WB_DFE2_DFE_FB_RF1_BASEADDR,8,2
#define WB_DFE3_DFE_FB_RF1_BASEADDR 0x906004A4
#define WB_DFE3_DFE_FB_RF1_BO WB_DFE3_DFE_FB_RF1_BASEADDR,0,3
#define WB_DFE3_DFE_FB_RF2_BO WB_DFE3_DFE_FB_RF1_BASEADDR,4,4
#define WB_DFE3_DFE_FB_LNA_BO WB_DFE3_DFE_FB_RF1_BASEADDR,8,2
#define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR 0x90200104
#define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,0,1
#define AFE_REG_D2A_TA_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,1,1
#define AFE_REG_D2A_TB_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,2,1
#define AFE_REG_D2A_TB_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,3,1
#define AFE_REG_D2A_TC_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,4,1
#define AFE_REG_D2A_TC_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,5,1
#define AFE_REG_D2A_TD_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,6,1
#define AFE_REG_D2A_TD_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,7,1
#define AFE_REG_AFE_REG_SPARE_BASEADDR 0x902000A0
#define AFE_REG_D2A_TA_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR,13,5
#define AFE_REG_AFE_REG_SPARE_BASEADDR1 0x902000B4
#define AFE_REG_D2A_TB_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR1,13,5
#define AFE_REG_AFE_REG_SPARE_BASEADDR2 0x902000C4
#define AFE_REG_D2A_TC_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR2,13,5
#define AFE_REG_AFE_REG_SPARE_BASEADDR3 0x902000D4
#define AFE_REG_D2A_TD_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR3,13,5
#define WB_DFE0_DFE_FB_AGC_BASEADDR 0x90300498
#define WB_DFE0_DFE_FB_AGC_APPLY WB_DFE0_DFE_FB_AGC_BASEADDR,0,1
#define WB_DFE1_DFE_FB_AGC_BASEADDR 0x90400498
#define WB_DFE1_DFE_FB_AGC_APPLY WB_DFE1_DFE_FB_AGC_BASEADDR,0,1
#define WB_DFE2_DFE_FB_AGC_BASEADDR 0x90500498
#define WB_DFE2_DFE_FB_AGC_APPLY WB_DFE2_DFE_FB_AGC_BASEADDR,0,1
#define WB_DFE3_DFE_FB_AGC_BASEADDR 0x90600498
#define WB_DFE3_DFE_FB_AGC_APPLY WB_DFE3_DFE_FB_AGC_BASEADDR,0,1
#define WDT_WD_INT_BASEADDR 0x8002000C
#define WDT_WD_INT_STATUS WDT_WD_INT_BASEADDR,0,1
#define FSK_TX_FTM_BASEADDR 0x80090000
#define FSK_TX_FTM_OE FSK_TX_FTM_BASEADDR,12,1
#define FSK_TX_FTM_TX_EN FSK_TX_FTM_BASEADDR,10,1
#define FSK_TX_FTM_FORCE_CARRIER_ON FSK_TX_FTM_BASEADDR,1,1
#define FSK_TX_FTM_FORCE_MARK_SPACE FSK_TX_FTM_BASEADDR,0,1
#define FSK_TX_FTM_TX_CNT_BASEADDR 0x80090018
#define FSK_TX_FTM_TX_CNT_INT FSK_TX_FTM_TX_CNT_BASEADDR,8,4
#define FSK_TX_FTM_TX_INT_EN FSK_TX_FTM_TX_CNT_BASEADDR,4,1
#define FSK_TX_FTM_TX_INT_SRC_SEL FSK_TX_FTM_TX_CNT_BASEADDR,0,2
#define AFE_REG_D2A_FSK_BIAS_BASEADDR 0x90200040
#define AFE_REG_D2A_FSK_BIAS_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,0,1
#define AFE_REG_D2A_FSK_TEST_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,10,1
#define AFE_REG_D2A_FSK_TEST_MODE AFE_REG_D2A_FSK_BIAS_BASEADDR,11,4
#define AFE_REG_D2A_FSK_TERM_INT_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,15,1
#define AFE_REG_D2A_FSK_RESETB_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,16,1
#define AFE_REG_D2A_FSK_REG_EN_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,17,1
#define AFE_REG_D2A_FSK_REG_EN_LKG_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,18,1
#define AFE_REG_D2A_FSK_REG_AMP_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,19,3
#define AFE_REG_D2A_FSK_REG_TEST_CTRL_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,22,2
#define AFE_REG_D2A_DSQ_RX_MODE AFE_REG_D2A_FSK_BIAS_BASEADDR,24,1
#define AFE_REG_D2A_DSQ_RX_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,25,1
#define AFE_REG_D2A_DSQ_HYST AFE_REG_D2A_FSK_BIAS_BASEADDR,26,2
#define AFE_REG_D2A_DSQ_RESETB_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,28,1
#define AFE_REG_D2A_FSK_CLKRX_ENA AFE_REG_D2A_FSK_BIAS_BASEADDR,29,1
#define DMD_TEI_BASEADDR 0x3FFFEBE0
#define DMD_TEI_ENA DMD_TEI_BASEADDR,0,1
#define xpt_shm_input_control0 0x90700270,0,8
#define xpt_shm_input_control1 0x90700270,8,8
#define xpt_shm_input_control2 0x90700270,16,8
#define xpt_shm_input_control3 0x90700270,24,8
#define xpt_shm_input_control4 0x90700274,0,8
#define xpt_shm_input_control5 0x90700274,8,8
#define xpt_shm_input_control6 0x90700274,16,8
#define xpt_shm_input_control7 0x90700274,24,8
#define xpt_shm_output_control0 0x90700278,0,8
#define xpt_shm_output_control1 0x90700278,8,8
#define xpt_shm_output_control2 0x90700278,16,8
#define xpt_shm_output_control3 0x90700278,24,8
#define xpt_shm_output_control4 0x9070027C,0,8
#define xpt_shm_output_control5 0x9070027C,8,8
#define xpt_shm_output_control6 0x9070027C,16,8
#define xpt_shm_output_control7 0x9070027C,24,8
#define xpt_mode_27mhz 0x90700184,0,1
#define xpt_enable_pcr_count 0x90700184,1,1
#define xcpu_ctrl_003c_reg 0x9072003C,0,4
#ifdef __cplusplus
}
#endif
#endif //__MXL58X_REGISTERS_H__

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/*
* stv0367.h
*
* Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
*
* Copyright (C) ST Microelectronics.
* Copyright (C) 2010,2011 NetUP Inc.
* Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef STV0367_H
#define STV0367_H
#include <linux/dvb/frontend.h>
#include "dvb_frontend.h"
enum stv0367_ts_mode {
STV0367_OUTPUTMODE_DEFAULT,
STV0367_SERIAL_PUNCT_CLOCK,
STV0367_SERIAL_CONT_CLOCK,
STV0367_PARALLEL_PUNCT_CLOCK,
STV0367_DVBCI_CLOCK
};
enum stv0367_clk_pol {
STV0367_CLOCKPOLARITY_DEFAULT,
STV0367_RISINGEDGE_CLOCK,
STV0367_FALLINGEDGE_CLOCK
};
struct stv0367_config {
u8 demod_address;
u32 xtal;
u32 if_khz;/*4500*/
int if_iq_mode;
int ts_mode;
int clk_pol;
};
enum stv0367_ter_if_iq_mode {
FE_TER_NORMAL_IF_TUNER = 0,
FE_TER_LONGPATH_IF_TUNER = 1,
FE_TER_IQ_TUNER = 2
};
#if defined(CONFIG_DVB_STV0367) || (defined(CONFIG_DVB_STV0367_MODULE) \
&& defined(MODULE))
extern struct
dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
struct i2c_adapter *i2c);
extern struct
dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
struct i2c_adapter *i2c);
#else
static inline struct
dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
struct i2c_adapter *i2c)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
static inline struct
dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
struct i2c_adapter *i2c)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

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/*
* stv0367_priv.h
*
* Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
*
* Copyright (C) ST Microelectronics.
* Copyright (C) 2010,2011 NetUP Inc.
* Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* Common driver error constants */
#ifndef STV0367_PRIV_H
#define STV0367_PRIV_H
#ifndef TRUE
#define TRUE (1 == 1)
#endif
#ifndef FALSE
#define FALSE (!TRUE)
#endif
#ifndef NULL
#define NULL 0
#endif
/* MACRO definitions */
#define ABS(X) ((X) < 0 ? (-1 * (X)) : (X))
#define MAX(X, Y) ((X) >= (Y) ? (X) : (Y))
#define MIN(X, Y) ((X) <= (Y) ? (X) : (Y))
#define INRANGE(X, Y, Z) \
((((X) <= (Y)) && ((Y) <= (Z))) || \
(((Z) <= (Y)) && ((Y) <= (X))) ? 1 : 0)
#ifndef MAKEWORD
#define MAKEWORD(X, Y) (((X) << 8) + (Y))
#endif
#define LSB(X) (((X) & 0xff))
#define MSB(Y) (((Y) >> 8) & 0xff)
#define MMSB(Y)(((Y) >> 16) & 0xff)
enum stv0367_ter_signal_type {
FE_TER_NOAGC = 0,
FE_TER_AGCOK = 5,
FE_TER_NOTPS = 6,
FE_TER_TPSOK = 7,
FE_TER_NOSYMBOL = 8,
FE_TER_BAD_CPQ = 9,
FE_TER_PRFOUNDOK = 10,
FE_TER_NOPRFOUND = 11,
FE_TER_LOCKOK = 12,
FE_TER_NOLOCK = 13,
FE_TER_SYMBOLOK = 15,
FE_TER_CPAMPOK = 16,
FE_TER_NOCPAMP = 17,
FE_TER_SWNOK = 18
};
enum stv0367_ter_bw {
FE_TER_CHAN_BW_6M = 6,
FE_TER_CHAN_BW_7M = 7,
FE_TER_CHAN_BW_8M = 8
};
#if 0
enum FE_TER_Rate_TPS {
FE_TER_TPS_1_2 = 0,
FE_TER_TPS_2_3 = 1,
FE_TER_TPS_3_4 = 2,
FE_TER_TPS_5_6 = 3,
FE_TER_TPS_7_8 = 4
};
#endif
enum stv0367_ter_mode {
FE_TER_MODE_2K,
FE_TER_MODE_8K,
FE_TER_MODE_4K
};
#if 0
enum FE_TER_Hierarchy_Alpha {
FE_TER_HIER_ALPHA_NONE, /* Regular modulation */
FE_TER_HIER_ALPHA_1, /* Hierarchical modulation a = 1*/
FE_TER_HIER_ALPHA_2, /* Hierarchical modulation a = 2*/
FE_TER_HIER_ALPHA_4 /* Hierarchical modulation a = 4*/
};
#endif
enum stv0367_ter_hierarchy {
FE_TER_HIER_NONE, /*Hierarchy None*/
FE_TER_HIER_LOW_PRIO, /*Hierarchy : Low Priority*/
FE_TER_HIER_HIGH_PRIO, /*Hierarchy : High Priority*/
FE_TER_HIER_PRIO_ANY /*Hierarchy :Any*/
};
#if 0
enum fe_stv0367_ter_spec {
FE_TER_INVERSION_NONE = 0,
FE_TER_INVERSION = 1,
FE_TER_INVERSION_AUTO = 2,
FE_TER_INVERSION_UNK = 4
};
#endif
#if 0
enum FE_TER_FECRate {
FE_TER_FEC_NONE = 0x00, /* no FEC rate specified */
FE_TER_FEC_ALL = 0xFF, /* Logical OR of all FECs */
FE_TER_FEC_1_2 = 1,
FE_TER_FEC_2_3 = (1 << 1),
FE_TER_FEC_3_4 = (1 << 2),
FE_TER_FEC_4_5 = (1 << 3),
FE_TER_FEC_5_6 = (1 << 4),
FE_TER_FEC_6_7 = (1 << 5),
FE_TER_FEC_7_8 = (1 << 6),
FE_TER_FEC_8_9 = (1 << 7)
};
enum FE_TER_Rate {
FE_TER_FE_1_2 = 0,
FE_TER_FE_2_3 = 1,
FE_TER_FE_3_4 = 2,
FE_TER_FE_5_6 = 3,
FE_TER_FE_6_7 = 4,
FE_TER_FE_7_8 = 5
};
#endif
enum stv0367_ter_force {
FE_TER_FORCENONE = 0,
FE_TER_FORCE_M_G = 1
};
enum stv0367cab_mod {
FE_CAB_MOD_QAM4,
FE_CAB_MOD_QAM16,
FE_CAB_MOD_QAM32,
FE_CAB_MOD_QAM64,
FE_CAB_MOD_QAM128,
FE_CAB_MOD_QAM256,
FE_CAB_MOD_QAM512,
FE_CAB_MOD_QAM1024
};
#if 0
enum {
FE_CAB_FEC_A = 1, /* J83 Annex A */
FE_CAB_FEC_B = (1 << 1),/* J83 Annex B */
FE_CAB_FEC_C = (1 << 2) /* J83 Annex C */
} FE_CAB_FECType_t;
#endif
struct stv0367_cab_signal_info {
int locked;
u32 frequency; /* kHz */
u32 symbol_rate; /* Mbds */
enum stv0367cab_mod modulation;
fe_spectral_inversion_t spect_inv;
s32 Power_dBmx10; /* Power of the RF signal (dBm x 10) */
u32 CN_dBx10; /* Carrier to noise ratio (dB x 10) */
u32 BER; /* Bit error rate (x 10000000) */
};
enum stv0367_cab_signal_type {
FE_CAB_NOTUNER,
FE_CAB_NOAGC,
FE_CAB_NOSIGNAL,
FE_CAB_NOTIMING,
FE_CAB_TIMINGOK,
FE_CAB_NOCARRIER,
FE_CAB_CARRIEROK,
FE_CAB_NOBLIND,
FE_CAB_BLINDOK,
FE_CAB_NODEMOD,
FE_CAB_DEMODOK,
FE_CAB_DATAOK
};
#endif

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#ifndef _STV0367DD_H_
#define _STV0367DD_H_
#include <linux/types.h>
#include <linux/i2c.h>
struct stv0367_cfg {
u8 adr;
u32 xtal;
u8 parallel;
u8 cont_clock;
};
extern struct dvb_frontend *stv0367_attach(struct i2c_adapter *i2c,
struct stv0367_cfg *cfg,
struct dvb_frontend **fe_t);
#endif

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/*
STV0900/0903 Multistandard Broadcast Frontend driver
Copyright (C) Manu Abraham <abraham.manu@gmail.com>
Copyright (C) ST Microelectronics
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __STV090x_H
#define __STV090x_H
enum stv090x_demodulator {
STV090x_DEMODULATOR_0 = 1,
STV090x_DEMODULATOR_1
};
enum stv090x_device {
STV0903 = 0,
STV0900,
};
enum stv090x_mode {
STV090x_DUAL = 0,
STV090x_SINGLE
};
enum stv090x_tsmode {
STV090x_TSMODE_SERIAL_PUNCTURED = 1,
STV090x_TSMODE_SERIAL_CONTINUOUS,
STV090x_TSMODE_PARALLEL_PUNCTURED,
STV090x_TSMODE_DVBCI
};
enum stv090x_clkmode {
STV090x_CLK_INT = 0, /* Clk i/p = CLKI */
STV090x_CLK_EXT = 2 /* Clk i/p = XTALI */
};
enum stv090x_i2crpt {
STV090x_RPTLEVEL_256 = 0,
STV090x_RPTLEVEL_128 = 1,
STV090x_RPTLEVEL_64 = 2,
STV090x_RPTLEVEL_32 = 3,
STV090x_RPTLEVEL_16 = 4,
STV090x_RPTLEVEL_8 = 5,
STV090x_RPTLEVEL_4 = 6,
STV090x_RPTLEVEL_2 = 7,
};
enum stv090x_adc_range {
STV090x_ADC_2Vpp = 0,
STV090x_ADC_1Vpp = 1
};
struct stv090x_config {
enum stv090x_device device;
enum stv090x_mode demod_mode;
enum stv090x_clkmode clk_mode;
u32 xtal; /* default: 8000000 */
u8 address; /* default: 0x68 */
u8 ts1_mode;
u8 ts2_mode;
u32 ts1_clk;
u32 ts2_clk;
u8 ts1_tei : 1;
u8 ts2_tei : 1;
enum stv090x_i2crpt repeater_level;
u8 tuner_bbgain; /* default: 10db */
enum stv090x_adc_range adc1_range; /* default: 2Vpp */
enum stv090x_adc_range adc2_range; /* default: 2Vpp */
bool diseqc_envelope_mode;
int (*tuner_init) (struct dvb_frontend *fe);
int (*tuner_sleep) (struct dvb_frontend *fe);
int (*tuner_set_mode) (struct dvb_frontend *fe, enum tuner_mode mode);
int (*tuner_set_frequency) (struct dvb_frontend *fe, u32 frequency);
int (*tuner_get_frequency) (struct dvb_frontend *fe, u32 *frequency);
int (*tuner_set_bandwidth) (struct dvb_frontend *fe, u32 bandwidth);
int (*tuner_get_bandwidth) (struct dvb_frontend *fe, u32 *bandwidth);
int (*tuner_set_bbgain) (struct dvb_frontend *fe, u32 gain);
int (*tuner_get_bbgain) (struct dvb_frontend *fe, u32 *gain);
int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk);
int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status);
void (*tuner_i2c_lock) (struct dvb_frontend *fe, int lock);
};
#if defined(CONFIG_DVB_STV090x) || (defined(CONFIG_DVB_STV090x_MODULE) && defined(MODULE))
extern struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
struct i2c_adapter *i2c,
enum stv090x_demodulator demod);
/* dir = 0 -> output, dir = 1 -> input/open-drain */
extern int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio,
u8 dir, u8 value, u8 xor_value);
#else
static inline struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
struct i2c_adapter *i2c,
enum stv090x_demodulator demod)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
static inline int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio,
u8 opd, u8 value, u8 xor_value)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return -ENODEV;
}
#endif /* CONFIG_DVB_STV090x */
#endif /* __STV090x_H */

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/*
STV0900/0903 Multistandard Broadcast Frontend driver
Copyright (C) Manu Abraham <abraham.manu@gmail.com>
Copyright (C) ST Microelectronics
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __STV090x_PRIV_H
#define __STV090x_PRIV_H
#include "dvb_frontend.h"
#define FE_ERROR 0
#define FE_NOTICE 1
#define FE_INFO 2
#define FE_DEBUG 3
#define FE_DEBUGREG 4
#define dprintk(__y, __z, format, arg...) do { \
if (__z) { \
if ((verbose > FE_ERROR) && (verbose > __y)) \
printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \
else if ((verbose > FE_NOTICE) && (verbose > __y)) \
printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \
else if ((verbose > FE_INFO) && (verbose > __y)) \
printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \
else if ((verbose > FE_DEBUG) && (verbose > __y)) \
printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \
} else { \
if (verbose > __y) \
printk(format, ##arg); \
} \
} while (0)
#define STV090x_READ_DEMOD(__state, __reg) (( \
(__state)->demod == STV090x_DEMODULATOR_1) ? \
stv090x_read_reg(__state, STV090x_P2_##__reg) : \
stv090x_read_reg(__state, STV090x_P1_##__reg))
#define STV090x_WRITE_DEMOD(__state, __reg, __data) (( \
(__state)->demod == STV090x_DEMODULATOR_1) ? \
stv090x_write_reg(__state, STV090x_P2_##__reg, __data) :\
stv090x_write_reg(__state, STV090x_P1_##__reg, __data))
#define STV090x_ADDR_OFFST(__state, __x) (( \
(__state->demod) == STV090x_DEMODULATOR_1) ? \
STV090x_P1_##__x : \
STV090x_P2_##__x)
#define STV090x_SETFIELD(mask, bitf, val) (mask = (mask & (~(((1 << STV090x_WIDTH_##bitf) - 1) <<\
STV090x_OFFST_##bitf))) | \
(val << STV090x_OFFST_##bitf))
#define STV090x_GETFIELD(val, bitf) ((val >> STV090x_OFFST_##bitf) & ((1 << STV090x_WIDTH_##bitf) - 1))
#define STV090x_SETFIELD_Px(mask, bitf, val) (mask = (mask & (~(((1 << STV090x_WIDTH_Px_##bitf) - 1) <<\
STV090x_OFFST_Px_##bitf))) | \
(val << STV090x_OFFST_Px_##bitf))
#define STV090x_GETFIELD_Px(val, bitf) ((val >> STV090x_OFFST_Px_##bitf) & ((1 << STV090x_WIDTH_Px_##bitf) - 1))
#define MAKEWORD16(__a, __b) (((__a) << 8) | (__b))
#define MSB(__x) ((__x >> 8) & 0xff)
#define LSB(__x) (__x & 0xff)
#define STV090x_IQPOWER_THRESHOLD 30
#define STV090x_SEARCH_AGC2_TH_CUT20 700
#define STV090x_SEARCH_AGC2_TH_CUT30 1400
#define STV090x_SEARCH_AGC2_TH(__ver) \
((__ver <= 0x20) ? \
STV090x_SEARCH_AGC2_TH_CUT20 : \
STV090x_SEARCH_AGC2_TH_CUT30)
enum stv090x_signal_state {
STV090x_NOAGC1,
STV090x_NOCARRIER,
STV090x_NODATA,
STV090x_DATAOK,
STV090x_RANGEOK,
STV090x_OUTOFRANGE
};
enum stv090x_fec {
STV090x_PR12 = 0,
STV090x_PR23,
STV090x_PR34,
STV090x_PR45,
STV090x_PR56,
STV090x_PR67,
STV090x_PR78,
STV090x_PR89,
STV090x_PR910,
STV090x_PRERR
};
enum stv090x_modulation {
STV090x_QPSK,
STV090x_8PSK,
STV090x_16APSK,
STV090x_32APSK,
STV090x_UNKNOWN
};
enum stv090x_frame {
STV090x_LONG_FRAME,
STV090x_SHORT_FRAME
};
enum stv090x_pilot {
STV090x_PILOTS_OFF,
STV090x_PILOTS_ON
};
enum stv090x_rolloff {
STV090x_RO_35,
STV090x_RO_25,
STV090x_RO_20
};
enum stv090x_inversion {
STV090x_IQ_AUTO,
STV090x_IQ_NORMAL,
STV090x_IQ_SWAP
};
enum stv090x_modcod {
STV090x_DUMMY_PLF = 0,
STV090x_QPSK_14,
STV090x_QPSK_13,
STV090x_QPSK_25,
STV090x_QPSK_12,
STV090x_QPSK_35,
STV090x_QPSK_23,
STV090x_QPSK_34,
STV090x_QPSK_45,
STV090x_QPSK_56,
STV090x_QPSK_89,
STV090x_QPSK_910,
STV090x_8PSK_35,
STV090x_8PSK_23,
STV090x_8PSK_34,
STV090x_8PSK_56,
STV090x_8PSK_89,
STV090x_8PSK_910,
STV090x_16APSK_23,
STV090x_16APSK_34,
STV090x_16APSK_45,
STV090x_16APSK_56,
STV090x_16APSK_89,
STV090x_16APSK_910,
STV090x_32APSK_34,
STV090x_32APSK_45,
STV090x_32APSK_56,
STV090x_32APSK_89,
STV090x_32APSK_910,
STV090x_MODCODE_UNKNOWN
};
enum stv090x_search {
STV090x_SEARCH_DSS = 0,
STV090x_SEARCH_DVBS1,
STV090x_SEARCH_DVBS2,
STV090x_SEARCH_AUTO
};
enum stv090x_algo {
STV090x_BLIND_SEARCH,
STV090x_COLD_SEARCH,
STV090x_WARM_SEARCH
};
enum stv090x_delsys {
STV090x_ERROR = 0,
STV090x_DVBS1 = 1,
STV090x_DVBS2,
STV090x_DSS
};
struct stv090x_long_frame_crloop {
enum stv090x_modcod modcod;
u8 crl_pilots_on_2;
u8 crl_pilots_off_2;
u8 crl_pilots_on_5;
u8 crl_pilots_off_5;
u8 crl_pilots_on_10;
u8 crl_pilots_off_10;
u8 crl_pilots_on_20;
u8 crl_pilots_off_20;
u8 crl_pilots_on_30;
u8 crl_pilots_off_30;
};
struct stv090x_short_frame_crloop {
enum stv090x_modulation modulation;
u8 crl_2; /* SR < 3M */
u8 crl_5; /* 3 < SR <= 7M */
u8 crl_10; /* 7 < SR <= 15M */
u8 crl_20; /* 10 < SR <= 25M */
u8 crl_30; /* 10 < SR <= 45M */
};
struct stv090x_reg {
u16 addr;
u8 data;
};
struct stv090x_tab {
s32 real;
s32 read;
};
struct stv090x_internal {
struct i2c_adapter *i2c_adap;
u8 i2c_addr;
struct mutex demod_lock; /* Lock access to shared register */
struct mutex tuner_lock; /* Lock access to tuners */
s32 mclk; /* Masterclock Divider factor */
u32 dev_ver;
int num_used;
};
struct stv090x_state {
enum stv090x_device device;
enum stv090x_demodulator demod;
enum stv090x_mode demod_mode;
struct stv090x_internal *internal;
struct i2c_adapter *i2c;
const struct stv090x_config *config;
struct dvb_frontend frontend;
u32 *verbose; /* Cached module verbosity */
enum stv090x_delsys delsys;
enum stv090x_fec fec;
enum stv090x_modulation modulation;
enum stv090x_modcod modcod;
enum stv090x_search search_mode;
enum stv090x_frame frame_len;
enum stv090x_pilot pilots;
enum stv090x_rolloff rolloff;
enum stv090x_inversion inversion;
enum stv090x_algo algo;
u32 frequency;
u32 srate;
s32 tuner_bw;
s32 search_range;
s32 DemodTimeout;
s32 FecTimeout;
};
#endif /* __STV090x_PRIV_H */

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1406
frontends/stv0910.c Normal file
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31
frontends/stv0910.h Normal file
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@@ -0,0 +1,31 @@
#ifndef _STV0910_H_
#define _STV0910_H_
#include <linux/types.h>
#include <linux/i2c.h>
struct stv0910_cfg {
u32 clk;
u8 adr;
u8 parallel;
u8 rptlvl;
};
#if defined(CONFIG_DVB_STV0910) || \
(defined(CONFIG_DVB_STV0910_MODULE) && defined(MODULE))
extern struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c,
struct stv0910_cfg *cfg, int nr);
#else
static inline struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c,
struct stv0910_cfg *cfg,
int nr)
{
pr_warn("%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

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/*
STV6110(A) Silicon tuner driver
Copyright (C) Manu Abraham <abraham.manu@gmail.com>
Copyright (C) ST Microelectronics
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/string.h>
#include "dvb_frontend.h"
#include "stv6110x_reg.h"
#include "stv6110x.h"
#include "stv6110x_priv.h"
static unsigned int verbose;
module_param(verbose, int, 0644);
MODULE_PARM_DESC(verbose, "Set Verbosity level");
static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data)
{
int ret;
const struct stv6110x_config *config = stv6110x->config;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {
{ .addr = config->addr, .flags = 0, .buf = b0, .len = 1 },
{ .addr = config->addr, .flags = I2C_M_RD, .buf = b1, .len = 1 }
};
ret = i2c_transfer(stv6110x->i2c, msg, 2);
if (ret != 2) {
dprintk(FE_ERROR, 1, "I/O Error");
return -EREMOTEIO;
}
*data = b1[0];
return 0;
}
static int stv6110x_write_regs(struct stv6110x_state *stv6110x, int start, u8 data[], int len)
{
int ret;
const struct stv6110x_config *config = stv6110x->config;
u8 buf[len + 1];
struct i2c_msg msg = {
.addr = config->addr,
.flags = 0,
.buf = buf,
.len = len + 1
};
if (start + len > 8)
return -EINVAL;
buf[0] = start;
memcpy(&buf[1], data, len);
ret = i2c_transfer(stv6110x->i2c, &msg, 1);
if (ret != 1) {
dprintk(FE_ERROR, 1, "I/O Error");
return -EREMOTEIO;
}
return 0;
}
static int stv6110x_write_reg(struct stv6110x_state *stv6110x, u8 reg, u8 data)
{
return stv6110x_write_regs(stv6110x, reg, &data, 1);
}
static int stv6110x_init(struct dvb_frontend *fe)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
int ret;
ret = stv6110x_write_regs(stv6110x, 0, stv6110x->regs,
ARRAY_SIZE(stv6110x->regs));
if (ret < 0) {
dprintk(FE_ERROR, 1, "Initialization failed");
return -1;
}
return 0;
}
static int stv6110x_set_frequency(struct dvb_frontend *fe, u32 frequency)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
u32 rDiv, divider;
s32 pVal, pCalc, rDivOpt = 0, pCalcOpt = 1000;
u8 i;
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_K, (REFCLOCK_MHz - 16));
if (frequency <= 1023000) {
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 1);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0);
pVal = 40;
} else if (frequency <= 1300000) {
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 1);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1);
pVal = 40;
} else if (frequency <= 2046000) {
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 0);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0);
pVal = 20;
} else {
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_DIV4SEL, 0);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1);
pVal = 20;
}
for (rDiv = 0; rDiv <= 3; rDiv++) {
pCalc = (REFCLOCK_kHz / 100) / R_DIV(rDiv);
if ((abs((s32)(pCalc - pVal))) < (abs((s32)(pCalcOpt - pVal))))
rDivOpt = rDiv;
pCalcOpt = (REFCLOCK_kHz / 100) / R_DIV(rDivOpt);
}
divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz;
divider = (divider + 5) / 10;
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_R_DIV, rDivOpt);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_N_DIV_11_8, MSB(divider));
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG0], TNG0_N_DIV_7_0, LSB(divider));
/* VCO Auto calibration */
STV6110x_SETFIELD(stv6110x->regs[STV6110x_STAT1], STAT1_CALVCO_STRT, 1);
stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x->regs[STV6110x_CTRL1]);
stv6110x_write_reg(stv6110x, STV6110x_TNG1, stv6110x->regs[STV6110x_TNG1]);
stv6110x_write_reg(stv6110x, STV6110x_TNG0, stv6110x->regs[STV6110x_TNG0]);
stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x->regs[STV6110x_STAT1]);
for (i = 0; i < TRIALS; i++) {
stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]);
if (!STV6110x_GETFIELD(STAT1_CALVCO_STRT, stv6110x->regs[STV6110x_STAT1]))
break;
msleep(1);
}
return 0;
}
static int stv6110x_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
stv6110x_read_reg(stv6110x, STV6110x_TNG1, &stv6110x->regs[STV6110x_TNG1]);
stv6110x_read_reg(stv6110x, STV6110x_TNG0, &stv6110x->regs[STV6110x_TNG0]);
*frequency = (MAKEWORD16(STV6110x_GETFIELD(TNG1_N_DIV_11_8, stv6110x->regs[STV6110x_TNG1]),
STV6110x_GETFIELD(TNG0_N_DIV_7_0, stv6110x->regs[STV6110x_TNG0]))) * REFCLOCK_kHz;
*frequency /= (1 << (STV6110x_GETFIELD(TNG1_R_DIV, stv6110x->regs[STV6110x_TNG1]) +
STV6110x_GETFIELD(TNG1_DIV4SEL, stv6110x->regs[STV6110x_TNG1])));
*frequency >>= 2;
return 0;
}
static int stv6110x_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
u32 halfbw;
u8 i;
halfbw = bandwidth >> 1;
if (halfbw > 36000000)
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, 31); /* LPF */
else if (halfbw < 5000000)
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, 0); /* LPF */
else
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_CF, ((halfbw / 1000000) - 5)); /* LPF */
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x0); /* cal. clk activated */
STV6110x_SETFIELD(stv6110x->regs[STV6110x_STAT1], STAT1_CALRC_STRT, 0x1); /* LPF auto cal */
stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x->regs[STV6110x_CTRL3]);
stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x->regs[STV6110x_STAT1]);
for (i = 0; i < TRIALS; i++) {
stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]);
if (!STV6110x_GETFIELD(STAT1_CALRC_STRT, stv6110x->regs[STV6110x_STAT1]))
break;
msleep(1);
}
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x1); /* cal. done */
stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x->regs[STV6110x_CTRL3]);
return 0;
}
static int stv6110x_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
stv6110x_read_reg(stv6110x, STV6110x_CTRL3, &stv6110x->regs[STV6110x_CTRL3]);
*bandwidth = (STV6110x_GETFIELD(CTRL3_CF, stv6110x->regs[STV6110x_CTRL3]) + 5) * 2000000;
return 0;
}
static int stv6110x_set_refclock(struct dvb_frontend *fe, u32 refclock)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
/* setup divider */
switch (refclock) {
default:
case 1:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 0);
break;
case 2:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 1);
break;
case 4:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 2);
break;
case 8:
case 0:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 3);
break;
}
stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x->regs[STV6110x_CTRL2]);
return 0;
}
static int stv6110x_get_bbgain(struct dvb_frontend *fe, u32 *gain)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
stv6110x_read_reg(stv6110x, STV6110x_CTRL2, &stv6110x->regs[STV6110x_CTRL2]);
*gain = 2 * STV6110x_GETFIELD(CTRL2_BBGAIN, stv6110x->regs[STV6110x_CTRL2]);
return 0;
}
static int stv6110x_set_bbgain(struct dvb_frontend *fe, u32 gain)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_BBGAIN, gain / 2);
stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x->regs[STV6110x_CTRL2]);
return 0;
}
static int stv6110x_set_mode(struct dvb_frontend *fe, enum tuner_mode mode)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
int ret;
switch (mode) {
case TUNER_SLEEP:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_SYN, 0);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_RX, 0);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_LPT, 0);
break;
case TUNER_WAKE:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_SYN, 1);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_RX, 1);
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL1], CTRL1_LPT, 1);
break;
}
ret = stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x->regs[STV6110x_CTRL1]);
if (ret < 0) {
dprintk(FE_ERROR, 1, "I/O Error");
return -EIO;
}
return 0;
}
static int stv6110x_sleep(struct dvb_frontend *fe)
{
if (fe->tuner_priv)
return stv6110x_set_mode(fe, TUNER_SLEEP);
return 0;
}
static int stv6110x_get_status(struct dvb_frontend *fe, u32 *status)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x->regs[STV6110x_STAT1]);
if (STV6110x_GETFIELD(STAT1_LOCK, stv6110x->regs[STV6110x_STAT1]))
*status = TUNER_PHASELOCKED;
else
*status = 0;
return 0;
}
static int stv6110x_release(struct dvb_frontend *fe)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
fe->tuner_priv = NULL;
kfree(stv6110x);
return 0;
}
static struct dvb_tuner_ops stv6110x_ops = {
.info = {
.name = "STV6110(A) Silicon Tuner",
.frequency_min = 950000,
.frequency_max = 2150000,
.frequency_step = 0,
},
.release = stv6110x_release
};
static struct stv6110x_devctl stv6110x_ctl = {
.tuner_init = stv6110x_init,
.tuner_sleep = stv6110x_sleep,
.tuner_set_mode = stv6110x_set_mode,
.tuner_set_frequency = stv6110x_set_frequency,
.tuner_get_frequency = stv6110x_get_frequency,
.tuner_set_bandwidth = stv6110x_set_bandwidth,
.tuner_get_bandwidth = stv6110x_get_bandwidth,
.tuner_set_bbgain = stv6110x_set_bbgain,
.tuner_get_bbgain = stv6110x_get_bbgain,
.tuner_set_refclk = stv6110x_set_refclock,
.tuner_get_status = stv6110x_get_status,
};
struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
const struct stv6110x_config *config,
struct i2c_adapter *i2c)
{
struct stv6110x_state *stv6110x;
u8 default_regs[] = {0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e};
stv6110x = kzalloc(sizeof (struct stv6110x_state), GFP_KERNEL);
if (!stv6110x)
return NULL;
stv6110x->i2c = i2c;
stv6110x->config = config;
stv6110x->devctl = &stv6110x_ctl;
memcpy(stv6110x->regs, default_regs, 8);
/* setup divider */
switch (stv6110x->config->clk_div) {
default:
case 1:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 0);
break;
case 2:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 1);
break;
case 4:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 2);
break;
case 8:
case 0:
STV6110x_SETFIELD(stv6110x->regs[STV6110x_CTRL2], CTRL2_CO_DIV, 3);
break;
}
fe->tuner_priv = stv6110x;
fe->ops.tuner_ops = stv6110x_ops;
printk(KERN_INFO "%s: Attaching STV6110x\n", __func__);
return stv6110x->devctl;
}
EXPORT_SYMBOL(stv6110x_attach);
MODULE_AUTHOR("Manu Abraham");
MODULE_DESCRIPTION("STV6110x Silicon tuner");
MODULE_LICENSE("GPL");

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/*
STV6110(A) Silicon tuner driver
Copyright (C) Manu Abraham <abraham.manu@gmail.com>
Copyright (C) ST Microelectronics
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __STV6110x_H
#define __STV6110x_H
struct stv6110x_config {
u8 addr;
u32 refclk;
u8 clk_div; /* divisor value for the output clock */
};
enum tuner_mode {
TUNER_SLEEP = 1,
TUNER_WAKE,
};
enum tuner_status {
TUNER_PHASELOCKED = 1,
};
struct stv6110x_devctl {
int (*tuner_init) (struct dvb_frontend *fe);
int (*tuner_sleep) (struct dvb_frontend *fe);
int (*tuner_set_mode) (struct dvb_frontend *fe, enum tuner_mode mode);
int (*tuner_set_frequency) (struct dvb_frontend *fe, u32 frequency);
int (*tuner_get_frequency) (struct dvb_frontend *fe, u32 *frequency);
int (*tuner_set_bandwidth) (struct dvb_frontend *fe, u32 bandwidth);
int (*tuner_get_bandwidth) (struct dvb_frontend *fe, u32 *bandwidth);
int (*tuner_set_bbgain) (struct dvb_frontend *fe, u32 gain);
int (*tuner_get_bbgain) (struct dvb_frontend *fe, u32 *gain);
int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk);
int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status);
};
#if defined(CONFIG_DVB_STV6110x) || (defined(CONFIG_DVB_STV6110x_MODULE) && defined(MODULE))
extern struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
const struct stv6110x_config *config,
struct i2c_adapter *i2c);
#else
static inline struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
const struct stv6110x_config *config,
struct i2c_adapter *i2c)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif /* CONFIG_DVB_STV6110x */
#endif /* __STV6110x_H */

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/*
STV6110(A) Silicon tuner driver
Copyright (C) Manu Abraham <abraham.manu@gmail.com>
Copyright (C) ST Microelectronics
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __STV6110x_PRIV_H
#define __STV6110x_PRIV_H
#define FE_ERROR 0
#define FE_NOTICE 1
#define FE_INFO 2
#define FE_DEBUG 3
#define FE_DEBUGREG 4
#define dprintk(__y, __z, format, arg...) do { \
if (__z) { \
if ((verbose > FE_ERROR) && (verbose > __y)) \
printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \
else if ((verbose > FE_NOTICE) && (verbose > __y)) \
printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \
else if ((verbose > FE_INFO) && (verbose > __y)) \
printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \
else if ((verbose > FE_DEBUG) && (verbose > __y)) \
printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \
} else { \
if (verbose > __y) \
printk(format, ##arg); \
} \
} while (0)
#define STV6110x_SETFIELD(mask, bitf, val) \
(mask = (mask & (~(((1 << STV6110x_WIDTH_##bitf) - 1) << \
STV6110x_OFFST_##bitf))) | \
(val << STV6110x_OFFST_##bitf))
#define STV6110x_GETFIELD(bitf, val) \
((val >> STV6110x_OFFST_##bitf) & \
((1 << STV6110x_WIDTH_##bitf) - 1))
#define MAKEWORD16(a, b) (((a) << 8) | (b))
#define LSB(x) ((x & 0xff))
#define MSB(y) ((y >> 8) & 0xff)
#define TRIALS 10
#define R_DIV(__div) (1 << (__div + 1))
#define REFCLOCK_kHz (stv6110x->config->refclk / 1000)
#define REFCLOCK_MHz (stv6110x->config->refclk / 1000000)
struct stv6110x_state {
struct i2c_adapter *i2c;
const struct stv6110x_config *config;
u8 regs[8];
struct stv6110x_devctl *devctl;
};
#endif /* __STV6110x_PRIV_H */

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/*
STV6110(A) Silicon tuner driver
Copyright (C) Manu Abraham <abraham.manu@gmail.com>
Copyright (C) ST Microelectronics
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __STV6110x_REG_H
#define __STV6110x_REG_H
#define STV6110x_CTRL1 0x00
#define STV6110x_OFFST_CTRL1_K 3
#define STV6110x_WIDTH_CTRL1_K 5
#define STV6110x_OFFST_CTRL1_LPT 2
#define STV6110x_WIDTH_CTRL1_LPT 1
#define STV6110x_OFFST_CTRL1_RX 1
#define STV6110x_WIDTH_CTRL1_RX 1
#define STV6110x_OFFST_CTRL1_SYN 0
#define STV6110x_WIDTH_CTRL1_SYN 1
#define STV6110x_CTRL2 0x01
#define STV6110x_OFFST_CTRL2_CO_DIV 6
#define STV6110x_WIDTH_CTRL2_CO_DIV 2
#define STV6110x_OFFST_CTRL2_RSVD 5
#define STV6110x_WIDTH_CTRL2_RSVD 1
#define STV6110x_OFFST_CTRL2_REFOUT_SEL 4
#define STV6110x_WIDTH_CTRL2_REFOUT_SEL 1
#define STV6110x_OFFST_CTRL2_BBGAIN 0
#define STV6110x_WIDTH_CTRL2_BBGAIN 4
#define STV6110x_TNG0 0x02
#define STV6110x_OFFST_TNG0_N_DIV_7_0 0
#define STV6110x_WIDTH_TNG0_N_DIV_7_0 8
#define STV6110x_TNG1 0x03
#define STV6110x_OFFST_TNG1_R_DIV 6
#define STV6110x_WIDTH_TNG1_R_DIV 2
#define STV6110x_OFFST_TNG1_PRESC32_ON 5
#define STV6110x_WIDTH_TNG1_PRESC32_ON 1
#define STV6110x_OFFST_TNG1_DIV4SEL 4
#define STV6110x_WIDTH_TNG1_DIV4SEL 1
#define STV6110x_OFFST_TNG1_N_DIV_11_8 0
#define STV6110x_WIDTH_TNG1_N_DIV_11_8 4
#define STV6110x_CTRL3 0x04
#define STV6110x_OFFST_CTRL3_DCLOOP_OFF 7
#define STV6110x_WIDTH_CTRL3_DCLOOP_OFF 1
#define STV6110x_OFFST_CTRL3_RCCLK_OFF 6
#define STV6110x_WIDTH_CTRL3_RCCLK_OFF 1
#define STV6110x_OFFST_CTRL3_ICP 5
#define STV6110x_WIDTH_CTRL3_ICP 1
#define STV6110x_OFFST_CTRL3_CF 0
#define STV6110x_WIDTH_CTRL3_CF 5
#define STV6110x_STAT1 0x05
#define STV6110x_OFFST_STAT1_CALVCO_STRT 2
#define STV6110x_WIDTH_STAT1_CALVCO_STRT 1
#define STV6110x_OFFST_STAT1_CALRC_STRT 1
#define STV6110x_WIDTH_STAT1_CALRC_STRT 1
#define STV6110x_OFFST_STAT1_LOCK 0
#define STV6110x_WIDTH_STAT1_LOCK 1
#define STV6110x_STAT2 0x06
#define STV6110x_STAT3 0x07
#endif /* __STV6110x_REG_H */

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/*
* Driver for the ST STV6111 tuner
*
* Copyright (C) 2014 Digital Devices GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA
* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <linux/version.h>
#include <asm/div64.h>
#include "dvb_frontend.h"
static inline u32 MulDiv32(u32 a, u32 b, u32 c)
{
u64 tmp64;
tmp64 = (u64)a * (u64)b;
do_div(tmp64, c);
return (u32) tmp64;
}
struct stv {
struct i2c_adapter *i2c;
u8 adr;
u8 reg[11];
u32 ref_freq;
};
static int i2c_read(struct i2c_adapter *adap,
u8 adr, u8 *msg, int len, u8 *answ, int alen)
{
struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0,
.buf = msg, .len = len},
{ .addr = adr, .flags = I2C_M_RD,
.buf = answ, .len = alen } };
if (i2c_transfer(adap, msgs, 2) != 2) {
pr_err("stv6111: i2c_read error\n");
return -1;
}
return 0;
}
static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
{
struct i2c_msg msg = {.addr = adr, .flags = 0,
.buf = data, .len = len};
if (i2c_transfer(adap, &msg, 1) != 1) {
pr_err("stv6111: i2c_write error\n");
return -1;
}
return 0;
}
static int write_regs(struct stv *state, int reg, int len)
{
u8 d[12];
memcpy(&d[1], &state->reg[reg], len);
d[0] = reg;
return i2c_write(state->i2c, state->adr, d, len + 1);
}
#if 0
static int write_reg(struct stv *state, u8 reg, u8 val)
{
u8 d[2] = {reg, val};
return i2c_write(state->i2c, state->adr, d, 2);
}
#endif
static int read_reg(struct stv *state, u8 reg, u8 *val)
{
return i2c_read(state->i2c, state->adr, &reg, 1, val, 1);
}
static int read_regs(struct stv *state, u8 reg, u8 *val, int len)
{
return i2c_read(state->i2c, state->adr, &reg, 1, val, len);
}
static void dump_regs(struct stv *state)
{
u8 d[11], *c = &state->reg[0];
read_regs(state, 0, d, 11);
#if 0
pr_info("stv6111_regs = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7],
d[8], d[9], d[10]);
pr_info("reg[] = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7],
c[8], c[9], c[10]);
#endif
}
static int wait_for_call_done(struct stv *state, u8 mask)
{
int status = 0;
u32 LockRetryCount = 10;
while (LockRetryCount > 0) {
u8 Status;
status = read_reg(state, 9, &Status);
if (status < 0)
return status;
if ((Status & mask) == 0)
break;
usleep_range(4000, 6000);
LockRetryCount -= 1;
status = -1;
}
return status;
}
static void init_state(struct stv *state)
{
u32 clkdiv = 0;
u32 agcmode = 0;
u32 agcref = 2;
u32 agcset = 0xffffffff;
u32 bbmode = 0xffffffff;
state->reg[0] = 0x08;
state->reg[1] = 0x41;
state->reg[2] = 0x8f;
state->reg[3] = 0x00;
state->reg[4] = 0xce;
state->reg[5] = 0x54;
state->reg[6] = 0x55;
state->reg[7] = 0x45;
state->reg[8] = 0x46;
state->reg[9] = 0xbd;
state->reg[10] = 0x11;
state->ref_freq = 16000;
if (clkdiv <= 3)
state->reg[0x00] |= (clkdiv & 0x03);
if (agcmode <= 3) {
state->reg[0x03] |= (agcmode << 5);
if (agcmode == 0x01)
state->reg[0x01] |= 0x30;
}
if (bbmode <= 3)
state->reg[0x01] = (state->reg[0x01] & ~0x30) | (bbmode << 4);
if (agcref <= 7)
state->reg[0x03] |= agcref;
if (agcset <= 31)
state->reg[0x02] = (state->reg[0x02] & ~0x1F) | agcset | 0x40;
}
static int attach_init(struct stv *state)
{
if (write_regs(state, 0, 11))
return -1;
dump_regs(state);
return 0;
}
static int sleep(struct dvb_frontend *fe)
{
/* struct tda_state *state = fe->tuner_priv; */
return 0;
}
static int init(struct dvb_frontend *fe)
{
/* struct tda_state *state = fe->tuner_priv; */
return 0;
}
static int release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static int set_bandwidth(struct dvb_frontend *fe, u32 CutOffFrequency)
{
struct stv *state = fe->tuner_priv;
u32 index = (CutOffFrequency + 999999) / 1000000;
if (index < 6)
index = 6;
if (index > 50)
index = 50;
if ((state->reg[0x08] & ~0xFC) == ((index-6) << 2))
return 0;
state->reg[0x08] = (state->reg[0x08] & ~0xFC) | ((index-6) << 2);
state->reg[0x09] = (state->reg[0x09] & ~0x0C) | 0x08;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
write_regs(state, 0x08, 2);
wait_for_call_done(state, 0x08);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return 0;
}
static int set_lof(struct stv *state, u32 LocalFrequency, u32 CutOffFrequency)
{
u32 index = (CutOffFrequency + 999999) / 1000000;
u32 Frequency = (LocalFrequency + 500) / 1000;
u32 p = 1, psel = 0, fvco, div, frac;
u8 Icp, tmp;
/* pr_info("F = %u, COF = %u\n", Frequency, CutOffFrequency); */
if (index < 6)
index = 6;
if (index > 50)
index = 50;
if (Frequency <= 1300000) {
p = 4;
psel = 1;
} else {
p = 2;
psel = 0;
}
fvco = Frequency * p;
div = fvco / state->ref_freq;
frac = fvco % state->ref_freq;
frac = MulDiv32(frac, 0x40000, state->ref_freq);
Icp = 0;
if (fvco < 2700000)
Icp = 0;
else if (fvco < 2950000)
Icp = 1;
else if (fvco < 3300000)
Icp = 2;
else if (fvco < 3700000)
Icp = 3;
else if (fvco < 4200000)
Icp = 5;
else if (fvco < 4800000)
Icp = 6;
else
Icp = 7;
state->reg[0x02] |= 0x80; /* LNA IIP3 Mode */
state->reg[0x03] = (state->reg[0x03] & ~0x80) | (psel << 7);
state->reg[0x04] = (div & 0xFF);
state->reg[0x05] = (((div >> 8) & 0x01) | ((frac & 0x7F) << 1)) & 0xff;
state->reg[0x06] = ((frac >> 7) & 0xFF);
state->reg[0x07] = (state->reg[0x07] & ~0x07) | ((frac >> 15) & 0x07);
state->reg[0x07] = (state->reg[0x07] & ~0xE0) | (Icp << 5);
state->reg[0x08] = (state->reg[0x08] & ~0xFC) | ((index - 6) << 2);
/* Start cal vco,CF */
state->reg[0x09] = (state->reg[0x09] & ~0x0C) | 0x0C;
write_regs(state, 2, 8);
wait_for_call_done(state, 0x0C);
usleep_range(10000, 12000);
read_reg(state, 0x03, &tmp);
if (tmp & 0x10) {
state->reg[0x02] &= ~0x80; /* LNA NF Mode */
write_regs(state, 2, 1);
}
read_reg(state, 0x08, &tmp);
dump_regs(state);
return 0;
}
static int set_params(struct dvb_frontend *fe)
{
struct stv *state = fe->tuner_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
int status;
u32 freq, symb, cutoff;
if (p->delivery_system != SYS_DVBS && p->delivery_system != SYS_DVBS2)
return -EINVAL;
freq = p->frequency * 1000;
symb = p->symbol_rate;
cutoff = 5000000 + MulDiv32(p->symbol_rate, 135, 200);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
set_lof(state, freq, cutoff);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return status;
}
static int get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
*frequency = 0;
return 0;
}
static u32 AGC_Gain[] = {
000, /* 0.0 */
000, /* 0.1 */
1000, /* 0.2 */
2000, /* 0.3 */
3000, /* 0.4 */
4000, /* 0.5 */
5000, /* 0.6 */
6000, /* 0.7 */
7000, /* 0.8 */
14000, /* 0.9 */
20000, /* 1.0 */
27000, /* 1.1 */
32000, /* 1.2 */
37000, /* 1.3 */
42000, /* 1.4 */
47000, /* 1.5 */
50000, /* 1.6 */
53000, /* 1.7 */
56000, /* 1.8 */
58000, /* 1.9 */
60000, /* 2.0 */
62000, /* 2.1 */
63000, /* 2.2 */
64000, /* 2.3 */
64500, /* 2.4 */
65000, /* 2.5 */
65500, /* 2.6 */
66000, /* 2.7 */
66500, /* 2.8 */
67000, /* 2.9 */
};
static int get_rf_strength(struct dvb_frontend *fe, u16 *st)
{
*st = 0;
#if 0
struct stv *state = fe->tuner_priv;
s32 Gain;
u32 Index = RFAgc / 100;
if (Index >= (sizeof(AGC_Gain) / sizeof(AGC_Gain[0]) - 1))
Gain = AGC_Gain[sizeof(AGC_Gain) / sizeof(AGC_Gain[0]) - 1];
else
Gain = AGC_Gain[Index] +
((AGC_Gain[Index+1] - AGC_Gain[Index]) *
(RFAgc % 100)) / 100;
*st = Gain;
#endif
return 0;
}
static int get_if(struct dvb_frontend *fe, u32 *frequency)
{
*frequency = 0;
return 0;
}
static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
return 0;
}
static struct dvb_tuner_ops tuner_ops = {
.info = {
.name = "STV6111",
.frequency_min = 950000,
.frequency_max = 2150000,
.frequency_step = 0
},
.init = init,
.sleep = sleep,
.set_params = set_params,
.release = release,
.get_frequency = get_frequency,
.get_if_frequency = get_if,
.get_bandwidth = get_bandwidth,
.get_rf_strength = get_rf_strength,
.set_bandwidth = set_bandwidth,
};
struct dvb_frontend *stv6111_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 adr)
{
struct stv *state;
int stat;
state = kzalloc(sizeof(struct stv), GFP_KERNEL);
if (!state)
return NULL;
state->adr = adr;
state->i2c = i2c;
memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops));
init_state(state);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
stat = attach_init(state);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
if (stat < 0) {
kfree(state);
return 0;
}
fe->tuner_priv = state;
return fe;
}
EXPORT_SYMBOL_GPL(stv6111_attach);
MODULE_DESCRIPTION("STV6111 driver");
MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel");
MODULE_LICENSE("GPL");
/*
* Local variables:
* c-basic-offset: 8
* End:
*/

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#ifndef _STV6111_H_
#define _STV6111_H_
struct dvb_frontend *stv6111_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 adr);
#endif

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/*
* NXP TDA18212HN silicon tuner driver
*
* Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef TDA18212_H
#define TDA18212_H
#include "dvb_frontend.h"
struct tda18212_config {
u8 i2c_address;
};
#if defined(CONFIG_DVB_TDA18212) || \
(defined(CONFIG_DVB_TDA18212_MODULE) && defined(MODULE))
extern struct dvb_frontend *tda18212_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, struct tda18212_config *cfg);
#else
static inline struct dvb_frontend *tda18212_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, struct tda18212_config *cfg)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

45
frontends/tda18212_priv.h Normal file
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@@ -0,0 +1,45 @@
/*
* NXP TDA18212HN silicon tuner driver
*
* Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef TDA18212_PRIV_H
#define TDA18212_PRIV_H
#include "tda18212.h"
#define LOG_PREFIX "tda18212"
#undef dbg
#define dbg(f, arg...) \
if (debug) \
printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
#undef err
#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
#undef info
#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
#undef warn
#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
struct tda18212_priv {
struct tda18212_config *cfg;
struct i2c_adapter *i2c;
u32 IF;
};
#endif

937
frontends/tda18212dd.c Normal file
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@@ -0,0 +1,937 @@
/*
* tda18212: Driver for the TDA18212 tuner
*
* Copyright (C) 2011-2013 Digital Devices GmbH
*
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA
* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <linux/version.h>
#include <asm/div64.h>
#include "dvb_frontend.h"
#ifndef CHK_ERROR
#define CHK_ERROR(s) if ((status = s) < 0) break
#endif
#define MASTER_PSM_AGC1 0
#define MASTER_AGC1_6_15dB 1
#define SLAVE_PSM_AGC1 1
#define SLAVE_AGC1_6_15dB 0
/* 0 = 2 Vpp ... 2 = 1 Vpp, 7 = 0.5 Vpp */
#define IF_LEVEL_DVBC 2
#define IF_LEVEL_DVBT 2
enum {
ID_1 = 0x00,
ID_2 = 0x01,
ID_3 = 0x02,
THERMO_1,
THERMO_2,
POWER_STATE_1,
POWER_STATE_2,
INPUT_POWER_LEVEL,
IRQ_STATUS,
IRQ_ENABLE,
IRQ_CLEAR,
IRQ_SET,
AGC1_1,
AGC2_1,
AGCK_1,
RF_AGC_1,
IR_MIXER_1 = 0x10,
AGC5_1,
IF_AGC,
IF_1,
REFERENCE,
IF_FREQUENCY_1,
RF_FREQUENCY_1,
RF_FREQUENCY_2,
RF_FREQUENCY_3,
MSM_1,
MSM_2,
PSM_1,
DCC_1,
FLO_MAX,
IR_CAL_1,
IR_CAL_2,
IR_CAL_3 = 0x20,
IR_CAL_4,
VSYNC_MGT,
IR_MIXER_2,
AGC1_2,
AGC5_2,
RF_CAL_1,
RF_CAL_2,
RF_CAL_3,
RF_CAL_4,
RF_CAL_5,
RF_CAL_6,
RF_FILTER_1,
RF_FILTER_2,
RF_FILTER_3,
RF_BAND_PASS_FILTER,
CP_CURRENT = 0x30,
AGC_DET_OUT = 0x31,
RF_AGC_GAIN_1 = 0x32,
RF_AGC_GAIN_2 = 0x33,
IF_AGC_GAIN = 0x34,
POWER_1 = 0x35,
POWER_2 = 0x36,
MISC_1,
RFCAL_LOG_1,
RFCAL_LOG_2,
RFCAL_LOG_3,
RFCAL_LOG_4,
RFCAL_LOG_5,
RFCAL_LOG_6,
RFCAL_LOG_7,
RFCAL_LOG_8,
RFCAL_LOG_9 = 0x40,
RFCAL_LOG_10 = 0x41,
RFCAL_LOG_11 = 0x42,
RFCAL_LOG_12 = 0x43,
REG_MAX,
};
enum HF_Standard {
HF_None = 0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio,
HF_AnalogMax, HF_DVBT_6MHZ, HF_DVBT_7MHZ, HF_DVBT_8MHZ,
HF_DVBT, HF_ATSC, HF_DVBC_6MHZ, HF_DVBC_7MHZ,
HF_DVBC_8MHZ, HF_DVBC
};
struct SStandardParams {
s32 m_IFFrequency;
u32 m_BandWidth;
u8 m_IF_1; /* FF IF_HP_fc:2 IF_Notch:1 LP_FC_Offset:2 LP_FC:3 */
u8 m_IR_MIXER_2; /* 03 :6 HI_Pass:1 DC_Notch:1 */
u8 m_AGC1_1; /* 0F :4 AGC1_Top:4 */
u8 m_AGC2_1; /* 0F :4 AGC2_Top:4 */
/*EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 */
u8 m_RF_AGC_1_Low;
/*EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 */
u8 m_RF_AGC_1_High;
u8 m_IR_MIXER_1; /* 0F :4 IR_mixer_Top:4 */
u8 m_AGC5_1; /* 1F :3 AGC5_Ana AGC5_Top:4 */
u8 m_AGCK_1; /* 0F :4 AGCK_Step:2 AGCK_Mode:2 */
u8 m_PSM_1; /* 20 :2 PSM_StoB:1 :5 */
bool m_AGC1_Freeze;
bool m_LTO_STO_immune;
};
#if 0
static struct SStandardParams
m_StandardTable[HF_DVBC_8MHZ - HF_DVBT_6MHZ + 1] = {
{ 3250000, 6000000, 0x20, 0x03, 0x00, 0x07, 0x2B,
0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_6MHZ */
{ 3500000, 7000000, 0x31, 0x01, 0x00, 0x07, 0x2B,
0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_7MHZ */
{ 4000000, 8000000, 0x22, 0x01, 0x00, 0x07, 0x2B,
0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_8MHZ */
{ 0000000, 0, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, false, false }, /* HF_DVBT (Unused) */
{ 3250000, 6000000, 0x20, 0x03, 0x0A, 0x07, 0x6D,
0x6D, 0x0E, 0x0E, 0x02, 0x20, false, false }, /* HF_ATSC */
{ 3600000, 6000000, 0x10, 0x01, 0x00, 0x07, 0x83,
0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, /* HF_DVBC_6MHZ */
{ 5000000, 7000000, 0x93, 0x03, 0x00, 0x07, 0x83,
0x83, 0x0B, 0x0B, 0x02, 0x00, true , true },
/* HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) */
{ 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x83,
0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, /* HF_DVBC_8MHZ */
};
#else
static struct SStandardParams
m_StandardTable[HF_DVBC_8MHZ - HF_DVBT_6MHZ + 1] = {
{ 4000000, 6000000, 0x41, 0x03, 0x00, 0x07, 0x2B,
0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_6MHZ */
{ 4500000, 7000000, 0x42, 0x03, 0x00, 0x07, 0x2B,
0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_7MHZ */
{ 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x2B,
0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_8MHZ */
/* ------------------------------ */
{ 0000000, 0, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, false, false }, /* HF_DVBT (Unused)*/
{ 3250000, 6000000, 0x20, 0x03, 0x0A, 0x07, 0x6D,
0x6D, 0x0E, 0x0E, 0x02, 0x20, false, false }, /* HF_ATSC */
{ 3600000, 6000000, 0x10, 0x01, 0x00, 0x07, 0x83,
0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, /* HF_DVBC_6MHZ */
{ 5000000, 7000000, 0x93, 0x03, 0x00, 0x07, 0x83,
0x83, 0x0B, 0x0B, 0x02, 0x00, true , true },
/* HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) */
{ 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x83,
0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, /* HF_DVBC_8MHZ */
};
#endif
struct tda_state {
struct i2c_adapter *i2c;
u8 adr;
enum HF_Standard m_Standard;
u32 m_Frequency;
u32 IF;
bool m_isMaster;
bool m_bPowerMeasurement;
bool m_bLTEnable;
bool m_bEnableFreeze;
u16 m_ID;
s32 m_SettlingTime;
u8 m_IFLevelDVBC;
u8 m_IFLevelDVBT;
u8 Regs[REG_MAX];
u8 m_LastPowerLevel;
};
static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len)
{
struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
.buf = data, .len = len} };
return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
}
static int i2c_read(struct i2c_adapter *adap,
u8 adr, u8 *msg, int len, u8 *answ, int alen)
{
struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0,
.buf = msg, .len = len},
{ .addr = adr, .flags = I2C_M_RD,
.buf = answ, .len = alen } };
if (i2c_transfer(adap, msgs, 2) != 2) {
pr_err("tda18212dd: i2c_read error\n");
return -1;
}
return 0;
}
static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
{
struct i2c_msg msg = {.addr = adr, .flags = 0,
.buf = data, .len = len};
if (i2c_transfer(adap, &msg, 1) != 1) {
pr_err("tda18212: i2c_write error\n");
return -1;
}
return 0;
}
static int write_regs(struct tda_state *state,
u8 SubAddr, u8 *Regs, u16 nRegs)
{
u8 data[REG_MAX + 1];
data[0] = SubAddr;
memcpy(data + 1, Regs, nRegs);
return i2c_write(state->i2c, state->adr, data, nRegs + 1);
}
static int write_reg(struct tda_state *state, u8 SubAddr, u8 Reg)
{
u8 msg[2] = {SubAddr, Reg};
return i2c_write(state->i2c, state->adr, msg, 2);
}
static int Read(struct tda_state *state, u8 *Regs)
{
return i2c_readn(state->i2c, state->adr, Regs, REG_MAX);
}
static int update_regs(struct tda_state *state, u8 RegFrom, u8 RegTo)
{
return write_regs(state, RegFrom,
&state->Regs[RegFrom], RegTo-RegFrom + 1);
}
static int update_reg(struct tda_state *state, u8 Reg)
{
return write_reg(state, Reg, state->Regs[Reg]);
}
static int read_regs(struct tda_state *state,
u8 SubAddr, u8 *Regs, u16 nRegs)
{
return i2c_read(state->i2c, state->adr,
&SubAddr, 1, Regs, nRegs);
}
static int read_reg(struct tda_state *state,
u8 SubAddr, u8 *Reg)
{
return i2c_read(state->i2c, state->adr,
&SubAddr, 1, Reg, 1);
}
static int read_reg1(struct tda_state *state, u8 Reg)
{
return read_reg(state, Reg, &state->Regs[Reg]);
}
static void init_state(struct tda_state *state)
{
u32 ulIFLevelDVBC = IF_LEVEL_DVBC;
u32 ulIFLevelDVBT = IF_LEVEL_DVBT;
u32 ulPowerMeasurement = 1;
u32 ulLTEnable = 1;
u32 ulEnableFreeze = 0;
state->m_Frequency = 0;
state->m_isMaster = true;
state->m_ID = 0;
state->m_LastPowerLevel = 0xFF;
state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07);
state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07);
state->m_bPowerMeasurement = (ulPowerMeasurement != 0);
state->m_bLTEnable = (ulLTEnable != 0);
state->m_bEnableFreeze = (ulEnableFreeze != 0);
}
static int StartCalibration(struct tda_state *state)
{
int status = 0;
do {
state->Regs[POWER_2] &= ~0x02; /* RSSI CK = 31.25 kHz */
CHK_ERROR(update_reg(state, POWER_2));
/* AGC1 Do Step = 2 */
state->Regs[AGC1_2] = (state->Regs[AGC1_2] & ~0x60) | 0x40;
CHK_ERROR(update_reg(state, AGC1_2)); /* AGC */
/* AGC2 Do Step = 1 */
state->Regs[RF_FILTER_3] =
(state->Regs[RF_FILTER_3] & ~0xC0) | 0x40;
CHK_ERROR(update_reg(state, RF_FILTER_3));
/* AGCs Assym Up Step = 3 // Datasheet sets all bits to 1! */
state->Regs[AGCK_1] |= 0xC0;
CHK_ERROR(update_reg(state, AGCK_1));
/* AGCs Assym Do Step = 2 */
state->Regs[AGC5_1] = (state->Regs[AGC5_1] & ~0x60) | 0x40;
CHK_ERROR(update_reg(state, AGC5_1));
state->Regs[IRQ_CLEAR] |= 0x80; /* Reset IRQ */
CHK_ERROR(update_reg(state, IRQ_CLEAR));
state->Regs[MSM_1] = 0x3B; /* Set Calibration */
state->Regs[MSM_2] = 0x01; /* Start MSM */
CHK_ERROR(update_regs(state, MSM_1, MSM_2));
state->Regs[MSM_2] = 0x00;
} while (0);
return status;
}
static int FinishCalibration(struct tda_state *state)
{
int status = 0;
u8 RFCal_Log[12];
do {
u8 IRQ = 0;
int Timeout = 150; /* 1.5 s */
while (true) {
CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ));
if ((IRQ & 0x80) != 0)
break;
Timeout -= 1;
if (Timeout == 0) {
status = -1;
break;
}
usleep_range(10000, 12000);
}
CHK_ERROR(status);
state->Regs[FLO_MAX] = 0x0A;
CHK_ERROR(update_reg(state, FLO_MAX));
state->Regs[AGC1_1] &= ~0xC0;
if (state->m_bLTEnable)
state->Regs[AGC1_1] |= 0x80; /* LTEnable */
state->Regs[AGC1_1] |= (state->m_isMaster ?
MASTER_AGC1_6_15dB :
SLAVE_AGC1_6_15dB) << 6;
CHK_ERROR(update_reg(state, AGC1_1));
state->Regs[PSM_1] &= ~0xC0;
state->Regs[PSM_1] |= (state->m_isMaster ?
MASTER_PSM_AGC1 : SLAVE_PSM_AGC1) << 6;
CHK_ERROR(update_reg(state, PSM_1));
state->Regs[REFERENCE] |= 0x03; /* XTOUT = 3 */
CHK_ERROR(update_reg(state, REFERENCE));
CHK_ERROR(read_regs(state, RFCAL_LOG_1,
RFCal_Log, sizeof(RFCal_Log)));
} while (0);
return status;
}
static int PowerOn(struct tda_state *state)
{
state->Regs[POWER_STATE_2] &= ~0x0F;
update_reg(state, POWER_STATE_2);
/* Digital clock source = Sigma Delta */
state->Regs[REFERENCE] |= 0x40;
update_reg(state, REFERENCE);
return 0;
}
static int Standby(struct tda_state *state)
{
int status = 0;
do {
/* Digital clock source = Quarz */
state->Regs[REFERENCE] &= ~0x40;
CHK_ERROR(update_reg(state, REFERENCE));
state->Regs[POWER_STATE_2] &= ~0x0F;
state->Regs[POWER_STATE_2] |= state->m_isMaster ? 0x08 : 0x0E;
CHK_ERROR(update_reg(state, POWER_STATE_2));
} while (0);
return status;
}
static int attach_init(struct tda_state *state)
{
int stat = 0;
u8 Id[2];
u8 PowerState = 0x00;
state->m_Standard = HF_None;
/* first read after cold reset sometimes fails on some cards,
try twice */
stat = read_regs(state, ID_1, Id, sizeof(Id));
stat = read_regs(state, ID_1, Id, sizeof(Id));
if (stat < 0)
return -1;
state->m_ID = ((Id[0] & 0x7F) << 8) | Id[1];
state->m_isMaster = ((Id[0] & 0x80) != 0);
if (!state->m_isMaster)
state->m_bLTEnable = false;
pr_info("tda18212dd: ChipID %04x %s\n", state->m_ID,
state->m_isMaster ? "master" : "slave");
if (state->m_ID != 18212)
return -1;
stat = read_reg(state, POWER_STATE_1 , &PowerState);
if (stat < 0)
return stat;
pr_info("tda18212dd: PowerState %02x\n", PowerState);
if (state->m_isMaster) {
if (PowerState & 0x02) {
/* msleep for XTAL Calibration
(on a PC this should be long done) */
u8 IRQStatus = 0;
int Timeout = 10;
while (Timeout > 0) {
read_reg(state, IRQ_STATUS, &IRQStatus);
if (IRQStatus & 0x20)
break;
Timeout -= 1;
usleep_range(10000, 12000);
}
if ((IRQStatus & 0x20) == 0)
stat = -ETIMEDOUT;
}
} else {
write_reg(state, FLO_MAX, 0x00);
write_reg(state, CP_CURRENT, 0x68);
}
Read(state, state->Regs);
PowerOn(state);
StartCalibration(state);
FinishCalibration(state);
Standby(state);
{
u8 RFCal_Log[12];
read_regs(state, RFCAL_LOG_1, RFCal_Log, sizeof(RFCal_Log));
pr_info("RFCal Log: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
RFCal_Log[0], RFCal_Log[1],
RFCal_Log[2], RFCal_Log[3],
RFCal_Log[4], RFCal_Log[5],
RFCal_Log[6], RFCal_Log[7],
RFCal_Log[8], RFCal_Log[9],
RFCal_Log[10], RFCal_Log[11]);
}
return stat;
}
static int PowerMeasurement(struct tda_state *state, u8 *pPowerLevel)
{
int status = 0;
do {
u8 IRQ = 0;
int Timeout = 70; /* 700 ms */
state->Regs[IRQ_CLEAR] |= 0x80; /* Reset IRQ */
CHK_ERROR(update_reg(state, IRQ_CLEAR));
state->Regs[MSM_1] = 0x80; /* power measurement */
state->Regs[MSM_2] = 0x01; /* Start MSM */
CHK_ERROR(update_regs(state, MSM_1, MSM_2));
state->Regs[MSM_2] = 0x00;
while (true) {
CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ));
if ((IRQ & 0x80) != 0)
break;
Timeout -= 1;
if (Timeout == 0) {
status = -1;
break;
}
usleep_range(10000, 12000);
}
CHK_ERROR(status);
CHK_ERROR(read_reg1(state, INPUT_POWER_LEVEL));
*pPowerLevel = state->Regs[INPUT_POWER_LEVEL] & 0x7F;
if (*pPowerLevel > 110)
*pPowerLevel = 110;
} while (0);
/* pr_info("PL %d\n", *pPowerLevel); */
return status;
}
static int SetFrequency(struct tda_state *state, u32 Frequency,
enum HF_Standard Standard)
{
int status = 0;
struct SStandardParams *StandardParams;
u32 f = Frequency / 1000;
u8 IRQ = 0;
int Timeout = 25; /* 250 ms */
u32 fRatio = Frequency / 16000000;
u32 fDelta = Frequency - fRatio * 16000000;
if (Standard < HF_DVBT_6MHZ || Standard > HF_DVBC_8MHZ)
return -EINVAL;
StandardParams = &m_StandardTable[Standard - HF_DVBT_6MHZ];
if (StandardParams->m_IFFrequency == 0)
return -EINVAL;
state->m_Standard = HF_None;
state->m_Frequency = 0;
do {
/* IF Level */
state->Regs[IF_AGC] = (Standard >= HF_DVBC_6MHZ) ?
state->m_IFLevelDVBC : state->m_IFLevelDVBT;
CHK_ERROR(update_reg(state, IF_AGC));
/* Standard setup */
state->Regs[IF_1] = StandardParams->m_IF_1;
CHK_ERROR(update_reg(state, IF_1));
state->Regs[IR_MIXER_2] = (state->Regs[IR_MIXER_2] & ~0x03) |
StandardParams->m_IR_MIXER_2;
CHK_ERROR(update_reg(state, IR_MIXER_2));
state->Regs[AGC1_1] = (state->Regs[AGC1_1] & ~0x0F) |
StandardParams->m_AGC1_1;
CHK_ERROR(update_reg(state, AGC1_1));
state->Regs[AGC2_1] = (state->Regs[AGC2_1] & ~0x0F) |
StandardParams->m_AGC2_1;
CHK_ERROR(update_reg(state, AGC2_1));
state->Regs[RF_AGC_1] &= ~0xEF;
if (Frequency < 291000000)
state->Regs[RF_AGC_1] |= StandardParams->m_RF_AGC_1_Low;
else
state->Regs[RF_AGC_1] |=
StandardParams->m_RF_AGC_1_High;
CHK_ERROR(update_reg(state, RF_AGC_1));
state->Regs[IR_MIXER_1] =
(state->Regs[IR_MIXER_1] & ~0x0F) |
StandardParams->m_IR_MIXER_1;
CHK_ERROR(update_reg(state, IR_MIXER_1));
state->Regs[AGC5_1] = (state->Regs[AGC5_1] & ~0x1F) |
StandardParams->m_AGC5_1;
CHK_ERROR(update_reg(state, AGC5_1));
state->Regs[AGCK_1] = (state->Regs[AGCK_1] & ~0x0F) |
StandardParams->m_AGCK_1;
CHK_ERROR(update_reg(state, AGCK_1));
state->Regs[PSM_1] = (state->Regs[PSM_1] & ~0x20) |
StandardParams->m_PSM_1;
CHK_ERROR(update_reg(state, PSM_1));
state->Regs[IF_FREQUENCY_1] = (StandardParams->m_IFFrequency /
50000);
CHK_ERROR(update_reg(state, IF_FREQUENCY_1));
if (state->m_isMaster && StandardParams->m_LTO_STO_immune) {
u8 tmp;
u8 RF_Filter_Gain;
CHK_ERROR(read_reg(state, RF_AGC_GAIN_1, &tmp));
RF_Filter_Gain = (tmp & 0x30) >> 4;
state->Regs[RF_FILTER_1] =
(state->Regs[RF_FILTER_1] & ~0x0C) |
(RF_Filter_Gain << 2);
CHK_ERROR(update_reg(state, RF_FILTER_1));
state->Regs[RF_FILTER_1] |= 0x10; /* Force */
CHK_ERROR(update_reg(state, RF_FILTER_1));
while (RF_Filter_Gain != 0) {
RF_Filter_Gain -= 1;
state->Regs[RF_FILTER_1] =
(state->Regs[RF_FILTER_1] & ~0x0C) |
(RF_Filter_Gain << 2);
CHK_ERROR(update_reg(state, RF_FILTER_1));
usleep_range(10000, 12000);
}
CHK_ERROR(status);
state->Regs[RF_AGC_1] |= 0x08;
CHK_ERROR(update_reg(state, RF_AGC_1));
}
state->Regs[IRQ_CLEAR] |= 0x80; /* Reset IRQ */
CHK_ERROR(update_reg(state, IRQ_CLEAR));
CHK_ERROR(PowerOn(state));
state->Regs[RF_FREQUENCY_1] = ((f >> 16) & 0xFF);
state->Regs[RF_FREQUENCY_2] = ((f >> 8) & 0xFF);
state->Regs[RF_FREQUENCY_3] = (f & 0xFF);
CHK_ERROR(update_regs(state, RF_FREQUENCY_1, RF_FREQUENCY_3));
state->Regs[MSM_1] = 0x41; /* Tune */
state->Regs[MSM_2] = 0x01; /* Start MSM */
CHK_ERROR(update_regs(state, MSM_1, MSM_2));
state->Regs[MSM_2] = 0x00;
while (true) {
CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ));
if ((IRQ & 0x80) != 0)
break;
Timeout -= 1;
if (Timeout == 0) {
status = -1;
break;
}
usleep_range(10000, 12000);
}
CHK_ERROR(status);
if (state->m_isMaster && StandardParams->m_LTO_STO_immune) {
state->Regs[RF_AGC_1] &= ~0x08;
CHK_ERROR(update_reg(state, RF_AGC_1));
msleep(50);
state->Regs[RF_FILTER_1] &= ~0x10; /* remove force */
CHK_ERROR(update_reg(state, RF_FILTER_1));
}
/* Spur reduction */
if (Frequency < 72000000)
state->Regs[REFERENCE] |= 0x40; /* Set digital clock */
else if (Frequency < 104000000)
state->Regs[REFERENCE] &= ~0x40; /*Clear digital clock*/
else if (Frequency < 120000000)
state->Regs[REFERENCE] |= 0x40; /* Set digital clock */
else {
if (fDelta <= 8000000) {
/* Clear or set digital clock */
if (fRatio & 1)
state->Regs[REFERENCE] &= ~0x40;
else
state->Regs[REFERENCE] |= 0x40;
} else {
/* Set or clear digital clock */
if (fRatio & 1)
state->Regs[REFERENCE] |= 0x40;
else
state->Regs[REFERENCE] &= ~0x40;
}
}
CHK_ERROR(update_reg(state, REFERENCE));
if (StandardParams->m_AGC1_Freeze && state->m_bEnableFreeze) {
u8 tmp;
int AGC1GainMin = 0;
int nSteps = 10;
int Step = 0;
CHK_ERROR(read_reg(state, AGC1_2, &tmp));
if ((tmp & 0x80) == 0) {
state->Regs[AGC1_2] |= 0x80; /* Loop off */
CHK_ERROR(update_reg(state, AGC1_2));
state->Regs[AGC1_2] |= 0x10; /* Force gain */
CHK_ERROR(update_reg(state, AGC1_2));
}
/* Adapt */
if (state->Regs[AGC1_1] & 0x40) { /* AGC1_6_15dB set */
AGC1GainMin = 6;
nSteps = 4;
}
while (Step < nSteps) {
int Down = 0;
int Up = 0, i;
u8 AGC1_Gain;
Step = Step + 1;
for (i = 0; i < 40; i += 1) {
CHK_ERROR(read_reg(state, AGC_DET_OUT,
&tmp));
Up += (tmp & 0x02) ? 1 : -4;
Down += (tmp & 0x01) ? 14 : -1;
usleep_range(1000, 2000);
}
CHK_ERROR(status);
AGC1_Gain = (state->Regs[AGC1_2] & 0x0F);
if (Up >= 15 && AGC1_Gain != 9) {
state->Regs[AGC1_2] =
(state->Regs[AGC1_2] & ~0x0F) |
(AGC1_Gain + 1);
CHK_ERROR(update_reg(state, AGC1_2));
} else if (Down >= 10 &&
AGC1_Gain != AGC1GainMin) {
state->Regs[AGC1_2] =
(state->Regs[AGC1_2] & ~0x0F) |
(AGC1_Gain - 1);
CHK_ERROR(update_reg(state, AGC1_2));
} else
Step = nSteps;
}
} else {
state->Regs[AGC1_2] &= ~0x10; /* unforce gain */
CHK_ERROR(update_reg(state, AGC1_2));
state->Regs[AGC1_2] &= ~0x80; /* Loop on */
CHK_ERROR(update_reg(state, AGC1_2));
}
state->m_Standard = Standard;
state->m_Frequency = Frequency;
if (state->m_bPowerMeasurement)
PowerMeasurement(state, &state->m_LastPowerLevel);
} while (0);
return status;
}
static int sleep(struct dvb_frontend *fe)
{
struct tda_state *state = fe->tuner_priv;
Standby(state);
return 0;
}
static int init(struct dvb_frontend *fe)
{
/* struct tda_state *state = fe->tuner_priv; */
return 0;
}
static int release(struct dvb_frontend *fe)
{
kfree(fe->tuner_priv);
fe->tuner_priv = NULL;
return 0;
}
static int set_params(struct dvb_frontend *fe)
{
struct tda_state *state = fe->tuner_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
int status = 0;
int Standard;
u32 bw;
bw = (p->bandwidth_hz + 999999) / 1000000;
state->m_Frequency = p->frequency;
/*pr_info("tuner bw=%u freq=%u\n", bw, state->m_Frequency);*/
if (p->delivery_system == SYS_DVBT ||
p->delivery_system == SYS_DVBT2 ||
p->delivery_system == SYS_ISDBT ||
p->delivery_system == SYS_DVBC2) {
switch (bw) {
case 6:
Standard = HF_DVBT_6MHZ;
break;
case 7:
Standard = HF_DVBT_7MHZ;
break;
default:
case 8:
Standard = HF_DVBT_8MHZ;
break;
}
} else if (p->delivery_system == SYS_DVBC_ANNEX_A) {
switch (bw) {
case 6:
Standard = HF_DVBC_6MHZ;
break;
case 7:
Standard = HF_DVBC_7MHZ;
break;
default:
case 8:
Standard = HF_DVBC_8MHZ;
break;
}
} else
return -EINVAL;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
SetFrequency(state, state->m_Frequency, Standard);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
return status;
}
static int get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
struct tda_state *state = fe->tuner_priv;
*frequency = state->IF;
return 0;
}
static int get_rf_strength(struct dvb_frontend *fe, u16 *st)
{
struct tda_state *state = fe->tuner_priv;
*st = state->m_LastPowerLevel;
return 0;
}
static int get_if(struct dvb_frontend *fe, u32 *frequency)
{
struct tda_state *state = fe->tuner_priv;
state->IF = 0;
if (state->m_Standard < HF_DVBT_6MHZ ||
state->m_Standard > HF_DVBC_8MHZ)
return 0;
state->IF = m_StandardTable[state->m_Standard -
HF_DVBT_6MHZ].m_IFFrequency;
*frequency = state->IF;
return 0;
}
static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
{
/* struct tda_state *state = fe->tuner_priv; */
/* *bandwidth = priv->bandwidth; */
return 0;
}
static struct dvb_tuner_ops tuner_ops = {
.info = {
.name = "NXP TDA18212",
.frequency_min = 47125000,
.frequency_max = 865000000,
.frequency_step = 62500
},
.init = init,
.sleep = sleep,
.set_params = set_params,
.release = release,
.get_frequency = get_frequency,
.get_if_frequency = get_if,
.get_bandwidth = get_bandwidth,
.get_rf_strength = get_rf_strength,
};
struct dvb_frontend *tda18212dd_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 adr)
{
struct tda_state *state;
int stat;
state = kzalloc(sizeof(struct tda_state), GFP_KERNEL);
if (!state)
return NULL;
state->adr = adr;
state->i2c = i2c;
memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops));
init_state(state);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
stat = attach_init(state);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
if (stat < 0) {
kfree(state);
return 0;
}
fe->tuner_priv = state;
return fe;
}
EXPORT_SYMBOL_GPL(tda18212dd_attach);
MODULE_DESCRIPTION("TDA18212 driver");
MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel");
MODULE_LICENSE("GPL");
/*
* Local variables:
* c-basic-offset: 8
* End:
*/

5
frontends/tda18212dd.h Normal file
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@@ -0,0 +1,5 @@
#ifndef _TDA18212DD_H_
#define _TDA18212DD_H_
struct dvb_frontend *tda18212dd_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 adr);
#endif

1330
frontends/tda18271c2dd.c Normal file
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File diff suppressed because it is too large Load Diff

17
frontends/tda18271c2dd.h Normal file
View File

@@ -0,0 +1,17 @@
#ifndef _TDA18271C2DD_H_
#define _TDA18271C2DD_H_
#if defined(CONFIG_DVB_TDA18271C2DD) || \
(defined(CONFIG_DVB_TDA18271C2DD_MODULE) \
&& defined(MODULE))
struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 adr);
#else
static inline struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c, u8 adr)
{
pr_warn("%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
#endif
#endif

814
frontends/tda18271c2dd_maps.h Normal file
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@@ -0,0 +1,814 @@
enum HF_S {
HF_None = 0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio,
HF_AnalogMax, HF_DVBT_6MHZ, HF_DVBT_7MHZ, HF_DVBT_8MHZ,
HF_DVBT, HF_ATSC, HF_DVBC_6MHZ, HF_DVBC_7MHZ,
HF_DVBC_8MHZ, HF_DVBC
};
struct SStandardParam m_StandardTable[] = {
{ 0, 0, 0x00, 0x00 }, /* HF_None */
{ 6000000, 7000000, 0x1D, 0x2C }, /* HF_B, */
{ 6900000, 8000000, 0x1E, 0x2C }, /* HF_DK, */
{ 7100000, 8000000, 0x1E, 0x2C }, /* HF_G, */
{ 7250000, 8000000, 0x1E, 0x2C }, /* HF_I, */
{ 6900000, 8000000, 0x1E, 0x2C }, /* HF_L, */
{ 1250000, 8000000, 0x1E, 0x2C }, /* HF_L1, */
{ 5400000, 6000000, 0x1C, 0x2C }, /* HF_MN, */
{ 1250000, 500000, 0x18, 0x2C }, /* HF_FM_Radio, */
{ 0, 0, 0x00, 0x00 }, /* HF_AnalogMax (Unused) */
{ 3300000, 6000000, 0x1C, 0x58 }, /* HF_DVBT_6MHZ */
{ 3500000, 7000000, 0x1C, 0x37 }, /* HF_DVBT_7MHZ */
{ 4000000, 8000000, 0x1D, 0x37 }, /* HF_DVBT_8MHZ */
{ 0, 0, 0x00, 0x00 }, /* HF_DVBT (Unused) */
{ 5000000, 6000000, 0x1C, 0x37 }, /* HF_ATSC (center = 3.25 MHz) */
{ 4000000, 6000000, 0x1D, 0x58 }, /* HF_DVBC_6MHZ (Chicago) */
{ 4500000, 7000000, 0x1E, 0x37 }, /* HF_DVBC_7MHZ (not documented by NXP) */
{ 5000000, 8000000, 0x1F, 0x37 }, /* HF_DVBC_8MHZ */
{ 0, 0, 0x00, 0x00 }, /* HF_DVBC (Unused) */
};
struct SMap m_BP_Filter_Map[] = {
{ 62000000, 0x00 },
{ 84000000, 0x01 },
{ 100000000, 0x02 },
{ 140000000, 0x03 },
{ 170000000, 0x04 },
{ 180000000, 0x05 },
{ 865000000, 0x06 },
{ 0, 0x00 }, /* Table End */
};
static struct SMapI m_RF_Cal_Map[] = {
{ 41000000, 0x0F },
{ 43000000, 0x1C },
{ 45000000, 0x2F },
{ 46000000, 0x39 },
{ 47000000, 0x40 },
{ 47900000, 0x50 },
{ 49100000, 0x16 },
{ 50000000, 0x18 },
{ 51000000, 0x20 },
{ 53000000, 0x28 },
{ 55000000, 0x2B },
{ 56000000, 0x32 },
{ 57000000, 0x35 },
{ 58000000, 0x3E },
{ 59000000, 0x43 },
{ 60000000, 0x4E },
{ 61100000, 0x55 },
{ 63000000, 0x0F },
{ 64000000, 0x11 },
{ 65000000, 0x12 },
{ 66000000, 0x15 },
{ 67000000, 0x16 },
{ 68000000, 0x17 },
{ 70000000, 0x19 },
{ 71000000, 0x1C },
{ 72000000, 0x1D },
{ 73000000, 0x1F },
{ 74000000, 0x20 },
{ 75000000, 0x21 },
{ 76000000, 0x24 },
{ 77000000, 0x25 },
{ 78000000, 0x27 },
{ 80000000, 0x28 },
{ 81000000, 0x29 },
{ 82000000, 0x2D },
{ 83000000, 0x2E },
{ 84000000, 0x2F },
{ 85000000, 0x31 },
{ 86000000, 0x33 },
{ 87000000, 0x34 },
{ 88000000, 0x35 },
{ 89000000, 0x37 },
{ 90000000, 0x38 },
{ 91000000, 0x39 },
{ 93000000, 0x3C },
{ 94000000, 0x3E },
{ 95000000, 0x3F },
{ 96000000, 0x40 },
{ 97000000, 0x42 },
{ 99000000, 0x45 },
{ 100000000, 0x46 },
{ 102000000, 0x48 },
{ 103000000, 0x4A },
{ 105000000, 0x4D },
{ 106000000, 0x4E },
{ 107000000, 0x50 },
{ 108000000, 0x51 },
{ 110000000, 0x54 },
{ 111000000, 0x56 },
{ 112000000, 0x57 },
{ 113000000, 0x58 },
{ 114000000, 0x59 },
{ 115000000, 0x5C },
{ 116000000, 0x5D },
{ 117000000, 0x5F },
{ 119000000, 0x60 },
{ 120000000, 0x64 },
{ 121000000, 0x65 },
{ 122000000, 0x66 },
{ 123000000, 0x68 },
{ 124000000, 0x69 },
{ 125000000, 0x6C },
{ 126000000, 0x6D },
{ 127000000, 0x6E },
{ 128000000, 0x70 },
{ 129000000, 0x71 },
{ 130000000, 0x75 },
{ 131000000, 0x77 },
{ 132000000, 0x78 },
{ 133000000, 0x7B },
{ 134000000, 0x7E },
{ 135000000, 0x81 },
{ 136000000, 0x82 },
{ 137000000, 0x87 },
{ 138000000, 0x88 },
{ 139000000, 0x8D },
{ 140000000, 0x8E },
{ 141000000, 0x91 },
{ 142000000, 0x95 },
{ 143000000, 0x9A },
{ 144000000, 0x9D },
{ 145000000, 0xA1 },
{ 146000000, 0xA2 },
{ 147000000, 0xA4 },
{ 148000000, 0xA9 },
{ 149000000, 0xAE },
{ 150000000, 0xB0 },
{ 151000000, 0xB1 },
{ 152000000, 0xB7 },
{ 152600000, 0xBD },
{ 154000000, 0x20 },
{ 155000000, 0x22 },
{ 156000000, 0x24 },
{ 157000000, 0x25 },
{ 158000000, 0x27 },
{ 159000000, 0x29 },
{ 160000000, 0x2C },
{ 161000000, 0x2D },
{ 163000000, 0x2E },
{ 164000000, 0x2F },
{ 164700000, 0x30 },
{ 166000000, 0x11 },
{ 167000000, 0x12 },
{ 168000000, 0x13 },
{ 169000000, 0x14 },
{ 170000000, 0x15 },
{ 172000000, 0x16 },
{ 173000000, 0x17 },
{ 174000000, 0x18 },
{ 175000000, 0x1A },
{ 176000000, 0x1B },
{ 178000000, 0x1D },
{ 179000000, 0x1E },
{ 180000000, 0x1F },
{ 181000000, 0x20 },
{ 182000000, 0x21 },
{ 183000000, 0x22 },
{ 184000000, 0x24 },
{ 185000000, 0x25 },
{ 186000000, 0x26 },
{ 187000000, 0x27 },
{ 188000000, 0x29 },
{ 189000000, 0x2A },
{ 190000000, 0x2C },
{ 191000000, 0x2D },
{ 192000000, 0x2E },
{ 193000000, 0x2F },
{ 194000000, 0x30 },
{ 195000000, 0x33 },
{ 196000000, 0x35 },
{ 198000000, 0x36 },
{ 200000000, 0x38 },
{ 201000000, 0x3C },
{ 202000000, 0x3D },
{ 203500000, 0x3E },
{ 206000000, 0x0E },
{ 208000000, 0x0F },
{ 212000000, 0x10 },
{ 216000000, 0x11 },
{ 217000000, 0x12 },
{ 218000000, 0x13 },
{ 220000000, 0x14 },
{ 222000000, 0x15 },
{ 225000000, 0x16 },
{ 228000000, 0x17 },
{ 231000000, 0x18 },
{ 234000000, 0x19 },
{ 235000000, 0x1A },
{ 236000000, 0x1B },
{ 237000000, 0x1C },
{ 240000000, 0x1D },
{ 242000000, 0x1E },
{ 244000000, 0x1F },
{ 247000000, 0x20 },
{ 249000000, 0x21 },
{ 252000000, 0x22 },
{ 253000000, 0x23 },
{ 254000000, 0x24 },
{ 256000000, 0x25 },
{ 259000000, 0x26 },
{ 262000000, 0x27 },
{ 264000000, 0x28 },
{ 267000000, 0x29 },
{ 269000000, 0x2A },
{ 271000000, 0x2B },
{ 273000000, 0x2C },
{ 275000000, 0x2D },
{ 277000000, 0x2E },
{ 279000000, 0x2F },
{ 282000000, 0x30 },
{ 284000000, 0x31 },
{ 286000000, 0x32 },
{ 287000000, 0x33 },
{ 290000000, 0x34 },
{ 293000000, 0x35 },
{ 295000000, 0x36 },
{ 297000000, 0x37 },
{ 300000000, 0x38 },
{ 303000000, 0x39 },
{ 305000000, 0x3A },
{ 306000000, 0x3B },
{ 307000000, 0x3C },
{ 310000000, 0x3D },
{ 312000000, 0x3E },
{ 315000000, 0x3F },
{ 318000000, 0x40 },
{ 320000000, 0x41 },
{ 323000000, 0x42 },
{ 324000000, 0x43 },
{ 325000000, 0x44 },
{ 327000000, 0x45 },
{ 331000000, 0x46 },
{ 334000000, 0x47 },
{ 337000000, 0x48 },
{ 339000000, 0x49 },
{ 340000000, 0x4A },
{ 341000000, 0x4B },
{ 343000000, 0x4C },
{ 345000000, 0x4D },
{ 349000000, 0x4E },
{ 352000000, 0x4F },
{ 353000000, 0x50 },
{ 355000000, 0x51 },
{ 357000000, 0x52 },
{ 359000000, 0x53 },
{ 361000000, 0x54 },
{ 362000000, 0x55 },
{ 364000000, 0x56 },
{ 368000000, 0x57 },
{ 370000000, 0x58 },
{ 372000000, 0x59 },
{ 375000000, 0x5A },
{ 376000000, 0x5B },
{ 377000000, 0x5C },
{ 379000000, 0x5D },
{ 382000000, 0x5E },
{ 384000000, 0x5F },
{ 385000000, 0x60 },
{ 386000000, 0x61 },
{ 388000000, 0x62 },
{ 390000000, 0x63 },
{ 393000000, 0x64 },
{ 394000000, 0x65 },
{ 396000000, 0x66 },
{ 397000000, 0x67 },
{ 398000000, 0x68 },
{ 400000000, 0x69 },
{ 402000000, 0x6A },
{ 403000000, 0x6B },
{ 407000000, 0x6C },
{ 408000000, 0x6D },
{ 409000000, 0x6E },
{ 410000000, 0x6F },
{ 411000000, 0x70 },
{ 412000000, 0x71 },
{ 413000000, 0x72 },
{ 414000000, 0x73 },
{ 417000000, 0x74 },
{ 418000000, 0x75 },
{ 420000000, 0x76 },
{ 422000000, 0x77 },
{ 423000000, 0x78 },
{ 424000000, 0x79 },
{ 427000000, 0x7A },
{ 428000000, 0x7B },
{ 429000000, 0x7D },
{ 432000000, 0x7F },
{ 434000000, 0x80 },
{ 435000000, 0x81 },
{ 436000000, 0x83 },
{ 437000000, 0x84 },
{ 438000000, 0x85 },
{ 439000000, 0x86 },
{ 440000000, 0x87 },
{ 441000000, 0x88 },
{ 442000000, 0x89 },
{ 445000000, 0x8A },
{ 446000000, 0x8B },
{ 447000000, 0x8C },
{ 448000000, 0x8E },
{ 449000000, 0x8F },
{ 450000000, 0x90 },
{ 452000000, 0x91 },
{ 453000000, 0x93 },
{ 454000000, 0x94 },
{ 456000000, 0x96 },
{ 457800000, 0x98 },
{ 461000000, 0x11 },
{ 468000000, 0x12 },
{ 472000000, 0x13 },
{ 473000000, 0x14 },
{ 474000000, 0x15 },
{ 481000000, 0x16 },
{ 486000000, 0x17 },
{ 491000000, 0x18 },
{ 498000000, 0x19 },
{ 499000000, 0x1A },
{ 501000000, 0x1B },
{ 506000000, 0x1C },
{ 511000000, 0x1D },
{ 516000000, 0x1E },
{ 520000000, 0x1F },
{ 521000000, 0x20 },
{ 525000000, 0x21 },
{ 529000000, 0x22 },
{ 533000000, 0x23 },
{ 539000000, 0x24 },
{ 541000000, 0x25 },
{ 547000000, 0x26 },
{ 549000000, 0x27 },
{ 551000000, 0x28 },
{ 556000000, 0x29 },
{ 561000000, 0x2A },
{ 563000000, 0x2B },
{ 565000000, 0x2C },
{ 569000000, 0x2D },
{ 571000000, 0x2E },
{ 577000000, 0x2F },
{ 580000000, 0x30 },
{ 582000000, 0x31 },
{ 584000000, 0x32 },
{ 588000000, 0x33 },
{ 591000000, 0x34 },
{ 596000000, 0x35 },
{ 598000000, 0x36 },
{ 603000000, 0x37 },
{ 604000000, 0x38 },
{ 606000000, 0x39 },
{ 612000000, 0x3A },
{ 615000000, 0x3B },
{ 617000000, 0x3C },
{ 621000000, 0x3D },
{ 622000000, 0x3E },
{ 625000000, 0x3F },
{ 632000000, 0x40 },
{ 633000000, 0x41 },
{ 634000000, 0x42 },
{ 642000000, 0x43 },
{ 643000000, 0x44 },
{ 647000000, 0x45 },
{ 650000000, 0x46 },
{ 652000000, 0x47 },
{ 657000000, 0x48 },
{ 661000000, 0x49 },
{ 662000000, 0x4A },
{ 665000000, 0x4B },
{ 667000000, 0x4C },
{ 670000000, 0x4D },
{ 673000000, 0x4E },
{ 676000000, 0x4F },
{ 677000000, 0x50 },
{ 681000000, 0x51 },
{ 683000000, 0x52 },
{ 686000000, 0x53 },
{ 688000000, 0x54 },
{ 689000000, 0x55 },
{ 691000000, 0x56 },
{ 695000000, 0x57 },
{ 698000000, 0x58 },
{ 703000000, 0x59 },
{ 704000000, 0x5A },
{ 705000000, 0x5B },
{ 707000000, 0x5C },
{ 710000000, 0x5D },
{ 712000000, 0x5E },
{ 717000000, 0x5F },
{ 718000000, 0x60 },
{ 721000000, 0x61 },
{ 722000000, 0x62 },
{ 723000000, 0x63 },
{ 725000000, 0x64 },
{ 727000000, 0x65 },
{ 730000000, 0x66 },
{ 732000000, 0x67 },
{ 735000000, 0x68 },
{ 740000000, 0x69 },
{ 741000000, 0x6A },
{ 742000000, 0x6B },
{ 743000000, 0x6C },
{ 745000000, 0x6D },
{ 747000000, 0x6E },
{ 748000000, 0x6F },
{ 750000000, 0x70 },
{ 752000000, 0x71 },
{ 754000000, 0x72 },
{ 757000000, 0x73 },
{ 758000000, 0x74 },
{ 760000000, 0x75 },
{ 763000000, 0x76 },
{ 764000000, 0x77 },
{ 766000000, 0x78 },
{ 767000000, 0x79 },
{ 768000000, 0x7A },
{ 773000000, 0x7B },
{ 774000000, 0x7C },
{ 776000000, 0x7D },
{ 777000000, 0x7E },
{ 778000000, 0x7F },
{ 779000000, 0x80 },
{ 781000000, 0x81 },
{ 783000000, 0x82 },
{ 784000000, 0x83 },
{ 785000000, 0x84 },
{ 786000000, 0x85 },
{ 793000000, 0x86 },
{ 794000000, 0x87 },
{ 795000000, 0x88 },
{ 797000000, 0x89 },
{ 799000000, 0x8A },
{ 801000000, 0x8B },
{ 802000000, 0x8C },
{ 803000000, 0x8D },
{ 804000000, 0x8E },
{ 810000000, 0x90 },
{ 811000000, 0x91 },
{ 812000000, 0x92 },
{ 814000000, 0x93 },
{ 816000000, 0x94 },
{ 817000000, 0x96 },
{ 818000000, 0x97 },
{ 820000000, 0x98 },
{ 821000000, 0x99 },
{ 822000000, 0x9A },
{ 828000000, 0x9B },
{ 829000000, 0x9D },
{ 830000000, 0x9F },
{ 831000000, 0xA0 },
{ 833000000, 0xA1 },
{ 835000000, 0xA2 },
{ 836000000, 0xA3 },
{ 837000000, 0xA4 },
{ 838000000, 0xA6 },
{ 840000000, 0xA8 },
{ 842000000, 0xA9 },
{ 845000000, 0xAA },
{ 846000000, 0xAB },
{ 847000000, 0xAD },
{ 848000000, 0xAE },
{ 852000000, 0xAF },
{ 853000000, 0xB0 },
{ 858000000, 0xB1 },
{ 860000000, 0xB2 },
{ 861000000, 0xB3 },
{ 862000000, 0xB4 },
{ 863000000, 0xB6 },
{ 864000000, 0xB8 },
{ 865000000, 0xB9 },
{ 0, 0x00 }, /* Table End */
};
static struct SMap2 m_KM_Map[] = {
{ 47900000, 3, 2 },
{ 61100000, 3, 1 },
{ 350000000, 3, 0 },
{ 720000000, 2, 1 },
{ 865000000, 3, 3 },
{ 0, 0x00 }, /* Table End */
};
static struct SMap2 m_Main_PLL_Map[] = {
{ 33125000, 0x57, 0xF0 },
{ 35500000, 0x56, 0xE0 },
{ 38188000, 0x55, 0xD0 },
{ 41375000, 0x54, 0xC0 },
{ 45125000, 0x53, 0xB0 },
{ 49688000, 0x52, 0xA0 },
{ 55188000, 0x51, 0x90 },
{ 62125000, 0x50, 0x80 },
{ 66250000, 0x47, 0x78 },
{ 71000000, 0x46, 0x70 },
{ 76375000, 0x45, 0x68 },
{ 82750000, 0x44, 0x60 },
{ 90250000, 0x43, 0x58 },
{ 99375000, 0x42, 0x50 },
{ 110375000, 0x41, 0x48 },
{ 124250000, 0x40, 0x40 },
{ 132500000, 0x37, 0x3C },
{ 142000000, 0x36, 0x38 },
{ 152750000, 0x35, 0x34 },
{ 165500000, 0x34, 0x30 },
{ 180500000, 0x33, 0x2C },
{ 198750000, 0x32, 0x28 },
{ 220750000, 0x31, 0x24 },
{ 248500000, 0x30, 0x20 },
{ 265000000, 0x27, 0x1E },
{ 284000000, 0x26, 0x1C },
{ 305500000, 0x25, 0x1A },
{ 331000000, 0x24, 0x18 },
{ 361000000, 0x23, 0x16 },
{ 397500000, 0x22, 0x14 },
{ 441500000, 0x21, 0x12 },
{ 497000000, 0x20, 0x10 },
{ 530000000, 0x17, 0x0F },
{ 568000000, 0x16, 0x0E },
{ 611000000, 0x15, 0x0D },
{ 662000000, 0x14, 0x0C },
{ 722000000, 0x13, 0x0B },
{ 795000000, 0x12, 0x0A },
{ 883000000, 0x11, 0x09 },
{ 994000000, 0x10, 0x08 },
{ 0, 0x00, 0x00 }, /* Table End */
};
static struct SMap2 m_Cal_PLL_Map[] = {
{ 33813000, 0xDD, 0xD0 },
{ 36625000, 0xDC, 0xC0 },
{ 39938000, 0xDB, 0xB0 },
{ 43938000, 0xDA, 0xA0 },
{ 48813000, 0xD9, 0x90 },
{ 54938000, 0xD8, 0x80 },
{ 62813000, 0xD3, 0x70 },
{ 67625000, 0xCD, 0x68 },
{ 73250000, 0xCC, 0x60 },
{ 79875000, 0xCB, 0x58 },
{ 87875000, 0xCA, 0x50 },
{ 97625000, 0xC9, 0x48 },
{ 109875000, 0xC8, 0x40 },
{ 125625000, 0xC3, 0x38 },
{ 135250000, 0xBD, 0x34 },
{ 146500000, 0xBC, 0x30 },
{ 159750000, 0xBB, 0x2C },
{ 175750000, 0xBA, 0x28 },
{ 195250000, 0xB9, 0x24 },
{ 219750000, 0xB8, 0x20 },
{ 251250000, 0xB3, 0x1C },
{ 270500000, 0xAD, 0x1A },
{ 293000000, 0xAC, 0x18 },
{ 319500000, 0xAB, 0x16 },
{ 351500000, 0xAA, 0x14 },
{ 390500000, 0xA9, 0x12 },
{ 439500000, 0xA8, 0x10 },
{ 502500000, 0xA3, 0x0E },
{ 541000000, 0x9D, 0x0D },
{ 586000000, 0x9C, 0x0C },
{ 639000000, 0x9B, 0x0B },
{ 703000000, 0x9A, 0x0A },
{ 781000000, 0x99, 0x09 },
{ 879000000, 0x98, 0x08 },
{ 0, 0x00, 0x00 }, /* Table End */
};
static struct SMap m_GainTaper_Map[] = {
{ 45400000, 0x1F },
{ 45800000, 0x1E },
{ 46200000, 0x1D },
{ 46700000, 0x1C },
{ 47100000, 0x1B },
{ 47500000, 0x1A },
{ 47900000, 0x19 },
{ 49600000, 0x17 },
{ 51200000, 0x16 },
{ 52900000, 0x15 },
{ 54500000, 0x14 },
{ 56200000, 0x13 },
{ 57800000, 0x12 },
{ 59500000, 0x11 },
{ 61100000, 0x10 },
{ 67600000, 0x0D },
{ 74200000, 0x0C },
{ 80700000, 0x0B },
{ 87200000, 0x0A },
{ 93800000, 0x09 },
{ 100300000, 0x08 },
{ 106900000, 0x07 },
{ 113400000, 0x06 },
{ 119900000, 0x05 },
{ 126500000, 0x04 },
{ 133000000, 0x03 },
{ 139500000, 0x02 },
{ 146100000, 0x01 },
{ 152600000, 0x00 },
{ 154300000, 0x1F },
{ 156100000, 0x1E },
{ 157800000, 0x1D },
{ 159500000, 0x1C },
{ 161200000, 0x1B },
{ 163000000, 0x1A },
{ 164700000, 0x19 },
{ 170200000, 0x17 },
{ 175800000, 0x16 },
{ 181300000, 0x15 },
{ 186900000, 0x14 },
{ 192400000, 0x13 },
{ 198000000, 0x12 },
{ 203500000, 0x11 },
{ 216200000, 0x14 },
{ 228900000, 0x13 },
{ 241600000, 0x12 },
{ 254400000, 0x11 },
{ 267100000, 0x10 },
{ 279800000, 0x0F },
{ 292500000, 0x0E },
{ 305200000, 0x0D },
{ 317900000, 0x0C },
{ 330700000, 0x0B },
{ 343400000, 0x0A },
{ 356100000, 0x09 },
{ 368800000, 0x08 },
{ 381500000, 0x07 },
{ 394200000, 0x06 },
{ 406900000, 0x05 },
{ 419700000, 0x04 },
{ 432400000, 0x03 },
{ 445100000, 0x02 },
{ 457800000, 0x01 },
{ 476300000, 0x19 },
{ 494800000, 0x18 },
{ 513300000, 0x17 },
{ 531800000, 0x16 },
{ 550300000, 0x15 },
{ 568900000, 0x14 },
{ 587400000, 0x13 },
{ 605900000, 0x12 },
{ 624400000, 0x11 },
{ 642900000, 0x10 },
{ 661400000, 0x0F },
{ 679900000, 0x0E },
{ 698400000, 0x0D },
{ 716900000, 0x0C },
{ 735400000, 0x0B },
{ 753900000, 0x0A },
{ 772500000, 0x09 },
{ 791000000, 0x08 },
{ 809500000, 0x07 },
{ 828000000, 0x06 },
{ 846500000, 0x05 },
{ 865000000, 0x04 },
{ 0, 0x00 }, /* Table End */
};
static struct SMap m_RF_Cal_DC_Over_DT_Map[] = {
{ 47900000, 0x00 },
{ 55000000, 0x00 },
{ 61100000, 0x0A },
{ 64000000, 0x0A },
{ 82000000, 0x14 },
{ 84000000, 0x19 },
{ 119000000, 0x1C },
{ 124000000, 0x20 },
{ 129000000, 0x2A },
{ 134000000, 0x32 },
{ 139000000, 0x39 },
{ 144000000, 0x3E },
{ 149000000, 0x3F },
{ 152600000, 0x40 },
{ 154000000, 0x40 },
{ 164700000, 0x41 },
{ 203500000, 0x32 },
{ 353000000, 0x19 },
{ 356000000, 0x1A },
{ 359000000, 0x1B },
{ 363000000, 0x1C },
{ 366000000, 0x1D },
{ 369000000, 0x1E },
{ 373000000, 0x1F },
{ 376000000, 0x20 },
{ 379000000, 0x21 },
{ 383000000, 0x22 },
{ 386000000, 0x23 },
{ 389000000, 0x24 },
{ 393000000, 0x25 },
{ 396000000, 0x26 },
{ 399000000, 0x27 },
{ 402000000, 0x28 },
{ 404000000, 0x29 },
{ 407000000, 0x2A },
{ 409000000, 0x2B },
{ 412000000, 0x2C },
{ 414000000, 0x2D },
{ 417000000, 0x2E },
{ 419000000, 0x2F },
{ 422000000, 0x30 },
{ 424000000, 0x31 },
{ 427000000, 0x32 },
{ 429000000, 0x33 },
{ 432000000, 0x34 },
{ 434000000, 0x35 },
{ 437000000, 0x36 },
{ 439000000, 0x37 },
{ 442000000, 0x38 },
{ 444000000, 0x39 },
{ 447000000, 0x3A },
{ 449000000, 0x3B },
{ 457800000, 0x3C },
{ 465000000, 0x0F },
{ 477000000, 0x12 },
{ 483000000, 0x14 },
{ 502000000, 0x19 },
{ 508000000, 0x1B },
{ 519000000, 0x1C },
{ 522000000, 0x1D },
{ 524000000, 0x1E },
{ 534000000, 0x1F },
{ 549000000, 0x20 },
{ 554000000, 0x22 },
{ 584000000, 0x24 },
{ 589000000, 0x26 },
{ 658000000, 0x27 },
{ 664000000, 0x2C },
{ 669000000, 0x2D },
{ 699000000, 0x2E },
{ 704000000, 0x30 },
{ 709000000, 0x31 },
{ 714000000, 0x32 },
{ 724000000, 0x33 },
{ 729000000, 0x36 },
{ 739000000, 0x38 },
{ 744000000, 0x39 },
{ 749000000, 0x3B },
{ 754000000, 0x3C },
{ 759000000, 0x3D },
{ 764000000, 0x3E },
{ 769000000, 0x3F },
{ 774000000, 0x40 },
{ 779000000, 0x41 },
{ 784000000, 0x43 },
{ 789000000, 0x46 },
{ 794000000, 0x48 },
{ 799000000, 0x4B },
{ 804000000, 0x4F },
{ 809000000, 0x54 },
{ 814000000, 0x59 },
{ 819000000, 0x5D },
{ 824000000, 0x61 },
{ 829000000, 0x68 },
{ 834000000, 0x6E },
{ 839000000, 0x75 },
{ 844000000, 0x7E },
{ 849000000, 0x82 },
{ 854000000, 0x84 },
{ 859000000, 0x8F },
{ 865000000, 0x9A },
{ 0, 0x00 }, /* Table End */
};
static struct SMap m_IR_Meas_Map[] = {
{ 200000000, 0x05 },
{ 400000000, 0x06 },
{ 865000000, 0x07 },
{ 0, 0x00 }, /* Table End */
};
static struct SMap2 m_CID_Target_Map[] = {
{ 46000000, 0x04, 18 },
{ 52200000, 0x0A, 15 },
{ 70100000, 0x01, 40 },
{ 136800000, 0x18, 40 },
{ 156700000, 0x18, 40 },
{ 186250000, 0x0A, 40 },
{ 230000000, 0x0A, 40 },
{ 345000000, 0x18, 40 },
{ 426000000, 0x0E, 40 },
{ 489500000, 0x1E, 40 },
{ 697500000, 0x32, 40 },
{ 842000000, 0x3A, 40 },
{ 0, 0x00, 0 }, /* Table End */
};
static struct SRFBandMap m_RF_Band_Map[7] = {
{ 47900000, 46000000, 0, 0},
{ 61100000, 52200000, 0, 0},
{ 152600000, 70100000, 136800000, 0},
{ 164700000, 156700000, 0, 0},
{ 203500000, 186250000, 0, 0},
{ 457800000, 230000000, 345000000, 426000000},
{ 865000000, 489500000, 697500000, 842000000},
};
u8 m_Thermometer_Map_1[16] = {
60, 62, 66, 64,
74, 72, 68, 70,
90, 88, 84, 86,
76, 78, 82, 80,
};
u8 m_Thermometer_Map_2[16] = {
92, 94, 98, 96,
106, 104, 100, 102,
122, 120, 116, 118,
108, 110, 114, 112,
};